Low noise charge pump device suitable for CMOS operational amplifier

Abstract

The application relates to a low-noise charge pump device suitable for a CMOS operational amplifier. The device comprises a slave charge pump unit, a main charge pump unit comprising a main charge pump, the main charge pump being connected with the slave charge pump to receive a slave pump pre-boost voltage loaded by the slave charge pump, wherein the main charge pump works under the slave pump pre-boost voltage and a global power supply, after the main charge pump works under the slave pump pre-boost voltage and the global power supply, the slave pump pre-boost voltage generated by the slave charge pump gradually enters a stable state, and the slave pump pre-boost voltage in the stable state is configured as a slave pump target voltage; based on the slave pump target voltage and the global power supply, the main charge pump generates a low-noise and stable main pump target voltage; the voltage value of the main pump target voltage is greater than that of the slave pump target voltage, and the voltage value of the slave pump target voltage is greater than that of the global power supply. The application can effectively reduce the ripple of the output voltage and meet the power supply demand of a low-noise rail-to-rail CMOS operational amplifier input stage.

Description

Technical Field

[0001] This invention relates to a low-noise charge pump device, and more particularly to a low-noise charge pump device suitable for CMOS operational amplifiers. Background Technology

[0002] The input common-mode range of a CMOS operational amplifier is an important parameter, typically requiring a rail-to-rail common-mode input range. Due to the input bias requirements of CMOS devices, a dual-input complementary approach is usually used to extend the common-mode input range. However, rail switching can introduce signal discontinuities, thereby increasing the harmonic distortion (THD) of the CMOS operational amplifier.

[0003] If only a single rail is desired as the input, while the input common-mode range must cover all power rails, then the local power supply voltage of the input stage needs to be increased to exceed the global power supply voltage. Currently, a boost charge pump can be used to increase the local power supply voltage of the input stage to exceed the global power supply voltage. However, existing boost charge pump circuits operate in a switched-capacitor manner, resulting in very large ripple in the boost charge pump output voltage. This severely affects the noise performance of large CMOS operational amplifiers, making it difficult to meet practical application requirements. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a low-noise charge pump device suitable for CMOS operational amplifiers, which can effectively reduce the ripple of the output voltage and meet the power supply requirements of the input stage of a low-noise rail-to-rail CMOS operational amplifier.

[0005] According to the technical solution provided by the present invention, a low-noise charge pump device suitable for CMOS operational amplifiers is provided, the low-noise charge pump device comprising:

[0006] The charge pump unit includes at least a slave charge pump, which operates under global power and pre-boosts the generated slave pump voltage to the main charge pump unit.

[0007] A main charge pump unit, comprising at least a main charge pump, wherein the main charge pump is adapted to be connected to a slave charge pump to receive a slave pump pre-boost applied by the slave charge pump, wherein,

[0008] The main charge pump operates with the slave pump pre-boosted and the global power supply.

[0009] After the main charge pump operates under the slave pump pre-boost and global power supply, the slave pump pre-boost generated by the slave charge pump gradually enters a stable state, and the slave pump pre-boost configuration in the stable state is used as the slave pump target voltage.

[0010] Based on the target voltage of the main pump and the global power supply, the main charge pump generates a low-noise and stable target voltage of the main pump;

[0011] The target voltage of the main pump is greater than the target voltage of the slave pump, and the target voltage of the slave pump is greater than the voltage of the global power supply.

[0012] The slave charge pump includes a slave pump main circuit operating under global power, a slave pump precharge power supply, and a slave pump compensation power supply, wherein...

[0013] The main circuit of the slave pump includes two slave pump unit branches, and each slave pump unit branch is adapted to be connected to the slave pump pre-charge power supply and the slave pump compensation power supply.

[0014] When generating the pre-pressurization of the slave pump, each slave pump unit branch is configured to alternately be in the slave branch pre-charge state and the slave branch output state. The working states of the two slave pump unit branches are non-overlapping, and the slave pump unit branch in the slave branch output state outputs the slave pump pre-pressurization.

[0015] For any slave pump unit branch in the slave pre-charge state, the slave pump unit branch is pre-charged using the slave pump pre-charge power supply. After that, the slave pump unit branch is configured to enter the slave output state from the slave pre-charge state.

[0016] For any slave pump unit branch in the slave output state, a slave pump compensation current is provided to the slave pump unit branch using a slave pump compensation power supply. When the slave pump compensation current matches the main pump load current, the slave pump unit branch outputs a slave pump pre-boost voltage that can serve as the target voltage of the slave pump. The main pump load current is the operating current of the main charge pump when it serves as the load of the slave pump unit branch.

[0017] For any slave pump unit branch, the slave pump unit branch includes a first slave pump capacitor and a second slave pump capacitor, wherein,

[0018] The first terminal of the first pump capacitor is connected to the drain terminal of the first pump NMOS transistor and the drain terminal of the first pump PMOS transistor, and the second terminal of the first pump capacitor is connected to the first terminal of the second pump capacitor, the drain terminal of the second pump NMOS transistor and the drain terminal of the second pump PMOS transistor.

[0019] The source terminals of the first NMOS transistor and the second NMOS transistor are both connected to floating ground. The source terminal of the first PMOS transistor is connected to the global power supply. The source terminal of the second PMOS transistor is connected to the output terminal of the pump compensation power supply. The power supply terminal of the pump compensation power supply is connected to the global power supply.

[0020] The second terminal of the second capacitor from the pump is connected to the drain terminal of the third PMOS transistor from the pump and the drain terminal of the fourth PMOS transistor from the pump. The source terminal of the third PMOS transistor from the pump is connected to the output terminal of the pre-charge power supply from the pump. The power supply terminal of the pre-charge power supply from the pump is connected to the global power supply.

[0021] The gate terminal of the fourth PMOS transistor in the pump is connected to the gate terminal of the third PMOS transistor in another pump unit branch.

[0022] The source terminals of the fourth PMOS transistors of the two pump units are interconnected and connected to the voltage output terminal of the charge pump. The voltage output terminal of the charge pump is connected to the global power supply through the charge pump output capacitor. The voltage output terminal of the charge pump is also connected to the cathode terminal of the charge pump diode, and the anode terminal of the charge pump diode is connected to the global power supply.

[0023] When the pump unit branch is in the branch pre-charge state, the first NMOS transistor, the second NMOS transistor, and the third PMOS transistor of the pump are configured to be in the on state to form a pump pre-charge circuit of pump pre-charge power source - pump third PMOS transistor - pump second capacitor - pump second NMOS transistor, and the pump second capacitor is pre-charged using the pump pre-charge circuit.

[0024] When the pump unit branch is in the output state, the first PMOS transistor, the second PMOS transistor, and the fourth PMOS transistor of the pump are configured to be in the conducting state, so as to form a pump discharge circuit based on the global power supply - the first PMOS transistor of the pump - the first capacitor of the pump - the second capacitor of the pump - the fourth PMOS transistor of the pump, and inject pump compensation current into the pump discharge circuit using the pump compensation power supply.

[0025] The slave charge pump unit further includes a slave pump control circuit for configuring the operating state of the slave pump unit branch within the slave charge pump, wherein,

[0026] Two slave pump unit branches are configured as slave pump unit first branch and slave pump unit second branch, respectively. The slave pump control circuit is adapted and connected to slave pump unit first branch and slave pump unit second branch to configure the corresponding operating states of slave pump unit first branch and slave pump unit second branch.

[0027] The pump control circuit generates clock signals CKA, CKAn, CKC, CKCn, CKD, and CKDn, among which...

[0028] Clock signal CKA is applied to the corresponding gate terminals of the first NMOS transistor and the second NMOS transistor in the first branch of the pump unit, and clock signal CKAn is applied to the corresponding gate terminals of the first NMOS transistor and the second NMOS transistor in the second branch of the pump unit.

[0029] The clock signal CKC is applied to the corresponding gate terminals of the first PMOS transistor and the second PMOS transistor in the first branch of the pump unit, and the clock signal CKCn is applied to the corresponding gate terminals of the first PMOS transistor and the second PMOS transistor in the second branch of the pump unit.

[0030] The clock signal CKD is applied to the gate of the third PMOS transistor in the first branch of the pump unit and the gate of the fourth PMOS transistor in the second branch of the pump unit. The clock signal CKDn is applied to the gate of the fourth PMOS transistor in the first branch of the pump unit and the gate of the third PMOS transistor in the second branch of the pump unit.

[0031] When configuring the corresponding operating states of the first branch and the second branch of the pump unit from the pump control circuit, it includes alternating first switching control and second switching control, wherein...

[0032] When the first switching control is executed, then:

[0033] When the first NMOS transistor and the second NMOS transistor in the first branch of the pump unit are configured to switch from the on state to the off state based on the clock signal CKA, the third PMOS transistor in the first branch of the pump and the fourth PMOS transistor in the second branch of the pump are configured to switch from the on state to the off state based on the clock signal CKD, and the third PMOS transistor in the second branch of the pump and the fourth PMOS transistor in the first branch of the pump are configured to switch from the on state to the off state based on the clock signal CKDn.

[0034] After the first and second NMOS transistors in the first branch of the pump unit are in the off state, the first and second NMOS transistors in the second branch of the pump unit are configured to enter the on state based on the clock signal CKAn. Before the first NMOS transistor in the second branch of the pump unit enters the on state, the first PMOS transistor and the second PMOS transistor in the second branch of the pump unit are configured to enter the off state based on the clock signal CKC. After the first NMOS transistor in the second branch of the pump unit enters the on state, the first PMOS transistor and the second PMOS transistor in the first branch of the pump unit are configured to enter the on state based on the clock signal CKCn.

[0035] If the second switching control is executed, then:

[0036] Before the first NMOS transistor and the second NMOS transistor in the first branch of the pump unit are configured to switch from the on state to the off state based on the clock signal CKA, the first NMOS transistor and the second NMOS transistor in the second branch of the pump unit are configured to switch from the on state to the off state based on the clock signal CKAn. The third PMOS transistor in the second branch of the pump unit and the fourth PMOS transistor in the first branch of the pump unit are configured to switch from the off state to the on state based on the clock signal CKDn. The first PMOS transistor and the second PMOS transistor in the first branch of the pump unit are configured to switch from the on state to the off state based on the clock signal CKCn.

[0037] When the first NMOS transistor and the second NMOS transistor in the first branch of the pump unit are configured to switch from the on state to the off state based on the clock signal CKA, the third PMOS transistor in the first branch of the pump unit and the fourth PMOS transistor in the second branch of the pump unit are configured to switch from the off state to the on state based on the clock signal CKD. After the first NMOS transistor and the second NMOS transistor in the first branch of the pump unit are configured to switch from the on state to the off state based on the clock signal CKA, the first PMOS transistor and the second PMOS transistor in the second branch of the pump unit are configured to switch from the off state to the on state based on the clock signal CKC.

[0038] The slave pump control circuit includes a slave clock generation circuit and a slave level conversion circuit adapted and connected to the slave clock generation circuit, wherein,

[0039] Based on the reference clock CLK, multiphase non-overlapping clock signals CKA, CKAn, CKB, CKBn, CKC, and CKCn are generated from the clock generation circuit.

[0040] The clock signals CKA, CKAn, CKC, and CKCn are directly loaded onto the charge pump.

[0041] Clock signals CKB and CKBn are applied to the slave level conversion circuit, and the slave level conversion circuit also receives the slave pump feedback voltage from the connected slave charge pump.

[0042] The pump feedback voltage is received from the pump feedback connection node within the level conversion circuit.

[0043] When the clock signal CKB and clock signal CKBn have rising edge transitions, the level conversion circuit boosts the slave node voltage value of the pump feedback connection node until the slave node voltage value at the pump feedback connection node is higher than the slave pump pre-boost output from the charge pump.

[0044] Based on the clock signal CKB and the slave node voltage value, the slave pump level conversion circuit generates a clock signal CKD, and makes the level state of the clock signal CKD match the voltage state of the slave pump pre-boost.

[0045] Based on the clock signal CKBn and the slave node voltage value, the slave pump level conversion circuit generates a clock signal CKDn, and makes the level state of the clock signal CKDn match the voltage state of the slave pump pre-boost.

[0046] The level conversion circuit includes a conversion generation master unit and a conversion coupling unit adapted and connected to the conversion generation master unit, wherein...

[0047] The conversion generation main unit includes two conversion generation sub-units. Each conversion generation sub-unit is connected to the conversion coupling unit, and the pump feedback connection node is connected to the conversion coupling unit and each conversion generation sub-unit.

[0048] The two conversion generation sub-units receive clock signal CKB and clock signal CKBn, respectively;

[0049] When the clock signal CKB or clock signal CKBn has a rising edge transition, the two conversion generation sub-units cooperate with the conversion coupling unit to raise and maintain the slave node voltage value at the pump feedback connection node;

[0050] Based on the clock signal CKB and the slave node voltage value, the conversion and generation subunit that receives the clock signal CKB generates a clock signal CKD that is synchronized with the clock signal CKB.

[0051] Based on the clock signal CKBn and the slave node voltage value, the conversion and generation subunit that receives the clock signal CKBn generates a clock signal CKDn that is synchronized with the clock signal CKBn.

[0052] The conversion generation subunit includes a conversion generation first NMOS transistor;

[0053] The source terminal of the first NMOS transistor is connected to a floating ground, and the gate terminal of the first NMOS transistor is connected to a clock signal CKB or a clock signal CKBn. The gate terminal of the first NMOS transistor is also connected to the first terminal of the conversion capacitor. The second terminal of the conversion capacitor is connected to the source terminal of the second NMOS transistor, the gate terminal of the PMOS transistor, and the conversion coupling unit.

[0054] The drain terminal of the first NMOS transistor is connected to the clock generation sub-unit, the gate terminal of the second NMOS transistor, and the drain terminal of the PMOS transistor. The negative power supply terminal of the clock generation sub-unit is connected to floating ground, and the positive power supply terminal of the clock generation sub-unit is connected to the pump feedback connection node. The clock generation sub-unit can generate a clock signal CKD or a clock signal CKDn.

[0055] The drain terminal of the second NMOS transistor is connected to the global power supply through the conversion generation resistor, and the source terminal of the PMOS transistor is connected to the pump feedback connection node.

[0056] When the clock signal CKB or clock signal CKBn has a rising edge transition, the charge on the conversion generation capacitor is transferred to the pump feedback connection node through the conversion coupling unit to increase the pump feedback voltage at the pump feedback connection node.

[0057] The switching coupling unit includes a first switching coupling PMOS transistor, a second switching coupling PMOS transistor, and a coupling holding capacitor, wherein...

[0058] The source terminal of the first PMOS transistor is connected to the gate terminal of the second PMOS transistor, the second terminal of the conversion generation capacitor in a conversion generation sub-unit, the gate terminal of the conversion generation PMOS transistor, and the source terminal of the second NMOS transistor.

[0059] The gate terminal of the first PMOS transistor and the source terminal of the second PMOS transistor are connected to the second terminal of the conversion generation capacitor in another conversion generation sub-unit, the gate terminal of the conversion generation PMOS transistor, and the source terminal of the second NMOS transistor.

[0060] The drain terminal of the first PMOS transistor and the drain terminal of the second PMOS transistor are connected to the first terminal of the coupling holding capacitor, the cathode terminal of the conversion generation diode, and the pump feedback connection node. The second terminal of the coupling holding capacitor is connected to the global power supply, and the anode terminal of the conversion generation diode is connected to the global power supply.

[0061] The floating land is provided by a floating land generation unit, wherein...

[0062] The floating ground generation unit includes a floating ground main circuit and a floating ground current limiting circuit adapted and connected to the floating ground main circuit.

[0063] Based on the reference voltage, the floating ground main circuit generates a floating ground corresponding to the reference voltage;

[0064] A floating ground current limiting circuit is used to limit the current when the floating ground main circuit is working.

[0065] The main charge pump includes a main pump main circuit, a main pump pre-charge power supply, and a main pump compensation power supply, wherein...

[0066] The main pump's main circuit and pre-charge power supply operate under global power supply conditions, while the main pump's compensation power supply operates under slave pump pre-boost conditions.

[0067] The main pump main circuit includes two main pump unit branches, and each main pump unit branch is adapted to and connected to the main pump pre-charge power supply and the main pump compensation power supply.

[0068] When generating the target voltage for the main pump, each main pump unit branch is configured to alternately be in the main branch pre-charge state and the main branch output state. The operating states of the two main pump unit branches are non-overlapping, and the target voltage for the main pump is output based on the main pump unit branch in the main branch output state.

[0069] For any main pump unit branch that is in the main branch pre-charge state, the main pump unit branch is pre-charged using the main pump pre-charge power supply. After that, the main pump unit branch is configured to enter the main branch output state from the main branch pre-charge state.

[0070] For any main pump unit branch in the main branch output state, a main pump compensation current is provided to the main pump unit branch using the main pump compensation power supply. When the slave pump target voltage is formed based on the slave pump pre-boost and the main pump compensation current matches the operational amplifier load current, the output of the main pump unit branch can reach the main pump target voltage.

[0071] The advantages of this invention are: the slave charge pump unit and the main charge pump unit are configured in a cascaded state. When the slave charge pump unit and the main charge pump unit operate under the same reference clock, a delay circuit is used to delay the operation of the main charge pump after the operation of the slave charge pump. This allows for faster output of the slave target power supply from the slave charge pump and the main target voltage from the main charge pump, reduces the noise of the main target voltage, and effectively increases the boost amplitude of the main target voltage. Attached Figure Description

[0072] Figure 1 This is a circuit block diagram of one embodiment of the low-noise charge pump device of the present invention.

[0073] Figure 2 This is a circuit schematic diagram of one embodiment of the clock generation circuit of the present invention.

[0074] Figure 3 This is a timing diagram of one embodiment of the present invention for generating clock signals from a clock generation circuit.

[0075] Figure 4 This is a circuit schematic diagram of one embodiment of the floating generation unit of the present invention.

[0076] Figure 5This is a circuit schematic diagram of one embodiment of the level conversion circuit of the present invention.

[0077] Figure 6 This is a circuit schematic diagram of one embodiment of the charge pump of the present invention.

[0078] Figure 7 This is a circuit diagram of one embodiment of the main charge pump of the present invention. Detailed Implementation

[0079] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0080] To effectively reduce output voltage ripple and meet the power supply requirements of the input stage of a low-noise rail-to-rail CMOS operational amplifier, this invention provides a low-noise charge pump device suitable for CMOS operational amplifiers. Specifically, the low-noise charge pump device includes:

[0081] The charge pump unit includes at least a slave charge pump, which operates under global power and pre-boosts the generated slave pump voltage to the main charge pump unit.

[0082] A main charge pump unit, comprising at least a main charge pump, wherein the main charge pump is adapted to be connected to a slave charge pump to receive a slave pump pre-boost applied by the slave charge pump, wherein,

[0083] The main charge pump operates with the slave pump pre-boosted and the global power supply.

[0084] After the main charge pump operates under the slave pump pre-boost and global power supply, the slave pump pre-boost generated by the slave charge pump gradually enters a stable state, and the slave pump pre-boost configuration in the stable state is used as the slave pump target voltage.

[0085] Based on the target voltage of the main pump and the global power supply, the main charge pump generates a low-noise and stable target voltage of the main pump;

[0086] The target voltage of the main pump is greater than the target voltage of the slave pump, and the target voltage of the slave pump is greater than the voltage of the global power supply.

[0087] To achieve a low-noise voltage, the low-noise charge pump device of this invention employs a two-stage charge pump configuration consisting of a slave charge pump unit and a main charge pump unit. Specifically, the slave charge pump unit serves as the first stage, and the main charge pump unit serves as the second stage. The slave pump target voltage required for the operation of the main charge pump unit is generated by the slave charge pump unit, and the main charge pump unit outputs the main pump target voltage. It should be understood that the main pump target voltage is the output voltage of the low-noise charge pump device of this invention. Based on the characteristics of charge pumps, the slave pump target voltage has low-noise characteristics. Therefore, the main pump target voltage generated by the main pump charge pump unit under the slave pump target voltage and the global power supply has superior low-noise characteristics, which may meet the power supply requirements of the input stage of a low-noise rail-to-rail CMOS operational amplifier.

[0088] In practical implementation, the charge pump unit should operate under a global power supply; that is, the global power supply is the power source for the charge pump unit. Figure 1 , Figures 4-7 In the following description, the global power supply VDD refers to power supply VDD. The configuration of power supply VDD can be consistent with existing technologies, such as providing a 5V voltage. The voltage provided by power supply VDD should meet the actual working requirements. In one embodiment of the present invention, when the slave charge pump is the stage preceding the master charge pump, the master charge pump serves as the load of the slave charge pump.

[0089] As explained above, the main charge pump unit should operate under both global power supply and slave pump pre-boost voltage. Therefore, this invention should configure the slave charge pump unit to enter the operating state before the main charge pump unit so that the slave charge pump unit can generate slave pump pre-boost voltage. It should be understood that, initially, the slave pump pre-boost voltage will be less than the global power supply voltage. After the slave charge pump generates the slave pump pre-boost voltage, it will be applied to the main charge pump. Only then will the main charge pump enter the effective operating state and act as the load for the slave charge pump.

[0090] It should be noted that the master charge pump and slave charge pump can operate on the same principle. When the master charge pump starts working and acts as the load for the slave charge pump, the slave pump pre-boost voltage generated by the slave charge pump will gradually increase and enter a steady state. Entering a steady state specifically means that the slave pump pre-boost voltage remains approximately stable. At this point, the generated slave pump pre-boost voltage can form the slave pump target voltage. Therefore, the slave pump target voltage is the voltage output by the slave charge pump and remains stable. Before the slave pump pre-boost voltage gradually increases to become the slave pump target voltage, the master charge pump operates under the slave pump pre-boost voltage and the global power supply. When the slave pump pre-boost voltage forms the slave pump target voltage, the master charge pump operates under the slave pump target voltage and the global power supply.

[0091] It should be understood that when the main charge pump is operating, the CMOS operational amplifier should act as the load of the main charge pump. When the main charge pump operates at the slave pump pre-boost and global voltage, the voltage supplied by the main charge pump to the CMOS operational amplifier will gradually increase. When the main charge pump operates at the slave pump target voltage and global voltage, the main charge pump can provide the CMOS operational amplifier with a stable and low-noise main pump target voltage.

[0092] In one embodiment of the present invention, both the slave charge pump and the main charge pump operate in boost mode. Therefore, the target voltage of the main pump is greater than the target voltage of the slave pump, and the target voltage of the slave pump is greater than the voltage of the global power supply. This indicates that the rail-to-rail power supply requirements of the CMOS operational amplifier are met.

[0093] In one embodiment of the present invention, the slave charge pump includes a slave pump main circuit operating under global power supply, a slave pump precharge power supply, and a slave pump compensation power supply, wherein,

[0094] The main circuit of the slave pump includes two slave pump unit branches, and each slave pump unit branch is adapted to be connected to the slave pump pre-charge power supply and the slave pump compensation power supply.

[0095] When generating the pre-pressurization of the slave pump, each slave pump unit branch is configured to alternately be in the slave branch pre-charge state and the slave branch output state. The working states of the two slave pump unit branches are non-overlapping, and the slave pump unit branch in the slave branch output state outputs the slave pump pre-pressurization.

[0096] For any slave pump unit branch in the slave pre-charge state, the slave pump unit branch is pre-charged using the slave pump pre-charge power supply. After that, the slave pump unit branch is configured to enter the slave output state from the slave pre-charge state.

[0097] For any slave pump unit branch in the slave output state, a slave pump compensation current is provided to the slave pump unit branch using a slave pump compensation power supply. When the slave pump compensation current matches the main pump load current, the slave pump unit branch outputs a slave pump pre-boost voltage that can serve as the target voltage of the slave pump. The main pump load current is the operating current of the main charge pump when it serves as the load of the slave pump unit branch.

[0098] To meet the aforementioned low-noise slave pump target voltage output, the slave charge pump may include a slave pump main circuit, a slave pump pre-charge power supply, and a slave pump compensation power supply, wherein the slave pump main circuit, slave pump pre-charge power supply, and slave pump compensation power supply are all powered by a global power supply. In specific implementations, the slave pump main circuit should include at least two slave pump unit branches. Preferably, the slave pump main circuit includes two slave pump unit branches, and each slave pump unit branch is connected to the slave pump pre-charge power supply and the slave pump compensation power supply.

[0099] It should be noted that each slave pump unit branch has the same operating mode. For example, each slave pump unit branch should alternate between the slave branch pre-charge state and the slave branch output state, and the operating states of two slave pump unit branches should not overlap. For example, if one slave pump unit branch is in the slave branch pre-charge state, then the other slave pump unit branch should not be in the slave branch pre-charge state at the same time. Similarly, when one slave pump unit branch is in the branch output state, that is, when generating slave pump pre-boost, there will not be two slave pump unit branches in the slave branch pre-charge state or in the slave branch output state at the same time, so as to ensure the reliability of slave charge pump operation.

[0100] To achieve the aforementioned pre-charge output from the slave pump and its application to the main charge pump, the slave pump unit branch in the slave output state should be configured to output voltage and pre-charge the slave pump to the main charge pump. Generally, when one slave pump unit branch is in the slave pre-charge state, another slave pump unit branch can be configured to be in the slave output state. That is, each slave pump unit branch alternates between the slave pre-charge state and the slave output state, and the two slave pump unit branches will be in the slave pre-charge state and the slave output state respectively. In other words, when one slave pump unit branch is in the slave pre-charge state, the other slave pump unit branch can be in the slave output state. Through the cooperation of the two slave pump unit branches, the continuous and stable pre-charge output from the slave pump can be guaranteed.

[0101] In specific implementation, when a slave pump unit branch is in the slave branch pre-charge state, it can be pre-charged using a slave pump pre-charge power supply. This reduces the change in output slave pump pre-boost voltage when the slave pump unit branch switches to slave branch output state, thereby reducing the ripple of the slave pump pre-boost voltage. The method and process of pre-charging the slave pump unit branch using a slave pump pre-charge power supply will be explained in detail below.

[0102] As explained above, when a slave pump unit branch is in slave output mode, a slave pump pre-boost output can be achieved. In one embodiment of the present invention, a slave pump compensation current is provided to the slave pump unit branch using a slave pump compensation power supply. Since the main charge pump acts as the load of the slave charge pump, when the slave pump compensation current matches the main pump load current, the slave pump unit branch outputs a slave pump pre-boost that can serve as the target voltage for the slave pump, i.e., a stable slave pump pre-boost can be formed at this time. It should be noted that the main pump load current is the operating current when the main charge pump acts as the load of the slave pump unit branch. The following will provide a detailed explanation of the slave pump compensation current provided by the slave pump compensation power supply and the slave pump unit branch outputting the slave pump pre-boost.

[0103] In one embodiment of the present invention, for any slave pump unit branch, the slave pump unit branch includes a first slave pump capacitor and a second slave pump capacitor, wherein,

[0104] The first terminal of the first pump capacitor is connected to the drain terminal of the first pump NMOS transistor and the drain terminal of the first pump PMOS transistor, and the second terminal of the first pump capacitor is connected to the first terminal of the second pump capacitor, the drain terminal of the second pump NMOS transistor and the drain terminal of the second pump PMOS transistor.

[0105] The source terminals of the first NMOS transistor and the second NMOS transistor are both connected to floating ground. The source terminal of the first PMOS transistor is connected to the global power supply. The source terminal of the second PMOS transistor is connected to the output terminal of the pump compensation power supply. The power supply terminal of the pump compensation power supply is connected to the global power supply.

[0106] The second terminal of the second capacitor from the pump is connected to the drain terminal of the third PMOS transistor from the pump and the drain terminal of the fourth PMOS transistor from the pump. The source terminal of the third PMOS transistor from the pump is connected to the output terminal of the pre-charge power supply from the pump. The power supply terminal of the pre-charge power supply from the pump is connected to the global power supply.

[0107] The gate terminal of the fourth PMOS transistor in the pump is connected to the gate terminal of the third PMOS transistor in another pump unit branch.

[0108] The source terminals of the fourth PMOS transistors of the two pump units are interconnected and connected to the voltage output terminal of the charge pump. The voltage output terminal of the charge pump is connected to the global power supply through the charge pump output capacitor. The voltage output terminal of the charge pump is also connected to the cathode terminal of the charge pump diode, and the anode terminal of the charge pump diode is connected to the global power supply.

[0109] When the pump unit branch is in the branch pre-charge state, the first NMOS transistor, the second NMOS transistor, and the third PMOS transistor of the pump are configured to be in the on state to form a pump pre-charge circuit of pump pre-charge power source - pump third PMOS transistor - pump second capacitor - pump second NMOS transistor, and the pump second capacitor is pre-charged using the pump pre-charge circuit.

[0110] When the pump unit branch is in the output state, the first PMOS transistor, the second PMOS transistor, and the fourth PMOS transistor of the pump are configured to be in the conducting state, so as to form a pump discharge circuit based on the global power supply - the first PMOS transistor of the pump - the first capacitor of the pump - the second capacitor of the pump - the fourth PMOS transistor of the pump, and inject pump compensation current into the pump discharge circuit using the pump compensation power supply.

[0111] Figure 6A circuit schematic of one embodiment of a charge pump is shown. The figure illustrates an embodiment in which the main circuit of the charge pump includes two slave pump unit branches. In the figure, capacitor C6, NMOS transistors MN10 and MN11, capacitor C8, PMOS transistors MP6, MP7, MP11, and MP12 constitute a slave pump unit branch. Capacitors C6 and C8 serve as the first and second slave pump capacitors in their respective slave pump unit branches. NMOS transistor MN10 forms the first slave pump NMOS transistor in its respective slave pump unit branch, and NMOS transistor MN11 forms the second slave pump NMOS transistor in its respective slave pump unit branch. PMOS transistors MP6, MP7, MP11, and MP12 form the first, second, third, and fourth slave pump PMOS transistors in their respective slave pump unit branches.

[0112] also, Figure 6 In this circuit, capacitor C5, NMOS transistors MN12 and MN13, capacitor C7, PMOS transistors MP8, MP9, MP10, and MP13 constitute another slave pump unit branch. Among them, capacitors C5 and C7 serve as the first and second slave pump capacitors in their respective slave pump unit branches. NMOS transistor MN12 forms the first slave pump NMOS transistor in its respective slave pump unit branch, and NMOS transistor MN13 forms the second slave pump NMOS transistor in its respective slave pump unit branch. PMOS transistors MP8, MP9, MP10, and MP13 form the first, second, third, and fourth slave pump PMOS transistors in their respective slave pump unit branches.

[0113] Furthermore, Figure 6 In this circuit, current source I3 is the power supply for pump compensation, current source I4 is the power supply for pump pre-charging, and Vssf is the floating ground. The corresponding power supply terminals of current sources I3 and I4 are connected to power supply VDD. Current sources I3 and I4 should generally be constant current sources.

[0114] It is understandable that, for the slave pump unit branch containing capacitor C6, when the slave pump unit branch is in the slave branch pre-charge state, at least NMOS transistors MN10, MN11, and MP11 are all in the conducting state, while PMOS transistors MP6, MP7, and MP12 are in the off state. At this time, current source I4 pre-charges capacitor C8 through PMOS transistor MP11-capacitor C8-NMOS transistor MN11-floating ground. When current source I4 is a constant current source, it can reduce noise injection into the power supply VDD. In addition, since the two ends of capacitor C6 are connected to the drain terminals of NMOS transistors MN10 and MN11 respectively, when NMOS transistors MN10 and MN11 are simultaneously in the conducting state, the voltage difference across capacitor C6 is 0, that is, the voltage across capacitor C6 is floating ground. Furthermore, the negative terminal voltage of capacitor C8 is also floating ground.

[0115] When the slave pump unit branch containing capacitor C6 is in slave output mode, at least PMOS transistors MP6, MP7, and MP12 must be in the conducting state. At this time, the power supply VDD, PMOS transistor MP6, capacitors C6 and C8, and PMOS transistor MP12 can form a slave pump discharge circuit. Current source I3 can inject slave pump compensation current into this discharge circuit. It should be noted that capacitor C8 is pre-charged before forming the slave pump discharge circuit. Therefore, when the slave pump discharge circuit outputs voltage, the charge on capacitor C8 will transfer to the voltage output terminal of the slave charge pump. Furthermore, since the negative terminal of capacitor C6 is connected to the power supply VDD, capacitor C6 will act as a booster to capacitor C8, thereby quickly transferring charge to the charge output terminal of the slave charge pump without relying on the slave pump compensation current injected by current source I3. This avoids voltage drop at the voltage output terminal of the slave charge pump and improves the efficiency and reliability of the slave pump pre-boost output.

[0116] For the slave pump unit branch where capacitor C5 is located, when the slave pump unit branch is in the slave branch pre-charge state or slave branch output state, refer to the corresponding description of the slave pump unit branch where capacitor C6 is located in the slave branch pre-charge state or slave branch output state. For example, when the slave pump unit branch where capacitor C5 is located is in the slave branch pre-charge state, the current source I4 charges capacitor C7 through PMOS transistor MP10-capacitor C7-NMOS transistor MN13-floating ground; when the slave pump unit branch where capacitor C5 is located is in the slave branch output state, the power supply VDD-PMOS transistor MP8-capacitor C5, capacitor C7 and PMOS transistor MP13 can form a slave pump discharge circuit, and the current source I3 is used to inject slave pump compensation current into the formed slave pump discharge circuit.

[0117] In order to configure the operating state of the slave pump unit branch as described above, in one embodiment of the present invention, the slave charge pump unit further includes a slave pump control circuit for configuring the operating state of the slave pump unit branch within the slave charge pump, wherein...

[0118] Two slave pump unit branches are configured as slave pump unit first branch and slave pump unit second branch, respectively. The slave pump control circuit is adapted and connected to slave pump unit first branch and slave pump unit second branch to configure the corresponding operating states of slave pump unit first branch and slave pump unit second branch.

[0119] The pump control circuit generates clock signals CKA, CKAn, CKC, CKCn, CKD, and CKDn, among which...

[0120] Clock signal CKA is applied to the corresponding gate terminals of the first NMOS transistor and the second NMOS transistor in the first branch of the pump unit, and clock signal CKAn is applied to the corresponding gate terminals of the first NMOS transistor and the second NMOS transistor in the second branch of the pump unit.

[0121] The clock signal CKC is applied to the corresponding gate terminals of the first PMOS transistor and the second PMOS transistor in the first branch of the pump unit, and the clock signal CKCn is applied to the corresponding gate terminals of the first PMOS transistor and the second PMOS transistor in the second branch of the pump unit.

[0122] The clock signal CKD is applied to the gate of the third PMOS transistor in the first branch of the pump unit and the gate of the fourth PMOS transistor in the second branch of the pump unit. The clock signal CKDn is applied to the gate of the fourth PMOS transistor in the first branch of the pump unit and the gate of the third PMOS transistor in the second branch of the pump unit.

[0123] When configuring the corresponding operating states of the first branch and the second branch of the pump unit from the pump control circuit, it includes alternating first switching control and second switching control, wherein...

[0124] When the first switching control is executed, then:

[0125] When the first NMOS transistor and the second NMOS transistor in the first branch of the pump unit are configured to switch from the on state to the off state based on the clock signal CKA, the third PMOS transistor in the first branch of the pump and the fourth PMOS transistor in the second branch of the pump are configured to switch from the on state to the off state based on the clock signal CKD, and the third PMOS transistor in the second branch of the pump and the fourth PMOS transistor in the first branch of the pump are configured to switch from the on state to the off state based on the clock signal CKDn.

[0126] After the first and second NMOS transistors in the first branch of the pump unit are in the off state, the first and second NMOS transistors in the second branch of the pump unit are configured to enter the on state based on the clock signal CKAn. Before the first NMOS transistor in the second branch of the pump unit enters the on state, the first PMOS transistor and the second PMOS transistor in the second branch of the pump unit are configured to enter the off state based on the clock signal CKC. After the first NMOS transistor in the second branch of the pump unit enters the on state, the first PMOS transistor and the second PMOS transistor in the first branch of the pump unit are configured to enter the on state based on the clock signal CKCn.

[0127] If the second switching control is executed, then:

[0128] Before the first NMOS transistor and the second NMOS transistor in the first branch of the pump unit are configured to switch from the on state to the off state based on the clock signal CKA, the first NMOS transistor and the second NMOS transistor in the second branch of the pump unit are configured to switch from the on state to the off state based on the clock signal CKAn. The third PMOS transistor in the second branch of the pump unit and the fourth PMOS transistor in the first branch of the pump unit are configured to switch from the off state to the on state based on the clock signal CKDn. The first PMOS transistor and the second PMOS transistor in the first branch of the pump unit are configured to switch from the on state to the off state based on the clock signal CKCn.

[0129] When the first NMOS transistor and the second NMOS transistor in the first branch of the pump unit are configured to switch from the on state to the off state based on the clock signal CKA, the third PMOS transistor in the first branch of the pump unit and the fourth PMOS transistor in the second branch of the pump unit are configured to switch from the off state to the on state based on the clock signal CKD. After the first NMOS transistor and the second NMOS transistor in the first branch of the pump unit are configured to switch from the on state to the off state based on the clock signal CKA, the first PMOS transistor and the second PMOS transistor in the second branch of the pump unit are configured to switch from the off state to the on state based on the clock signal CKC.

[0130] It should be understood that, Figure 6 In this configuration, the pump unit branch formed by the pump unit branch containing capacitors C6 and C8 is configured as the first pump unit branch, and the pump unit branch formed by the pump unit branch containing capacitors C5 and C7 is configured as the second pump unit branch. Figure 6In this configuration, clock signal CKA is simultaneously applied to the gates of NMOS transistors MN10 and MN11, clock signal CKAn is simultaneously applied to the gates of NMOS transistors MN12 and MN13, clock signal CKC is simultaneously applied to the gates of PMOS transistors MP8 and MP9, clock signal CKCn is simultaneously applied to the gates of PMOS transistors MP6 and MP7, clock signal CKD is simultaneously applied to the gates of PMOS transistors MP11 and MP13, and clock signal CKDn is simultaneously applied to the gates of PMOS transistors MP10 and MP12.

[0131] As explained above, the operating states of the first branch and the second branch of the pump unit are non-overlapping. For example, if the first branch of the pump unit is in the pre-charge state, then the second branch of the pump unit is in the output state. At this time, for... Figure 6 In the embodiment of the charge pump shown, NMOS transistors MN10, MN11, and MP11 are in the ON state to configure the first branch of the slave pump unit containing capacitor C6 to be in the slave branch pre-charge state. At this time, PMOS transistors MP8, MP9, and MP13 should also be in the ON state to enable the second branch of the slave pump unit to be in the slave branch output state. Similarly, when NMOS transistors MN12, MN13, and MP10 are in the ON state to configure the second branch of the slave pump unit to be in the pre-charge state, PMOS transistors MP6, MP7, and MP12 should also be in the ON state to configure the first branch of the slave pump unit to be in the slave branch output state.

[0132] Figure 3 The diagram shows the timing diagrams for clock signals CKA, CKAn, CKC, and CKCn. As can be seen, clock signals CKA and CKAn are essentially inverses of each other, but their transitions are not asynchronous. The situation is similar for clock signals CKC and CKCn; please refer to [reference needed] for details. Figure 3 And this is an explanation. It should be noted that... Figure 3 The clock signals CKD and CKDn are not shown in the diagram, but CKD can be generated synchronously from clock signal CKB, and CKDn can be generated synchronously from clock signal CKBn. The generation methods of clock signals CKD and CKDn will be explained in detail below.

[0133] As explained above, during operation, both the first and second branches of the pump unit alternate between pre-charge and output states. Since the corresponding operating states of the first and second branches should not overlap, the state switching of the first and second branches should be controlled to improve the stability and reliability of the pump. For example, when the first branch is in the pre-charge state, the second branch will be in the output state. Therefore, the switching process of the first branch from the pre-charge state to the output state and the switching process of the second branch from the output state to the pre-charge state should be controlled.

[0134] In order to achieve switching control, in one embodiment of the present invention, a first switching control and a second switching control are configured to be performed alternately by means of a pump control circuit. When the first switching control is executed, the first branch of the pump unit is mainly made to exit the pre-charge state of the branch, and then the first branch of the pump unit is made to enter the output state of the branch. The process of executing the first switching control state is illustrated below.

[0135] When executing the first switching state control, such as Figure 3 As shown, the clock signal CKA transitions from a high level to a low level (i.e., a falling edge appears on the clock signal CKA, as shown in the image). Figure 3 (The position indicated by the dashed line on the left side of the middle section) At this point, it can be driven based on the clock signal CKA. Figure 6 NMOS transistors MN10 and MN11 transition from the ON state to the OFF state. The rising edge of the clock signal CKD can be synchronized with the falling edge of the clock signal CKA. Therefore, when NMOS transistor MN10 is turned off, the clock signal CKD can be used to drive PMOS transistors MP11 and MP13 to turn off.

[0136] The clock signal CKAn will only rise after the clock signal CKA transitions to a low level. This means the falling edge of clock signal CKA and the rising edge of clock signal CKAn are not synchronized. When the clock signal CKAn reaches a rising edge, then... Figure 6 NMOS transistors MN12 and MN13 will transition from the off state to the on state. Subsequently, before the falling edge of the clock signal CKAn occurs, NMOS transistors MN12 and MN13 will remain on.

[0137] In addition, by Figure 3 It can be seen that after the falling edge of the clock signal CKA occurs and before the rising edge of the clock signal CKAn occurs, the rising edge of the clock signal CKC occurs, and after the rising edge of the clock signal CKAn occurs, the falling edge of the clock signal CKCn occurs.

[0138] Combination Figure 3 and Figure 6 It can be seen that before executing the first switching control state, the first branch of the pump unit is in the pre-charge state, while the second branch of the pump unit is in the output state. When executing the first switching control state, based on the clock signal CKA, NMOS transistors MN10 and MN11 are configured to turn off. At the same time, PMOS transistors MP11 and MP13 can be configured to turn off, thereby shutting down the voltage output of the second branch of the pump unit. Before NMOS transistors MN12 and MN13 are configured to enter the conduction state based on the clock signal CKAn, when the clock signal CKC has a rising edge transition, PMOS transistors MP8 and MP9 are turned off, which means that the charging of capacitors C5 and C7 is stopped, and the second branch of the pump unit completely exits the output state.

[0139] It should be noted that when PMOS transistor MP13 is turned off, the clock signal CKC will also quickly rise and change. Therefore, when PMOS transistors MP8 and MP9 are turned off after PMOS transistor MP13 is turned off, it has almost no impact on the exit of the output state of the second branch of the pump unit, nor will it affect the operation of the first branch of the pump unit.

[0140] When NMOS transistors MN12 and MN13 are turned on based on clock signal CKAn, and PMOS transistors MP10 and MP12 are turned on based on clock signal CKDn, the second branch of the pump unit enters the slave branch pre-charge state. Since the falling edge of clock signal CNCn is after the rising edge of clock signal CNKA, when PMOS transistors MP6 and MP7 are turned on based on clock signal CNCn (PMOS transistor MP12 is already turned on), the first branch of the pump unit enters the slave branch output state. That is, the first branch of the pump unit will only enter the slave branch output state after the second branch of the pump unit enters the slave branch pre-charge state.

[0141] It should be understood that executing the second switching control primarily switches the first branch of the pump unit from the branch output state to the branch pre-charge state. Figure 3 It can be seen that when executing the second switching control, the clock signal CKA should be configured to transition from a low level to a high level (that is, when the clock signal CKA has a rising edge, such as...). Figure 3 (At the position indicated by the dashed line in the middle), at this time, the clock signal CKA can drive NMOS transistors MN10 and MN11 to conduct. Since the clock signal CKD is synchronized with the clock signal CKB, ... Figure 3It can be seen that when NMOS transistor MN10 is turned on, the clock signal CKD will have a falling edge, and PMOS transistors MP11 and MP13 will be turned on. As explained above, when NMOS transistors MN10, MN11, and MP11 are turned on, the first branch of the pump unit enters the pre-charge state of the slave branch.

[0142] In addition, since PMOS transistor MP13 is already turned on, the charge on capacitor C7 will be transferred through PMOS transistor MP13 to the charge output terminal of the charge pump, thus preventing a voltage drop at the charge output terminal of the charge pump.

[0143] Depend on Figure 3 It can be seen that before the rising edge of the clock signal CKA, the falling edge of the clock signal CKAn has already occurred. Therefore, NMOS transistors MN12 and MN13 are turned off before NMOS transistor MN10 is turned on. Furthermore, when NMOS transistor MN12 is turned off, PMOS transistors MP10 and MP12 are driven to turn off based on the clock signal CKDn. Thus, before the first branch of the pump unit enters the pre-charge state, the second branch of the pump unit has already exited the output state. In addition, before the rising edge of the clock signal CKA and after the falling edge of the clock signal CKAn, the rising edge of the clock signal CKCn will occur, which will drive PMOS transistors MP6 and MP7 to turn off, thereby disconnecting the power supply VDD from the capacitors C6 and C8 in the first branch of the pump unit.

[0144] The clock signal CKC will only have a falling edge after the rising edge of the clock signal CKCn. When the falling edge of the clock signal CKC occurs, PMOS transistors MP8 and MP9 will be turned on. Since PMOS transistor MP13 has already been turned on and the PMOS transistors have been turned off, the second branch of the pump unit has fully entered the output state of the branch.

[0145] In one embodiment of the present invention, the slave pump control circuit includes a slave clock generation circuit and a slave level conversion circuit adapted and connected to the slave clock generation circuit, wherein,

[0146] Based on the reference clock CLK, multiphase non-overlapping clock signals CKA, CKAn, CKB, CKBn, CKC, and CKCn are generated from the clock generation circuit.

[0147] The clock signals CKA, CKAn, CKC, and CKCn are directly loaded onto the charge pump.

[0148] Clock signals CKB and CKBn are applied to the slave level conversion circuit, and the slave level conversion circuit also receives the slave pump feedback voltage from the connected slave charge pump.

[0149] The pump feedback voltage is received from the pump feedback connection node within the level conversion circuit.

[0150] When the clock signal CKB and clock signal CKBn have rising edge transitions, the level conversion circuit boosts the slave node voltage value of the pump feedback connection node until the slave node voltage value at the pump feedback connection node is higher than the slave pump pre-boost output from the charge pump.

[0151] Based on the clock signal CKB and the slave node voltage value, the slave pump level conversion circuit generates a clock signal CKD, and makes the level state of the clock signal CKD match the voltage state of the slave pump pre-boost.

[0152] Based on the clock signal CKBn and the slave node voltage value, the slave pump level conversion circuit generates a clock signal CKDn, and makes the level state of the clock signal CKDn match the voltage state of the slave pump pre-boost.

[0153] In order to generate the aforementioned clock signal, Figure 1 The figure illustrates one embodiment of a pump control circuit. The pump control circuit may include a clock generation circuit and a level conversion circuit, and receives a reference clock CLK via the clock generation circuit. The reference clock CLK can be selected as needed. Figure 3 The diagram illustrates one embodiment of the reference clock CLK. Upon receiving the reference clock CLK, the clock generation circuit simultaneously generates clock signals CKA, CKAn, CKB, CKBn, CKC, and CKCn. It should be noted that clock signals CKA, CKAn, CKC, and CKCn are directly loaded onto the slave charge pump. For details on loading onto the slave charge pump, please refer to [reference needed]. Figure 6 The above explanation will not be repeated here.

[0154] Depend on Figure 6As explained above, the source terminals of PMOS transistors MP12 and MP13 are both connected to the voltage output terminal of the charge pump. The conduction state of PMOS transistor MP12 is driven by the clock signal CKDn, and the conduction state of PMOS transistor MP13 is driven by the clock signal CKD. Therefore, in order to improve the reliability of driving PMOS transistors MP12 and MP13, the clock signal CKD can be generated based on the clock signal CKB and the level conversion circuit, and the clock signal CKDn can be generated based on the clock signal CKBn and the level conversion circuit. It can be understood that the level states of the clock signals CKD and CKD should be adapted to the level states of the voltage output terminal of the charge pump.

[0155] In order to configure the corresponding level states of clock signals CKD and CKDn, the voltage output from the charge pump can be fed back to the level conversion circuit. Figure 6 In this circuit, Vc represents the pre-boost voltage output from the charge pump. The sources of PMOS transistors MP12 and MP13, the first terminal of capacitor C4, and the cathode of diode D1 are interconnected to form the charge pump's voltage output. The second terminal of capacitor C4 and the anode of diode D1 are connected to the power supply VDD. Capacitor C acts as a filter to regulate the voltage, reducing the voltage ripple of the pump feedback voltage VhC. The pre-boost voltage output is fed back to the level shifting circuit via resistor R4. Figure 6 In this context, VHc represents the feedback voltage from the charge pump to the pump.

[0156] right Figure 6 In the initial state of the charge pump, when the pre-boost voltage of the charge pump is lower than the power supply VDD, diode D1 will be in the on state, so that the power supply VDD will provide a reference voltage at the voltage output terminal. As the pre-charge-branch voltage output occurs alternately in the charge pump, the pre-boost voltage of the charge pump can be gradually increased to be higher than the power supply VDD through capacitor C7 / C8, and the pre-boost voltage of the charge pump can be kept higher than the power supply VDD. At this time, diode D1 will be in the off state.

[0157] It is understandable that, since the pump pre-boost voltage can form the pump feedback voltage through resistor R4, the pump feedback voltage is generally slightly lower than the pump pre-boost voltage output from the charge pump. In one embodiment of the present invention, a pump feedback connection node for receiving the pump feedback voltage is provided in the level conversion circuit, such as when there is a connection with... Figure 6 The node connected to resistor R4 in the middle, that is, the node connected to resistor R4 in the level conversion circuit, can form a pump feedback connection node. The specific situation of forming a pump feedback node will be explained in detail below.

[0158] Within the level shifting circuit, when the clock signal CKB or clock signal CKBn experiences a rising edge transition, the slave node voltage at the slave pump feedback connection node can be increased, ultimately making the slave node voltage greater than the slave pump pre-boost output from the charge pump. Furthermore, based on the clock signal CKB and the slave node voltage value, a clock signal CKD can be generated. The level state of the clock signal CKD is matched with the voltage state of the slave pump pre-boost to improve the stability and reliability of driving PMOS transistors MP11 and MP13. The method for generating the clock signal CKDn can be the same as that for generating the clock signal CKD; therefore, based on the clock signal CKDn, the stability and reliability of driving PMOS transistors MP10 and MP12 can be improved.

[0159] Figure 2 The diagram shows a circuit schematic of one embodiment of the clock generation circuit. Figure 2 In this circuit, the clock generation circuit may include an inverter INV1, a NAND gate NAND1, and a NAND gate NAND2, wherein...

[0160] The input of inverter INV1 and one input of NAND gate NAND1 receive the reference clock CLK. The output of inverter INV1 is connected to one input of NAND gate NAND2. The other input of NAND gate NAND1 is connected to the output of buffer BUF3. The input of buffer BUF3 is connected to the output of inverter INV5. The input of inverter INV5 is connected to the output of inverter INV2.

[0161] The other input of NAND gate NAND2 is connected to the output of buffer BUF2, the input of buffer BUF2 is connected to the output of inverter INV7, and the input of inverter INV7 is connected to the output of inverter INV9.

[0162] The output of NAND gate NAND1 is connected to the input of inverter INV9 and the input of buffer BUF1. The output of buffer BUF1 is connected to the input of inverter INV11. The output of inverter INV11 outputs the clock signal CKAn.

[0163] The output of inverter IV9 is also connected to the input of inverter INV10 and the input of buffer BUF6. The output of buffer BUF6 is connected to the input of inverter INV8. The clock signal CKBn can be generated through the output of inverter INV10, and the clock signal CKCn can be generated through the output of inverter INV8.

[0164] The output of NAND gate NAND2 is connected to the input of inverter INV2 and the input of buffer BUF4. The output of buffer BUF4 is connected to the input of inverter INV3. The output of inverter INV3 outputs the clock signal CLKA.

[0165] The output of inverter INV2 is also connected to the input of inverter INV4 and the input of buffer BUF5. The output of buffer BUF5 is connected to the input of inverter INV6. The clock signal CLKB can be generated through the output of inverter INV4, and the clock signal CKC can be generated through inverter INV6.

[0166] It should be noted that buffers BUF1 to BUF6 can adopt existing commonly used forms. Timing delays can be implemented using buffers. The timing delays provided by buffers BUF1 to BUF6 can be the same, or they can be different, depending on the specific configuration. Figure 3 The clock signal CKA is the standard, and will not be elaborated here. Of course, other circuit configurations can be used for the clock generation circuit, and the specific configuration can be selected according to the needs, which will not be elaborated here.

[0167] In practical implementation, for the aforementioned slave clock generating circuit, the positive power supply terminal of the device within the slave clock generating circuit is generally connected to the global power supply, while the negative power supply terminal of the device should be connected to the floating ground. It should be understood that the specific connection details between the positive and negative power supply terminals of the device and the global power supply and floating ground are not specified in the provided text. Figure 2 As shown in the image.

[0168] In order to generate clock signals CKD and CKDn, in one embodiment of the present invention, the level conversion circuit includes a conversion generation master unit and a conversion coupling unit adapted and connected to the conversion generation master unit, wherein...

[0169] The conversion generation main unit includes two conversion generation sub-units. Each conversion generation sub-unit is connected to the conversion coupling unit, and the pump feedback connection node is connected to the conversion coupling unit and each conversion generation sub-unit.

[0170] The two conversion generation sub-units receive clock signal CKB and clock signal CKBn, respectively;

[0171] When the clock signal CKB or clock signal CKBn has a rising edge transition, the two conversion generation sub-units cooperate with the conversion coupling unit to raise and maintain the slave node voltage value at the pump feedback connection node;

[0172] Based on the clock signal CKB and the slave node voltage value, the conversion and generation subunit that receives the clock signal CKB generates a clock signal CKD that is synchronized with the clock signal CKB.

[0173] Based on the clock signal CKBn and the slave node voltage value, the conversion and generation subunit that receives the clock signal CKBn generates a clock signal CKDn that is synchronized with the clock signal CKBn.

[0174] Specifically, the level conversion circuit may include a conversion generation main unit and a conversion coupling unit. The conversion generation main unit may include at least two conversion generation sub-units. Generally, the conversion generation main unit has two conversion generation sub-units, which can be used to generate clock signals CKD and CKDn respectively. The conversion generation sub-units and conversion coupling units are described in detail below.

[0175] In one embodiment of the present invention, the conversion generation subunit includes a conversion generation first NMOS transistor;

[0176] The source terminal of the first NMOS transistor is connected to a floating ground, and the gate terminal of the first NMOS transistor is connected to a clock signal CKB or a clock signal CKBn. The gate terminal of the first NMOS transistor is also connected to the first terminal of the conversion capacitor. The second terminal of the conversion capacitor is connected to the source terminal of the second NMOS transistor, the gate terminal of the PMOS transistor, and the conversion coupling unit.

[0177] The drain terminal of the first NMOS transistor is connected to the clock generation sub-unit, the gate terminal of the second NMOS transistor, and the drain terminal of the PMOS transistor. The negative power supply terminal of the clock generation sub-unit is connected to floating ground, and the positive power supply terminal of the clock generation sub-unit is connected to the pump feedback connection node. The clock generation sub-unit can generate a clock signal CKD or a clock signal CKDn.

[0178] The drain terminal of the second NMOS transistor is connected to the global power supply through the conversion generation resistor, and the source terminal of the PMOS transistor is connected to the pump feedback connection node.

[0179] When the clock signal CKB or clock signal CKBn has a rising edge transition, the charge on the conversion generation capacitor is transferred to the slave pump feedback connection node through the conversion coupling unit to boost the slave node voltage at the slave pump feedback connection node.

[0180] Figure 5The figure illustrates an embodiment where the main conversion generation unit has two conversion generation sub-units. In the figure, resistor R1, NMOS transistor MN6, PMOS transistor MP2, capacitor C1, NMOS transistor MN8, and inverter INV11 form one conversion generation sub-unit, which can generate the clock signal CKD; resistor R2, NMOS transistor MN7, PMOS transistor MP3, capacitor C2, NMOS transistor MN9, and inverter INV12 form another conversion generation sub-unit, which can generate the clock signal CKDn.

[0181] For the conversion generation sub-unit where resistor R1 is located, NMOS transistor MN8 forms the first conversion generation NMOS transistor, capacitor C1 forms the conversion generation capacitor, NMOS transistor MN6 forms the second conversion generation NMOS transistor, PMOS transistor MP2 forms the conversion generation PMOS transistor, and inverter INV11 forms the clock generation sub-unit. Unlike the power supply connections of the components in the aforementioned clock generation circuit, the positive power supply terminal of inverter INV11 should be connected to the slave pump feedback connection node, while the negative power supply terminal of inverter INV11 is connected to floating ground. That is, the positive power supply terminal of inverter INV11 is powered by the slave node voltage, thus allowing the level state of the generated clock signal CKD to match the voltage state of the slave pump pre-boost.

[0182] For the conversion generation sub-unit where resistor R2 is located, NMOS transistor MN9 forms the first conversion generation NMOS transistor, capacitor C2 forms the conversion generation capacitor, NMOS transistor MN7 forms the second conversion generation NMOS transistor, PMOS transistor MP3 forms the conversion generation PMOS transistor, and inverter INV12 forms the clock generation sub-unit. Specifically, the situation of the formed clock generation sub-unit can be referred to the corresponding description of the conversion generation sub-unit where resistor R1 is located, which will not be repeated here.

[0183] In one embodiment of the present invention, the switching coupling unit includes a first switching coupling PMOS transistor, a second switching coupling PMOS transistor, and a coupling holding capacitor, wherein,

[0184] The source terminal of the first PMOS transistor is connected to the gate terminal of the second PMOS transistor, the second terminal of the conversion generation capacitor in a conversion generation sub-unit, the gate terminal of the conversion generation PMOS transistor, and the source terminal of the second NMOS transistor.

[0185] The gate terminal of the first PMOS transistor and the source terminal of the second PMOS transistor are connected to the second terminal of the conversion generation capacitor in another conversion generation sub-unit, the gate terminal of the conversion generation PMOS transistor, and the source terminal of the second NMOS transistor.

[0186] The drain terminal of the first PMOS transistor and the drain terminal of the second PMOS transistor are connected to the first terminal of the coupling holding capacitor, the cathode terminal of the conversion generation diode, and the pump feedback connection node. The second terminal of the coupling holding capacitor is connected to the global power supply, and the anode terminal of the conversion generation diode is connected to the global power supply.

[0187] Figure 5 An embodiment of the conversion coupling unit is also shown in the figure. Figure 5 In the process, PMOS transistors MP4 and MP5 can respectively form the first PMOS transistor and the second PMOS transistor in the conversion coupling unit, capacitor C3 forms the coupling holding capacitor, and diode D0 can form the conversion generation diode.

[0188] for Figure 5 The level shifting circuit shown in the diagram allows the clock signal CKB to drive NMOS transistor MN8 to conduct when CKB is high. The input of inverter INV11 is then connected to floating ground via NMOS transistor MN8. In this case, inverter INV11 outputs a high-level clock signal CKD, ensuring synchronization between clock signals CKD and CKB. Similarly, when clock signal CKBn is high, inverter INV12 outputs a high-level clock signal CKDn.

[0189] Depend on Figure 3 It can be seen that clock signals CKB and CKBn are primarily inverted states, but there are also states where both clock signals CKB and CKBn are high. When both clock signals CKB and CKBn are high, NMOS transistors MN8 and MN9 are simultaneously turned on, resulting in inverter INV11 outputting a high-level clock signal CKD, and inverter INV12 also outputting a high-level clock signal. Conversely, when clock signals CKB and CKBn are not simultaneously high, clock signals CKD and CKDn are inverted states.

[0190] The following example illustrates the operation of the slave level conversion circuit of this invention, using the rising edge of the clock signal CKB and the subsequent boosting of the slave node voltage. Specifically, before the rising edge of the clock signal CKB, the clock signal CKB is in a low-level state. Therefore, for Figure 5Regarding capacitor C1, both the first and second terminals of capacitor C1 are at low levels. Since the second terminal of capacitor C1 is connected to the gate terminal of PMOS transistor MP2, the source terminal of PMOS transistor MP2 is the slave node voltage. The slave node voltage is related to the slave pump feedback voltage and the power supply VDD. If the voltage difference between the power supply VDD and the slave pump feedback voltage is greater than the conduction threshold of diode D0, then the slave node voltage is the power supply VDD minus the voltage drop of diode D0 when it is conducting. If the slave pump feedback voltage is greater than the power supply VDD, then diode D0 is turned off, and the slave node voltage is the slave pump feedback voltage.

[0191] When the second terminal of capacitor C1 is low, based on the above description of the slave node voltage, PMOS transistor MP2 will be turned on. After PMOS transistor MP2 is turned on, NMOS transistor MN6 will be turned on. The power supply VDD is connected to the second terminal of capacitor C1 through resistor R1, NMOS transistor MN6, and so on, thereby increasing the voltage at the second terminal of capacitor C1. Figure 3 As can be seen, when the clock signal CKB has a rising edge, the clock signal CKBn will remain at a high level. At this time, the second terminal of capacitor C2 is at a high level, causing the gate terminal of PMOS transistor MP5 and the source terminal of PMOS transistor MP4 to be at a high level. When the clock signal CKBn has a falling edge, the second terminal of capacitor C2 is at a low level. At this time, PMOS transistor MP5 is turned on, and the charge pumped into capacitor C1 by the rising edge of the clock signal CKB can be transferred to the slave-pump feedback connection node through PMOS transistor MP5. This can increase the voltage of the slave-pump feedback connection node, and thus increase the slave node voltage. Figure 5 In the above, the slave node voltage VHc is the node corresponding to the slave node voltage VHc, which is the slave pump feedback connection node. The transferred charge is a jump height of the clock signal CKB.

[0192] As explained above, when the clock signal CKB is low, PMOS transistor MP2 and NMOS transistor MN6 will conduct sequentially. At this time, the power supply VDD is connected to the second terminal of capacitor C1 through resistor R1 and NMOS transistor MN6, and the voltage at the second terminal of capacitor C1 is VDD. When the clock signal CKB has a rising edge transition, the voltage at the second terminal of capacitor C1 becomes VDD plus a transition voltage. Therefore, when the voltage at the pump feedback connection node is balanced with the voltage at the second terminal of capacitor C1, the slave node voltage will remain stable, that is, the voltage stability of the pump feedback connection node can be maintained during operation. When the slave node voltage is the sum of VDD and a transition voltage, the slave node voltage will be greater than the voltage at the voltage output terminal of the charge pump. The clock signal CKD generated under the slave node voltage can effectively improve the stability and reliability of driving PMOS transistors MP12 and MP13 to conduct.

[0193] It should be understood that when the clock signal CKBn has a rising edge, the operation of the level conversion circuit can be referred to the above description, and will not be repeated here.

[0194] In one embodiment of the present invention, the floating land is provided by a floating land generation unit, wherein,

[0195] The floating ground generation unit includes a floating ground main circuit and a floating ground current limiting circuit adapted and connected to the floating ground main circuit.

[0196] Based on the reference voltage, the floating ground main circuit generates a floating ground corresponding to the reference voltage;

[0197] A floating ground current limiting circuit is used to limit the current when the floating ground main circuit is working.

[0198] As can be seen from the above description, the charge pump operates on the global power supply and the floating ground. Therefore, by adjusting the voltage of the floating ground, the voltage level of the charge pump device of the present invention can be adjusted, such as by adjusting the voltage level of the pump pre-boost and the target voltage of the main pump by adjusting the reference ground.

[0199] To ensure the floating ground meets low-noise requirements, the floating ground of this invention is provided by a floating ground generation unit, meaning the floating ground can be generated through this unit. The floating ground generation unit generally includes a floating ground main circuit and a floating ground current-limiting circuit. The floating ground main circuit receives a reference voltage and generates a floating ground corresponding to that voltage. Specifically, the floating ground corresponds to the reference voltage, meaning the voltage of the floating ground is approximately or substantially consistent with the reference voltage. During operation, the floating ground current-limiting circuit limits the push and pull currents of the floating ground main circuit, reducing noise coupled to the floating ground generation unit when the floating ground load changes abruptly, thereby improving the low-noise performance of the floating ground provided by the floating ground generation unit. The floating ground load is the circuit operating under the floating ground. In one embodiment of this invention, the floating ground load is a slave charge pump and a main charge pump.

[0200] Figure 4 The diagram illustrates a circuit schematic of one embodiment of the floating ground generation unit. In the diagram, the floating ground main circuit may include PMOS transistors MP0 and MP1, Vref is the reference voltage, and Vssf is the floating ground. The floating ground is connected to the gate of PMOS transistor MP1. The reference voltage is applied to the gate of PMOS transistor MP0, which drives PMOS transistor MP1 to conduct. It can be understood that PMOS transistors MP0 and MP1 form a differential pair to achieve closed-loop control of the floating ground, and can form two input terminals similar to an operational amplifier. Based on the input characteristics of an operational amplifier, the floating ground is essentially the same as the reference voltage. In one embodiment of the invention, the floating ground may be 1.2V.

[0201] Figure 4 In this circuit, the floating current limiting circuit may include a constant current source I1, an NMOS transistor MN1, and an NMOS transistor MN2. The power supply terminal of the constant current source I1 is connected to the power supply VDD. The output terminal of the constant current source I1 is connected to the source terminal of the PMOS transistor MP0 and the source terminal of the PMOS transistor MP1. The drain terminal of the PMOS transistor MP1 is connected to the drain terminal of the NMOS transistor MN1, the gate terminal of the NMOS transistor MN1, and the gate terminal of the NMOS transistor MN2. The source terminals of the NMOS transistors MN1 and MN2, as well as the drain terminal of the PMOS transistor MP1, are all connected to GND. The drain terminal of the NMOS transistor MN2 is connected to the gate terminal of the PMOS transistor MP1.

[0202] Depend on Figure 4 It can be seen that NMOS transistors MN1 and MN2 can form a current mirror. By cooperating with the constant current source I1 through the current mirror, the floating current can be limited.

[0203] Figure 4 The floating ground generation unit further includes a floating stabilization acceleration unit. This stabilization acceleration unit includes a constant current source I2, NMOS transistors MN0, MN3, and MN4. The drain terminals of NMOS transistors MN0 and MN3, the gate terminal of NMOS transistor MN3, and the gate terminal of NMOS transistor MN4 are all connected to the output terminal of the constant current source I2. The power supply terminal of the constant current source I2 is connected to the power supply VDD.

[0204] The gate of NMOS transistor MN0 is connected to the reference voltage. The source of NMOS transistor MN0 is connected to the drain of NMOS transistor MN4 and one end of capacitor C0, the drain of NMOS transistor MN2 and the gate of PMOS transistor MP1. The other end of capacitor C0 is connected to the power supply VDD. The corresponding source terminals of NMOS transistors MN3 and MN4 are connected to GND.

[0205] Depend on Figure 4 As explained above, NMOS transistors MN3 and NM4 form a current mirror. When the floating ground is lower than the reference voltage by one NMOS threshold voltage, NMOS transistor MN0 can be driven to conduct under both the reference voltage and the floating ground to quickly pull up the floating ground. The constant current source I2, in conjunction with the current mirror formed by NMOS transistors MN3 and NM4, can rapidly accelerate the recovery of the floating ground and maintain it in line with the reference voltage. Furthermore, current limiting after stable acceleration can be achieved through the stabilization acceleration unit. It can be understood that when the floating ground recovers rapidly, current limiting of the push current can also be achieved. When the floating ground is not lower than the reference voltage by one NMOS threshold voltage, NMOS transistor MN0 is turned off, thereby further improving the stability of the floating ground and thus improving the stability and reliability of the entire charge pump device.

[0206] In one embodiment of the present invention, the main charge pump includes a main pump main circuit, a main pump pre-charge power supply, and a main pump compensation power supply, wherein,

[0207] The main pump's main circuit and pre-charge power supply operate under global power supply conditions, while the main pump's compensation power supply operates under slave pump pre-boost conditions.

[0208] The main pump main circuit includes two main pump unit branches, and each main pump unit branch is adapted to and connected to the main pump pre-charge power supply and the main pump compensation power supply.

[0209] When generating the target voltage for the main pump, each main pump unit branch is configured to alternately be in the main branch pre-charge state and the main branch output state. The operating states of the two main pump unit branches are non-overlapping, and the target voltage for the main pump is output based on the main pump unit branch in the main branch output state.

[0210] For any main pump unit branch that is in the main branch pre-charge state, the main pump unit branch is pre-charged using the main pump pre-charge power supply. After that, the main pump unit branch is configured to enter the main branch output state from the main branch pre-charge state.

[0211] For any main pump unit branch in the main branch output state, a main pump compensation current is provided to the main pump unit branch using the main pump compensation power supply. When the slave pump target voltage is formed based on the slave pump pre-boost and the main pump compensation current matches the operational amplifier load current, the output of the main pump unit branch can reach the main pump target voltage.

[0212] Figure 1 The diagram illustrates an embodiment of a main charge pump unit. As shown, in addition to the main charge pump, the main charge pump unit may also include a delay circuit, a main clock generation circuit, and a main level conversion circuit. As shown, both the main charge pump unit and the slave charge pump unit operate under the same reference clock. The delay circuit allows the operation of the main charge pump unit and the slave charge pump unit to be staggered, and enables the slave charge pump to provide a stable target voltage. The delay circuit can adopt existing forms, such as forming a delayed clock, which can be a delay of 1 / 4 clock cycle from the reference clock.

[0213] Figure 7 The diagram shows a circuit schematic of one embodiment of the main charge pump. As can be seen from the diagram, the working principle of the main charge pump is basically similar to that of the slave charge pump described above. Therefore... Figure 5 In this circuit, constant current source I5 serves as the power supply for the main pump compensation point, and constant current source I6 serves as the pre-charge power supply for the main pump. Unlike the aforementioned slave charge pump, the power supply terminal of constant current source I5 is connected to the voltage output terminal of the slave charge pump. That is, constant current source I5 operates under the pre-boost voltage of the slave pump, while constant current source I6 still operates under the global voltage.

[0214] For the two main pump unit branches within the main pump circuit, referring to the above description of the charge pump, capacitor C11, PMOS transistor MP14, NMOS transistor MN14, MMOS transistor M15, capacitor C13, PMOS transistor MP15, PMOS transistor MP19, and PMOS transistor MP20 can form one main pump unit branch. Capacitor C10, PMOS transistor MP16, NMOS transistor MN16, NMOS transistor MN17, PMOS transistor MP17, capacitor C12, PMOS transistor MP18, and PMOS transistor MP21 can form the other main pump unit branch. Furthermore, the source terminals of PMOS transistor MP21 and MP20 are interconnected to form the voltage output terminal of the main charge pump. The voltage output terminal of the main charge pump is also connected to one end of capacitor C9, the cathode of diode D2, and one end of resistor R5. The other end of capacitor C9 and the anode of diode D2 are connected to the power supply VDD, and the other end of resistor R5 is connected to... Figure 1 The main level conversion circuit is connected, and the voltage VHz is the main pump feedback voltage. For the main pump feedback voltage, please refer to the above description of the slave pump feedback voltage. Figure 7 In this context, Vout is the main pump target voltage output by the low-noise charge pump device of this invention.

[0215] Depend on Figure 7 It can be seen that the corresponding source terminals of NMOS transistors MN14 and MN15 are connected to floating ground, and the corresponding gate terminals of NMOS transistors MN14 and MN15 are connected to the clock signal CKAz. The drain terminal of PMOS transistor MP14 is connected to one end of capacitor C11 and the drain terminal of NMOS transistor MN14. The source terminal of PMOS transistor MP14 is connected to the power supply VDD. The other end of capacitor C11 is connected to the drain terminals of NMOS transistor MN15, PMOS transistor MP15, and one end of capacitor C13. The source terminal of PMOS transistor MP15 is connected to the output terminal of constant current source I5. The other end of capacitor C13 is connected to the drain terminals of PMOS transistor MP20 and PMOS transistor MP19. The source terminal of PMOS transistor MP19 is connected to the output terminal of constant current source I6.

[0216] The source terminals of NMOS transistors MN16 and MN17 are connected to floating ground. The gate terminals of NMOS transistors MN16 and MN17 are connected to the clock signal CKAzn. The drain terminal of PMOS transistor MP16 is connected to one end of capacitor C10 and the drain terminal of NMOS transistor MN16. The source terminal of PMOS transistor MP16 is connected to power supply VDD. The other end of capacitor C10 is connected to the drain terminals of NMOS transistor MN17, PMOS transistor MP17, and one end of capacitor C12. The source terminal of PMOS transistor MP17 is connected to the output terminal of constant current source I5. The other end of capacitor C12 is connected to the drain terminals of PMOS transistors MP18 and MP21. The source terminal of PMOS transistor MP18 is connected to the output terminal of constant current source I6.

[0217] Figure 7 In this configuration, the gate of PMOS transistor MP14 is connected to the clock signal CKCzn, PMOS transistor MP16 is connected to the clock signal CKCz, the gates of PMOS transistors MP15, MP18, and MP20 are all connected to the clock signal CKDzn, and the gates of PMOS transistors MP17, MP19, and MP21 are all connected to the clock signal CKDz.

[0218] It should be noted that the relationship between clock signals CKAz and CKAzn can be found in the descriptions of clock signals CKA and CKAn above. Similarly, the relationship between clock signals CKCz and CKCzn can be found in the descriptions of clock signals CKC and CKCn above. Likewise, the relationship between clock signals CKDz and CKDzn can be found in the descriptions of clock signals CKD and CKDn above.

[0219] In specific implementation, the clock signal CLK, after passing through the delay circuit, can generate a delayed clock CLK-d, which is then loaded into the master clock generation circuit. The master clock generation circuit can adopt the same form as the slave clock generation circuit mentioned above, thereby generating clock signals CKAz, CKAzn, CKBz, CKBzn, CKCz, and CKCzn. Among them, clock signals CKAz, CKAzn, CKCz, and CKCzn are directly loaded into the main charge pump, while clock signals CKBz and CKBzn are loaded into the main level conversion circuit to generate clock signals CKDz and CKDzn. The method and process of generating clock signals CKDz and CKDzn can be referred to the corresponding descriptions of clock signals CKD and CKDn mentioned above, and will not be repeated here.

[0220] Unlike the charge pump described above, since the constant current source I5 operates under the pre-boost voltage of the slave pump, and since the pre-boost voltage of the slave pump can be greater than the voltage value of the global power supply, in one embodiment of the present invention, the PMOS transistors MP15 and MP17 connected to the main pump compensation power supply are driven and controlled by the clock signals CKDzn and CKDz, respectively, so as to match the voltage state of the pre-boost voltage of the slave pump.

[0221] It should be understood that each main pump unit branch alternately enters the main branch pre-charge state and the main branch output state in sequence. The method of switching between the main branch pre-charge state and the main branch output state, as well as the method of switching between the main branch pre-charge state and the main branch output state, can be referred to the corresponding description of the charge pump mentioned above, and will not be repeated here.

[0222] It should be noted that the current output by constant current source I5 should be consistent with the current output by constant current source I3. In order to make the pre-charge setup time of capacitors C7 and C8 from the charge pump the same as the pre-charge setup time of capacitors C12 and C13 from the main charge pump, in one embodiment of the present invention, the current output by constant current source I6 can be consistent with the current output by constant current source I4. When the operational amplifier load current is consistent with the current output by constant current sources I5 and I3 during operation, a low-noise voltage can be provided for the CMOS operational amplifier.

[0223] As described above, the low-noise charge pump device of the present invention includes a slave charge pump unit and a main charge pump unit cascaded with the slave charge pump unit. When the slave charge pump unit and the main charge pump unit operate under the same reference clock, a delay circuit is used to delay the operation of the main charge pump after the operation of the slave charge pump. This allows for faster output of the slave target power supply from the slave charge pump and the main target voltage from the main charge pump, reducing the noise of the main target voltage and effectively increasing the boost amplitude of the main target voltage.

[0224] Simulation results show that, under the same output capacitance and load current conditions, the ripple of the main pump target voltage of the charge pump device of the present invention is reduced by half compared to a single-stage structure (such as a single slave charge pump unit / main charge pump unit). With a power supply VDD voltage of 5V, the main pump target voltage of the present invention can boost the power supply VDD voltage by more than 1.2V, reaching 6.2V, and the output ripple noise is less than 5mV, thus simultaneously meeting the requirements of low noise and high common-mode input for the input stage of a CMOS operational amplifier.

Claims

1. A low noise charge pump device suitable for CMOS operational amplifiers, characterized by, The low-noise charge pump device comprises: a slave charge pump unit comprising at least a slave charge pump, which works under a global power supply and loads a generated slave pump pre-boost to a master charge pump unit; the master charge pump unit comprising at least a master charge pump, which is adaptively connected with the slave charge pump to receive the slave pump pre-boost loaded by the slave charge pump, wherein, the master charge pump works under the slave pump pre-boost and the global power supply, after the master charge pump works under the slave pump pre-boost and the global power supply, the slave pump pre-boost generated by the slave charge pump gradually enters a stable state, and the slave pump pre-boost in the stable state is configured as a slave pump target voltage; based on the slave pump target voltage and the global power supply, the master charge pump generates a low-noise and stable master pump target voltage; the voltage value of the master pump target voltage is greater than that of the slave pump target voltage, and the voltage value of the slave pump target voltage is greater than that of the global power supply; the slave charge pump comprises a slave pump main circuit, a slave pump pre-charge power supply and a slave pump compensation power supply which work under the global power supply, wherein, the slave pump main circuit comprises two slave pump unit branches, and each slave pump unit branch is adaptively connected with the slave pump pre-charge power supply and the slave pump compensation power supply; when generating the slave pump pre-boost, each slave pump unit branch is configured to alternately be in a slave branch pre-charge state and a slave branch output state, wherein the working states of the two slave pump unit branches are non-overlapping, and the slave pump unit branch in the slave branch output state outputs the slave pump pre-boost; for any slave pump unit branch in the slave branch pre-charge state, the slave pump unit branch is pre-charged by using the slave pump pre-charge power supply, and then the slave pump unit branch is configured to enter the slave branch output state from the slave branch pre-charge state; for any slave pump unit branch in the slave branch output state, the slave pump unit branch is provided with a slave pump compensation current by using the slave pump compensation power supply, wherein when the slave pump compensation current matches a master pump load current, the slave pump unit branch outputs the slave pump pre-boost which can be used as the slave pump target voltage, and the master pump load current is the working current of the master charge pump as a load of the slave pump unit branch.

2. The low noise charge pump device suitable for CMOS operational amplifier according to claim 1, characterized in that, for any slave pump unit branch, the slave pump unit branch comprises a slave pump first capacitor and a slave pump second capacitor, wherein, a first end of the slave pump first capacitor is connected with a drain end of a slave pump first NMOS tube and a drain end of a slave pump first PMOS tube, and a second end of the slave pump first capacitor is connected with a first end of the slave pump second capacitor, a drain end of a slave pump second NMOS tube and a drain end of a slave pump second PMOS tube; a source end of the slave pump first NMOS tube and a source end of the slave pump second NMOS tube are both connected with a floating ground, a source end of the slave pump first PMOS tube is connected with the global power supply, a source end of the slave pump second PMOS tube is connected with an output end of the slave pump compensation power supply, and a power supply end of the slave pump compensation power supply is connected with the global power supply; a second end of the slave pump second capacitor is connected with a drain end of a slave pump third PMOS tube and a drain end of a slave pump fourth PMOS tube, a source end of the slave pump third PMOS tube is connected with an output end of the slave pump pre-charge power supply, and a power supply end of the slave pump pre-charge power supply is connected with the global power supply. a gate terminal of the fourth PMOS transistor in the slave pumping unit branch is connected with a gate terminal of the third PMOS transistor in the other slave pumping unit branch, a source terminal of the fourth PMOS transistor in the two slave pumping unit branches is connected with each other, and is connected with a voltage output terminal of the slave charge pump, the voltage output terminal of the slave charge pump is connected with a global power supply through a slave charge pump output terminal capacitor, and the voltage output terminal of the slave charge pump is also connected with a cathode terminal of a slave charge pump diode, and an anode terminal of the slave charge pump diode is connected with the global power supply; when the slave pumping unit branch is in a slave branch pre-charging state, the first NMOS transistor, the second NMOS transistor and the third PMOS transistor in the slave pumping unit branch are configured to be in a conducting state to form a slave pumping pre-charging loop of slave pumping pre-charging power supply-slave pumping third PMOS transistor-slave pumping second capacitor-slave pumping second NMOS transistor, and the slave pumping second capacitor is pre-charged by using the slave pumping pre-charging loop; when the slave pumping unit branch is in a slave branch output state, the first PMOS transistor, the second PMOS transistor and the fourth PMOS transistor in the slave pumping unit branch are configured to be in a conducting state to form a slave pumping discharging loop of global power supply-slave pumping first PMOS transistor-slave pumping first capacitor-slave pumping second capacitor-slave pumping fourth PMOS transistor, and a slave pumping compensation current is injected into the slave pumping discharging loop by using a slave pumping compensation power supply.

3. The low noise charge pump suitable for CMOS operational amplifier according to claim 2, characterized in that, The slave charge pump unit further comprises a slave pumping control circuit for configuring the working state of the slave pumping unit branch in the slave charge pump, wherein, the two slave pumping unit branches are respectively configured as a first slave pumping unit branch and a second slave pumping unit branch, the slave pumping control circuit is adaptively connected with the first slave pumping unit branch and the second slave pumping unit branch to configure the corresponding working state of the first slave pumping unit branch and the second slave pumping unit branch, wherein, the slave pumping control circuit generates clock signals CKA, CKAn, CKC, CKCn, CKD and CKDn, wherein, the clock signal CKA is loaded to the corresponding gate terminals of the first NMOS transistor and the second NMOS transistor in the first slave pumping unit branch, and the clock signal CKAn is loaded to the corresponding gate terminals of the first NMOS transistor and the second NMOS transistor in the second slave pumping unit branch; the clock signal CKC is loaded to the corresponding gate terminals of the first PMOS transistor and the second PMOS transistor in the first slave pumping unit branch, and the clock signal CKCn is loaded to the corresponding gate terminals of the first PMOS transistor and the second PMOS transistor in the second slave pumping unit branch; the clock signal CKD is loaded to the gate terminal of the third PMOS transistor in the first slave pumping unit branch and the gate terminal of the fourth PMOS transistor in the second slave pumping unit branch, and the clock signal CKDn is loaded to the gate terminal of the fourth PMOS transistor in the first slave pumping unit branch and the gate terminal of the third PMOS transistor in the second slave pumping unit branch; when the slave pumping control circuit configures the corresponding working state of the first slave pumping unit branch and the second slave pumping unit branch, the configuration includes alternately performing first switching control and second switching control, wherein, when the first switching control is performed, then: When the first NMOS transistor and the second NMOS transistor in the first branch of the slave pump unit are configured to enter the off state from the on state based on the clock signal CKA, the third PMOS transistor in the first branch and the fourth PMOS transistor in the second branch are configured to enter the off state from the on state based on the clock signal CKD, and the third PMOS transistor in the second branch and the fourth PMOS transistor in the first branch are configured to enter the off state from the on state based on the clock signal CKDn; After the first NMOS transistor and the second NMOS transistor in the first branch of the slave pump unit are in the off state, the first NMOS transistor and the second NMOS transistor in the second branch of the slave pump unit are configured to enter the on state from the off state based on the clock signal CKAn, and before the first NMOS transistor in the second branch of the slave pump unit enters the on state from the off state, the first PMOS transistor and the second PMOS transistor in the second branch of the slave pump unit are configured to enter the off state from the on state based on the clock signal CKC, and after the first NMOS transistor in the second branch of the slave pump unit enters the on state, the first PMOS transistor and the second PMOS transistor in the first branch of the slave pump unit are configured to enter the on state from the off state based on the clock signal CKCn; When the first NMOS transistor and the second NMOS transistor in the first branch of the slave pump unit are configured to enter the off state from the on state based on the clock signal CKA, the third PMOS transistor in the first branch and the fourth PMOS transistor in the second branch are configured to enter the off state from the on state based on the clock signal CKD, and the third PMOS transistor in the second branch and the fourth PMOS transistor in the first branch are configured to enter the off state from the on state based on the clock signal CKDn; When the first NMOS transistor and the second NMOS transistor in the first branch of the slave pump unit are configured to enter the off state from the on state based on the clock signal CKA, the third PMOS transistor in the first branch and the fourth PMOS transistor in the second branch are configured to enter the off state from the on state based on the clock signal CKD, and the third PMOS transistor in the second branch and the fourth PMOS transistor in the first branch are configured to enter the off state from the on state based on the clock signal CKDn; When the first NMOS transistor and the second NMOS transistor in the first branch of the slave pump unit are configured to enter the off state from the on state based on the clock signal CKA, the third PMOS transistor in the first branch and the fourth PMOS transistor in the second branch are configured to enter the off state from the on state based on the clock signal CKD, and the third PMOS transistor in the second branch and the fourth PMOS transistor in the first branch are configured to enter the off state from the on state based on the clock signal CKDn; 4. The low noise charge pump suitable for CMOS operational amplifier according to claim 3, characterized in that, The slave pump control circuit comprises a slave clock generation circuit and a slave level conversion circuit connected to the slave clock generation circuit, wherein The slave clock generation circuit generates multiple-phase non-overlapping clock signals CKA, CKAn, CKB, CKBn, CKC and CKCn based on a reference clock CLK, The slave clock generation circuit generates multiple-phase non-overlapping clock signals CKA, CKAn, CKB, CKBn, CKC and CKCn based on a reference clock CLK, The clock signal CKA, the clock signal CKAn, the clock signal CKC and the clock signal CKCn are directly loaded to the slave charge pump; The clock signal CKB and the clock signal CKBn are loaded to the slave level conversion circuit, and the slave level conversion circuit also receives the slave pump feedback voltage fed back from the connected slave charge pump, wherein, The slave pump feedback voltage is received by the slave level conversion circuit through the slave pump feedback connection node; When the clock signal CKB and the clock signal CKBn occur rising edge jump, the slave level conversion circuit raises the slave node voltage value of the slave pump feedback connection node until the slave node voltage value at the slave pump feedback connection node is higher than the slave pump pre-boost voltage output by the slave charge pump; Based on the clock signal CKB and the slave node voltage value, the slave level conversion circuit generates the clock signal CKD, and the level state of the clock signal CKD is adapted to the voltage state of the slave pump pre-boost; Based on the clock signal CKBn and the slave node voltage value, the slave level conversion circuit generates the clock signal CKDn, and the level state of the clock signal CKDn is adapted to the voltage state of the slave pump pre-boost.

5. The low noise charge pump suitable for CMOS operational amplifier according to claim 4, characterized in that, The slave level conversion circuit comprises a conversion generation main unit and a conversion coupling unit connected with the conversion generation main unit, wherein, The conversion generation main unit comprises two conversion generation sub-units, each conversion generation sub-unit is connected with the conversion coupling unit, and the slave pump feedback connection node is connected with the conversion coupling unit and each conversion generation sub-unit; The two conversion generation sub-units respectively receive the clock signal CKB and the clock signal CKBn; When the clock signal CKB or the clock signal CKBn occurs rising edge jump, the two conversion generation sub-units cooperate with the conversion coupling unit to raise and maintain the slave node voltage value at the slave pump feedback connection node; Based on the clock signal CKB and the slave node voltage value, the conversion generation sub-unit receiving the clock signal CKB generates the clock signal CKD synchronized with the clock signal CKB, Based on the clock signal CKBn and the slave node voltage value, the conversion generation sub-unit receiving the clock signal CKBn generates the clock signal CKDn synchronized with the clock signal CKBn.

6. The low noise charge pump suitable for CMOS operational amplifier according to claim 5, characterized in that, The conversion generation sub-unit comprises a conversion generation first NMOS tube; The source end of the conversion generation first NMOS tube is connected with the floating ground, the gate end of the conversion generation first NMOS tube is connected with the clock signal CKB or the clock signal CKBn, and the gate end of the conversion generation first NMOS tube is also connected with the first end of the conversion generation capacitor, the second end of the conversion generation capacitor is connected with the source end of the conversion generation second NMOS tube, the gate end of the conversion generation PMOS tube and the conversion coupling unit, The drain end of the conversion generation first NMOS tube is connected with the clock generation sub-unit, the gate end of the conversion generation second NMOS tube and the drain end of the conversion generation PMOS tube, the power negative end of the clock generation sub-unit is connected with the floating ground, the power positive end of the clock generation sub-unit is connected with the slave pump feedback connection node, and the clock signal CKD or the clock signal CKDn can be generated through the clock generation sub-unit; The drain terminal of the second NMOS transistor is connected to the resistance and the global power supply through the conversion, and the source terminal of the PMOS transistor is connected to the feedback connection node of the slave pump; When the clock signal CKB or the clock signal CKBn has a rising edge jump, the charge on the conversion capacitor is transmitted to the feedback connection node of the slave pump through the conversion coupling unit to raise the feedback voltage of the slave pump at the feedback connection node of the slave pump.

7. The low noise charge pump suitable for CMOS operational amplifier according to claim 5, characterized in that, The conversion coupling unit includes a conversion coupling first PMOS transistor, a conversion coupling second PMOS transistor, and a coupling holding capacitor, wherein, The source terminal of the conversion coupling first PMOS transistor, the gate terminal of the second PMOS transistor generated by conversion, the second terminal of the conversion capacitor in the conversion generation subunit, the gate terminal of the PMOS transistor generated by conversion, and the source terminal of the second NMOS transistor generated by conversion are connected; The gate terminal of the conversion coupling first PMOS transistor, the source terminal of the conversion coupling second PMOS transistor, the second terminal of the conversion capacitor in the other conversion generation subunit, the gate terminal of the PMOS transistor generated by conversion, and the source terminal of the second NMOS transistor generated by conversion are connected; The drain terminal of the conversion coupling first PMOS transistor, the drain terminal of the conversion coupling second PMOS transistor, the first terminal of the coupling holding capacitor, the cathode terminal of the conversion diode, and the feedback connection node of the slave pump are connected, the second terminal of the coupling holding capacitor is connected to the global power supply, and the anode terminal of the conversion diode is connected to the global power supply.

8. A low noise charge pump device suitable for a CMOS operational amplifier according to any one of claims 2 to 7, characterized in that, The floating ground is provided by a floating ground generation unit, wherein The floating ground generation unit includes a floating ground main circuit and a floating ground current limiting circuit connected to the floating ground main circuit; Based on the reference voltage, the floating ground main circuit generates a floating ground corresponding to the reference voltage; The floating ground current limiting circuit limits the current when the floating ground main circuit is working.

9. A low noise charge pump device suitable for CMOS operational amplifiers according to any one of claims 1 to 7, characterized in that, The main charge pump includes a main pump main circuit, a main pump pre-charge power supply, and a main pump compensation power supply, wherein The main pump main circuit and the main pump pre-charge power supply work under the global power supply, and the main pump compensation power supply works under the slave pump pre-boosting, The main pump main circuit includes two main pump unit branches, and each main pump unit branch is connected to the main pump pre-charge power supply and the main pump compensation power supply. When generating the main pump target voltage, each main pump unit branch is configured to alternately be in a main branch pre-charge state and a main branch output state, wherein the working states of the two main pump unit branches are non-overlapping, and the main pump target voltage is output based on the main pump unit branch in the main branch output state; For any main pump unit branch in the main branch pre-charge state, the main pump pre-charge power supply is used to pre-charge the main pump unit branch, and then the main pump unit branch is configured to enter the main branch output state from the main branch pre-charge state; For any main pump unit branch in the main branch output state, the main pump compensation power supply is used to provide a main pump compensation current to the main pump unit branch, wherein when the slave pump target voltage is formed based on the slave pump pre-boosting, and the main pump compensation current matches the operational amplifier load current, the main pump unit branch outputs the main pump target voltage.

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