Non-volatile two-terminal memory device and memory system
By shorting adjacent bit lines and sharing source lines in the non-volatile end-to-end memory module, the problems of increased line resistance and parasitic capacitance are solved, realizing a high-density integrated and low-cost non-volatile memory design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INNOSTAR SEMICON (SHANGHAI) CO LTD
- Filing Date
- 2025-08-05
- Publication Date
- 2026-07-24
AI Technical Summary
When increasing storage capacity, existing non-volatile end-point memory faces problems such as excessive line resistance, increased parasitic capacitance and resistance, which makes high-density chip integration difficult and increases production costs.
By shorting adjacent bit lines in the non-volatile end-to-end memory module, the bit line width is increased, the bit line resistance and parasitic capacitance are reduced, signal integrity is optimized, and the source line is shared to reduce the use of metal layers.
It reduces bit line resistance and power consumption, improves signal speed and integration, reduces production costs, reduces crosstalk and leakage problems, and enhances the reliability and density of memory devices.
Smart Images
Figure CN121191552B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a non-volatile two-terminal memory device and memory system. Background Technology
[0002] Semiconductor memory devices can be classified into volatile memory devices and non-volatile memory devices. When power is interrupted, volatile memory devices will lose the stored data, while non-volatile memory devices will not lose the stored data.
[0003] Unlike non-volatile three-terminal memories (such as NOR flash or NAND flash), which control the conductivity between the other two terminals by controlling the gate terminal, non-volatile two-terminal memories generally include a first electrode, a second electrode, and a switching layer placed between the first electrode and the second electrode. Non-volatile two-terminal memories control the conductivity state of the switching layer by applying different electrical signals to the two electrode terminals, thereby forming different conductivity states between the two electrode terminals. Various non-volatile two-terminal memory technologies (e.g., resistive switching memory, magnetoresistive memory, ferroelectric memory, phase-change memory, conductive bridged memory) have compelling evidence to demonstrate significant advantages over competing technologies in the semiconductor electronics industry.
[0004] Taking resistive random access memory (RRAM) as an example, in existing technologies, data can be written, read, and stored using RRAM. RRAM has advantages such as high density, low power consumption, and fast read / write speeds, thus it has broad application prospects in the field of data storage.
[0005] As the demand for storage capacity of non-volatile two-dimensional memory increases, traditional non-volatile two-dimensional memory is gradually facing the physical limits of size reduction. Improving storage capacity while reducing production costs has become a major problem that needs to be solved.
[0006] In existing technologies, chip density and storage capacity are increased by increasing the number of storage cells on each bit line in non-volatile end-to-end memory. However, as the bit line length increases, so do the parasitic capacitance and resistance. Excessive line resistance also increases the need for metal layers in the layout, which is detrimental to high-density chip integration. Summary of the Invention
[0007] The present invention aims to at least solve one of the technical problems existing in the prior art. Therefore, one object of the present invention is to provide a non-volatile two-terminal storage device that can reduce line resistance.
[0008] Another object of the present invention is to provide a storage system.
[0009] According to an embodiment of the present invention, a non-volatile two-ended memory device includes: a non-volatile two-ended memory array, comprising a plurality of non-volatile two-ended memory modules, each of the non-volatile two-ended memory modules including at least two non-volatile two-ended memory cells; each non-volatile two-ended memory cell includes a selector and a non-volatile two-ended memory connected in series with the selector, a first terminal of the selector being electrically connected to a second terminal of the non-volatile two-ended memory, the second terminal of the selector being electrically connected to a source line, and a first terminal of the non-volatile two-ended memory being electrically connected to a bit line; all non-volatile two-ended memory cells in the non-volatile two-ended memory module share a source line, and the bit lines corresponding to two adjacent non-volatile two-ended memory modules are shorted to each other at least two points.
[0010] Therefore, by shorting the bit lines of two adjacent non-volatile two-ended memory modules, when a driving voltage is applied to the target non-volatile two-ended memory cell, the width of the bit lines can be increased. With increased bit line width, the bit line resistance can be reduced, the bit line signal delay can be reduced, parasitic capacitance and inductance can be reduced, signal integrity can be optimized, power consumption and thermal effects can be reduced, and the freedom of wiring design can be increased. On the other hand, the use of metal layers on the non-volatile two-ended memory device can be reduced, which is conducive to reducing production costs and improving the integration of non-volatile two-ended memory cells.
[0011] According to some embodiments of the present invention, each of the non-volatile two-ended storage modules includes two non-volatile two-ended storage cells, and the two non-volatile two-ended storage cells share a source line.
[0012] According to some embodiments of the present invention, two adjacent non-volatile two-terminal memory modules are designated as a first non-volatile two-terminal memory module and a second non-volatile two-terminal memory module, respectively. In the first non-volatile two-terminal memory module, the bit line electrically connected to the non-volatile two-terminal memory adjacent to the second non-volatile two-terminal memory module is designated as a first bit line. In the second non-volatile two-terminal memory module, the bit line electrically connected to the non-volatile two-terminal memory adjacent to the first non-volatile two-terminal memory module is designated as a second bit line. The system also includes jumpers, which include at least a first jumper and a second jumper. The first jumper is connected between a first end in the length direction of the first bit line and a first end in the length direction of the second bit line, and the second jumper is connected between a second end in the length direction of the first bit line and a second end in the length direction of the second bit line.
[0013] According to some embodiments of the present invention, the jumper wire further includes a third jumper wire, which is connected between the first bit wire and the second bit wire, and the third jumper wire is spaced apart from both ends of the first bit wire and the second bit wire in the length direction.
[0014] According to some embodiments of the present invention, one end of the third shorting wire is connected to the middle part of the first bit line in the length direction, and the other end of the third shorting wire is connected to the middle part of the second bit line in the length direction.
[0015] According to some embodiments of the present invention, there are multiple third shorting wires, and the multiple third shorting wires are arranged at intervals.
[0016] According to some embodiments of the present invention, the selector is a MOS transistor.
[0017] According to some embodiments of the present invention, the non-volatile two-terminal memory device further includes a word line, a first terminal of the selector being a first non-gate of the MOS transistor, the first non-gate of the MOS transistor being electrically connected to a second terminal of the non-volatile two-terminal memory, a second terminal of the selector being a second non-gate of the MOS transistor, the second non-gate of the MOS transistor being electrically connected to the source line, and the MOS transistor also having a gate, the gate being electrically connected to the word line.
[0018] According to some embodiments of the present invention, the selector is a two-terminal switching device.
[0019] The storage system according to an embodiment of the present invention includes the non-volatile dual-ended storage device described above.
[0020] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0021] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a partial schematic diagram of a non-volatile two-ended memory array according to an embodiment of the present invention; Figure 2 This is a partial schematic diagram of a non-volatile two-ended memory array according to some embodiments of the present invention; Figure 3 This is a partial schematic diagram of a non-volatile two-ended memory array according to other embodiments of the present invention; Figure 4 This is a partial schematic diagram of a non-volatile dual-ended memory array according to some embodiments of the present invention.
[0022] Figure label: 100. Non-volatile two-ended storage array; 10. Non-volatile two-ended memory module; 11. First non-volatile two-ended memory module; 12. Second non-volatile two-ended memory module; 111. Non-volatile two-ended memory cell; 1111. Selector; 11111. Drain; 11112. Source; 11113. Gate; 1112. Non-volatile two-ended memory; 20. Source line; 30. Position line; 31. First position line; 32. Second position line; 40. Jumper wire; 41. First jumper wire; 42. Second jumper wire; 43. Third jumper wire; 50. Character line. Detailed Implementation
[0023] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.
[0024] The following is for reference. Figures 1-4 A non-volatile two-terminal memory device is described according to embodiments of the present invention. In these embodiments, the non-volatile two-terminal memory device includes, but is not limited to, resistive random access memory (RRAM) and phase-change memory (PCM). This non-volatile two-terminal memory device can be applied to a storage system.
[0025] Combination Figures 1-4 As shown, the non-volatile two-end storage device according to an embodiment of the present invention may mainly include a non-volatile two-end storage array 100, wherein the non-volatile two-end storage array 100 includes a plurality of non-volatile two-end storage modules 10, each non-volatile two-end storage module 10 includes at least two non-volatile two-end units, and the non-volatile two-end storage unit 111 includes a selector 1111 and a non-volatile two-end memory 1112 connected in series with the selector 1111. The selector 1111 can be selectively turned on under different voltage conditions to control the non-volatile two-end memory 1112 to perform read and write operations respectively.
[0026] Furthermore, the first terminal of the selector 1111 is electrically connected to the second terminal of the non-volatile two-ended memory 1112, the second terminal of the selector 1111 is electrically connected to the source line 20, the first terminal of the non-volatile two-ended memory 1112 is electrically connected to the bit line 30, and the third terminal of the selector 1111 is electrically connected to the word line 50.
[0027] In embodiments of the present invention, the source line 20 typically serves as a primary current path for the operation of the non-volatile two-dimensional memory cell 111. During write and read operations, current can be supplied or extracted to the non-volatile two-dimensional memory device via the source line 20 to change or detect the resistance state of the non-volatile two-dimensional memory device. Furthermore, the source line 20 allows for precise control of the voltage applied to the non-volatile two-dimensional memory cell 111; appropriate voltage management ensures accurate data writing and reliable data reading.
[0028] In embodiments of the present invention, bit line 30 and word line 50 are important components of the non-volatile two-ended memory array 100, and can be used to select a target non-volatile two-ended memory cell 111 for read and write operations.
[0029] With this configuration, when the selector 1111 is connected to the non-volatile two-ended memory 1112, one end of the selector 1111 is electrically connected to the word line 50, and one end of the non-volatile two-ended memory 1112 is electrically connected to the bit line 30. In this way, voltage can be applied to the non-volatile two-ended memory cell 111 through the word line 50 and the bit line 30, and the voltage on the non-volatile two-ended memory cell 111 can be controlled through the source line 20 to control the non-volatile two-ended memory 1112 to perform different operations.
[0030] Furthermore, all non-volatile two-dimensional storage cells 111 in the non-volatile two-dimensional storage module 10 share a single source line 20. That is, the current of all non-volatile two-dimensional storage cells 111 in a non-volatile two-dimensional storage module 10 flows out through the same source line 20. This can significantly reduce the number of source lines 20 in the non-volatile two-dimensional storage module 10 and reduce the space occupied by the source lines 20 in the non-volatile two-dimensional storage module 10, thereby improving the design integration of the non-volatile two-dimensional storage module 10. On the other hand, the shared source line 20 design can reduce the consumption of metal required for the source line 20, thereby reducing the manufacturing cost of the non-volatile two-dimensional storage module 10.
[0031] Furthermore, in an embodiment of the present invention, the bit lines 30 corresponding to two adjacent non-volatile two-terminal storage modules 10 are shorted to each other at least in two places. With this configuration, when a driving voltage is applied to the target non-volatile two-terminal storage cell 111, it is equivalent to increasing the width of the bit lines 30, thereby reducing the resistance of the bit lines 30.
[0032] In embodiments of the present invention, increasing the width of bit line 30 can reduce the resistance of bit line 30 conductors and reduce the signal delay of bit line 30. According to existing technology, the resistance of bit line 30 is inversely proportional to its linewidth, specifically: bit line 30 conductor resistance = bit line 30 material resistivity × bit line 30 length / bit line 30 conductor cross-sectional area. Therefore, increasing the linewidth of bit line 30 can increase the conductor cross-sectional area, significantly reducing the conductor resistance. This, in turn, reduces voltage drop and power consumption during signal transmission, and reduces the risk of read / write anomalies in the design of the large-capacity non-volatile two-ended storage module 10 due to the inability to obtain the target voltage at the far end of the non-volatile two-ended storage unit 111 during read / write operations. This reduces the signal delay of bit line 30, increases the speed of bit line 30 electrical signals, and provides the non-volatile two-ended storage module 10 with higher read / write speeds or higher frequency read / write operations per unit time.
[0033] Furthermore, increasing the width of bit line 30 can reduce parasitic capacitance and inductance, optimizing signal integrity. In the prior art, high-frequency circuits are often used in non-volatile memories, where the parasitic capacitance and inductance of the bit line 30 conductors can significantly affect signal integrity. In this embodiment of the invention, by increasing the conductor width of bit line 30, parasitic capacitance can be reduced, thereby reducing the overall impedance of bit line 30 and reducing the attenuation and distortion of the high-frequency electrical signals transmitted by bit line 30. In addition, a wider bit line 30 conductor can reduce distributed inductance, thereby reducing high-frequency noise and crosstalk, and improving the stability and reliability of the bit line 30 signal.
[0034] Furthermore, increasing the width of bit line 30 can reduce power consumption and thermal effects. In the prior art, according to P=I×I×R, in the embodiments of the present invention, after increasing the width of bit line 30 and reducing the line resistance of bit line 30, the power consumption loss when current passes through bit line 30 can be reduced, thereby alleviating the problem of local temperature rise caused by power consumption loss, and further improving the reliability of non-volatile two-terminal memory module 10, where P is the power consumption loss when current passes through the wire, I is the current passing through the wire, and R is the line resistance of the wire.
[0035] Furthermore, increasing the width of the bit line 30 can improve the flexibility of routing design on the non-volatile two-ended memory module 10. Since the bit lines 30 of two adjacent non-volatile two-ended memory cells 111 are shorted, the width of a single bit line 30 can be further compressed under the premise that the width of the bit line 30 of the target non-volatile two-ended memory cell 111 is fixed. This allows the bit line 30 to occupy less routing space in the non-volatile two-ended memory module 10, improving the flexibility of routing design. This is beneficial for the higher integration design of the non-volatile two-ended memory module 10.
[0036] In addition, by shorting at least two points on the bit lines 30 corresponding to two adjacent non-volatile two-ended memory modules 10, it can be ensured that the voltages of the non-target non-volatile two-ended memory cells 111 adjacent to the target non-volatile two-ended memory cell 111 are at the same bias voltage. This can avoid crosstalk and leakage problems in the non-target non-volatile two-ended memory cells 111 adjacent to the target non-volatile two-ended memory cell 111 in the non-volatile two-ended memory array 100.
[0037] Combination Figures 2-4 As shown, each non-volatile two-dimensional storage module 10 includes two non-volatile two-dimensional storage cells 111. The two non-volatile two-dimensional storage cells 111 share a source line 20. That is, the current of the two non-volatile two-dimensional storage cells 111 in the same non-volatile two-dimensional storage module 10 flows out through the same source line 20. With this configuration, in a non-volatile two-dimensional storage module 10, the two non-volatile two-dimensional storage cells 111 can be connected to the power supply through a source line 20. In this way, more non-volatile two-dimensional storage cells 111 can be powered through a single source line 20. Under the combined action of the word line 50 and the bit line 30, the target non-volatile two-dimensional storage cell 111 can be operated. This not only reduces the line resistance in the non-volatile two-dimensional storage device, but also ensures the operational accuracy of the non-volatile two-dimensional storage device.
[0038] Combination Figures 1-4 As shown, two adjacent non-volatile two-ended memory modules 10 are designated as a first non-volatile two-ended memory module 11 and a second non-volatile two-ended memory module 12, respectively. In the first non-volatile two-ended memory module 11, the bit line 30 electrically connected to the non-volatile two-ended memory 1112 adjacent to the second non-volatile two-ended memory module 12 is designated as the first bit line 31. In the second non-volatile two-ended memory module 12, the bit line 30 electrically connected to the non-volatile two-ended memory 1112 adjacent to the first non-volatile two-ended memory module 11 is designated as the second bit line 32.
[0039] According to some embodiments of the present invention, in combination Figures 2-4As shown, the non-volatile two-terminal storage device also includes a jumper wire 40, which includes at least a first jumper wire 41 and a second jumper wire 42. The first jumper wire 41 is connected between the first end of the first bit line 31 in the length direction and the first end of the second bit line 32 in the length direction. The second jumper wire 42 is connected between the second end of the first bit line 31 in the length direction and the second end of the second bit line 32 in the length direction. This not only allows the first bit line 31, the first jumper wire 41, the second bit line 32 and the second jumper wire 42 to form a loop, but also ensures that the target non-volatile two-terminal storage cell 111 is connected to the target non-volatile two-terminal storage cell 111. The current on the adjacent non-target non-volatile two-ended memory cells 111 all flows to the source line 20. Furthermore, the first bit line 31 and the second bit line 32 can be directly connected to increase the width of the bit line 30, reduce the resistance of the bit line 30 in the non-volatile two-ended memory device, and thus reduce the use of metal layers in the non-volatile two-ended memory device. This can reduce the layout area in the non-volatile two-ended memory device, increase the storage density of the non-volatile two-ended memory device, and reduce the manufacturing cost of the non-volatile two-ended memory device. This can provide a reference for the design and manufacturing of large-scale high-density low-power memory systems.
[0040] According to other embodiments of the present invention, in combination Figure 4 As shown, the shorting wire 40 also includes a third shorting wire 43, which is connected between the first bit line 31 and the second bit line 32. The two ends of the third shorting wire 43 and the first bit line 31 and the second bit line 32 in the length direction are spaced apart from each other, which can further shorten the distance that the current travels from the bit line 30 to the source line 20 after the first bit line 31 and the second bit line 32 are shorted.
[0041] This configuration further reduces the resistance of bit line 30 and decreases the signal delay of bit line 30. Specifically, the resistance of bit line 30 is calculated as: bit line 30 conductor resistance = bit line 30 material resistivity × bit line 30 length / bit line 30 conductor cross-sectional area. Therefore, by shortening the length through which current flows through bit line 30, the resistance of bit line 30 can be further reduced. This, in turn, further reduces the voltage drop and power consumption during signal transmission via bit line 30. This reduces the risk of read / write anomalies caused by the inability of the remote non-volatile two-ended storage cell 111 to obtain the target voltage during read / write operations in the design of the large-capacity non-volatile two-ended storage module 10. It also reduces the signal delay of bit line 30, increases the speed of the bit line 30 electrical signal, and provides the non-volatile two-ended storage module 10 with higher read / write speeds or higher frequency read / write operations per unit time.
[0042] Furthermore, shortening the distance the current travels from bit line 30 to source line 20 after the first bit line 31 and the second bit line 32 are shorted can further reduce parasitic capacitance and inductance, optimizing signal integrity. In this embodiment of the invention, by increasing the conductor width of bit line 30, parasitic capacitance can be reduced, and the distance the current travels through bit line 30 can be further shortened, thereby further reducing the overall impedance of bit line 30, and further reducing the attenuation and distortion of the high-frequency electrical signal transmitted by bit line 30. In addition, a wider and shorter conductor of bit line 30 can reduce distributed inductance, thereby reducing high-frequency noise and crosstalk, and improving the stability and reliability of the bit line 30 signal.
[0043] Furthermore, shortening the distance the current travels from bit line 30 to source line 20 after the first bit line 31 and the second bit line 32 are shorted can further reduce power consumption and thermal effects. In this embodiment of the invention, by reducing the length and increasing the width of bit line 30, the line resistance of bit line 30 can be further reduced, thereby reducing power loss when current passes through bit line 30. This alleviates the problem of localized temperature rise caused by power loss and further improves the reliability of the non-volatile two-terminal memory module 10.
[0044] Furthermore, shortening the distance the current travels from bit line 30 to source line 20 after the first bit line 31 and the second bit line 32 are shorted can further improve the freedom of wiring design on the non-volatile two-ended memory module 10. Since the bit lines 30 of two adjacent non-volatile two-ended memory cells 111 are shorted, the width of a single bit line 30 can be further compressed under the premise that the width of the bit line 30 of the target non-volatile two-ended memory cell 111 is fixed, and the distance between the bit lines 30 in the non-volatile two-ended memory cell 111 is shorter, so that the bit lines 30 occupy less wiring space in the non-volatile two-ended memory module 10, improving the freedom of wiring design. This is beneficial for the higher integration design of the non-volatile two-ended memory module 10.
[0045] In embodiments of the present invention, combined with Figure 4 As shown, one end of the third jumper wire 43 is connected to the middle of the first bit line 31 along its length, and the other end of the third jumper wire 43 is connected to the middle of the second bit line 32 along its length. Specifically, the middle of the first bit line 31 along its length is a position equidistant from both the first and second ends of the first bit line 31 along its length, and the middle of the second bit line 32 along its length is a position equidistant from both the first and second ends of the second bit line 32 along its length.
[0046] This configuration ensures that the connection position of the third shorting wire 43 to the first wire 31 is equidistant from the first end and the second end of the first wire 31 along the length of the first wire 31, and also ensures that the connection position of the third shorting wire 43 to the second wire 32 is equidistant from the first end and the second end of the second wire 32 along the length of the second wire 32.
[0047] Thus, when current flows into the non-volatile two-terminal storage module 10 from the first end of the first bit line 31 and the first end of the second bit line 32, the current on the second bit line 32 can flow to the first bit line 31 through the third jumper wire 43, and similarly, the current on the first bit line 31 can also flow to the second bit line 32 through the third jumper wire 43.
[0048] Furthermore, when current flows into the non-volatile two-terminal storage module 10 from the second end of the first bit line 31 and the second end of the second bit line 32, the current on the second bit line 32 can flow to the first bit line 31 through the third jumper wire 43, and the current on the first bit line 31 can also flow to the second bit line 32 through the third jumper wire 43.
[0049] This configuration not only helps reduce the line resistance in the non-volatile two-way memory module 10, but also ensures that the resistance of the bit line 30 encountered when current flows into the non-volatile two-way memory module 10 from the second end of the first bit line 31 and the second end of the second bit line 32 is equal to the resistance of the bit line 30 encountered when current flows into the non-volatile two-way memory module 10 from the first end of the first bit line 31 and the first end of the second bit line 32. This prevents a part of the circuit in the non-volatile two-way memory device from being short-circuited, thus protecting the circuit safety of the non-volatile two-way memory device.
[0050] In embodiments of the present invention, combined with Figure 4 As shown, there are multiple third shorting wires 43, which are spaced apart from each other. Specifically, multiple spaced third shorting wires 43 are provided between the first bit line 31 and the second bit line 32. This allows for the formation of shorter bit line 30 loops in the non-volatile two-terminal storage module 10, thereby shortening the current flow distance on the bit line 30 and further reducing the line resistance of the non-volatile two-terminal storage device.
[0051] Combination Figures 2-4As shown, the non-volatile two-ended memory device includes a word line 50, a selector 1111 which is a MOS transistor, a first terminal of the selector 1111 which is the first non-gate 11113 of the MOS transistor, the first non-gate 11113 of the MOS transistor is electrically connected to the second terminal of the non-volatile two-ended memory 1112, the second terminal of the selector 1111 which is the second non-gate 11113 of the MOS transistor, the second non-gate 11113 of the MOS transistor is electrically connected to the source line 20, and the MOS transistor also has a gate 11113 which is electrically connected to the word line 50.
[0052] Specifically, in an embodiment of the present invention, one of the first non-gate 11113 and the second non-gate 11113 of the MOS transistor is a drain 11111, and the other is a source 11112. The drain 11111 of the MOS transistor is electrically connected to the second terminal of the non-volatile two-ended memory 1112, and the source 11112 of the MOS transistor is electrically connected to the source line 20. In an embodiment of the present invention, the target non-volatile two-ended memory cell 111 is selected by turning on and off the word line 50 and the bit line 30, and read / write operations are performed in conjunction with the source line 20 where the target non-volatile two-ended memory cell 111 is located.
[0053] According to an embodiment of the present invention, the selector 1111 is a two-terminal switching device, which is used to control the non-volatile two-terminal memory 1112 to perform read and write operations. In embodiments of the present invention, the selector 1111 includes, but is not limited to, diodes, transistors, and selector transistors.
[0054] According to an embodiment of the present invention, a non-volatile two-ended storage device can be applied to a storage system. By shorting the bit lines 30 of adjacent non-volatile two-ended storage cells 111 with a jumper wire 40, the width of the bit lines 30 can be increased, thereby reducing the line resistance in the non-volatile two-ended storage device. This can solve the crosstalk and leakage problems between adjacent non-volatile two-ended storage cells 111, thus helping to reduce the number of non-volatile two-ended storage devices.
[0055] In embodiments of the present invention, a non-volatile two-ended memory array 100 may have one or more bit lines 30, one or more word lines 50, and one or more source lines 20. If each non-volatile two-ended memory module 10 includes two non-volatile two-ended memory cells 111, then the number of source lines 20 in a non-volatile two-ended memory array 100 is half the number of bit lines 30.
[0056] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "circumferential," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0057] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.
[0058] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims
1. A non-volatile two-terminal storage device, characterized in that, include: The non-volatile two-end storage array (100) includes a plurality of non-volatile two-end storage modules (10), each of the non-volatile two-end storage modules (10) including at least two non-volatile two-end storage cells (111). The non-volatile two-ended memory unit (111) includes a gate (1111) and a non-volatile two-ended memory (1112) connected in series with the gate (1111). The first end of the gate (1111) is electrically connected to the second end of the non-volatile two-ended memory (1112), the second end of the gate (1111) is electrically connected to the source line (20), and the first end of the non-volatile two-ended memory (1112) is electrically connected to the bit line (30). All non-volatile two-ended storage cells (111) in the non-volatile two-ended storage module (10) share a source line (20), and the bit lines (30) corresponding to two adjacent non-volatile two-ended storage modules (10) are shorted to each other at least twice.
2. The non-volatile two-terminal storage device according to claim 1, characterized in that, Each of the non-volatile two-ended storage modules (10) includes two non-volatile two-ended storage units (111), and the two non-volatile two-ended storage units (111) share a source line (20).
3. The non-volatile two-terminal storage device according to claim 2, characterized in that, Two adjacent non-volatile two-ended memory modules (10) are designated as a first non-volatile two-ended memory module (11) and a second non-volatile two-ended memory module (12), respectively. In the first non-volatile two-ended memory module (11), the bit line (30) electrically connected to the non-volatile two-ended memory (1112) adjacent to the second non-volatile two-ended memory module (12) is designated as the first bit line (31). In the second non-volatile two-ended memory module (12), the bit line (30) electrically connected to the non-volatile two-ended memory (1112) adjacent to the first non-volatile two-ended memory module (11) is designated as the second bit line (32). It also includes a jumper wire (40), which includes at least a first jumper wire (41) and a second jumper wire (42). The first jumper wire (41) is connected between the first end of the first bit line (31) in the length direction and the first end of the second bit line (32) in the length direction, and the second jumper wire (42) is connected between the second end of the first bit line (31) in the length direction and the second end of the second bit line (32) in the length direction.
4. The non-volatile two-terminal storage device according to claim 3, characterized in that, The shorting wire (40) also includes a third shorting wire (43), which is connected between the first bit line (31) and the second bit line (32). The third shorting wire (43) is spaced apart from both ends of the first bit line (31) and the second bit line (32) in the length direction.
5. The non-volatile two-terminal storage device according to claim 4, characterized in that, One end of the third shorting wire (43) is connected to the middle of the first bit line (31) along its length, and the other end of the third shorting wire (43) is connected to the middle of the second bit line (32) along its length.
6. The non-volatile two-terminal storage device according to claim 4, characterized in that, There are multiple third short wires (43), and the multiple third short wires (43) are arranged at intervals.
7. The non-volatile two-terminal storage device according to claim 1, characterized in that, The selector (1111) is a MOS transistor.
8. The non-volatile two-terminal storage device according to claim 7, characterized in that, It also includes a word line (50), the first end of the selector (1111) is the first non-gate (11113) of the MOS transistor, the first non-gate (11113) of the MOS transistor is electrically connected to the second end of the non-volatile two-terminal memory (1112), the second end of the selector (1111) is the second non-gate (11113) of the MOS transistor, the second non-gate (11113) of the MOS transistor is electrically connected to the source line (20), and the MOS transistor also has a gate (11113), the gate (11113) is electrically connected to the word line (50).
9. The non-volatile two-terminal storage device according to claim 1, characterized in that, The selector (1111) is a two-terminal switching device.
10. A storage system, characterized in that, The non-volatile dual-ended storage device includes any one of claims 1-9.