A driving method, device, chip and electronic equipment

Abstract

The application relates to the field of motors, in particular to a driving method, a driving device, a chip and electronic equipment, wherein the driving method comprises the following steps: collecting a first circuit parameter of a driving circuit, the first circuit parameter being directly proportional to an output current of the driving circuit, the output current being sequentially in a growth stage or a decay stage in each driving period of the driving circuit, each driving period having the same time length; comparing the first circuit parameter with a target parameter to determine a first time length during which the first circuit parameter is greater than the target parameter in a current period; and controlling the time length during which the output current is in the growth stage in a next period according to the first time length, the next period being a next period of the current period. In this way, the average driving current at a stable driving frequency can be kept around a target average current value, and noise can be prevented.

Description

Technical Field

[0001] This application relates to the field of electric motors, specifically to a driving method, device, chip, and electronic device. Background Technology

[0002] Traditional current chopping control schemes for motor drives have several drawbacks. First, due to the non-fixed drive frequency strategy, it is difficult to avoid the chopping frequency falling into the sensitive frequency band (such as 20Hz-20kHz) across the entire speed range of the motor, resulting in audible electromagnetic noise. Second, existing ripple suppression technologies rely on manual configuration or complex adaptive algorithms. For example, manually configuring the turn-off time (Toff) in each drive cycle significantly increases the complexity of circuit control configuration, and the algorithm's adaptability is weak. Third, the peak current control algorithm introduced by the current chopping mechanism causes the actual phase current to remain below the set value (i.e., the integral value of the current above the set value is less than the integral value of the current below the set value), and a forced zero-crossing dead zone is generated at the sine zero-crossing point during current commutation. During this period, the motor torque vacuum causes rotor oscillation and low-frequency vibration, limiting the quiet performance of the drive system. Summary of the Invention

[0003] To address the aforementioned problems, this application provides a driving method, apparatus, chip, and electronic device.

[0004] In a first aspect, this application provides a driving method, the method comprising: real-time acquisition of first circuit parameters of a driving circuit, the first circuit parameters being proportional to the output current of the driving circuit, the output current being in different state stages sequentially in each driving cycle of the driving circuit, each driving cycle having the same duration; comparing the first circuit parameters with target parameters to determine a first duration in the current cycle for which the first circuit parameters are greater than the target parameters, wherein the first duration is the duration for which the output current is greater than the target average current in the current cycle; and, based on the first duration, controlling the duration for which the output current is in the growth stage in the next cycle of the current cycle, the growth stage being one of the different state stages.

[0005] In this embodiment, by controlling the duration of each driving cycle to be the same—for example, stabilizing the driving frequency at 25kHz when the driving frequency is high—the driving frequency is kept outside the range of human hearing, avoiding fluctuations into the range of human hearing, thereby reducing noise. Furthermore, by adjusting the duration of the output current in the increasing phase of the next driving cycle (the following cycle) based on the first duration during which the first circuit parameter of the previous driving cycle (the current cycle) is greater than the target parameter, the average value of the output current of the driving circuit can be stabilized, for example, stabilized near the target average current value.

[0006] In one possible implementation of the first aspect, according to the first duration, controlling the duration of the output current in the growth phase in the next cycle of the current cycle includes: controlling the duration of the output current in the growth phase in the next cycle to be a second duration, the second duration being the difference between the duration of the output current in the growth phase in the current cycle and the timeout duration of the current cycle, the timeout duration of the current cycle being the difference between the first duration and a preset duration, and the first duration being greater than the preset duration.

[0007] In one possible implementation of the first aspect, according to the first duration, controlling the duration of the output current in the growth phase in the next cycle of the current cycle includes: controlling the duration of the output current in the growth phase in the next cycle to be a third duration, the third duration being the sum of the duration of the output current in the growth phase in the current cycle and the insufficient duration of the current cycle, the insufficient duration of the current cycle being the difference between a preset duration and the first duration, and the first duration being less than the preset duration.

[0008] In one possible implementation of the first aspect, the different state stages also include a decay stage, and the method further includes: during the decay stage of each driving cycle, when the duration for which the first circuit parameter is greater than the target parameter reaches a preset duration, the decay rate of the control output current is increased.

[0009] In this embodiment, the preset duration is, for example, half of the drive cycle. When the duration during which the first circuit parameter is greater than the target parameter reaches the preset duration, the screening rate of the output current is increased. This can ensure that the first duration during which the first circuit parameter is greater than the target parameter is approximately half of the drive cycle, and that the duty cycle during which the output current of the drive circuit is greater than the target average current is approximately 50%. This ultimately stabilizes the average coil current of the load near the target average current.

[0010] In one possible implementation of the first aspect, after the decay rate of the output current is increased, the method further includes: when the output current decreases to the target parameter, controlling the decay rate of the output current to decrease.

[0011] In one possible implementation of the first aspect, the different state stages further include an attenuation stage. The operating modes of the drive circuit in the attenuation stage include a first mode and a second mode. In the first mode, the output current of the drive circuit attenuates at a first rate, and in the second mode, the output current of the drive circuit attenuates at a second rate, wherein the first rate is less than the second rate. Controlling the attenuation rate of the output current to increase includes controlling the operating mode of the drive circuit to switch from the first mode to the second mode. Controlling the attenuation rate of the output current to decrease includes controlling the operating mode of the drive circuit to switch from the second mode to the first mode.

[0012] In one possible implementation of the first aspect, the first circuit parameter is a voltage parameter or a current parameter.

[0013] Secondly, this application provides a driving device, comprising: a driving circuit for connection to a load; a sampling circuit connected to the driving circuit for acquiring first circuit parameters of the driving circuit, the first circuit parameters being proportional to the output current of the driving circuit, the output current being in different state stages sequentially in each driving cycle of the driving circuit, each driving cycle having the same duration; a controller connected to the sampling circuit and the driving circuit for comparing the first circuit parameters with target parameters and determining a first duration in the current cycle for which the first circuit parameters are greater than the target parameters, wherein the first duration is the duration for which the output current is greater than the target average current in the current cycle; the controller is further configured to control the duration for which the output current is in the growth stage in the next cycle of the current cycle based on the first duration, the growth stage being one of the different state stages.

[0014] In this embodiment, by controlling the duration of each driving cycle to be the same—for example, stabilizing the driving frequency at 25kHz when the driving frequency is high—the driving frequency is kept outside the range of human hearing, avoiding fluctuations into the range of human hearing, thereby reducing noise. Furthermore, by adjusting the duration of the output current in the increasing phase of the next driving cycle (the following cycle) based on the first duration during which the first circuit parameter of the previous driving cycle (the current cycle) is greater than the target parameter, the average value of the output current of the driving circuit can be stabilized, for example, stabilized near the target average current value.

[0015] In one possible implementation of the second aspect, the operating modes of the drive circuit during the decay phase include a first mode and a second mode. In the first mode, the output current of the drive circuit decays at a first speed, and in the second mode, the output current of the drive circuit decays at a second speed, wherein the first speed is less than the second speed. The controller is also configured to switch the operating mode of the drive circuit from the first mode to the second mode when the duration for which the first circuit parameter is greater than the target parameter reaches a preset duration during the decay period of each drive cycle.

[0016] In one possible implementation of the second aspect, when the output current decreases to the target parameter, the operating mode of the control drive circuit switches from the second mode to the first mode.

[0017] In one possible implementation of the second aspect, the driving circuit is an H-bridge circuit. The first, second, third, and fourth arms of the H-bridge circuit are respectively equipped with a first switch, a second switch, a third switch, and a fourth switch. The first connection point between the first and third arms is used to connect one end of the load, the second connection point between the second and fourth arms is used to connect the other end of the load, the third connection point between the third and fourth arms is used to connect a first power supply, and the fourth connection point between the first and second arms is used to ground.

[0018] In one possible implementation of the second aspect, in the first mode, the first switch is turned on, the second switch is turned on, the third switch is turned off, and the fourth switch is turned off; in the second mode, the first switch is turned on, the second switch is turned off, the third switch is turned off, and the fourth switch is turned on.

[0019] In one possible implementation of the second aspect, the sampling circuit includes: a first sampling circuit connected to the source and drain of the first switching transistor and a controller, used to acquire a first voltage between the source and drain of the first switching transistor when the driving circuit is operating in the second mode, and to output the first circuit parameters to the controller after scaling and biasing the first voltage; and a second sampling circuit connected to the source and drain of the second switching transistor and a controller, used to acquire a second voltage between the source and drain of the second switching transistor when the driving circuit is operating in the first mode, and to output the first circuit parameters to the controller after scaling and biasing the second voltage.

[0020] In one possible implementation of the second aspect, the first circuit parameter includes a third voltage, and the first sampling circuit includes: a first switching module, the control terminal of the first switching module being connected to the gate of the second switching transistor, the first switching module being connected to the drain and source of the first switching transistor, for obtaining a first voltage between the source and drain of the first switching transistor; a first operational amplifier module, connected to the first switching module, for scaling and biasing the first voltage to obtain a first intermediate voltage; and a first mirror module, connected to the first operational amplifier module and the controller, for scaling the first intermediate voltage to obtain the third voltage.

[0021] In one possible implementation of the second aspect, the first circuit parameter includes a fourth voltage, and the second sampling circuit includes: a second switching module, the control terminal of the second switching module being connected to the gate of the second switching transistor, the second switching module being connected to the drain and source of the first switching transistor, for obtaining a second voltage between the source and drain of the first switching transistor; a second operational amplifier module, connected to the second switching module, for scaling and biasing the second voltage to obtain a second intermediate voltage; and a second mirror module, connected to the second operational amplifier module and the controller, for scaling the second intermediate voltage to obtain the fourth voltage.

[0022] In one possible implementation of the second aspect, the sampling circuit includes: a first sampling circuit connected to the source and drain of the fourth switch and a controller, used to acquire a first voltage between the source and drain of the first switch when the driving circuit is operating in the second mode, and to output the first circuit parameters to the controller after scaling and biasing the first voltage; and a second sampling circuit connected to the source and drain of the second switch and a controller, used to acquire a second voltage between the source and drain of the second switch when the driving circuit is operating in the first mode, and to output the first circuit parameters to the controller after scaling and biasing the second voltage.

[0023] In one possible implementation of the second aspect, the driving circuit includes a measuring resistor connected in series with the load, and the sampling circuit includes a first sampling circuit connected to both ends of the measuring resistor and a controller, used to acquire a first voltage across the measuring resistor when the driving circuit is operating in a first mode and a second mode, and to output a first circuit parameter to the controller after scaling and biasing the first voltage.

[0024] In one possible implementation of the second aspect, according to the first duration, controlling the duration of the output current in the growth phase in the next cycle of the current cycle includes: controlling the duration of the output current in the growth phase in the next cycle to be a second duration, the second duration being the difference between the duration of the output current in the growth phase in the current cycle and the timeout duration of the current cycle, the timeout duration of the current cycle being the difference between the first duration and a preset duration, and the first duration being greater than the preset duration.

[0025] In one possible implementation of the second aspect, according to the first duration, controlling the duration of the output current in the growth phase in the next cycle of the current cycle includes: controlling the duration of the output current in the growth phase in the next cycle to be a third duration, the third duration being the sum of the duration of the output current in the growth phase in the current cycle and the insufficient duration of the current cycle, the insufficient duration of the current cycle being the difference between a preset duration and the first duration, and the first duration being less than the preset duration.

[0026] Thirdly, this application provides a chip including the driving device of the first aspect.

[0027] Fourthly, this application provides an electronic device including the chip of the second aspect. Attached Figure Description

[0028] Figure 1A A first schematic diagram of an H-bridge circuit is shown according to an embodiment of this application;

[0029] Figure 1B A second schematic diagram of an H-bridge circuit is shown according to an embodiment of this application;

[0030] Figure 1CA third schematic diagram of an H-bridge circuit is shown according to an embodiment of this application;

[0031] Figure 2 A first structural schematic diagram of a first type of driving device is shown according to an embodiment of this application;

[0032] Figure 3A A schematic diagram of a second structure of a first type of driving device is shown according to an embodiment of this application;

[0033] Figure 3B A schematic diagram of the structure of a second type of driving device is shown according to an embodiment of this application;

[0034] Figure 3C A schematic diagram of the structure of a third type of driving device is shown according to an embodiment of this application;

[0035] Figure 4 A schematic diagram of a third structure of a first type of driving device is shown according to an embodiment of this application;

[0036] Figure 5 A schematic diagram of the structure of the first sampling circuit of the first driving device is shown according to an embodiment of this application;

[0037] Figure 6 A schematic diagram of the structure of the second sampling circuit of the first driving device is shown according to an embodiment of this application;

[0038] Figure 7 A schematic diagram of the structure of the first sampling circuit of the second driving device is shown according to an embodiment of this application;

[0039] Figure 8 A schematic diagram of the structure of the first sampling circuit of the third driving device is shown according to an embodiment of this application;

[0040] Figure 9 A schematic diagram of the driving process of a driving device is shown according to an embodiment of this application;

[0041] Figure 10A An embodiment of this application illustrates a current modulation variation diagram for a current rising step;

[0042] Figure 10B An embodiment of this application illustrates a current modulation variation diagram of a current decrease step;

[0043] Figure 11 An exemplary flowchart of a driving method is shown according to an embodiment of this application;

[0044] Figure 12 A schematic diagram of the structure of an electronic device is shown according to an embodiment of this application. Detailed Implementation

[0045] The illustrative embodiments of this application include, but are not limited to, a driving method, apparatus, chip, and electronic device.

[0046] The specific implementation process of the technical solution provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0047] As mentioned above, traditional current chopper control schemes for motor drives suffer from problems such as excessive noise, poor algorithm adaptability, and average current values ​​lower than the target value. To address these issues, the embodiments provided in this application achieve accurate motor bridge drive duty cycle control through a simplified algorithm and a small number of additional circuit components.

[0048] The following is based on Figures 1A-1C Taking the H-bridge circuit as an example, we will introduce three working modes of the driving circuit.

[0049] First, refer to Figure 1A The H-bridge circuit includes four switching transistors. The input terminal of switching transistor MN0, the output terminal of switching transistor MN2, and the first terminal of motor M are connected together. The input terminal of switching transistor MN1, the output terminal of switching transistor MN3, and the second terminal of motor M are connected together. The output terminals of switching transistors MN0 and MN1 are grounded. The input terminals of switching transistors MN2 and MN3 are connected to the power supply VM.

[0050] like Figure 1A As shown, in drive mode, the switching transistors MN1 and MN2 of the H-bridge circuit are working. At this time, the current I (i.e., the output current of the H-bridge circuit) through switching transistor MN1, motor M, and switching transistor MN2 increases, that is, it is in the growth phase.

[0051] like Figure 1B As shown, in slow decay mode, the switches MN0 and MN1 of the H-bridge circuit are operating. At this time, the current I (i.e., the output current of the H-bridge circuit) flowing through switch MN0, motor M, and switch MN1 decays slowly, i.e., it is in the decay phase. For example, it decays at the first speed.

[0052] like Figure 1C As shown, in the rapid decay mode, switches MN0 and MN3 of the H-bridge circuit are operating. At this time, the current I (i.e., the output current of the H-bridge circuit) flowing through switch MN0, motor M, and switch MN3 decays rapidly, indicating that the circuit is in the decay phase. For example, it decays at a second speed, where the second speed is greater than the first speed.

[0053] It is understood that, in the embodiments of this application, the H-bridge circuit can first operate in drive mode T within one drive cycle. on The duration, and then working in decay modes (such as fast decay mode and / or slow decay mode) T offThe duration is specified, and then a drive cycle ends.

[0054] For example, in T off Within this timeframe, when the rate of current decay reaches the expected level (e.g., current I is greater than the current threshold I), target If the time is less than or equal to half a drive cycle (e.g., the drive cycle is 40 microseconds), the H-bridge circuit can be controlled to continuously operate in slow decay mode.

[0055] For example, in T off Internally, the H-bridge circuit can be controlled to initially operate in slow decay mode. If the current decay rate does not reach the expected level (e.g., current I is greater than the current threshold I), the H-bridge circuit can be controlled to operate in slow decay mode. target If the time is greater than half a drive cycle (e.g., a drive cycle of 40 microseconds), the H-bridge circuit can be switched to fast decay mode until the current drops to the current threshold, at which point the H-bridge circuit can be switched back to slow decay mode. This ensures that I > I0. target The duty cycle is approximately 50%, thus ultimately controlling the average coil current of motor M within I. target Nearby, and at the same time, by precisely controlling the current chopping drive frequency, the drive frequency is always kept outside the range of human hearing. For example, when the drive cycle is 40 microseconds, the drive frequency is 25KHz, which is outside the range of human hearing.

[0056] It is understood that in this application, NM represents an N-channel MOSFET, the control terminal of which can be the gate, the input terminal can be the source, and the output terminal can be the drain. PM represents a P-channel MOSFET, the control terminal of which can be the gate, the input terminal can be the drain, and the output terminal can be the source.

[0057] like Figure 2 As shown, according to some embodiments, the driving device includes a driving circuit, a sampling circuit, and a controller.

[0058] The drive circuit can periodically drive the load and operate in drive mode and decay mode in sequence during each drive cycle. The decay mode includes a first mode (i.e., slow decay mode) and a second mode (i.e., fast decay mode). In drive mode, the output current of drive circuit gradually increases. In slow decay mode, the output current of drive circuit decays at a first speed. In fast decay mode, the output current of drive circuit decays at a second speed. The first speed is less than the second speed.

[0059] The sampling circuit is connected to the driving circuit and is used to collect the first circuit parameter of the driving circuit. The first circuit parameter is proportional to the output current of the driving circuit. The first circuit parameter can be a voltage parameter or a current parameter, and this application does not limit it.

[0060] The controller is connected to the drive circuit and the sampling circuit.

[0061] According to some embodiments, the controller compares a first circuit parameter with a target parameter to determine a first duration during which the first circuit parameter is greater than the target parameter in the current cycle. Based on the first duration, the controller controls the duration for which the output current is in the growth phase (i.e., the drive circuit is in drive mode) in the next cycle, where the next cycle is the cycle following the current cycle. Thus, the controller can adjust the duration of the drive mode in the next cycle based on the current conditions of the previous cycle, thereby stabilizing the average output current of the drive circuit near the target average current corresponding to the target parameter.

[0062] According to some embodiments, the controller is further configured to, when the drive circuit is operating in slow decay mode, determine a first duration during which the first circuit parameter is greater than the target parameter in the current drive cycle, and if the first duration is greater than a preset duration (e.g., half of the drive cycle), control the operating mode of the drive circuit to switch from slow decay mode to fast decay mode, wherein the preset duration is half the duration of each drive cycle; and when the drive circuit is operating in fast decay mode, control the operating mode of the drive circuit to switch from fast decay mode to slow decay mode if the first circuit parameter is less than or equal to the target parameter.

[0063] The following is based on Figures 3A-3C Examples of the three drive devices are described separately.

[0064] refer to Figure 3A The driving circuit is an H-bridge circuit, and the sampling circuit includes a first sampling circuit CURRENT SENSE 1 and a second sampling circuit CURRENT SENSE 2.

[0065] The first, second, third, and fourth arms of the H-bridge circuit are equipped with a first switch MN0, a second switch MN1, a third switch MN2, and a fourth switch MN3, respectively.

[0066] The first connection point between the first bridge arm and the third bridge arm, namely the drain of the first switching transistor MN0 and the source of the third switching transistor MN2, is used to connect one end of the load L (i.e., the bridge drive output port XOUT1).

[0067] The second connection point between the second bridge arm and the fourth bridge arm, namely the drain of the second switch MN1 and the source of the fourth switch MN3, is used to connect the other end of the load L (i.e., the bridge drive output port XOUT2).

[0068] The third connection point between the third bridge arm and the fourth bridge arm, namely the drain of the third switch MN2 and the drain of the fourth switch MN3, is used to connect the first power supply VM.

[0069] The fourth connection point between the first bridge arm and the second bridge arm, namely the source of the first switch MN0 and the source of the second switch MN1, is used for grounding (i.e., connected to the grounding port PGND).

[0070] The first sampling circuit, CURRENT SENSE 1, is connected to the source and drain of the first switching transistor MN0 and to the controller. It acquires the first voltage between the source and drain of MN0, scales and biases this first voltage to obtain a third voltage, and outputs this third voltage (as an example of the first circuit parameters) to the controller. It can be understood that since the first switching transistor MN0 operates in the slow decay mode and fast decay mode of the H-bridge circuit, but not in the drive mode, the first sampling circuit CURRENT SENSE 1 can sample the voltage drop across the first switching transistor MN0 caused by the current I flowing through the load L (i.e., the output current of the H-bridge circuit, or the operating current of the load L) when the H-bridge circuit is in slow decay mode or fast decay mode.

[0071] The second sampling circuit, CURRENT SENSE 2, is connected to the source and drain of the second switch MN1 and to the controller. It acquires the second voltage between the source and drain of the second switch MN1, scales and biases this second voltage to obtain a fourth voltage, and outputs this fourth voltage (as an example of the first circuit parameter) to the controller. It can be understood that since the second switch MN1 operates in the drive mode and slow decay mode of the H-bridge circuit, but not in the fast decay mode, the first sampling circuit CURRENT SENSE 2 can sample the voltage drop across the second switch MN1 caused by the current I flowing through the load L (i.e., the output current of the H-bridge circuit, or the operating current of the load L) when the H-bridge circuit is in drive mode and slow decay mode.

[0072] The controller, connected to the first sampling circuit CURRENT SENSE 1 and the second sampling circuit CURRENT SENSE 2, is used to compare the fourth voltage and the target parameter when the H-bridge circuit is in slow decay mode, and determine that the fourth voltage is greater than the target parameter (corresponding to I>I). target If the duration of the sampling circuit exceeds the preset duration, the first switch MN0 is turned on, the second switch MN1 is turned off, the third switch MN2 is turned off, and the fourth switch MN3 is turned on. This controls the H-bridge circuit to switch from slow attenuation mode to fast attenuation mode and controls the second sampling circuit to conduct. The preset duration is half of the preset drive period T.

[0073] The controller is also used to compare the third voltage and the target parameter when the H-bridge circuit is operating in fast decay mode, and to determine the third voltage when it is less than the target parameter (corresponding to I < I<I ... target In the case of ), the first switch MN0 is turned on, the second switch MN1 is turned on, the third switch MN2 is turned off, and the fourth switch MN3 is turned off, that is, the working mode of the H-bridge circuit is switched from fast attenuation mode to slow attenuation mode, and the first sampling circuit is turned on.

[0074] refer to Figure 3B , Figure 3B The drive device shown and Figure 3A The difference in the driving device shown is that the first sampling circuit 1 is used to sample the circuit parameters of the fourth switching transistor MN3.

[0075] Specifically, the first sampling circuit, CURRENT SENSE 1, is connected to the source and drain of the fourth switch MN3 and to the controller. It is used to acquire the first voltage between the source and drain of the fourth switch MN3, scale and bias the first voltage to obtain the third voltage, and then output the third voltage to the controller. It can be understood that since the fourth switch MN3 operates in the fast decay mode of the H-bridge circuit but not in the drive mode or slow decay mode, the first sampling circuit, CURRENT SENSE 1, can sample the voltage drop across the fourth switch MN3 caused by the current I flowing through the load L (i.e., the output current of the H-bridge circuit, or the operating current of the load L) when the H-bridge circuit is in fast decay mode.

[0076] refer to Figure 3C , Figure 3C The drive device shown and Figure 3A The difference in the driving device shown is that it has only one sampling circuit, namely the first sampling circuit CURRENT SENSE 1, which is used to sample the measuring resistor R. The measuring resistor R can be connected in series with the load L; that is, the first end of the measuring resistor R is connected to the bridge drive output port XOUT1, the second end of the measuring resistor R is connected to the first end of the load L, and the second end of the load L is connected to the bridge drive output port XOUT2.

[0077] Specifically, the first sampling circuit CURRENT SENSE 1 is connected to both ends of the measuring resistor R and to the controller. It is used to acquire a first voltage across the measuring resistor R, scale and bias the first voltage to obtain a third voltage, and then output the third voltage to the controller. It can be understood that the first sampling circuit CURRENT SENSE 1 can sample the voltage drop across the measuring resistor R caused by the current I flowing through the load L (i.e., the output current of the H-bridge circuit, or the operating current of the load L) when the H-bridge circuit is in any mode (such as drive mode, fast decay mode, or slow decay mode).

[0078] The following is based on Figure 3A Taking the drive device shown as an example, combined with Figure 4 The circuit structure of the controller in the drive device will be further described.

[0079] like Figure 4 As shown, the controller includes an H-bridge driver controller Gate_Driver, a feedback controller, a first comparator COMP1, a second comparator COMP2, a first digital-to-analog converter DAC1, a second digital-to-analog converter DAC2, a first amplifier OP_1, and a second amplifier OP_2.

[0080] Specifically, the first output terminal of the H-bridge driver Gate_Driver is connected to the gate of the first switching transistor MN0 and the control terminal of the first sampling circuit CURRENT SENSE 1; the second output terminal of the H-bridge driver Gate_Driver is connected to the gate of the second switching transistor MN1 and the control terminal of the second sampling circuit CURRENT SENSE 2; the third output terminal of the H-bridge driver Gate_Driver is connected to the gate of the third switching transistor MN2; and the fourth output terminal of the H-bridge driver Gate_Driver is connected to the gate of the fourth switching transistor MN3.

[0081] It can be understood that the drive signal LN1_GD output from the first output terminal of the H-bridge driver controller Gate_Driver can simultaneously control the first switch MN0 and the first sampling circuit CURRENT SENSE 1 to turn on or off. The drive signal LN2_GD output from the second output terminal of the H-bridge driver controller Gate_Driver can simultaneously control the second switch MN1 and the second sampling circuit CURRENT SENSE 2 to turn on or off. The drive signal HN1_GD output from the third output terminal of the H-bridge driver controller Gate_Driver can control the third switch MN2 to turn on or off. The drive signal HN2_GD output from the fourth output terminal of the H-bridge driver controller Gate_Driver can control the fourth switch MN3 to turn on or off. In this way, the H-bridge driver controller Gate_Driver can control the turn-on or turn-off of each switch by outputting control signals to the control terminals of each switch in the H-bridge circuit, thereby controlling the H-bridge circuit to be in different operating modes.

[0082] The feedback controller is connected to the input terminals of the first digital-to-analog converter (DAC1), the second digital-to-analog converter (DAC2), the output terminals of the first comparator (COMP1), the second comparator (COMP2), and the input terminal of the H-bridge driver (Gate_Driver). This connection allows for inputting a first digital signal to the first DAC1 and a second digital signal to the second DAC2. The first and second digital signals are identical. The first DAC1 converts the first digital signal into a first analog signal, and the second DAC2 converts the second digital signal into a second analog signal. The first and second analog signals can be the same.

[0083] The input terminal of the first amplifier OP_1 is connected to the output terminal of the first digital-to-analog converter DAC1. The first amplifier OP_1 is used to scale the first analog signal to obtain the target parameters.

[0084] The input terminal of the second amplifier OP_ is connected to the output terminal of the second digital-to-analog converter DAC2. The second amplifier OP_2 is used to scale the second analog signal to obtain the target parameters.

[0085] The input terminals of the first comparator COMP1 are connected to the output terminals of the first amplifier OP_1 and the first sampling circuit CURRENT SENSE 1, respectively, and are used to input the first comparison result of the third voltage and the target parameter to the feedback controller. For example, the non-inverting input terminal of the first comparator COMP1 is connected to the output terminal of the first amplifier OP_1, and the inverting input terminal of the first comparator COMP1 is connected to the output terminal of the first sampling circuit CURRENT SENSE 1.

[0086] The input terminals of the second comparator COMP2 are connected to the output terminals of the second amplifier OP_2 and the second sampling circuit CURRENT SENSE 2, respectively, to input the second comparison result of the fourth voltage and the target parameter to the feedback controller. For example, the non-inverting input terminal of the second comparator COMP2 is connected to the output terminal of the second amplifier OP_2, and the negative-inverting input terminal of the second comparator COMP2 is connected to the output terminal of the second sampling circuit CURRENT SENSE 2.

[0087] The feedback controller is used to, when the drive circuit is operating in slow decay mode, send a first command to the H-bridge drive controller if, based on a first comparison result, it is determined that the duration for which the second voltage is greater than the target parameter is greater than a preset duration (e.g., T / 2). The first command instructs the H-bridge drive controller to control the first switch MN0 to turn on, the second switch MN1 to turn off, the third switch MN2 to turn off, and the fourth switch MN3 to turn on, and also controls the first sampling circuit to conduct. That is, it controls the H-bridge circuit to operate in fast decay mode and samples the voltage across the first switch MN0 through the first sampling circuit.

[0088] The feedback controller is used to, when the drive circuit is operating in fast decay mode, send a second command to the H-bridge drive controller based on the first comparison result indicating that the second voltage is less than the target parameter. The second command instructs the H-bridge drive controller to turn on the first switch MN0, turn on the second switch MN1, turn off the third switch MN2, and turn off the fourth switch MN3, and also controls the second sampling circuit to conduct. That is, it controls the H-bridge circuit to operate in slow decay mode and samples the voltage across the second switch MN1 through the second sampling circuit.

[0089] According to some embodiments, the feedback controller is used to receive an input square wave signal via the STEP pin (i.e., the input pin for controlling the stepping) and determine the driving period for the load L based on the period of the square wave signal.

[0090] According to some embodiments, the first digital-to-analog converter (DAC) also receives a reference level VREF and converts the first digital signal into a first analog signal based on the reference level VREF. For example, the first digital signal is divided by a preset value and then multiplied by the reference level VREF to obtain the voltage value of the first analog signal.

[0091] According to some embodiments, the second digital-to-analog converter (DAC) also receives a reference level VREF and converts the second digital signal into a second analog signal based on the reference level VREF. For example, the second digital signal is divided by a preset value and then multiplied by the reference level VREF to obtain the voltage value of the second analog signal.

[0092] Understandable, Figure 3BIn the embodiment of the driving device shown, the structure of the controller and Figure 4 Similar to the example shown. In Figure 3C In the embodiment of the driving device shown, the structure of the controller and Figure 4 The difference in the structure shown is that it does not include the second amplifier OP_2, the second comparator COMP2, or the second digital-to-analog converter DAC2.

[0093] In this embodiment, a comparator is used to compare the sampled voltage across the operating switch in the H-bridge circuit with the target parameter. By setting the values ​​of each component in the driving device, the comparison result between the sampled voltage (i.e., the first circuit parameter, such as the third voltage or the fourth voltage) and the target parameter is made equivalent to the current I flowing through the load L and the target average current I. target The comparison results, thus based on I and I target The size relationship between them and I>I target The duration controls the H-bridge circuit to operate in different modes, ensuring I > I0. target The duty cycle is close to 50%, and the average current of the final load L is close to the target average current I. target .

[0094] The following is combined Figure 5 ,right Figure 3A The specific structure of the H-bridge circuit and the first sampling circuit CURRENT SENSE1 in the driving device shown will be further described. For example, Figure 5 The load L shown in the diagram can be understood as the equivalent load of the stepper motor.

[0095] Please refer to Figure 5 The first sampling circuit CURRENT SENSE 1 includes a first switching module, a first operational amplifier module, and a first mirror module.

[0096] The control terminal of the first switching module is connected to the gate of the first switching transistor MN0, and the drain and source of the first switching module are connected to the first switching transistor MN0, which is used to obtain the first voltage between the source and drain of the first switching transistor MN0.

[0097] Specifically, the first switching module includes a fifth switch transistor MN0_2 and a sixth switch transistor MN0_3. The source of the fifth switch transistor MN0_2 is connected to the drain of the second switch transistor MN0. The drain of the fifth switch transistor MN0_2 is connected to the input terminal of the first operational amplifier module. The gate of the fifth switch transistor MN0_2 is connected to the gate of the second switch transistor MN0. The source of the sixth switch transistor MN0_3 is connected to the source of the second switch transistor MN0. The drain of the sixth switch transistor MN0_3 is connected to the input terminal of the first operational amplifier module. The gate of the sixth switch transistor MN0_3 is connected to the gate of the second switch transistor MN0.

[0098] It can be understood that the fifth switch MN0_2, the sixth switch MN0_3, and the second switch MN0 are all used to receive the control signal LN1_GD output by the H-bridge drive controller. That is, the H-bridge drive controller simultaneously controls the fifth switch MN0_2, the sixth switch MN0_3, and the second switch MN0 to be turned on or off.

[0099] For example, the second switch MN0 includes m first-type switches connected in series, and the fifth switch MN0_2 and the sixth switch MN0_3 are also first-type switches, that is, R MN0 / R MN0_2 =m,R MN0 / R MN0_3 =m.

[0100] The first operational amplifier module is connected to the first switching module. The first operational amplifier module is used to scale and bias the first voltage to obtain the first intermediate voltage.

[0101] Specifically, the first operational amplifier module includes a first operational amplifier OP1, a first resistor R1, and a second resistor R2, wherein the impedances of the first resistor R1 and the second resistor R2 are the same. One end of the first resistor R1 and the drain of the fifth switching transistor MN0_2 are connected to the non-inverting input terminal of the first operational amplifier OP1, and the other end of the first resistor R1 is connected to the second power supply 0.5*VDD. The second resistor R2 and the drain of the sixth switching transistor MN0_3 are connected to the non-inverting input terminal and the output terminal of the first operational amplifier OP1. The output terminal of the first operational amplifier OP1 is connected to the input terminal of the first mirror module, and the output terminal of the first operational amplifier OP1 is used to output a first intermediate voltage.

[0102] In some embodiments, the first intermediate voltage output by the first operational amplifier module can be expressed as ISEN = 0.5VDD + I*R MN0 *R1 / R MN0_2 Where I is the current flowing through the load L or the first switching transistor MN0.

[0103] The first mirror module is connected to the first operational amplifier module. The first mirror module is used to scale the first intermediate voltage to obtain the third voltage.

[0104] Specifically, the first mirror module includes a second operational amplifier OP2, a seventh switch PM1, an eighth switch PM2, a third resistor R3, and a fourth resistor R4. The negative input terminal of the second operational amplifier OP2 is connected to the output terminal of the first operational amplifier OP1. The gate of the seventh switch PM1 is connected to the output terminal of the second operational amplifier OP2. The source of the seventh switch PM1 is connected to the third power supply VDD. The drain of the seventh switch PM1 is connected to one end of the third resistor R3 and the positive input terminal of the second operational amplifier OP2, while the other end of the third resistor R3 is grounded. The gate of the eighth switch PM2 is connected to the output terminal of the second operational amplifier OP2. The gate of the eighth switch PM2 is connected to the third power supply VDD. The drain of the eighth switch PM2 is connected to one end of the fourth resistor R4, while the other end of the fourth resistor R4 is grounded. The connection point between the drain of the eighth switch PM2 and the fourth resistor R4 can be connected to the controller; this connection point is used to output the third voltage ISENX.

[0105] It can be understood that the third voltage ISENX is the voltage drop across the fourth resistor R4 caused by the output current of the first sampling circuit CURRENT SENSE 1 (i.e., the current flowing through the fourth resistor R4). In some embodiments, the third voltage ISENX can be expressed as ISENX = ISEN * R4 / R3.

[0106] In this embodiment, the first operational amplifier module can scale the level of the current flowing into or out of the first switch MN0 on the first arm of the H-bridge circuit. At the same time, by increasing the bias voltage by 0.5VDD, the differential signal is converted into a single-ended signal ISEN. The single-ended signal ISEN is biased to a set common-mode level VDD by the mirror module. The mirror module performs a second scaling to obtain the calculated voltage signal ISENX. Thus, the calculated voltage signal ISENX is reduced compared to the voltage across the first switch MN0, and the voltage across the first switch MN0 is converted into a single-ended signal that can be input to the first comparator COMP1.

[0107] The following is combined Figure 6 ,right Figure 3A The specific structures of the H-bridge circuit and the second sampling circuit CURRENT SENSE2 in the driving device shown will be further described. Figure 6 The load L shown in the diagram can be understood as the equivalent load of the stepper motor.

[0108] Please refer to Figure 6 The second sampling circuit CURRENT SENSE 2 includes a second switching module, a second operational amplifier module, and a second mirror module.

[0109] The control terminal of the second switching module is connected to the gate of the second switching transistor MN1, and the drain and source of the second switching module and the second switching transistor MN1 are connected to obtain the second voltage between the source and drain of the second switching transistor MN1.

[0110] Specifically, the second switching module includes a ninth switch MN1_2 and a tenth switch MN1_3. The source of the ninth switch MN1_2 is connected to the drain of the second switch MN1, the drain of the ninth switch MN1_2 is connected to the input terminal of the second operational amplifier module, and the gate of the ninth switch MN1_2 is connected to the gate of the second switch MN1. The source of the tenth switch MN1_3 is connected to the source of the second switch MN1, the drain of the tenth switch MN1_3 is connected to the input terminal of the second operational amplifier module, and the gate of the tenth switch MN1_3 is connected to the gate of the second switch MN1.

[0111] It can be understood that the ninth switch MN1_2, the tenth switch MN1_3, and the second switch MN1 are all used to receive the control signal LN2_GD output by the H-bridge drive controller. That is, the H-bridge drive controller simultaneously controls the ninth switch MN1_2, the tenth switch MN1_3, and the second switch MN1 to be turned on or off.

[0112] For example, the second switch MN1 includes m second-type switches connected in series, and the ninth switch MN1_2 and the tenth switch MN1_3 are also second-type switches, that is, R MN1 / R MN1_2 =m,R MN1 / R MN1_3 =m.

[0113] The second operational amplifier module is connected to the second switch module. The second operational amplifier module is used to scale and bias the second voltage to obtain the second intermediate voltage.

[0114] Specifically, the second operational amplifier module includes a second operational amplifier OP1, a fifth resistor R5, and a sixth resistor R6, wherein the impedances of the fifth resistor R5 and the sixth resistor R6 are the same. One end of the fifth resistor R5, the drain of the ninth switch MN1_2, is connected to the non-inverting input terminal of the second operational amplifier OP1, and the other end of the fifth resistor R5 is connected to the second power supply 0.5*VDD. The sixth resistor R6, the drain of the tenth switch MN1_3, is connected to the non-inverting input terminal and the output terminal of the second operational amplifier OP1. The output terminal of the second operational amplifier OP1 is connected to the input terminal of the second mirror module, and the output terminal of the second operational amplifier is used to output the second intermediate voltage.

[0115] In some embodiments, the second intermediate voltage output by the second operational amplifier module can be expressed as ISEN = 0.5VDD + I*R MN1 *R1 / R MN1_2 Where I is the current flowing through the load L or the second switch MN0.

[0116] The second mirror module is connected to the second operational amplifier module. The second mirror module is used to scale the second intermediate voltage to obtain the fourth voltage.

[0117] Specifically, the second mirror module includes a second operational amplifier OP2, an eleventh switch PM3, a twelfth switch PM4, a seventh resistor R7, and an eighth resistor R8. The negative input of the second operational amplifier OP2 is connected to the output of the second operational amplifier OP1. The gate of the eleventh switch PM3 is connected to the output of the second operational amplifier OP2. The source of the eleventh switch PM3 is connected to the third power supply VDD. The drain of the eleventh switch PM3 is connected to one end of the seventh resistor R7 and the positive input of the second operational amplifier OP2, while the other end of the seventh resistor R7 is grounded. The gate of the twelfth switch PM4 is connected to the output of the second operational amplifier OP2. The gate of the twelfth switch PM4 is connected to the third power supply VDD. The drain of the twelfth switch PM4 is connected to one end of the eighth resistor R8, while the other end of the fourth resistor R8 is grounded. The connection point between the drain of the twelfth switch PM4 and the eighth resistor R8 is connected to the controller; this connection point is used to output the fourth voltage ISENX.

[0118] It can be understood that the fourth voltage ISENX is the voltage drop across the eighth resistor R8 caused by the output current of the second sampling circuit CURRENT SENSE 1 (i.e., the current flowing through the eighth resistor R8). In some embodiments, the fourth voltage ISENX can be expressed as ISENX = ISEN * R8 / R7.

[0119] In this embodiment, the second operational amplifier module can scale the level of the current flowing into or out of the second switch MN1 on the second arm of the H-bridge circuit. At the same time, by increasing the bias voltage by 0.5VDD, the differential signal is converted into a single-ended signal ISEN. The single-ended signal ISEN is biased to a set common-mode level VDD by the mirror module. The mirror module performs a second scaling to obtain the calculated voltage signal ISENX. This reduces the voltage across the second switch MN1 compared to the voltage across the second switch MN1, and converts the voltage across the second switch MN1 into a single-ended signal that can be input to the second comparator COMP2.

[0120] It is understood that in some other embodiments, the driving circuit may also include sampling circuits for other switching transistors, for example, such as Figure 7As shown, the sampling circuit corresponding to the fourth switch MN3 is set up (i.e. Figure 3B (The embodiment shown); or, a sampling circuit that samples the measured resistance by connecting a measuring resistor in series between the load L and the drive output port XOUT2. Figure 3C The illustrated embodiment, for example, such as Figure 8 As shown, a sampling circuit for the series-connected measuring resistor R is configured. Other sampling circuits can also be configured to sample the first circuit parameters, where the first circuit parameters are proportional to the output current I of the driving circuit. This allows for the comparison of I and Itarget, and the recording of the time when I > Itarget. This application does not impose any limitations on this. Figure 7 or Figure 8 The specific structure of the sampling circuit shown can be found in the section above. Figure 4 or Figure 5 The explanation will not be repeated here.

[0121] The following continues with Figure 3A Taking the embodiment of the driving device shown as an example, this application introduces a driving method provided by the embodiment of the present application.

[0122] It is understandable that, since the second switch MN1 and the first sampling circuit CURRENT SENSE 1 are turned on when the H-bridge circuit is in drive mode or slow decay mode, the first sampling circuit CURRENT SENSE 1 can sample the current of the H-bridge circuit in drive mode or slow decay mode. Similarly, since the first switch MN0 and the second sampling circuit CurrentSense2 are turned on when the H-bridge circuit is in fast decay mode or slow decay mode, the second sampling circuit CurrentSense2 can sample the current of the H-bridge circuit in fast drive mode or slow drive mode.

[0123] According to some embodiments, based on the driving device provided in the embodiments of this application, the feedback controller in the algorithm module can record the output results of the first comparator COMP1 and the second comparator COMP2.

[0124] For example, the first comparator COMP1 outputs a first signal indicating that the current I flowing through the load L is less than I0. target The first comparator COMP1 outputs a second signal indicating that the current I flowing through the load L is greater than I0. targetIn the fast decay mode of the H-bridge circuit, when the second signal output by the first comparator COMP1 flips to the first signal, it indicates that the current I in the coil of the load L (such as a stepper motor) has begun to decrease to the target set value. When the feedback controller receives the second signal output by the first comparator COMP1 flipping to the first signal, it can feed back to the H-bridge drive controller, causing the H-bridge drive controller to control the H-bridge circuit to switch from the fast decay mode to the slow decay mode, so that the current I quickly decreases to I0. target .

[0125] For example, the second comparator COMP2 outputs a first signal indicating that the current I flowing through the load L is less than I0. target The second comparator COMP2 outputs a second signal indicating that the current I flowing through the load L is greater than I. target In the slow decay mode of the H-bridge circuit, when the first signal output by the second comparator COMP2 flips to the second signal, it indicates that the current I on the coil has begun to reach the target set value. Upon receiving this flip, the feedback controller begins recording the time exceeding the target set value and compares it to half of the current cycle set value (i.e., the cycle set value corresponding to the fixed chopping frequency, for example, 25kHz). When the time exceeding the current set value exceeds half of the chopping drive cycle, the feedback controller immediately sends feedback to the H-bridge drive controller, causing the H-bridge drive controller to control the H-bridge circuit to enter the fast decay mode, so that the current I quickly decreases to I0. target .

[0126] According to some embodiments, if a high average current occurs within a drive cycle, for example, if a fast decay mode is enabled and I is greater than I... target If the duration of the drive mode exceeds half of the drive cycle T, the duration of the drive mode can be reduced in the next drive cycle, thereby making the average current closer to I. target For example, the feedback controller can record the duration of the fast decay mode, that is, the total time from when the feedback controller commands the H-bridge drive controller to start the fast decay mode to when the feedback controller commands the H-bridge drive controller to stop the fast decay mode, which is also the time when I is greater than I. target The timeout period exceeds half of the drive cycle T, and compensation is made for the timeout period in the next drive cycle. For example, the total duration of the drive mode in the previous drive cycle is subtracted from the total duration of the fast decay mode in the previous adjustment cycle to obtain the total duration of the drive mode in the next drive cycle, so as to dynamically adjust the duty cycle of the H-bridge output and ultimately control the average coil current within I. target nearby.

[0127] In other cases, if the average current is low within a drive cycle, for example, if fast decay mode is not enabled and I is greater than I... target If the duration of the drive mode is less than half of the drive cycle T, the duration of the drive mode can be increased in the next drive cycle, thereby making the average current closer to I. target For example, a feedback controller can record that I is greater than I. target The duration, and half of the driving cycle T minus the above I greater than I target The timeout duration is calculated to obtain the compensation duration. Then, in the next drive cycle, the timeout duration is compensated, i.e., the total duration of the drive mode in the previous drive cycle is added to the compensation duration to obtain the total duration of the drive mode in the next drive cycle. This dynamically adjusts the duty cycle of the H-bridge output, ultimately controlling the average coil current within I... target nearby.

[0128] In this way, the average coil current is ultimately controlled at I. target Nearby, the current chopping drive frequency is consistently controlled outside the range of human hearing (i.e., 20Hz to 20kHz). It is understood that this application does not limit the value of the fixed chopping frequency; in other embodiments, a faster chopping frequency can be set to further suppress fluctuations and ensure that the chopping frequency remains outside the range of human hearing.

[0129] The following is based on Figure 7 This paper provides a detailed description of the driving method of a driving device.

[0130] refer to Figure 7 The durations of the first drive cycle T1, the second drive cycle T2, the third drive cycle T3, and the fourth drive cycle T4 are all the same, and all are T.

[0131] The first drive cycle T1, as an example of a cycle without fluctuations, has HN1_GD at a high level for a duration TON, which is the preset on-time for the H-bridge circuit to drive the third switch MN2, i.e., the duration the H-bridge circuit is in drive mode. During the subsequent TOFF period, the H-bridge circuit is in slow decay mode, and HN1_GD is low. Within the first drive cycle T1, I exceeds I... target The time is T / 2.

[0132] The second drive cycle T2 (as an example of a timeout cycle) is the period in which fluctuations occur. Within the second drive cycle T2, HN1_GD is high for a duration of TON (as an example of the first duration). During the subsequent TOFF period, since I exceeds I... targetThe time is greater than T / 2, causing the H-bridge circuit to first enter a slow decay mode and then a fast decay mode, until I decreases to I0. target Then it returns to the slow decay mode until the end of the second drive cycle T2. This can be understood as the feedback controller recording I exceeds I... target When the time (i.e., the time of the second signal output by the second comparator COMP2) is greater than T / 2, a command can be sent to the H-bridge drive controller to cause the H-bridge drive controller to control the H-bridge circuit in fast decay mode; the feedback controller detects that I drops to I target When the output of the first comparator COM1 switches from the second signal to the first signal, a command can be sent to the H-bridge drive controller to control the H-bridge circuit in slow decay mode. The feedback controller can record the duration Δt1 of the H-bridge circuit operating in fast decay mode during the second drive cycle T2 (as an example of the second duration) to adjust the duty cycle of the next cycle, i.e., the third drive cycle T3.

[0133] The third driving cycle T3 (as the advance cycle, i.e., I exceeds I) target An example of a timeout period (where the time is less than T / 2) is called a timeout period (i.e., I exceeds I). target The time is greater than T / 2) in the next cycle. Within the third drive cycle T3, the duration of HN1_GD being high and the duration the H-bridge circuit is in drive mode is the difference between the duration of HN1_GD being high (TON) and the timeout duration Δt1 in the second drive cycle T2 (i.e., the previous cycle), i.e., TON-Δt1 (as an example of the third duration). After ΔTON-Δt1 and before the end of the third drive cycle T3, the H-bridge circuit is in slow decay mode, and I exceeds I target The time is less than T / 2.

[0134] That is, within the third drive cycle T3, when the H-bridge circuit is operating in drive mode, and the duration of operation in drive mode reaches TON-Δt1, the controller can switch the H-bridge circuit's operating mode from drive mode to slow decay mode. This can be understood as the feedback controller recording Δt1 and then sending ΔTON-Δt1 to the H-bridge drive controller, causing the H-bridge drive controller to control the H-bridge circuit in drive mode for ΔTON-Δt1, and then switch the H-bridge circuit from drive mode to slow decay mode after the time is reached. Furthermore, the feedback controller can record I exceeding I... target The time (as an example of the seventh duration) is less than the advance duration Δt2 of T / 2 (as an example of the sixth duration), which is used to adjust the duty cycle of the next cycle, namely the fourth driving cycle T4.

[0135] The fourth driving cycle, T4, is the advance cycle (i.e., I exceeds I). target The time is less than T / 2) in the next cycle. During the fourth drive cycle T3, the duration of HN1_GD being high and the duration of the H-bridge circuit being in drive mode are the sum of the duration of HN1_GD being high in the third drive cycle T3 (i.e., TON-△t1, as an example of the fifth duration) and the advance duration △t2, i.e., TON-△t1+△t2 (as an example of the fourth duration). After △TON-△t1+△t2 and before the end of the fourth drive cycle T4, the H-bridge circuit is in slow decay mode. Furthermore, during the fourth drive cycle T4, I exceeds I... target The time is less than T / 2, but the advance time of less than T / 2 is less than the threshold. Therefore, the fifth driving cycle T5 can use the duration of the driving mode in the fourth driving cycle T4, that is, △TON-△t1+△t2.

[0136] That is, within the fourth driving cycle T3, when the H-bridge circuit is operating in driving mode, and the duration of operation in driving mode reaches TON-△t1+△t2, the controller can switch the operating mode of the H-bridge circuit from driving mode to slow decay mode. It can be understood that after the feedback controller of the algorithm module records △t2, it can send △TON-△t1+△t2 to the H-bridge drive controller, causing the H-bridge drive controller to control the H-bridge circuit in driving mode for a duration of △TON-△t1+△t2. Furthermore, the feedback controller can record I exceeding I... target If the advance time is less than T / 2 and the advance time is less than the advance time, then the fifth drive cycle T5 does not need further adjustment.

[0137] It is understandable that the drive cycle of the H-bridge circuit is not limited to... Figure 6 The example can include a total of n driving cycles, where n is a natural number. For any timeout cycle in the n driving cycles and the driving method of the next cycle, please refer to the explanations above for the second driving cycle T2 and the third driving cycle T3; for any advance cycle in the n driving cycles and the driving method of the next cycle, please refer to the explanations above for the third driving cycle T3 and the fourth driving cycle T4, or for the fourth driving cycle T4 and the fifth driving cycle T5.

[0138] The following is based on Figure 10A and Figure 10B This application will now describe an embodiment of a step modulation process based on a driving device.

[0139] Figure 10A A current modulation variation diagram for a current rise step is shown. (Reference) Figure 10AItrip0 is the Itarget before the step jump, and Itrip1 is the Itarget after the step jump.

[0140] During the first cycle after the step jump, I reaches Itrip1, and the H-bridge circuit enters a slow decay mode until the end of the first cycle. The duration of this driving mode is increased by t1 compared to the cycle before the step jump, i.e., Tdrive1 = Ton + t1.

[0141] In the second cycle after the step jump, the duration of the drive mode is the same as that in the previous cycle, i.e., Tdrive2 = Tdrive1. Subsequently, the motor enters a slow decay mode until the duration of I > Itrip1 is greater than T / 2. At this point, the motor switches from slow decay mode to fast decay mode until I = Itrip1, returning to slow decay mode. The duration of the fast decay mode is t2.

[0142] In the second cycle after the step jump, the duration of the drive mode is reduced by t2 compared to the duration of the drive mode in the previous cycle, i.e., Tdrive3 = Tdrive2 - t2. Subsequently, the motor enters a slow decay mode until the duration of I > Itrip1 is greater than T / 2. At this point, the motor switches from slow decay mode to fast decay mode until I = Itrip1, returning to slow decay mode. The duration of the fast decay mode is t3.

[0143] In the third cycle after the step jump, the duration of the drive mode is reduced by t3 compared to the duration of the drive mode in the previous cycle, i.e., Tdrive4 = Tdrive3 - t3. Subsequently, the motor enters a slow decay mode, where the difference between the duration of I>Itrip1 and T / 2 is t4.

[0144] In the fourth cycle after the step jump, the duration of the drive mode increases by t4 compared to the duration of the drive mode in the previous cycle, i.e., Tdrive5 = Tdrive4 + t4. Subsequently, the motor enters a slow decay mode, where the difference between the duration of I > Itrip1 and T / 2 is less than the time threshold. In this case, the duration of the drive mode in the next cycle remains unchanged and is consistent with Tdrive5.

[0145] Figure 10B A current modulation variation diagram for a current decrease step is shown. (Reference) Figure 10B Itrip0 is the Itarget before the step jump, and Itrip1 is the Itarget after the step jump.

[0146] In the last cycle before the step jump, the duration of the drive mode is Ton.

[0147] In the first cycle after the step transition, the duration of the drive mode is the same as the previous cycle, i.e., Ton. After the drive mode ends, the H-bridge circuit enters a slow decay mode until the duration of I > Itrip1 is greater than T / 2. At this point, the motor switches from the slow decay mode to the fast decay mode until I = Itrip1, returning to the slow decay mode. The duration of the fast decay mode is t1.

[0148] During the second cycle after the step jump, since Ton-t1 < 0, i.e., Ton < t1, the duration of the drive mode is the preset duration Tblank. Subsequently, the motor enters a slow decay mode, where the difference between the duration of I > Itrip1 and T / 2 is t2.

[0149] In the third cycle after the step jump, the duration of the drive mode increases by t2 compared to the duration of the drive mode in the previous cycle, i.e., Tdrive1 = Tblank + t2. Subsequently, the motor enters a slow decay mode until the duration of I > Itrip1 is greater than T / 2. At this point, the motor switches from the slow decay mode to the fast decay mode until I = Itrip1, returning to the slow decay mode. The duration of the fast decay mode is t4.

[0150] In the fourth cycle after the step jump, the duration of the drive mode is reduced by t4 compared to the duration of the drive mode in the previous cycle, i.e., Tdrive3 = Tdrive2 - t4. Subsequently, the motor enters a slow decay mode, where the difference between the duration of I > Itrip1 and T / 2 is less than the time threshold. In this case, the duration of the drive mode in the next cycle remains unchanged and is consistent with Tdrive3.

[0151] Through the embodiments of this application, by employing a bidirectional sampling circuit, and using a relatively small area cost (such as a lower timeout duration within a drive cycle, allowing I to quickly decrease to Itarget), the overall noise reduction effect of the solution can be upgraded. This significantly reduces the difficulty of the algorithm and the adaptability across the entire speed range. Simultaneously, it avoids the drawback of the average current being lower than the actual set current, thus improving the motor torque utilization rate. Furthermore, it solves the problem of motor vibration noise at the zero-crossing point of the sine wave when the current reverses direction.

[0152] Figure 11 An exemplary flowchart of a driving method provided in an embodiment of this application is shown. Figure 11 As shown, the exemplary process includes the following steps.

[0153] S101: Acquire the first circuit parameters of the drive circuit. The first circuit parameters are proportional to the output current of the drive circuit. The output current is in different state stages in each drive cycle of the drive circuit, and each drive cycle has the same duration.

[0154] For example, different state stages may include one or more of the growth stage and the decay stage.

[0155] It is understood that the first circuit parameter can be a voltage or current parameter, and this application does not impose any restrictions on it.

[0156] According to some embodiments, S101 can be performed by a sampling circuit, for example, as Figure 3A As shown, the sampling circuit includes a first sampling circuit CURRENT SENSE 1 and a second sampling circuit CURRENT SENSE 2. The first circuit parameters may include a third voltage and a fourth voltage. The third voltage is obtained by scaling and biasing the first voltage, which is the voltage between the source and drain of the first switching transistor MN0. The fourth voltage is obtained by scaling and biasing the second voltage, which is the voltage between the source and drain of the second switching transistor MN1.

[0157] It can be understood that the growth phase is the phase in which the drive circuit operates in drive mode, and the decay phase is the phase in which the drive circuit operates in slow decay mode (i.e., the first mode) or fast decay mode (i.e., the second mode). It can be understood that in slow decay mode, the output current of the drive circuit decays at a first rate, and in fast decay mode, the output current of the drive circuit decays at a second rate, with the first rate being less than the second rate.

[0158] S102: Compare the first circuit parameter and the target parameter to determine the first duration during which the first circuit parameter is greater than the target parameter in the current cycle, wherein the first duration is the duration during which the output current is greater than the target average current in the current cycle.

[0159] According to some embodiments, S102 can be executed by the controller. It can be understood that within the current cycle, the first circuit parameter is greater than the target parameter for a first duration, i.e., the duration during which I > Itarget within the current cycle.

[0160] For example, such as Figure 4As shown, the feedback controller is used to input a first digital signal to the first digital-to-analog converter (DAC) and a second digital signal to the second DAC. The first DAC1 and the second DAC2 convert the first digital signal and the second digital signal into a first analog signal and a second analog signal, respectively. These signals are then amplified by the first amplifier OP_1 and the second amplifier OP_2 to obtain target parameters, which are then input to the first comparator COMP1 and the second comparator COMP2 for comparison with the first circuit parameters output by the sampling circuit, yielding a first comparison result and a second comparison result. For example, the first circuit parameters include a third voltage output by the first sampling circuit CURRENT SENSE 1 and a fourth voltage output by the second sampling circuit CURRENT SENSE 2. The feedback controller is used to determine, within the current cycle, the duration for which the first comparison result output by the first comparator COMP1 indicates that the third voltage is greater than the target parameter, as the first duration for which the first circuit parameter is greater than the target parameter.

[0161] S103: Based on the first duration, control the duration of the output current in the growth phase in the next cycle of the current cycle. The growth phase is one of the different state phases.

[0162] According to some embodiments, S102 can be executed by the controller. It is understood that the output current is in the growth phase, i.e., the drive circuit is in drive mode.

[0163] For example, if the first duration is longer than a preset duration, the duration for which the output current remains in an increasing state in the next cycle is designated as the second duration. The second duration is the difference between the duration of the increasing output current phase in the current cycle and the timeout duration of the current cycle. The timeout duration of the current cycle is the difference between the first duration and the preset duration, where the first duration is longer than the preset duration. For example, if the current cycle is... Figure 9 The second driving cycle T2 is shown, and the next cycle is... Figure 9 The third drive cycle T3 shown above can be referred to for a related description. Figure 9 The explanation will not be repeated here.

[0164] For example, if the first duration is less than or equal to the preset duration, the duration during which the output current is in an increasing state in the next cycle is designated as the third duration. The third duration is the sum of the duration during which the output current is in an increasing phase in the current cycle and the insufficient duration of the current cycle. The insufficient duration of the current cycle is the difference between the preset duration and the first duration. For example, if the current cycle is... Figure 9 The third driving cycle T3 is shown, and the next cycle is... Figure 9 The fourth drive cycle T4 shown above can be referred to for a related description. Figure 9 The explanation will not be repeated here.

[0165] In some embodiments, the method further includes: during the decay phase of each drive cycle, when during the drive cycle (e.g.) Figure 9 During the second drive cycle T2 (as shown), when the duration for which the first circuit parameter is greater than the target parameter reaches a preset duration, the decay rate of the control output current increases; for example, the control drive circuit switches from a slow decay mode to a fast decay mode. When the output current decreases to the target parameter, the decay rate of the control output current decreases; for example, the control drive circuit switches from a fast decay mode to a slow decay mode.

[0166] Figure 12 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown.

[0167] It is understood that the driving method provided in this application is applicable to electronic devices including but not limited to: in-vehicle devices, terminal devices, tablet computers, computers with wireless transceiver capabilities, virtual reality (VR) devices, augmented reality (AR) devices, wireless devices in self-driving vehicles, wireless devices in smart grids, wireless devices in transportation safety, wireless devices in smart cities, and so on.

[0168] In one embodiment, system 1200 may include one or more processors 1204, system control logic 1208 connected to at least one of the processors 1204, system memory 1212 connected to system control logic 1208, non-volatile memory (NVM) 1216 connected to system control logic 1208, and network interface 1220 connected to system control logic 1208.

[0169] In some embodiments, processor 1204 may include one or more single-core or multi-core processors. In some embodiments, processor 1204 may include any combination of general-purpose processors and special-purpose processors (e.g., graphics processors, application processors, baseband processors, etc.). In embodiments where system 1200 employs an evolved node B (eNB) or radio access network (RAN) controller, processor 1204 may be configured to perform various corresponding embodiments.

[0170] In some embodiments, system control logic 1208 may include any suitable interface controller to provide any suitable interface to at least one of the processors 1204 and / or any suitable device or component communicating with system control logic 1208.

[0171] In some embodiments, system control logic 1208 may include one or more memory controllers to provide an interface to system memory 1212. System memory 1212 may be used to load and store data and / or instructions. In some embodiments, memory 1212 of system 1200 may include any suitable volatile memory, such as suitable dynamic random access memory (DRAM).

[0172] NVM memory 1216 may include one or more tangible, non-transitory computer-readable media for storing data and / or instructions. In some embodiments, NVM memory 1216 may include any suitable non-volatile memory such as flash memory and / or any suitable non-volatile storage device, such as at least one of a hard disk drive (HDD), a compact disc (CD) drive, and a digital versatile disc (DVD) drive.

[0173] NVM storage 1216 may include a portion of storage resources on the device on which system 1200 is installed, or it may be accessible by the device, but is not necessarily part of the device. For example, NVM storage 1216 may be accessed over a network via network interface 1220.

[0174] Specifically, system memory 1212 and NVM memory 1216 may each include a temporary copy and a permanent copy of instruction 1224. Instruction 1224 may include, when executed by at least one of processors 1204, causing system 1200 to implement as shown in Figure 1 and... Figure 6 The instructions for the method shown. In some embodiments, instructions 1224, hardware, firmware and / or their software components may additionally / alternatively be located in system control logic 1208, network interface 1220 and / or processor 1204.

[0175] Network interface 1220 may include a transceiver for providing a radio interface to system 1200, thereby enabling communication with any other suitable device (such as a front-end module, antenna, etc.) via one or more networks. In some embodiments, network interface 1220 may be integrated into other components of system 1200. For example, network interface 1220 may be integrated into at least one of processor 1204, system memory 1212, NVM memory 1216, and firmware device (not shown) with instructions, wherein system 1200 implements the methods of embodiments of this application when at least one of processor 1204 executes instructions.

[0176] The network interface 1220 may further include any suitable hardware and / or firmware to provide a multiple-input multiple-output radio interface. For example, the network interface 1220 may be a network adapter, a wireless network adapter, a telephone modem, and / or a wireless modem.

[0177] In one embodiment, at least one of the processors 1204 may be packaged together with the logic of one or more controllers for system control logic 1208 to form a system-in-package (SiP). In another embodiment, at least one of the processors 1204 may be integrated on the same die with the logic of one or more controllers for system control logic 1208 to form a system-on-a-chip (SoC).

[0178] System 1200 may further include an input / output (I / O) device 1232. The I / O device 1232 may include a user interface enabling a user to interact with system 1200; the peripheral component interface is designed to allow peripheral components to also interact with system 1200. In some embodiments, system 1200 may also include sensors for determining at least one of environmental conditions and location information related to system 1200.

[0179] In some embodiments, the user interface may include, but is not limited to, a display (e.g., a liquid crystal display, a touch screen display, etc.), a speaker, a microphone, one or more cameras (e.g., a still image camera and / or a video camera), a flashlight (e.g., a light-emitting diode flash), and a keyboard.

[0180] In some embodiments, the peripheral component interface may include, but is not limited to, a non-volatile memory port, an audio jack, and a power interface.

[0181] In some embodiments, the sensor may include, but is not limited to, a gyroscope sensor, an accelerometer, a proximity sensor, an ambient light sensor, and a positioning unit. The positioning unit may also be part of or interact with the network interface 1220 to communicate with components of the positioning network (e.g., Global Positioning System (GPS) satellites).

[0182] This application also provides a computer program product, which includes computer instructions that, when executed on an electronic device, cause the electronic device to perform the aforementioned driving method.

[0183] This application also provides a chip including the aforementioned driving device.

[0184] According to some embodiments, the electronic device provided in this application may include the chip described above.

[0185] It is understood that, as used herein, the term “module” may refer to or include, or be part of, an application-specific integrated circuit (ASIC), electronic circuitry, a processor (shared, dedicated, or grouped) and / or memory that executes one or more software or firmware programs, combinational logic circuitry, and / or other suitable hardware components that provide the described functionality.

[0186] It is understood that in the various embodiments of this application, the processor may be a microprocessor, a digital signal processor, a microcontroller, etc., and / or any combination thereof. According to another aspect, the processor may be a single-core processor, a multi-core processor, etc., and / or any combination thereof.

[0187] The embodiments disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of this application can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0188] Program code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0189] The program code can be implemented using a high-level procedural language or an object-oriented programming language to communicate with the processing system. Assembly language or machine language can also be used when needed. In fact, the mechanisms described in this application are not limited to any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0190] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, CD-ROMs, magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other forms of propagated signals. Therefore, machine-readable media includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0191] This specification provides the methods or processes shown in the embodiments or flowcharts, but based on conventional or non-inventive labor, more or fewer operation steps may be included. The order of steps listed in the embodiments is merely one of many execution orders and does not represent the only execution order. In actual execution, the methods or processes shown in the embodiments or drawings can be executed in sequence or in parallel (e.g., in a parallel controller or multi-threaded processing environment).

[0192] The embodiments disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of this application can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0193] Program code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0194] The program code can be implemented using a high-level procedural language or an object-oriented programming language to communicate with the processing system. Assembly language or machine language can also be used when needed. In fact, the mechanisms described in this application are not limited to any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0195] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, CD-ROMs, magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other propagation signals. Therefore, machine-readable media include any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0196] As used herein, the term “module” may refer to, as part of, or include: memory (shared, dedicated, or grouped) for running one or more software or firmware programs, application-specific integrated circuits (ASICs), electronic circuits and / or processors (shared, dedicated, or grouped), combinational logic circuits, and / or other suitable components that provide functionality.

[0197] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order is not necessary. Rather, in some embodiments, these features may be illustrated in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular drawing does not mean that all embodiments need to include such features; in some embodiments, these features may be omitted, or they may be combined with other features.

[0198] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, the use of the technical solutions of this application is not limited to the various applications mentioned in the embodiments of this patent. Various structures and modifications can be easily implemented with reference to the technical solutions of this application to achieve the various beneficial effects mentioned herein. Within the scope of knowledge possessed by those skilled in the art, all changes made without departing from the spirit of this application should be considered within the scope of this patent application.

Claims

1. A driving method, characterized in that, The method includes: The first circuit parameter of the driving circuit is acquired in real time. The first circuit parameter is proportional to the output current of the driving circuit. The output current is in different state stages in each driving cycle of the driving circuit. Each driving cycle has the same duration. The first circuit parameter and the target parameter are compared to determine the first duration during which the first circuit parameter is greater than the target parameter in the current cycle, wherein the first duration is the duration during which the output current is greater than the target average current in the current cycle; Based on the first duration, the duration of the output current in the growth phase in the next cycle of the current cycle is controlled, wherein the growth phase is one of the different state phases; The step of controlling the duration of the output current in the growth phase in the next cycle of the current cycle according to the first duration includes: controlling the duration of the output current in the growth phase in the next cycle to be a second duration, the second duration being the difference between the duration of the output current in the growth phase in the current cycle and the timeout duration of the current cycle, the timeout duration of the current cycle being the difference between the first duration and a preset duration, and the first duration being greater than the preset duration; or The duration during which the output current is in an increasing state in the next cycle is defined as a third duration. The third duration is the sum of the duration during which the output current is in an increasing phase in the current cycle and the insufficient duration of the current cycle. The insufficient duration of the current cycle is the difference between a preset duration and the first duration, where the first duration is less than the preset duration.

2. The method according to claim 1, characterized in that, The different state stages also include a decay stage, and the method further includes: During the decay phase of each driving cycle, when the duration for which the first circuit parameter is greater than the target parameter reaches a preset duration, the decay rate of the output current is controlled to increase.

3. The method according to claim 2, characterized in that, After the attenuation rate of the output current is increased, the method further includes: When the output current decreases to the target parameter, the decay rate of the output current is controlled to decrease.

4. The method according to claim 3, characterized in that, The driving circuit operates in two modes during the attenuation phase: a first mode and a second mode. In the first mode, the output current of the driving circuit attenuates at a first speed, and in the second mode, the output current of the driving circuit attenuates at a second speed, wherein the first speed is less than the second speed. The control of increasing the attenuation rate of the output current includes: The operating mode of the drive circuit is switched from the first mode to the second mode; The control of reducing the decay rate of the output current includes: The operating mode of the drive circuit is switched from the second mode to the first mode.

5. The method according to any one of claims 1-4, characterized in that, The first circuit parameter is a voltage parameter or a current parameter.

6. A driving device, characterized in that, include: A drive circuit, used to connect to the load; A sampling circuit, connected to the driving circuit, is used to collect a first circuit parameter of the driving circuit. The first circuit parameter is proportional to the output current of the driving circuit. The output current is in different state stages in each driving cycle of the driving circuit, and each driving cycle has the same duration. A controller, connected to the sampling circuit and the driving circuit, is used to compare the first circuit parameter and the target parameter to determine a first duration during which the first circuit parameter is greater than the target parameter in the current cycle, wherein the first duration is the duration during which the output current is greater than the target average current in the current cycle; The controller is also configured to control the duration of the output current in the growth phase in the next cycle of the current cycle according to the first duration, wherein the growth phase is one of the different state phases; The step of controlling the duration for which the output current is in the growth phase in the next cycle of the current cycle, based on the first duration, includes: The duration of the output current in the growth phase within the next cycle is defined as a second duration, which is the difference between the duration of the output current in the growth phase within the current cycle and the timeout duration of the current cycle. The timeout duration of the current cycle is the difference between the first duration and a preset duration, where the first duration is greater than the preset duration; or The duration of the output current in the growth phase in the next cycle is controlled as a third duration. The third duration is the sum of the duration of the output current in the growth phase in the current cycle and the insufficient duration of the current cycle. The insufficient duration of the current cycle is the difference between a preset duration and the first duration, and the first duration is less than the preset duration.

7. The apparatus according to claim 6, characterized in that, The different state stages include an attenuation stage. The operating modes of the driving circuit in the attenuation stage include a first mode and a second mode. In the first mode, the output current of the driving circuit attenuates at a first speed, and in the second mode, the output current of the driving circuit attenuates at a second speed. The first speed is less than the second speed. The controller is further configured to, during the decay phase of each driving cycle, when the duration for which the first circuit parameter is greater than the target parameter reaches a preset duration, control the operating mode of the driving circuit to switch from the first mode to the second mode.

8. The apparatus according to claim 7, characterized in that, The controller is also configured to switch the operating mode of the drive circuit from the second mode to the first mode when the output current decreases to the target parameter.

9. The apparatus according to claim 7 or 8, characterized in that, The driving circuit is an H-bridge circuit. The first, second, third, and fourth arms of the H-bridge circuit are respectively equipped with a first switch, a second switch, a third switch, and a fourth switch. The first connection point between the first and third arms is used to connect one end of the load. The second connection point between the second and fourth arms is used to connect the other end of the load. The third connection point between the third and fourth arms is used to connect to a first power supply. The fourth connection point between the first and second arms is used for grounding.

10. The apparatus according to claim 9, characterized in that, In the first mode, the first switch is turned on, the second switch is turned on, the third switch is turned off, and the fourth switch is turned off; In the second mode, the first switch is turned on, the second switch is turned off, the third switch is turned off, and the fourth switch is turned on.

11. The apparatus according to claim 10, characterized in that, The sampling circuit includes: The first sampling circuit is connected to the source and drain of the first switching transistor and the controller. When the driving circuit is working in the second mode, it obtains the first voltage between the source and drain of the first switching transistor, and after scaling and biasing the first voltage, outputs the first circuit parameters to the controller. The second sampling circuit, connected to the source and drain of the second switching transistor and the controller, is used to obtain the second voltage between the source and drain of the second switching transistor when the driving circuit is working in the first mode, and after scaling and biasing the second voltage, output the first circuit parameters to the controller.

12. The apparatus according to claim 11, characterized in that, The first circuit parameters include a third voltage, and the first sampling circuit includes: A first switching module, wherein the control terminal of the first switching module is connected to the gate of the second switching transistor, and the drain and source of the first switching transistor are connected to the first switching module, for obtaining a first voltage between the source and drain of the first switching transistor; The first operational amplifier module is connected to the first switching module and is used to scale and bias the first voltage to obtain the first intermediate voltage. The first mirror module, connected to the first operational amplifier module and the controller, is used to scale the first intermediate voltage to obtain the third voltage.

13. The apparatus according to claim 11, characterized in that, The first circuit parameters include a fourth voltage, and the second sampling circuit includes: The second switching module has its control terminal connected to the gate of the second switching transistor, and its drain and source connected to the drain of the second switching transistor, for obtaining the second voltage between the source and drain of the second switching transistor. The second operational amplifier module, connected to the second switching module, is used to scale and bias the second voltage to obtain the second intermediate voltage. The second mirror module, connected to the second operational amplifier module and the controller, is used to scale the second intermediate voltage to obtain the fourth voltage.

14. The apparatus according to claim 10, characterized in that, The sampling circuit includes: The first sampling circuit is connected to the source and drain of the fourth switching transistor and the controller. When the driving circuit is working in the second mode, it obtains the first voltage between the source and drain of the fourth switching transistor, scales and biases the first voltage, and then outputs the first circuit parameters to the controller. The second sampling circuit, connected to the source and drain of the second switching transistor and the controller, is used to obtain the second voltage between the source and drain of the second switching transistor when the driving circuit is working in the first mode, and after scaling and biasing the second voltage, output the first circuit parameters to the controller.

15. The apparatus according to claim 10, characterized in that, The driving circuit includes a measuring resistor connected in series with the load, and the sampling circuit includes: The first sampling circuit is connected to both ends of the measuring resistor and the controller. When the driving circuit is working in the first mode and the second mode, it acquires the first voltage across the measuring resistor, scales and biases the first voltage, and then outputs the first circuit parameters to the controller.

16. A chip, characterized in that, Includes the drive device as described in any one of claims 6-15.

17. An electronic device, characterized in that, Includes the chip as described in claim 16.

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