A method and device for dynamically generating a unique EDID compatible with PnP
By performing ASCII encoding conversion, padding, and cyclic compression on product model information to generate a unique EDID dynamic method, the problem of confusing identification of devices of the same model is solved, ensuring the uniqueness of PnP ID and realizing accurate driver matching and installation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN PROITAV TECH CO LTD
- Filing Date
- 2025-11-24
- Publication Date
- 2026-05-12
AI Technical Summary
The existing EDIDs contain the same manufacturer identification code, which causes confusion in the identification of different devices of the same model, resulting in abnormal audio driver matching and failure to trigger the installation of new drivers.
By performing ASCII encoding conversion, padding, and cyclic compression on the product model information, a unique binary variable value is generated. This value is then modulo 216 and embedded into the corresponding field of the EDID to ensure the global uniqueness of the PnP ID.
It ensures the uniqueness of the product ID in the EDID of devices of the same model, accurately triggers driver matching and installation, reduces the user's reliance on manually distinguishing devices, and avoids compatibility risks caused by driver matching issues.
Smart Images

Figure CN121193268B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of product ID generation technology, and in particular to a method and apparatus for dynamically generating unique EDIDs compatible with PnP. Background Technology
[0002] Extended Display Identification Data (EDID) is a VESA standard data format that contains parameters about the monitor and its performance, such as vendor information, maximum image size, and color settings. The bytes 0x08 to 0x0A of the EDID use a three-byte Plug and Play ID encoding scheme to uniquely identify the manufacturer and specific product model of the computer hardware device.
[0003] However, in the current EDID, the Manufacturer ID and Product ID are fixed values, such as Manufacturer ID "AAA" + Product ID "0000". This results in the same format (VEN_Manufacturer ID and DEV_Product ID) for devices of the same model. When multiple devices are connected to the Windows system, the system considers them to be "the same device" and only retains the driver configuration of the first device. Subsequent devices cannot trigger the installation of new drivers, leading to audio driver mismatch (such as the HDMI audio channel not being activated). Summary of the Invention
[0004] The purpose of this application is to propose a PnP-compatible method and apparatus for dynamically generating unique EDIDs, in order to solve the problem of identification confusion caused by the same manufacturer identification code in the EDIDs of different devices of the same model.
[0005] A method for dynamically generating unique EDIDs compatible with PnP includes:
[0006] S100. Obtain the product model information of the target device, preprocess the product model information and then perform ASCII encoding conversion to obtain the first string, and calculate the first binary length of the first string.
[0007] S200. If the length of the first binary string is less than 512 bits, then the binary bits of the first string are padded to obtain a target string with 512 binary bits.
[0008] S300. Initialize the buffer register, divide the target string into blocks to obtain a 32-bit word of the first quantity block, expand the 32-bit word of the first quantity block to obtain a 32-bit word of the second quantity block, and perform a second round of cyclic compression on the 32-bit word of the second quantity block to obtain the binary variable value of the first quantity.
[0009] S400: Extract a binary variable value spanning a specified interval from the binary variable value of the first quantity bits to obtain a first 32-bit binary variable value; perform modulo 2 on the first 32-bit binary variable value. 16 The product ID is obtained through calculation. After converting the product ID to hexadecimal, it is embedded into the corresponding field of the original EDID to obtain the unique EDID of the product device.
[0010] Furthermore, S200 includes:
[0011] S210. Add 1 to the end of the first string to obtain the second string;
[0012] S220. Perform a padding operation of zeros on the second string to obtain the third string;
[0013] S230. Add the 64-bit binary number of the first string to the end of the third string to obtain the target string.
[0014] Furthermore, S300 includes:
[0015] S310. Initialize a specified number of 32-bit registers, such that each of the 32-bit registers is a specified hexadecimal value;
[0016] S320. Convert the hexadecimal value of each of the 32-bit registers into a 32-bit binary value.
[0017] Furthermore, following S320, S300 also includes:
[0018] S330. Obtain the 32-bit word of the first quantity block;
[0019] S340. The 32-bit word of the first quantity block is processed according to the formula:
[0020] W_t=(W_{t-3} XOR W_{t-8} XOR W_{t-14} XOR W_{t-16})<<<1 (1),
[0021] Perform a 1-bit circular left shift expansion to obtain the 32-bit word of the second quantity block;
[0022] Where W_t is the t-th 32-bit word (t ranges from 16 to 79, and "<<<" indicates a circular left shift).
[0023] Furthermore, following S340, S300 also includes:
[0024] S350. Assign a temporary value to the initial value of the 32-bit register;
[0025] S360. Calculate the logic function value and logic constant of the cyclic compression segment by segment using the temporary variable, and update the temporary variable using the left-shifted temporary variable, logic function value, logic constant and the 32-bit word of the current block;
[0026] S370. After the loop ends, the binary variable value of the first number of bits is calculated based on the updated temporary variable and the initial value of the 32-bit register.
[0027] Furthermore, S360 includes:
[0028] S361. Obtain the temporary variable and use the temporary variable to perform segmented calculations on the value of the logic function;
[0029] S362. Obtain the logical constant by assigning values in segments;
[0030] S363. Obtain the temporary variable after left shift, the logical function value, the logical constant, and the 32-bit word of the current block. Calculate the logical temporary value using the temporary variable after left shift, the logical function value, the logical constant, and the 32-bit word of the current block. Update the temporary variable using the logical temporary value and the temporary variable after left shift.
[0031] Furthermore, S400 includes:
[0032] S410. Convert the first 32-bit binary variable value into a decimal unsigned integer;
[0033] S420, Perform modulo 2 on the unsigned decimal integer. 16 The calculation is performed to obtain the remainder, and the remainder is used as the product ID.
[0034] To address the aforementioned issues, a PnP-compatible unique EDID dynamic generation device is provided, employing the aforementioned PnP-compatible unique EDID dynamic generation method, comprising:
[0035] The conversion module is used to obtain the product model information of the target device, convert the product model information into ASCII encoding to obtain a first string, and calculate the first binary length of the first string.
[0036] The padding module is used to pad the binary bits of the first string if the length of the first binary string is less than 512 bits, so as to obtain a target string with 512 binary bits.
[0037] The cyclic compression module is used to initialize the buffer register, divide the target string into blocks to obtain a 32-bit word of the first block, expand the 32-bit word of the first block to obtain a 32-bit word of the second block, and perform a second round of cyclic compression on the 32-bit word of the second block to obtain the binary variable value of the first block.
[0038] The embedding module is used to extract a binary variable value spanning a specified range from the first number of binary variable values to obtain a first 32-bit binary variable value, and to perform a modulo 2 operation on the first 32-bit binary variable value. 16 The product ID is obtained through calculation. After converting the product ID to hexadecimal, it is embedded into the corresponding field of the original EDID to obtain the unique EDID of the product device.
[0039] Compared with the prior art, the embodiments of this application have the following main technical effects: by converting, filling and cyclically compressing the original product model information, the unique identifier of each individual is extracted from the product signal information and embedded into the product ID field of the EDID, ensuring that the PnP ID in the EDID is globally unique and that different product IDs of the same model device are unique, accurately triggering the matching and installation of the corresponding driver, reducing the reliance on users to manually distinguish devices; it also avoids compatibility risks caused by driver matching problems when the device is connected to an operating system that supports PnP. Attached Figure Description
[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0041] Figure 1 This is a schematic diagram illustrating a specific implementation of a PnP-compatible dynamic EDID generation method according to the present invention.
[0042] Figure 2 for Figure 1 A schematic diagram of a specific implementation of S200;
[0043] Figure 3 for Figure 1 A schematic diagram of a specific implementation of S300;
[0044] Figure 4 for Figure 3 A schematic diagram of another specific implementation method following S320;
[0045] Figure 5 for Figure 4 A schematic diagram of a specific implementation of S340 in the diagram;
[0046] Figure 6 for Figure 5 A schematic diagram of a specific implementation of S360 in the diagram;
[0047] Figure 7 for Figure 1 A schematic diagram of a specific implementation of S400 in the diagram;
[0048] Figure 8 This is a schematic diagram of a PnP-compatible unique EDID dynamic generation device according to the present invention. Detailed Implementation
[0049] The technical solutions of this invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are all within the scope of protection of this invention.
[0050] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings of this application are intended to cover non-exclusive inclusion.
[0052] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0053] The purpose of this application is to propose a PnP-compatible method and apparatus for dynamically generating unique EDIDs, in order to solve the problem of identification confusion caused by the same manufacturer identification code in the EDIDs of different devices of the same model.
[0054] A PnP-compatible method for dynamically generating unique EDIDs, such as Figure 1 , Figure 1 This is a schematic diagram illustrating a specific implementation of a PnP-compatible dynamic EDID generation method according to the present invention; including:
[0055] S100. Obtain the product model information of the target device, preprocess the product model information and then perform ASCII encoding conversion to obtain the first string, and calculate the first binary length of the first string.
[0056] In this embodiment, PnP ID, short for Plug and Play ID, is a three-byte manufacturer identifier used to uniquely identify the manufacturer and specific product model of a computer hardware device. It is typically represented by a combination of three letters or numbers, in the format AAA (e.g., ANA is the code for Analog Devices, and DEL is the code for Dell). Sometimes, a format like AAA#### is also seen, where the first three letters represent the manufacturer, and the last four numbers represent the product model. It is a core component of Microsoft's "Plug and Play" system. When a new device (such as a graphics card, monitor, sound card, or printer) is plugged into a computer, the operating system (such as Windows) reads the device's PnP ID. The system can then find and automatically install the best matching driver from its driver library, thus achieving a "plug and play" experience without requiring manual user specification.
[0057] Therefore, PnP ID is a standardized solution established by Microsoft to ensure hardware compatibility and simplify the user installation process. EDID utilizes PnP ID to identify the monitor's manufacturer and model, thus working seamlessly with Microsoft's Plug and Play operating system to achieve automatic identification and configuration of display devices.
[0058] In this embodiment, assuming the product model information is: MTX3-88-PR, MTX3-88-PR is preprocessed, that is, spliced encoding, to obtain the original input for ASCII encoding conversion = product signal + individual unique identifier = "MTX3-88-PR" + "F611" = "MTX3-88-PRF611"; where F611 is the last 4 bits of the MAC address burned into each device at the factory, and the ASCII encoding conversion is shown in Table 1.
[0059] Table 1 ASCII Encoding Conversion Table for Product Model Information
[0060] character M T X 3 - 8 8 - P R F 6 1 1 ASCII code 77 84 88 51 45 56 56 45 80 82 70 54 49 49 8-bit binary 01001101 01010100 01011000 00110011 00101101 00111000 00111000 00101101 01010000 01010010 01000110 00110110 00110001 00110001
[0061] Each character of the first string corresponds to an 8-bit binary number. Then, calculate the original message length, which is the first binary length of the first string. After concatenation, the string has a total of 14 characters, with each character occupying 8 bits. Therefore, the original message length L = 14 × 8 = 112 bits (subsequent padding needs to be calculated based on this length).
[0062] S200. If the length of the first binary string is less than 512 bits, then the binary bits of the first string are padded to obtain a target string with 512 binary bits.
[0063] In one possible implementation, such as Figure 2 , Figure 2 for Figure 1 A schematic diagram of a specific implementation of S200 is shown below; S200 includes: S210, padding the end of the first string with 1s to obtain the second string; S220, padding the second string with 0s for a specified number of bits to obtain the third string; S230, appending the 64-bit binary number of the first string to the end of the third string to obtain the target string.
[0064] In this embodiment, because the length of the input message must be a multiple of 512 bits, a padding operation of "padding with 1s + padding with 0s + padding with length" is required. Specifically, the implementation is as follows:
[0065] Padding with 1: Add a "1" bit to the end of the original message, and the message length becomes 112 + 1 = 113 bits.
[0066] Padding with 0: Calculate the number of 0 bits to be padded. The formula is "number of 0 bits to be padded = 448 - (original length + 1) mod 512". Substituting mod 512 = 113, we get 448 - 113 = 335 bits. That is, after "padding with 1", add 335 "0" bits. At this time, the message length becomes 113 + 335 = 448 bits.
[0067] Padding: A 64-bit binary representation of the original message length L (112 bits) is appended to the end of the 448-bit message (SHA-1 specifies that the original length is stored in 64 bits; if less than 64 bits, leading zeros are padded). The 64-bit binary representation of 112 is 000000000000000 00000000 00000000 00000000 00000000 01110000. After padding, the total length is 448 + 64 = 512 bits, satisfying the input requirement of being a multiple of 512 bits.
[0068] S300: Initialize the buffer register, divide the target string into blocks to obtain a 32-bit word of the first block, expand the 32-bit word of the first block to obtain a 32-bit word of the second block, and perform a second round of cyclic compression on the 32-bit word of the second block to obtain the binary variable value of the first block.
[0069] In one possible implementation, such as Figure 3 , Figure 3 for Figure 1 A schematic diagram of a specific implementation of S300 is shown below; S300 includes: S310, initializing a specified number of 32-bit registers so that each 32-bit register is a specified hexadecimal value; S320, converting the hexadecimal value of each 32-bit register into a 32-bit binary value.
[0070] In this embodiment, five 32-bit registers (160 bits in total) are used to store the initial hash value, which is fixed as the following hexadecimal value and needs to be converted to a 32-bit binary value for later use:
[0071] A = 0x67452301, its binary value is: 01100111 01000101 00100011 00000001.
[0072] B=0xEFCDAB89, its binary value is: 11101111 11001101 10101011 10001001.
[0073] C=0x98BADCFE, its binary value is: 10011000 10111010 11011100 11111110.
[0074] D=0x10325476, its binary value is: 00010000 00110010 01010100 01110110.
[0075] E=0xC3D2E1F0, its binary value is: 11000011 11010010 11100001 11110000.
[0076] In this embodiment, since the padded message length is 512 bits (only one block, denoted as M0), this block needs to be compressed 80 times in a loop, with each round using a different logical function (f0-f 79 ), logical constants (K0-K) 79 The five registers (A, B, C, D, E) are updated via shift operations, and the specific process is as follows:
[0077] In one possible implementation, such as Figure 4 , Figure 4 for Figure 3 The diagram shows another specific implementation following S320; after S320, S300 further includes: S330, obtaining the 32-bit word of the first quantity block; S340, processing the 32-bit word of the first quantity block according to the formula:
[0078] W_t=(W_{t-3} XOR W_{t-8} XOR W_{t-14} XOR W_{t-16})<<<1 (1),
[0079] Perform a 1-bit circular left shift expansion to obtain the 32-bit word of the second quantity block;
[0080] Where W_t is the t-th 32-bit word (t ranges from 16 to 79, and "<<<" indicates a circular left shift).
[0081] In this embodiment, block expansion is performed. First, the 512-bit M0 is divided into 16 blocks of 32-bit words (W1-W2). 15 ), that is, the 32-bit word of the first quantity block, which is then expanded into 80 32-bit words (W0-W) using formula (1). 79 This forms the input sequence for compressed computation.
[0082] In one possible implementation, after S340, as... Figure 5 , Figure 5 for Figure 4 A schematic diagram of a specific embodiment of S340; S300 also includes:
[0083] S350: Assign the initial value of the 32-bit register to a temporary variable; S360: Calculate the logic function value and logic constant of the loop compression in segments using the temporary variable, and update the temporary variable using the left-shifted temporary variable, logic function value, logic constant, and the 32-bit word of the current block.
[0084] In this embodiment, the temporary variables are first assigned values: the initial values of the five registers are assigned to the temporary variables, namely a=A, b=B, c=C, d=D, e=E.
[0085] In one possible implementation, such as Figure 6 , Figure 6 for Figure 5 A schematic diagram of a specific implementation of S360; S360 includes:
[0086] S361. Obtain a temporary variable and use it to perform segmented calculations on the logic function value. S362. Obtain the logic constant through segmented assignment. S363. Obtain the temporary variable after left shift, the logic function value, the logic constant, and the 32-bit word of the current block. Use the temporary variable after left shift, the logic function value, the logic constant, and the 32-bit word of the current block to calculate and obtain the temporary logic value. Use the temporary logic value and the temporary variable after left shift to update the temporary variable.
[0087] S370. After the loop ends, the first number of binary variable values are calculated based on the updated temporary variable and the initial value of the 32-bit register.
[0088] In this embodiment,
[0089] For t ranging from 0 to 79, perform the following operations:
[0090] Calculate the logical function f_t:
[0091] When 0≤t≤19, f_t=(b AND c) OR ((NOT b) AND d),
[0092] When 20 ≤ t ≤ 39, f_t = b XOR c XOR d.
[0093] When 40≤t≤59, f_t=(b AND c) OR (b AND d) OR (c AND d),
[0094] When 60 ≤ t ≤ 79, f_t = b XOR c XOR d.
[0095] Calculate the logical constant K_t:
[0096] When 0 ≤ t ≤ 19, K_t = 0x5A827999.
[0097] When 20≤t≤39, K_t=0x6ED9EBA1,
[0098] When 40≤t≤59, K_t=0x8F1BBCDC,
[0099] When 60≤t≤79, K_t=0xCA62C1D6,
[0100] Calculate the temporary logical value T: T = (a <<< 5) + f_t + e + K_t + W_t ("+" represents 32-bit unsigned addition), update the temporary variables: e = d, d = c, c = (b <<< 30), b = a, a = T, update the 32-bit register value: After 80 loops, add the temporary variable to the initial value (32-bit unsigned addition) to obtain the final 160-bit binary value, which is the value of the first number of bits of the binary variable.
[0101] A_new=A+a, B_new=B+b, C_new=C+c, D_new=D+d, E_new=E+e;
[0102] The final binary variable value of the first number of bits = A_new (32 bits) + B_new (32 bits) + C_new (32 bits) + D_new (32 bits) + E_new (32 bits).
[0103] S400. Truncate the binary variable value of the first digit's binary variable value within a specified range to obtain the first 32-bit binary variable value. Perform modulo 2 on the first 32-bit binary variable value. 16 The calculation yields the product ID. After converting the product ID to hexadecimal, the corresponding field of the original EDID is embedded to obtain the unique EDID of the product device.
[0104] In one possible implementation, such as Figure 7 , Figure 7 for Figure 1 A schematic diagram of a specific implementation of S400; S400 includes: S410, converting the first 32-bit binary variable value into a decimal unsigned integer; S420, performing modulo 2 on the decimal unsigned integer. 16 Perform the calculation, obtain the remainder, and use the remainder as the product ID.
[0105] In this embodiment, the 160-bit binary value is divided into 5 segments, each 32 bits: 00110100 10101100 01011101 11000010 10011010 00111010 11001001 01010110 01100011 10100101 11101000 00111001 10110100 01001100 10001010 01100101 00011010 11001100 00101110 10110001
[0111] When truncating binary variable values within a specified range,
[0112] Extract bits 40-71 (32 bits) of the 160-bit hash value.
[0113] The SHA-1 160-bit hash value is numbered from left to right (the 1st bit is the most significant bit, and the 160th bit is the least significant bit). Bits 40-71 (a total of 32 bits) need to be extracted.
[0114] Taking the 160-bit binary hash value of S5 as an example, the 40th to 71st bits are extracted in segments:
[0115] The hash value is divided into 160-bit segments (each segment is 32 bits, for a total of 5 segments):
[0116] Segment 1 (bits 1-32): 00110100 10101100 01011101 11000010,
[0117] Segment 2 (digits 33-64): 10011010 00111010 11001001 01010110,
[0118] Segment 3 (bits 65-96): 01100011 10100101 11101000 00111001,
[0119] Positions 40-71 span both segment 2 and segment 3, with positions 33-64 belonging to segment 2 and positions 65-96 belonging to segment 3.
[0120] Precise truncation: Bits 40-64 (bits 8-32 of segment 2): 0 00111010 11001001 01010110 (25 bits), Bits 65-71 (bits 1-7 of segment 3): 0110001 (7 bits), Combined bits 40-71 (32 bits in total): 000 1110101100100101 0101100110001 (This needs to be precisely truncated based on the actual 160-bit hash value. Example 32-bit binary: 00011101 01100100 10101011 00110001).
[0121] In this embodiment, the first 32-bit binary variable value is converted into a decimal unsigned integer, that is, the 32-bit binary value is converted into a decimal integer, and the truncated 32-bit binary value is converted into a decimal unsigned integer (weighted summation from "high bit to low bit"):
[0122] Example 32-bit binary: 00011101 01100100 10101011 00110001 Decimal calculation yields decimal integer X = 493136689 (example value; actual calculation should be performed using precise 32-bit binary).
[0123] Then, execute mod2. 16 The operation (mod 65536) calculates the 2-byte Product ID:
[0124] Substitute the example decimal integer X = 493136689, and calculate:
[0125] 493136689 ÷ 65536 = 7524 remainder 43825
[0126] (Verification: 65536×7524=493092864, 493136689-493092864=43825)
[0127] The decimal Product ID is 43825. Then, the decimal Product ID is converted into a 2-byte hexadecimal value (embedded in EDID). The Product ID field of EDID (bytes 10-11) needs to be stored as a 2-byte hexadecimal value. Therefore, the decimal 43825 is converted into hexadecimal 0xAB31, and then split into 2 bytes: the high byte is 0xAB (corresponding to byte 10 of EDID), and the low byte is 0x31 (corresponding to byte 11 of EDID). It can be directly embedded into the EDID data structure.
[0128] In this application, EDID is a data structure generated by a display device (such as a monitor, television, or projector) and sent to a video source (such as a graphics card or laptop). It contains a series of information about the capabilities and attributes of the display device.
[0129] In one usage scenario, an HDMI matrix product has HDMI input and HDMI output interfaces. In an engineering application, the matrix connects to a laptop via the HDMI input interface and to a display device via the HDMI output interface. In this connection scenario, the HDMI input interface of the matrix acts as the "display device" for the video source. Therefore, it is necessary to write EDID data into the HDMI input interface of the matrix so that the source can identify it.
[0130] The following is an EDID used by a product in a scenario. According to the standard EDID data structure definition, the first 128 bytes are the basic block, and the last 128 bytes are the extended block.
[0131] Basic blocks:
[0132] 00 FF FF FF FF FF FF 00 04 21 00 00 66 00 00 00
[0133] 20 19 01 03 80 59 32 78 0A EE 91 A3 54 4C 99 26
[0134] 0F 50 54 BD EF 80 71 4F 81 C0 81 00 81 80 95 00
[0135] A9 C0 B3 00 01 01 08 E8 00 30 F2 70 5A 80 B0 58
[0136] 8A 00 C4 8E 21 00 00 1E 02 3A 80 18 71 38 2D 40
[0137] 58 2C 45 00 50 1D 74 00 00 1E 00 00 00 FD 00 17
[0138] 3D 0F 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
[0139] 00 48 44 4D 49 0A 20 20 20 20 20 20 20 20 01 D3
[0140] Expansion block:
[0141] 02 03 40 F1 55 61 10 1F 04 13 05 14 20 21 22 5D
[0142] 5E 5F 60 65 66 07 12 03 16 01 23 09 07 07 83 01
[0143] 00 00 00 6E 03 0C 00 10 00 B8 3C 21 10 80 01 02
[0144] 03 04 67 D8 5D C4 01 78 80 03 E2 00 4F E3 0F 01
[0145] E0 01 1D 80 D0 72 1C 16 20 10 2C 25 80 50 1D 74
[0146] 00 00 9E 66 21 56 AA 51 00 1E 30 46 8F 33 00 50
[0147] 1D 74 00 00 1E 00 00 00 00 00 00 00 00 00 00 00
[0148] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C1
[0149] In this application, after the above algorithm, two bytes of data AB 31 are obtained, which replace the 00 in Byte 10 and Byte 11 of the EDID. The change of these two bytes is then checked by CRC, which changes the D3 value of the 127th byte of the base block to F7, and a new EDID is generated as follows:
[0150] 00 FF FF FF FF FF FF 00 04 21 AB 31 66 00 00 00
[0151] 20 19 01 03 80 59 32 78 0A EE 91 A3 54 4C 99 26
[0152] 0F 50 54 BD EF 80 71 4F 81 C0 81 00 81 80 95 00
[0153] A9 C0 B3 00 01 01 08 E8 00 30 F2 70 5A 80 B0 58
[0154] 8A 00 C4 8E 21 00 00 1E 02 3A 80 18 71 38 2D 40
[0155] 58 2C 45 00 50 1D 74 00 00 1E 00 00 00 FD 00 17
[0156] 3D 0F 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
[0157] 00 48 44 4D 49 0A 20 20 20 20 20 20 20 20 01 F7
[0158] 02 03 40 F1 55 61 10 1F 04 13 05 14 20 21 22 5D
[0159] 5E 5F 60 65 66 07 12 03 16 01 23 09 07 07 83 01
[0160] 00 00 00 6E 03 0C 00 10 00 B8 3C 21 10 80 01 02
[0161] 03 04 67 D8 5D C4 01 78 80 03 E2 00 4F E3 0F 01
[0162] E0 01 1D 80 D0 72 1C 16 20 10 2C 25 80 50 1D 74
[0163] 00 00 9E 66 21 56 AA 51 00 1E 30 46 8F 33 00 50
[0164] 1D 74 00 00 1E 00 00 00 00 00 00 00 00 00 00 00
[0165] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C1.
[0166] In this embodiment, by converting, filling, and cyclically compressing the original product model information, a unique identifier is extracted from the product signal information and embedded into the product ID field of the EDID. This ensures that the PnP ID in the EDID is globally unique, and that different product IDs of the same model device are unique. This accurately triggers the matching and installation of the corresponding driver, reducing the reliance on users to manually distinguish devices. It also avoids compatibility issues caused by driver matching problems when the device is connected to an operating system that supports PnP.
[0167] To address the aforementioned issues, a PnP-compatible unique EDID dynamic generation device is provided, employing a PnP-compatible unique EDID dynamic generation method, such as... Figure 8 , Figure 8 This is a schematic diagram of a PnP-compatible unique EDID dynamic generation device according to the present invention; including:
[0168] The conversion module 501 is used to obtain the product model information of the target device, convert the product model information into ASCII encoding to obtain a first string, and calculate the first binary length of the first string.
[0169] The padding module 502 is used to pad the binary bits of the first string if the length of the first binary string is less than 512 bits, so as to obtain a target string with 512 binary bits.
[0170] The cyclic compression module 503 is used to initialize the buffer register, divide the target string into blocks to obtain a 32-bit word of the first block, expand the 32-bit word of the first block to obtain a 32-bit word of the second block, and perform a second round of cyclic compression on the 32-bit word of the second block to obtain the binary variable value of the first block.
[0171] Embedded module 504 is used to truncate the binary variable value of a specified range within the first number of bits to obtain a first 32-bit binary variable value, and then modulo 2 the first 32-bit binary variable value. 16 The calculation yields the product ID. After converting the product ID to hexadecimal, the corresponding field of the original EDID is embedded to obtain the unique EDID of the product device.
[0172] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for dynamically generating unique EDIDs compatible with PnP, characterized in that, include: S100. Obtain the product model information of the target device, preprocess the product model information and then perform ASCII encoding conversion to obtain the first string, and calculate the first binary length of the first string. S200. If the length of the first binary string is less than 512 bits, then the binary bits of the first string are padded to obtain a target string with 512 binary bits. S300. Initialize the buffer register, divide the target string into blocks to obtain a 32-bit word of the first quantity block, expand the 32-bit word of the first quantity block to obtain a 32-bit word of the second quantity block, and perform a second round of cyclic compression on the 32-bit word of the second quantity block to obtain the binary variable value of the first quantity. S400: Extract a binary variable value spanning a specified interval from the binary variable value of the first quantity bits to obtain a first 32-bit binary variable value; perform modulo 2 on the first 32-bit binary variable value. 16 The product ID is obtained through calculation. After converting the product ID to hexadecimal, it is embedded into the corresponding field of the original EDID to obtain the unique EDID of the product device.
2. The method for dynamically generating a unique EDID compatible with PnP according to claim 1, characterized in that, S200 includes: S210. Add 1 to the end of the first string to obtain the second string; S220. Perform a padding operation of zeros on the second string to obtain the third string; S230. Add the 64-bit binary number of the first string to the end of the third string to obtain the target string.
3. The method for dynamically generating a unique EDID compatible with PnP according to claim 1, characterized in that, The S300 includes: S310. Initialize a specified number of 32-bit registers, such that each of the 32-bit registers is a specified hexadecimal value; S320. Convert the hexadecimal value of each of the 32-bit registers to a 32-bit binary value.
4. The method for dynamically generating a unique EDID compatible with PnP according to claim 3, characterized in that, Following S320, S300 further includes: S330. Obtain the 32-bit word of the first quantity block; S340. The 32-bit word of the first quantity block is processed according to the formula: W_t=(W_{t-3} XOR W_{t-8} XOR W_{t-14} XOR W_{t-16})<<<1, Perform a 1-bit circular left shift expansion to obtain the 32-bit word of the second quantity block; Where W_t is the t-th 32-bit word, t ranges from 16 to 79, and "<<<" indicates a circular left shift.
5. The method for dynamically generating a unique EDID compatible with PnP according to claim 4, characterized in that, Following S340, S300 further includes: S350. Assign a temporary value to the initial value of the 32-bit register; S360. Calculate the logic function value and logic constant of the cyclic compression segment by segment using the temporary variable, and update the temporary variable using the left-shifted temporary variable, logic function value, logic constant and the 32-bit word of the current block; S370. After the loop ends, the binary variable value of the first number of bits is calculated based on the updated temporary variable and the initial value of the 32-bit register.
6. The method for dynamically generating a unique EDID compatible with PnP according to claim 5, characterized in that, The S360 includes: S361. Obtain the temporary variable and use the temporary variable to perform segmented calculations on the value of the logic function; S362. Obtain the logical constant by assigning values in segments; S363. Obtain the temporary variable after left shift, the logical function value, the logical constant, and the 32-bit word of the current block. Calculate the logical temporary value using the temporary variable after left shift, the logical function value, the logical constant, and the 32-bit word of the current block. Update the temporary variable using the logical temporary value and the temporary variable after left shift.
7. The method for dynamically generating a unique EDID compatible with PnP according to claim 1, characterized in that, The S400 includes: S410. Convert the first 32-bit binary variable value into a decimal unsigned integer; S420, Perform modulo 2 on the unsigned decimal integer. 16 The calculation is performed to obtain the remainder, and the remainder is used as the product ID.
8. A PnP-compatible unique EDID dynamic generation device, employing the PnP-compatible unique EDID dynamic generation method according to any one of claims 1-7, characterized in that, include: The conversion module is used to obtain the product model information of the target device, convert the product model information into ASCII encoding to obtain a first string, and calculate the first binary length of the first string. The padding module is used to pad the binary bits of the first string if the length of the first binary string is less than 512 bits, so as to obtain a target string with 512 binary bits. The cyclic compression module is used to initialize the buffer register, divide the target string into blocks to obtain a 32-bit word of the first block, expand the 32-bit word of the first block to obtain a 32-bit word of the second block, and perform a second round of cyclic compression on the 32-bit word of the second block to obtain the binary variable value of the first block. The embedding module is used to extract a binary variable value spanning a specified range from the first number of binary variable values to obtain a first 32-bit binary variable value, and to perform a modulo 2 operation on the first 32-bit binary variable value. 16 The product ID is obtained through calculation. After converting the product ID to hexadecimal, it is embedded into the corresponding field of the original EDID to obtain the unique EDID of the product device.