Sub-pixel, display device and electronic device

Abstract

The invention discloses a sub-pixel, a display device and an electronic device. The sub-pixel includes a first transistor, a second transistor, and a third transistor, and a light emitting element. The first transistor is connected between a first node receiving a first driving power and a second node to generate a driving current, and includes a control electrode connected to a third node. The second transistor is connected between the data line and the first node, and is turned on in response to a first scan signal. The third transistor is connected between the second node and a third node, and is turned on in response to a first scan signal. The light emitting element receives the driving current to emit light.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0080168, filed with the Korean Intellectual Property Office on June 20, 2024, and Korean Patent Application No. 10-2024-0108383, filed with the Korean Intellectual Property Office on August 13, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to subpixels, display devices including subpixels, and electronic devices including display devices. Background Technology

[0004] With the development of information technology, the importance of display devices as the connection medium between users and information has become increasingly prominent. Therefore, the use of display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) has increased.

[0005] Head-mounted displays (HMDs) have recently been developed. These are displays worn by users in the form of glasses or helmets to enable virtual reality (VR) or augmented reality (AR) that is focused at a distance close to the eyes. Displays that can reduce the size of the dead space area where the scanning actuators are located can benefit head-mounted displays and other electronic devices. Summary of the Invention

[0006] This disclosure provides subpixels that reduce the size of the dead space region, a display device including subpixels, and an electronic device including the display device.

[0007] The sub-pixel implementation includes: a first transistor connected between a first node and a second node receiving a first driving power to generate a driving current, and including a control electrode connected to a third node; a second transistor connected between a data line and the first node, and turned on in response to a first scan signal; a third transistor connected between the second node and the third node, and turned on in response to the first scan signal; and a light-emitting element receiving the driving current to emit light.

[0008] Each of the second and third transistors can be an NMOS transistor.

[0009] The sub-pixel may further include a fourth transistor connected between the third node and a first power line providing the first initialization power, and turned on in response to a second scan signal.

[0010] The sub-pixel may further include: a fifth transistor connected between the first node and a second power line providing the voltage of the first driving power, and turned on in response to an emission control signal; and a sixth transistor connected between the second node and the fourth node, and turned on in response to an emission control signal, wherein the light-emitting element may be connected between the fourth node and a third power line providing the second driving power.

[0011] The sub-pixel may further include: a seventh transistor connected between the fourth node and a fourth power line providing a second initialization power voltage, and turned on in response to a third scan signal; and an eighth transistor connected between the first node and a fifth power line providing a bias power voltage, and turned on in response to a third scan signal.

[0012] Each of the second, third, and fourth transistors may be an NMOS transistor, and each of the first, fifth, sixth, seventh, and eighth transistors may be a PMOS transistor.

[0013] In operation, a frame may include a non-transmit period and a transmit period. The non-transmit period may include a first period, a second period, and a third period. In the first period, the second scan signal may have a high logic level. In the second period following the first period, the first scan signal may have a high logic level. In the third period following the second period, the third scan signal may have a low logic level.

[0014] An embodiment of the display device includes: a sub-pixel, the sub-pixel including a first transistor and a light-emitting element, the first transistor being connected between a first node and a second node receiving a first driving power to generate a driving current, the first transistor including a control electrode connected to a third node, the sub-pixel being connected to a first scan line, an emission control line, and a data line; an emission driver supplying an emission control signal to the emission control line; a first scan driver supplying a first scan signal to the first scan line; and a data driver supplying a data signal to the data line, wherein the first scan signal controls the timing of the data signal being supplied to the first node and the timing of the connection between the second node and the third node.

[0015] The sub-pixel may further include: a second transistor connected between the data line and the first node and turned on in response to the first scan signal; and a third transistor connected between the second node and the third node and turned on in response to the first scan signal, wherein the light-emitting element receives a driving current to emit light.

[0016] Each of the second and third transistors can be an NMOS transistor.

[0017] The display device may further include: a second scan driver that supplies a second scan signal to a second scan line, wherein the sub-pixel may further include: a fourth transistor connected between a third node and a first power line that provides first initialization power, and turned on in response to the second scan signal.

[0018] The sub-pixel may further include: a fifth transistor connected between the first node and a second power line providing the voltage of the first driving power, and turned on in response to an emission control signal; and a sixth transistor connected between the second node and the fourth node, and turned on in response to an emission control signal, wherein the light-emitting element may be connected between the fourth node and a third power line providing the second driving power.

[0019] The display device may further include: a third scan driver that supplies a third scan signal to a third scan line, wherein the sub-pixel may further include: a seventh transistor connected between a fourth node and a fourth power line providing a second initialization power voltage and turned on in response to the third scan signal; and an eighth transistor connected between a first node and a fifth power line providing a bias power voltage and turned on in response to the third scan signal.

[0020] Each of the second, third, and fourth transistors may be an NMOS transistor, and each of the first, fifth, sixth, seventh, and eighth transistors may be a PMOS transistor.

[0021] An embodiment of the electronic device includes: a processor that provides input image data; and a display device that displays an image based on the input image data, wherein the display device includes: a sub-pixel including a first transistor and a light-emitting element, the first transistor being connected between a first node and a second node receiving a first driving power to generate a driving current, the first transistor including a control electrode connected to a third node, the sub-pixel being connected to an i-th first scan line, an (i-1)-th first scan line, an i-th transmit control line, and a j-th data line; a transmit driver that supplies an i-th transmit control signal to the i-th transmit control line; a first scan driver that supplies an i-th first scan signal to the i-th first scan line and supplies an (i-1)-th first scan signal to the (i-1)-th first scan line; and a data driver that supplies a data signal to the j-th data line, wherein the i-th first scan signal controls the timing of the data signal being supplied to the first node and the timing of the connection between the second node and the third node, and i is a natural number greater than 1, and j is a natural number greater than 0.

[0022] The sub-pixel further includes: a second transistor connected between the j-th data line and the first node, and turned on in response to the i-th first scan signal; and a third transistor connected between the second node and the third node, and turned on in response to the i-th first scan signal, wherein the light-emitting element receives a driving current to emit light.

[0023] The sub-pixel also includes a fourth transistor connected between the third node and the first power line providing the first initialization power, and turned on in response to the (i-1)th first scan signal.

[0024] The sub-pixel also includes: a fifth transistor connected between the first node and a second power line providing the voltage of the first driving power, and turned on in response to the i-th emission control signal; and a sixth transistor connected between the second node and the fourth node, and turned on in response to the i-th emission control signal, wherein the light-emitting element is connected between the fourth node and a third power line providing the second driving power.

[0025] The electronic device further includes: a second scan driver that supplies the i-th second scan signal to the i-th second scan line, wherein the sub-pixel further includes: a seventh transistor connected between the fourth node and a fourth power line providing a second initialization power voltage, and turned on in response to the i-th second scan signal; and an eighth transistor connected between the first node and a fifth power line providing a bias power voltage, and turned on in response to the i-th second scan signal.

[0026] Each of the second, third, and fourth transistors is an NMOS transistor, and each of the first, fifth, sixth, seventh, and eighth transistors is a PMOS transistor.

[0027] According to the embodiments of the present disclosure, the size of the area in which the scan driver is arranged can be reduced by integrating a scan driver that controls the transistors included in the sub-pixels.

[0028] However, the effects of this disclosure are not limited to those described above, and various extensions may be made without departing from the spirit and scope of this disclosure. Attached Figure Description

[0029] Figure 1 The illustration shows a display device according to an embodiment of the present disclosure.

[0030] Figure 2 This is a circuit diagram illustrating an implementation of the sub-pixel.

[0031] Figure 3 This is a timing diagram of an example of the signals supplied to the pixels during the frame period.

[0032] Figure 4 The illustration shows a display device according to an embodiment of the present disclosure.

[0033] Figure 5 This is a circuit diagram illustrating an implementation of the sub-pixel.

[0034] Figure 6 This is a timing diagram of an example of the signals supplied to the pixels during the frame period.

[0035] Figure 7 The illustration shows a display device according to an embodiment of the present disclosure.

[0036] Figure 8 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0037] Figure 9 The illustration shows one of them. Figure 8 An example of an electronic device is implemented as a smartphone. Detailed Implementation

[0038] In the following description, the present disclosure will be more fully described with reference to the accompanying drawings, which illustrate embodiments thereof. As will be appreciated by those skilled in the art, the described embodiments can be modified in various ways without departing from the spirit and scope of the present disclosure.

[0039] In the accompanying drawings, parts or portions not related to this disclosure have been omitted to clarify the description of this disclosure, and similar reference numerals designate similar constituent elements throughout the specification.

[0040] Throughout this specification, when describing an element as "connected" to another element, this includes not only "direct connection" but also "indirect connection" where another device is intermediate. The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the scope of the invention. Throughout this specification, unless explicitly stated otherwise, the words "comprise" and "include" (and variations such as "comprises" or "comprising") are to be understood as implying the inclusion of the stated element but not excluding any other element. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used in this article, the word “or” means logical “or”, so unless the context otherwise indicates, the expression “A, B or C” means “A and B and C”, “A and B but no C”, “A and C but no B”, “B and C but no A”, “A but no B and no C”, “B but no A and no C”, and “C but no A and no B”.

[0041] Although the terms first, second, etc., may be used herein to describe various constituent elements, these constituent elements should not be limited by these terms. These terms are used to distinguish one constituent element from another. Therefore, without departing from the teachings of this disclosure, the first constituent element discussed below may be referred to as the second constituent element.

[0042] Figure 1 The illustration shows a display device according to an embodiment of the present disclosure.

[0043] The display device 10 can display images at various frame rates (refresh rate, drive frequency, or screen refresh rate) depending on operating conditions. Frame rate is the frequency at which data voltage is substantially written to the drive transistors of pixels PX per second. For example, frame rate is also referred to as screen refresh rate or screen refresh frequency, and represents the frequency at which the display screen plays back images per second.

[0044] In this embodiment, the display device 10 can adjust the output frequencies of the scan driver 200 and the transmit driver 300, as well as the output frequency of the corresponding data driver 400, according to driving conditions. For example, the display device 10 can display images corresponding to various frame frequencies from 1 Hz to 120 Hz. However, this is just an example, and the display device 10 can display images at frame frequencies of 120 Hz or higher (e.g., 240 Hz or 480 Hz).

[0045] The display device 10 may include a display panel 100, a scan driver 200, a transmit driver 300, a data driver 400, and a timing controller 500.

[0046] The display panel 100 may include a display area in which pixels PX are arranged and a non-display area arranged in a peripheral area (e.g., an edge area) of the display area. Pixels PX may be arranged in the display area. Components for controlling pixels PX may be arranged in the non-display area. For example, wiring connected to sub-pixels SP, such as first scan lines S1 to nth scan lines Sn and first data lines DL1 to mth data lines DLm, may be arranged in the non-display area. m and n may be integers greater than 1.

[0047] At least one of the scan driver 200, transmit driver 300, data driver 400 and timing controller 500 may be arranged in the non-display area of ​​the display panel 100.

[0048] Each of a plurality of pixels PX may include a plurality of subpixels SP. Each of the plurality of subpixels SP may emit light of a color. For example, a pixel PX may include a red subpixel that emits red light (e.g., a first color), a green subpixel that emits green light (e.g., a second color), and a blue subpixel that emits blue light (e.g., a third color). However, the color emitted by the subpixel SP and the type or number of subpixels SP are not limited thereto.

[0049] According to the implementation method, sub-pixels SP can be based on stripes or pentiles. The arrangement of the structure is possible, but this disclosure is not limited thereto, and various examples may be applied to this disclosure.

[0050] The timing controller 500 can receive input image data IRGB and control signals (e.g., synchronization signal Sync and data enable signal DE) from a host system such as an application processor (AP) via a predetermined interface.

[0051] The timing controller 500 can generate a first control signal SCS, a second control signal ECS, and a third control signal DCS based on the input image data IRGB, a synchronization signal Sync (e.g., a vertical synchronization signal, a horizontal synchronization signal, etc.), a data enable signal DE, and a clock signal. The first control signal SCS can be supplied to the scan driver 200, the second control signal ECS can be supplied to the transmit driver 300, and the third control signal DCS can be supplied to the data driver 400. The timing controller 500 can rearrange the input image data IRGB to supply it to the data driver 400.

[0052] The scan driver 200 can receive a first control signal SCS from the timing controller 500 and can supply scan signals to the first scan lines S1 to the nth scan lines Sn based on the first control signal SCS.

[0053] The scan signal can be set to a gate on-level corresponding to the type of transistor to which the corresponding scan signal is supplied. When a scan signal is supplied, the transistor receiving the scan signal can be turned on. For example, the gate on-level of the scan signal supplied to a P-channel metal-oxide-semiconductor (PMOS) transistor can be logic low, and the gate on-level of the scan signal supplied to an N-channel metal-oxide-semiconductor (NMOS) transistor can be logic high. In the following text, "supply scan signal" can be understood as supplying the scan signal at a logic level used to turn on the transistor controlled by the scan signal.

[0054] The transmit driver 300 can supply transmit control signals to the first transmit control line E1 through the nth transmit control line En based on the second control signal ECS. For example, the transmit control signals can be supplied sequentially to the first transmit control line E1 through the nth transmit control line En.

[0055] The emit control signal can be set to a gate turn-off voltage (e.g., a high voltage). The transistor receiving the emit control signal is turned off when the emit control signal is supplied, and can be turned on under other conditions. In the following text, "supply emit control signal" can be understood as supplying the emit control signal at a logic level that turns off the transistor controlled by the emit control signal.

[0056] exist Figure 1 In this disclosure, for better understanding and ease of description, each of the scan driver 200 and the transmit driver 300 is shown as a single configuration, but this disclosure is not limited thereto. Furthermore, at least one of the scan driver 200 and the transmit driver 300 may be integrated into a single drive circuit, module, etc.

[0057] The data driver 400 can receive a third control signal DCS and digital image data RGB from the timing controller 500. The data driver 400 can convert the digital image data RGB into an analog data signal (data voltage). The data driver 400 can supply the analog data signal to the first data line DL1 to the m-th data line DLm in response to the third control signal DCS.

[0058] In an embodiment, the display device 10 may further include a power supply. The power supply may supply the voltages of a first driving power VDD, a second driving power VSS, a first power Vint1 (or a first initialization power), a second power Vint2 (or a second initialization power), and a third power Vbs (or a bias power) used to drive the pixel PX to the display panel 100.

[0059] Figure 2 This is a circuit diagram illustrating an implementation of the sub-pixel.

[0060] exist Figure 2 In order to better understand and facilitate description, the sub-pixel SPij, which is arranged on the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line DLj, is illustrated (where i is a natural number greater than 1 and j is a natural number greater than 0).

[0061] refer to Figure 1 and Figure 2 The sub-pixel SPij may include a light-emitting element LD, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8, as well as a storage capacitor Cst.

[0062] The first electrode (anode or cathode) of the light-emitting element LD can be connected to the sixth transistor M6, and the second electrode (cathode or anode) of the light-emitting element LD can be connected to the third power line PL3 that provides the second driving power VSS. The light-emitting element LD can generate light with a predetermined brightness corresponding to the amount of current supplied from the first transistor M1.

[0063] In one embodiment, the light-emitting element LD may be an organic light-emitting diode including an organic light-emitting layer. In another embodiment, the light-emitting element LD may be an inorganic light-emitting element made of inorganic materials. In yet another embodiment, the light-emitting element LD may be a light-emitting element made of a composite of inorganic and organic materials. The light-emitting element LD may have a form in which multiple inorganic light-emitting elements are connected in parallel or series between a third power line PL3 providing the second driving power VSS and a sixth transistor M6.

[0064] The first electrode of the first transistor M1 (or driving transistor) can be connected to the first node N1, and the second electrode of the first transistor M1 can be connected to the second node N2. The gate electrode of the first transistor M1 can be connected to the third node N3. The first node N1 can receive the first driving power VDD through the fifth transistor M5.

[0065] The first transistor M1 can control the amount of current flowing from the second power line PL2, which provides the first drive power VDD, through the light-emitting element LD to the third power line PL3, which provides the second drive power VSS, in response to the voltage of the third node N3. For this purpose, the first drive power VDD can be set to a higher voltage than the second drive power VSS.

[0066] The second transistor M2 can be connected between the j-th data line DLj (hereinafter referred to as the data line) and the first node N1. The gate electrode of the second transistor M2 can be connected to the i-th first scan line S1i (hereinafter referred to as the first scan line). When the first scan signal is supplied to the first scan line S1i, the second transistor M2 can be turned on to electrically connect the data line DLj and the first node N1.

[0067] That is, the timing of the data signal being provided to the first node N1 can be controlled by providing a first scan signal to the first scan line S1i.

[0068] The third transistor M3 can be connected between the second electrode (second node N2) and the third node N3 of the first transistor M1. The gate electrode of the third transistor M3 can be connected to the first scan line S1i. When the first scan signal is supplied to the first scan line S1i, the third transistor M3 can be turned on to electrically connect the second electrode (second node N2) and the third node N3 of the first transistor M1.

[0069] The timing of the connection between the second electrode (e.g., drain electrode) and the gate electrode of the first transistor M1 can be controlled by providing a first scan signal to the first scan line S1i. When the third transistor M3 is turned on, the first transistor M1 can be diode connected.

[0070] The fourth transistor M4 can be connected between the third node N3 and the first power line PL1 that provides the first power Vint1 (hereinafter referred to as the first initialization power).

[0071] The gate electrode of the fourth transistor M4 can be connected to the i-th second scan line S2i (hereinafter referred to as the second scan line).

[0072] When the second scan signal is supplied to the second scan line S2i, the fourth transistor M4 can be turned on to supply the voltage of the first initialization power Vint1 to the third node N3. Here, the voltage of the first initialization power Vint1 can be set to a voltage lower than the lowest level voltage of the data signal supplied to the data line DLj.

[0073] Therefore, by turning on the fourth transistor M4, the gate voltage of the first transistor M1 can be initialized to the voltage of the first initialization power Vint1.

[0074] The fifth transistor M5 can be connected between the second power line PL2, which provides the first drive power VDD, and the first node N1. The gate electrode of the fifth transistor M5 can be connected to the i-th emitter control line Ei (hereinafter referred to as the emitter control line). The fifth transistor M5 is turned off when the emitter control signal EM is supplied to the emitter control line Ei, and turned on under other conditions.

[0075] When the fifth transistor M5 is turned on, the voltage of the first drive power VDD can be supplied to the first node N1.

[0076] The sixth transistor M6 can be connected between the second electrode (second node N2) of the first transistor M1 and the first electrode (fourth node N4) of the light-emitting element LD. The gate electrode of the sixth transistor M6 can be connected to the emission control line Ei. The sixth transistor M6 can be controlled in substantially the same way as the fifth transistor M5.

[0077] The seventh transistor M7 can be connected between the first electrode (fourth node N4) of the light-emitting element LD and the fourth power line PL4 that provides the second power Vint2 (hereinafter referred to as the second initialization power). In an embodiment, the gate electrode of the seventh transistor M7 can be connected to the i-th third scan line S3i (hereinafter referred to as the third scan line).

[0078] When the third scan signal is supplied to the third scan line S3i, the seventh transistor M7 can be turned on to supply the voltage of the second initialization power Vint2 to the first electrode of the light-emitting element LD.

[0079] The eighth transistor M8 can be connected between the first node N1 and the fifth power line PL5, which provides the voltage of the third power line Vbs. The eighth transistor M8 can be turned on in response to the third scan signal supplied to the third scan line S3i, and can supply the voltage of the third power line Vbs to the first node N1. Here, the voltage of the third power line Vbs and the timing of its supply to the first node N1 can be controlled by the third scan signal.

[0080] In this implementation, the voltage of the third power Vbs may be less than the voltage of the first driving power VDD, and may be greater than the voltage of the second driving power VSS.

[0081] Therefore, by turning on the eighth transistor M8, a predetermined voltage can be applied to the first electrode (e.g., the source electrode) of the first transistor M1. In this case, when the third transistor M3 is in the off state, the first transistor M1 can have a conduction bias state (where the first transistor M1 can be turned on, which may be referred to as conduction bias).

[0082] A storage capacitor Cst can be connected between the second power line PL2 and the third node N3. The storage capacitor Cst can store the voltage applied to the third node N3.

[0083] In this embodiment, the first transistor M1, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 may be formed as polycrystalline silicon semiconductor transistors. For example, the first transistor M1, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 may include a polycrystalline silicon semiconductor layer formed by a low-temperature polycrystalline silicon (LTPS) process as an active layer (which may be referred to as a channel).

[0084] Furthermore, the first transistor M1, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 can be P-type transistors (e.g., PMOS transistors). Therefore, the gate turn-on voltage for turning on the first transistor M1, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 can be at a low logic level.

[0085] The second transistor M2, the third transistor M3, and the fourth transistor M4 can be formed as oxide semiconductor transistors. For example, the second transistor M2, the third transistor M3, and the fourth transistor M4 can be N-type oxide semiconductor transistors (e.g., NMOS transistors), and may include an oxide semiconductor layer as an active layer. Therefore, the gate on-state voltage for turning on the second transistor M2, the third transistor M3, and the fourth transistor M4 can be at a high logic level.

[0086] Since the gate turn-on voltages for the second transistor M2 and the third transistor M3 are the same at high logic levels, the second transistor M2 and the third transistor M3 can be controlled by a signal (e.g., a first scan signal). Therefore, the turn-on periods of the second transistor M2 and the third transistor M3 can be the same.

[0087] Furthermore, since the second transistor M2 is formed as an NMOS transistor, the leakage current caused by the second transistor M2 can be reduced compared to the case where the second transistor M2 is formed as a PMOS transistor.

[0088] Figure 3 This is a timing diagram of an example of the signals supplied to the pixels during the frame period.

[0089] refer to Figure 3 A frame may include a non-emission period (NEP) and an emission period (EP). For example, a light-emitting element (LD) may emit light during the emission period (EP). The non-emission period (NEP) may include a first period (P1), a second period (P2), and a third period (P3).

[0090] During the non-emit cycle (NEP), the transmit control signal EM can be supplied to the transmit control line Ei. Therefore, the fifth transistor M5 and the sixth transistor M6 can be turned off during the non-emit cycle (NEP).

[0091] During the first cycle P1, the scan driver 200 can supply the second scan signal GC to the second scan line S2i. When the second scan signal GC is supplied, the fourth transistor M4 can be turned on. Therefore, the gate voltage of the first transistor M1 can be initialized to the voltage of the first initialization power Vint1.

[0092] In the second cycle P2, the scan driver 200 can supply the first scan signal GW to the first scan line S1i. When the first scan signal GW is supplied, the second transistor M2 and the third transistor M3 can be turned on. Therefore, since the data signal supplied to the data line DLj is supplied to the first node N1 and the first transistor M1 is diode-connected, data writing and threshold voltage compensation of the first transistor M1 can be performed.

[0093] The second transistor M2 and the third transistor M3 can be turned on for the second period P2. That is, after data is written, the threshold voltage compensation operation of the first transistor M1 can be omitted. Therefore, defects that may occur due to the threshold voltage compensation of the first transistor M1 after data is written can be avoided.

[0094] In the third cycle P3, the scan driver 200 can supply the third scan signal GB to the third scan line S3i. When the third scan signal GB is supplied, the seventh transistor M7 and the eighth transistor M8 can be turned on.

[0095] With the eighth transistor M8 turned on, the voltage of the third power Vbs can be supplied to the first node N1. With the seventh transistor M7 turned on, the voltage of the second initialization power Vint2 can be supplied to the fourth node N4.

[0096] Subsequently, during the transmission cycle EP, the transmit driver 300 can stop supplying the transmission control signal EM to the transmission control line Ei. Therefore, the fifth transistor M5 and the sixth transistor M6 can be turned on, and the drive current based on the data signal can be supplied to the light-emitting element LD through the first transistor M1. The light-emitting element LD can emit light with a brightness corresponding to the drive current.

[0097] Figure 4 The illustration shows a display device according to an embodiment of the present disclosure.

[0098] refer to Figure 1 and Figure 4 The scan driver 200 may include a first scan driver 210, a second scan driver 220 and a third scan driver 230. Figure 1 The display panel 100, transmit driver 300, and data driver 400 are similar to Figure 4 The display panel 100, the transmitter driver 300, and the data driver 400 are included, so repeated descriptions can be omitted.

[0099] The timing controller 500 can generate a first scan control signal SCS1, a second scan control signal SCS2, and a third scan control signal SCS3.

[0100] The first scan control signal SCS1 can be supplied to the first scan driver 210, the second scan control signal SCS2 can be supplied to the second scan driver 220, and the third scan control signal SCS3 can be supplied to the third scan driver 230.

[0101] The first scan control signal SCS1 may include a first scan start pulse and a clock signal. The first scan start pulse controls the first timing of the scan signal output from the first scan driver 210. The clock signal can be used to shift the first scan start pulse.

[0102] The second scan control signal SCS2 may include a second scan start pulse and a clock signal. The second scan start pulse controls the first timing of the scan signal output from the second scan driver 220. The clock signal can be used to shift the second scan start pulse.

[0103] The third scan control signal SCS3 may include a third scan start pulse and a clock signal. The third scan start pulse controls the first timing of the scan signal output from the third scan driver 230. The clock signal can be used to shift the third scan start pulse.

[0104] The first scan driver 210 may receive a first scan control signal SCS1 from the timing controller 500 and supply scan signals (e.g., first scan signals) to the first scan lines S11 to S1n based on the first scan control signal SCS1.

[0105] For example, the first scan driver 210 can sequentially supply first scan signals to first scan lines S11 to S1n. When the first scan signals are supplied sequentially, sub-pixels SP are selected in horizontal line units (or pixel row units), and data signals can be supplied to the sub-pixels SP. That is, the first scan signals can be signals used for data writing.

[0106] refer to Figure 2 The second transistor M2 and the third transistor M3, which receive the first scan signal, can be set to the on state when the first scan signal is supplied.

[0107] That is, the second transistor M2 and the third transistor M3 can be integrated and controlled by a single first scan driver 210, instead of the second transistor M2 and the third transistor M3 being controlled separately by separate scan drivers.

[0108] Therefore, the number of scan drivers required is reduced, thereby reducing the non-display area (e.g., dead zone) in which the scan drivers are arranged.

[0109] The second scan driver 220 may receive a second scan control signal SCS2 from the timing controller 500 and supply a scan signal (e.g., a second scan signal) to the second scan lines S21 to S2n based on the second scan control signal SCS2.

[0110] For example, the second scan driver 220 can sequentially supply the second scan signal to the second scan lines S21 to S2n. When the second scan signal is supplied, the sub-pixel SP can perform threshold voltage compensation.

[0111] refer to Figure 2 The fourth transistor M4, which receives the second scan signal, can be set to the on state when the second scan signal is supplied.

[0112] The third scan driver 230 may receive a third scan control signal SCS3 from the timing controller 500 and supply scan signals (e.g., third scan signals) to the third scan lines S31 to S3n based on the third scan control signal SCS3. For example, the third scan driver 230 may sequentially supply the third scan signals to the third scan lines S31 to S3n.

[0113] refer to Figure 2 The seventh transistor M7 and the eighth transistor M8, which receive the third scan signal, can be set to the on state when the third scan signal is supplied.

[0114] Figure 5 This is a circuit diagram illustrating an implementation of the sub-pixel.

[0115] exist Figure 5 In order to better understand and facilitate description, the sub-pixel SPij, which is arranged on the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line DLj, is illustrated (where i is a natural number greater than 1 and j is a natural number greater than 0).

[0116] refer to Figure 5 The sub-pixel SPij may include a light-emitting element LD, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8, as well as a storage capacitor Cst. Because... Figure 5 The sub-pixel SPij is similar to Figure 2 The sub-pixels SPij are omitted, thus redundant descriptions are omitted.

[0117] The second transistor M2 can be connected between the j-th data line DLj (hereinafter referred to as the data line) and the first node N1. The gate electrode of the second transistor M2 can be connected to the i-th first scan line S1i. When the i-th first scan signal GW[i] is supplied to the i-th first scan line S1i, the second transistor M2 can be turned on to electrically connect the data line DLj and the first node N1.

[0118] The third transistor M3 can be connected between the second electrode (second node N2) of the first transistor M1 and the third node N3. The gate electrode of the third transistor M3 can be connected to the i-th first scan line S1i. When the i-th first scan signal GW[i] is supplied to the i-th first scan line S1i, the third transistor M3 can be turned on to electrically connect the second electrode of the first transistor M1 and the third node N3.

[0119] The fourth transistor M4 can be connected between the third node N3 and the second power line PL2 that provides the first initialization power Vint1. The gate electrode of the fourth transistor M4 can be connected to the (i-1)th first scan line S1[i-1].

[0120] That is, the gate electrode of the fourth transistor M4 can be controlled in the same way as the second transistor M2 and the third transistor M3 of the sub-pixel arranged in the (i-1)th horizontal line (or the (i-1)th pixel row).

[0121] When the (i-1)th first scan signal GW[i-1] is supplied to the (i-1)th first scan line S1[i-1], the fourth transistor M4 can be turned on to supply the voltage of the first initialization power Vint1 to the third node N3.

[0122] Since the gate turn-on voltages used to turn on the second transistor M2 to the fourth transistor M4 are the same at the high logic level, the scan signals used to control the second transistor M2 to the fourth transistor M4 can be integrated into the first scan signal.

[0123] The fifth transistor M5 can be connected between the first power line PL1, which provides the first drive power VDD, and the first node N1. The gate electrode of the fifth transistor M5 can be connected to the i-th transmit control line Ei. The fifth transistor M5 is turned off when the transmit control signal EM is supplied to the i-th transmit control line Ei, and turned on under other conditions.

[0124] The sixth transistor M6 can be connected between the second electrode (second node N2) of the first transistor M1 and the first electrode (fourth node N4) of the light-emitting element LD. The gate electrode of the sixth transistor M6 can be connected to the i-th emission control line Ei. The sixth transistor M6 can be controlled in substantially the same way as the fifth transistor M5.

[0125] The seventh transistor M7 can be connected between the first electrode (fourth node N4) of the light-emitting element LD and the third power line PL3 that provides the second power Vint2. In an embodiment, the gate electrode of the seventh transistor M7 can be connected to the i-th second scan line S2i.

[0126] When the second scan signal GB is supplied to the i-th second scan line S2i, the seventh transistor M7 can be turned on to supply the voltage of the second initialization power Vint2 to the first electrode of the light-emitting element LD.

[0127] The eighth transistor M8 can be connected between the first node N1 and the fourth power line PL4, which provides the voltage of the third power Vbs. The eighth transistor M8 can be turned on in response to the second scan signal GB supplied to the i-th second scan line S2i, and can supply the voltage of the third power Vbs to the first node N1.

[0128] Figure 6 This is a timing diagram of an example of the signals supplied to the pixels during the frame period.

[0129] refer to Figure 6 A frame may include a non-emission period (NEP) and an emission period (EP). For example, a light-emitting element (LD) may emit light during the emission period (EP). The non-emission period (NEP) may include a first period (P1), a second period (P2), and a third period (P3).

[0130] Figure 6 Non-launch-periodic NEP and launch-periodic EP are similar Figure 5 The non-emission period (NEP) and the emission period (EP) are omitted, thus redundant descriptions are omitted.

[0131] During the non-emit cycle (NEP), the transmit control signal EM can be supplied to the i-th transmit control line Ei. Therefore, the fifth transistor M5 and the sixth transistor M6 can be turned off during the non-emit cycle (NEP).

[0132] In the first cycle P1, the scan driver 200 can supply the (i-1)th first scan signal GW[i-1] to the (i-1)th first scan line S1[i-1]. When the (i-1)th first scan signal GW[i-1] is supplied, the fourth transistor M4 can be turned on. Therefore, the gate voltage of the first transistor M1 can be initialized to the voltage of the first initialization power Vint1.

[0133] In the second cycle P2, the scan driver 200 can supply the i-th first scan signal GW[i] to the i-th first scan line S1i. When the i-th first scan signal GW[i] is supplied, the second transistor M2 and the third transistor M3 can be turned on. Therefore, since the data signal supplied to the data line DLj is supplied to the first node N1 and the first transistor M1 is diode connected, data writing and threshold voltage compensation of the first transistor M1 can be performed.

[0134] Figure 7 The illustration shows a display device according to an embodiment of the present disclosure.

[0135] refer to Figure 1 and Figure 7 The scan driver 200 may include a first scan driver 210 and a second scan driver 220. Figure 1 The display panel 100, transmit driver 300, and data driver 400 are similar to Figure 7 The display panel 100, the transmitter driver 300, and the data driver 400 are included, so repeated descriptions can be omitted.

[0136] The timing controller 500 can generate a first scan control signal SCS1 and a second scan control signal SCS2.

[0137] The first scan control signal SCS1 can be supplied to the first scan driver 210, and the second scan control signal SCS2 can be supplied to the second scan driver 220.

[0138] The first scan control signal SCS1 may include a first scan start pulse and a clock signal. The first scan start pulse controls the first timing of the scan signal output from the first scan driver 210. The clock signal can be used to shift the first scan start pulse.

[0139] The second scan control signal SCS2 may include a second scan start pulse and a clock signal. The second scan start pulse controls the first timing of the scan signal output from the second scan driver 220. The clock signal can be used to shift the second scan start pulse.

[0140] The first scan driver 210 may receive a first scan control signal SCS1 from the timing controller 500 and supply scan signals (e.g., first scan signals) to the first scan lines S11 to S1n based on the first scan control signal SCS1.

[0141] For example, the first scan driver 210 can sequentially supply the first scan signal to the first scan lines S11 to S1n. The transistor included in the sub-pixel SPij and receiving the first scan signal can be set to the on state when the first scan signal is supplied.

[0142] refer to Figure 5 and Figure 6 The second transistor M2 and the third transistor M3 can be set to the on state when the first scan signal GW[i] is supplied, and the fourth transistor M4 can be set to the on state when the first scan signal GW[i] is supplied.

[0143] The signal is set to the on state when the first scan signal GW[i-1] is received.

[0144] The second scan driver 220 may receive a second scan control signal SCS2 from the timing controller 500 and supply a scan signal (e.g., a second scan signal) to the second scan lines S21 to S2n based on the second scan control signal SCS2.

[0145] For example, the second scan driver 220 can sequentially supply the second scan signal to the second scan lines S21 to S2n.

[0146] refer to Figure 5 and Figure 6 The seventh transistor M7 and the eighth transistor M8 can be set to the on state when the second scan signal GB is supplied.

[0147] That is, the second transistor M2 to the fourth transistor M4 can be integrated and controlled by the first scan driver 210, rather than being controlled separately by a single scan driver.

[0148] Therefore, the number of required scan drivers is reduced, thereby reducing the non-display area in which the scan drivers are located.

[0149] In addition, refer to Figure 7 The diagram shows a first scan driver 210 arranged on one side of the display panel 100 and a second scan driver 220 arranged on the other side of the display panel 100. However, this disclosure is not limited to this, and the first scan driver 210 and the second scan driver 220 can be arranged in various ways depending on the embodiment. For example, the first scan driver 210, which outputs the first scan signal, can be arranged on both sides of the display panel 100.

[0150] Figure 8 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure, and Figure 9 The illustration shows one of them. Figure 8 An example of an electronic device is implemented as a smartphone.

[0151] refer to Figure 8 and Figure 9The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. In this case, the display device 1060 may be... Figure 1 The display device 10. Furthermore, the electronic device 1000 may also include multiple ports capable of communicating with video cards, sound cards, memory cards, USB devices, etc., or with other systems. In embodiments, such as Figure 9 As shown, the electronic device 1000 can be implemented as a smartphone. However, this is just an example, and the electronic device 1000 is not limited to this. For example, the electronic device 1000 can be implemented as a mobile phone, video phone, smartpad, smartwatch, tablet PC, vehicle navigation system, computer monitor, laptop computer, head-mounted display device, etc.

[0152] Processor 1010 can perform specific calculations or tasks. In some embodiments, processor 1010 may be a microprocessor, central processing unit, application processor, etc. Processor 1010 can be connected to other components via address bus, control bus, and data bus. In some embodiments, processor 1010 may also be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0153] The memory device 1020 can store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), nano-floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM), or volatile memory devices such as dynamic random access memory (DRAM), static random access memory (SRAM), and mobile DRAM.

[0154] Storage device 1030 may include solid-state drive (SSD), hard disk drive (HDD), CD-ROM, etc.

[0155] Input / output device 1040 may include input devices such as a keyboard, keypad, touchpad, touch screen, mouse, etc., and output devices such as a speaker, printer, etc. In some embodiments, display device 1060 may be included in input / output device 1040.

[0156] The power supply 1050 provides the power required for the operation of the electronic device 1000. For example, the power supply 1050 may be a power management integrated circuit (PMIC).

[0157] Display device 1060 can display images corresponding to the visual information of electronic device 1000. In this case, display device 1060 can be an organic light-emitting display device or a quantum dot light-emitting display device, but is not limited thereto. Display device 1060 can be connected to other components via a bus or other communication links.

[0158] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the scope and spirit of this disclosure as set forth in the appended claims.

Claims

1. A sub-pixel comprising: a first transistor connected between a first node that receives a first driving power and a second node to generate a driving current, and including a control electrode connected to a third node; a second transistor connected between a data line and the first node, and turned on in response to a first scan signal; a third transistor connected between the second node and the third node, and turned on in response to the first scan signal; and a light emitting element that receives the driving current to emit light.

2. The sub-pixel according to claim 1, wherein each of the second transistor and the third transistor is an NMOS transistor.

3. The sub-pixel according to claim 1, further comprising: a fourth transistor connected between the third node and a first power line that provides a first initialization power, and turned on in response to a second scan signal.

4. The sub-pixel according to claim 3, further comprising: a fifth transistor connected between the first node and a second power line that provides a voltage of the first driving power, and turned on in response to an emission control signal; and a sixth transistor connected between the second node and a fourth node, and turned on in response to the emission control signal, wherein the light emitting element is connected between the fourth node and a third power line that provides a second driving power.

5. The sub-pixel according to claim 4, further comprising: a seventh transistor connected between the fourth node and a fourth power line that provides a voltage of a second initialization power, and turned on in response to a third scan signal; and an eighth transistor connected between the first node and a fifth power line that provides a voltage of a bias power, and turned on in response to the third scan signal.

6. The sub-pixel according to claim 5, wherein each of the second transistor, the third transistor, and the fourth transistor is an NMOS transistor, and each of the first transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor is a PMOS transistor.

7. The sub-pixel according to claim 5, wherein in operation, a frame includes a non-emission period and an emission period, the non-emission period includes a first period, a second period, and a third period, in the first period, the second scan signal has a high logic level, in the second period after the first period, the first scan signal has the high logic level, and in the third period after the second period, the third scan signal has a low logic level.

8. A display device comprising: ​ ​ ​ a sub-pixel including a first transistor and a light emitting element, the first transistor connected between a first node receiving a first driving power and a second node to generate a driving current, the first transistor including a control electrode connected to a third node, the sub-pixel connected to a first scan line, an emission control line, and a data line; an emission driver supplying an emission control signal to the emission control line; a first scan driver supplying a first scan signal to the first scan line; and a data driver supplying a data signal to the data line, wherein the first scan signal controls timing of the data signal being supplied to the first node and timing of the second node and the third node being connected.

9. The display device according to claim 8, wherein the sub-pixel further includes: a second transistor connected between the data line and the first node, and turned on in response to the first scan signal; and a third transistor connected between the second node and the third node, and turned on in response to the first scan signal, wherein the light emitting element receives the driving current to emit light.

10. The display device according to claim 9, wherein each of the second transistor and the third transistor is an NMOS transistor.

11. The display device according to claim 9, further comprising: a second scan driver supplying a second scan signal to the second scan line, wherein the sub-pixel further includes: a fourth transistor connected between the third node and a first power line providing a first initialization power, and turned on in response to the second scan signal.

12. The display device according to claim 11, wherein the sub-pixel further includes: a fifth transistor connected between the first node and a second power line providing a voltage of the first driving power, and turned on in response to the emission control signal; and a sixth transistor connected between the second node and a fourth node, and turned on in response to the emission control signal, wherein the light emitting element is connected between the fourth node and a third power line providing a second driving power.

13. The display device according to claim 12, further comprising: a third scan driver supplying a third scan signal to a third scan line, wherein the sub-pixel further includes: a seventh transistor connected between the fourth node and a fourth power line providing a voltage of a second initialization power, and turned on in response to the third scan signal; and an eighth transistor connected between the first node and a fifth power line providing a voltage of a bias power, and turned on in response to the third scan signal.

14. The display device according to claim 13, wherein ​ Each of the second transistor, the third transistor, and the fourth transistor is an NMOS transistor, and Each of the first transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor is a PMOS transistor. 15.An electronic device comprising: a processor that provides input image data; and a display device that displays an image based on the input image data, wherein the display device comprises: a sub-pixel that includes a first transistor connected between a first node that receives a first driving power and a second node to generate a driving current, the first transistor including a control electrode connected to a third node, the sub-pixel connected to an i-th first scan line, an i-1-th first scan line, an i-th emission control line, and a j-th data line; an emission driver that supplies an i-th emission control signal to the i-th emission control line; a first scan driver that supplies an i-th first scan signal to the i-th first scan line and an i-1-th first scan signal to the i-1-th first scan line; and a data driver that supplies a data signal to the j-th data line, wherein the i-th first scan signal controls timing at which the data signal is supplied to the first node and timing at which the second node and the third node are connected, and i is a natural number greater than 1, and j is a natural number greater than 0. 16.The electronic device of claim 15, wherein the sub-pixel further includes: a second transistor connected between the j-th data line and the first node and turned on in response to the i-th first scan signal; and a third transistor connected between the second node and the third node and turned on in response to the i-th first scan signal, wherein the light emitting element receives the driving current to emit light. 17.The electronic device of claim 16, wherein the sub-pixel further includes: a fourth transistor connected between the third node and a first power line that provides a first initialization power and turned on in response to the i-1-th first scan signal. 18.The electronic device of claim 17, wherein the sub-pixel further includes: a fifth transistor connected between the first node and a second power line that provides a voltage of the first driving power and turned on in response to the i-th emission control signal; and a sixth transistor connected between the second node and a fourth node and turned on in response to the i-th emission control signal, wherein the light emitting element is connected between the fourth node and a third power line that provides a second driving power. 19.The electronic device of claim 18, further comprising: a second scan driver that supplies an i-th second scan signal to an i-th second scan line, The sub-pixel further includes: a seventh transistor connected between the fourth node and a fourth power line providing a voltage of second initialization power and turned on in response to the ith second scan signal; and an eighth transistor connected between the first node and a fifth power line providing a voltage of bias power and turned on in response to the ith second scan signal. 20.The electronic device of claim 19, wherein, each of the second transistor, the third transistor, and the fourth transistor is an NMOS transistor, and each of the first transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor is a PMOS transistor.

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