data processing apparatus

By using a unified storage architecture and a data processing device with co-designed hardware and software, the problems of poor expansion effect and complex synchronous maintenance of multi-standard and multi-antenna data processing have been solved, and flexible resource expansion and efficient multi-standard and multi-cell data processing have been achieved.

CN121277879BActive Publication Date: 2026-07-24NEXWISE INTELLIGENCE CHINA LTD
1 Cites 0 Cited by

Patent Information

Application Number
CN202511284248.X
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2025-09-09
Publication Date
2026-07-24
Estimated Expiration
2045-09-09

AI Technical Summary

Technical Problem

Existing multi-standard, multi-antenna data processing performs poorly when expanded, requiring independent hardware and computing resources, making architecture expansion difficult, and multi-cell synchronous maintenance is complex, as is FPGA-level synchronous maintenance.

Method used

The data processing device adopts a unified storage architecture and hardware-software co-design. By combining FPGA chips and data storage, it uses a switching control module to realize cross-switching of radio frequency and address, supports multi-standard and multi-cell data processing, and combines FPGA hardware acceleration and CPU non-real-time scheduling collaborative architecture to achieve high-speed preprocessing and hardware acceleration.

Benefits of technology

It improves the compatibility, scalability, and computing efficiency of data processing, simplifies resource expansion and maintenance, and supports unified storage and dynamic processing of multi-standard and multi-cell data.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

The application provides a data processing device, belonging to the technical field of wireless communication, and the device comprises: an FPGA chip and a data storage for storing air interface IQ data; the FPGA chip further comprises: a storage interface module; a frequency point digital down conversion module, which is used for sampling rate conversion on a digital signal input into the FPGA chip, obtaining the air interface IQ data, and storing the air interface IQ data into the data storage; a frequency point digital down conversion module, which is used for responding to a starting instruction of a central processing unit, extracting target air interface IQ data according to pre-configured data reading parameters, and performing sampling rate recovery on the target air interface IQ data to obtain output IQ data; and a post-processing module, which is used for processing the output IQ data and returning a processing result to the central processing unit. The application is based on a combined FPGA hardware acceleration and CPU non-real-time scheduling cooperative architecture as a whole, supports flexible expansion, simple maintenance, and unified storage and dynamic processing of multi-mode and multi-cell data.
Need to check novelty before this filing date? Find Prior Art