A neutron transport simulation method, related apparatus and computer program product

Abstract

The present disclosure provides a neutron transport simulation method, related device and computer program product, relating to the technical field of computer technology and nuclear physics. The method is implemented in the following manner: CSG modeling is performed on a reactor core to construct a CSG tree; N projection planes are generated around the reactor core, and an incident point array is generated on all the projection planes; a blank Segment list is constructed, and recursive characteristic line tracking is performed on all the incident points starting from the root node of the CSG tree, and Segment data is sequentially filled into the blank Segment list; GPU layer and GPU internal thread layer load balancing is performed; the characteristic line, FSR and material data are transmitted to each GPU; each GPU performs transport scanning calculation; the global FSR angular flux is calculated; each GPU calculates the fission moment and the fission source; the K effective value is calculated and whether it converges is verified. The technical solution of the present disclosure can break the CSG geometry construction restriction in the existing neutron transport simulation method, reduce unnecessary characteristic line generation to save computing resources, and improve the iteration solving speed to speed up the simulation.

Description

Technical Field

[0001] This disclosure relates to the fields of computer technology and nuclear physics, and in particular to a neutron transport simulation method, related apparatus and computer program product. Background Technology

[0002] A virtual reactor is a comprehensive software system that uses computer modeling and simulation technology to highly realistically reproduce the physical processes, engineering characteristics, and operating conditions of a nuclear reactor. It enables comprehensive research on reactor design, operation, and safety analysis without relying on actual core experiments. Virtual reactors not only help reduce R&D costs and experimental risks, but also support the optimized design of advanced reactor types, the prediction and verification of accident conditions, and nuclear engineering education and training. They are considered an important tool and platform for promoting the development of nuclear energy science.

[0003] The neutron transport equation is the core of virtual reactor simulation. It describes the spatial and energy distribution and evolution of neutrons, and can depict the changes in neutrons within the nuclear reactor core caused by processes such as scattering, absorption, and fission. Currently, one of the mainstream numerical solutions to the neutron transport equation is the Method of Characteristics (MOC). This method combines high fidelity with excellent geometric adaptability, and is therefore widely used in full-reactor simulations of various reactor cores.

[0004] The main process of solving MOC is divided into two parts: feature line generation and iterative solution.

[0005] In feature line generation, the first step is to perform geometric modeling of the core, commonly using Constructive Solid Structure (CSG). This method accurately represents the geometric structure and constructs a modeling tree by performing intersection, union, and complement calculations on the spatial planes. Node types on the modeling tree can be categorized as Cell, Universe, Lattice, and Material. A Cell is a geometric space enclosed by one or more surfaces, filled with Universes or Materials; a Universe is a three-dimensional spatial extent composed of a series of Cells; a Lattice can quickly represent multiple structurally similar Universes; and a Material is a type of Cell node, a leaf node of the CSG tree, and is filled with only a single material. From the perspective of node type, the CSG tree structure can be categorized as follows: Figure 1 As shown.

[0006] These nodes correspond to components such as fuel rods and moderators in the reactor core. Each node in the modeling tree is then further divided into multiple base space units called Flat Source Regions (FSRs). Subsequently, multiple projection planes at different angles are generated around the reactor core, each containing an array of feature line origin points. Each origin point generates a ray perpendicular to the plane, which is the feature line. As the feature line traverses the reactor core, it is segmented by the pre-constructed FSRs. The process of determining which FSRs a feature line will pass through, and the actual length of each segment on this feature line, is called feature line tracing. After feature line tracing is performed on all incident points on the projection planes, the feature line generation phase ends.

[0007] In the iterative solution, each iteration's calculation can be divided into two parts. First, the transport scan calculation involves sequentially traversing each segment along a feature line in both forward and reverse directions, updating the angular flux increment of each FSR traversed. Second, the numerical transformation converts the angular flux increment of each FSR into a fission moment distribution, the effective value of K, and a global fission source. The fission moment represents the power distribution within the reactor core, and the effective value of K represents the neutron effective multiplication factor. After completing these calculations, the algorithm determines whether to terminate based on whether the difference between the effective values ​​of K from the previous step and the current step, as well as the difference in the global fission source, is lower than a pre-set threshold.

[0008] Existing neutron transport simulation methods suffer from several technical problems, such as limited CSG modeling geometry, wasted computational resources due to unnecessary feature line generation, and low efficiency in iterative solutions. Therefore, there is an urgent need in this field for an efficient neutron transport simulation method adaptable to cores with arbitrary geometries. Summary of the Invention

[0009] This disclosure provides a neutron transport simulation method, apparatus, electronic device, computer-readable medium, and computer program product.

[0010] Firstly, this disclosure provides a neutron transport simulation method, including:

[0011] CSG modeling is performed on the core to construct a CSG tree; the core can be of arbitrary geometry; CSG modeling supports the intersection operation of CSG tree parent and child nodes as well as the intersection-union-complement operation between surfaces of the highest order 4; the CSG tree nodes are divided into FSRs and each FSR is assigned a first FSR number; the first FSR number is a random number; the essence of each CSG tree node is the sequence of intersection points of the feature line and the FSR boundary; the intersection-union-complement operation maintains the intersection point calculation sequence as a tree structure;

[0012] N projection surfaces are generated around the core, and an array of incident points is generated on all projection surfaces; where... The angles between these N projection planes and the core are all different; all incident points generate a feature line perpendicular to the projection plane where the incident point is located.

[0013] Construct a blank Segment list. Starting from the root node of the CSG tree, perform recursive feature line tracing on all incident points and fill the blank Segment list with Segment data in sequence. This feature line tracing calculates the sequence of intersection points and combines the polynomials of the highest quartic surface and the feature line polynomials to transform the intersection, union, and complement operations into an intersection point sequence solution operation.

[0014] Load balancing is performed at the GPU layer and within the GPU thread layer. For GPU layer load balancing, feature lines are grouped into a first feature line group based on their direction. A consecutive sequence number is assigned to each feature line within the first feature line group to obtain the first feature line number. Based on the first feature line group and the first feature line number, the feature lines are round-robin allocated to the GPU. For GPU thread layer load balancing, feature lines with the same first FSR number that pass through the first FSR are grouped into a second feature line group. A consecutive sequence number is assigned to each feature line within the second feature line group to obtain the second feature line number. Based on the second feature line number, a greedy grouping method is used to allocate the feature lines to adjacent GPU threads. The termination condition for this greedy grouping is that the number of segments in a GPU thread is not less than a preset upper limit.

[0015] Feature line data, FSR data, and material data are transferred to each GPU;

[0016] Each GPU performs transport scan calculations; where transport scan calculations refer to each GPU traversing the feature lines and updating the angular flux of the local FSR.

[0017] Calculate the global FSR angular flux; where the global FSR angular flux is obtained through the full reduction operation of the NVSHMEM inter-GPU communication library;

[0018] Each GPU calculates the fission moment and fission source;

[0019] Transmit the total fission source quality value to the CPU;

[0020] Calculate the effective value of K and verify whether it converges; if the verification is negative, continue with transport scan calculation, global FSR angular flux calculation, fission moment and fission source calculation, total fission source quality value transfer, K effective value calculation and verification; if the verification is positive, end the simulation.

[0021] Secondly, this disclosure provides a neutron transport simulation device, comprising:

[0022] The CSG modeling unit is configured to perform CSG modeling on the core, constructing a CSG tree; the core can be of arbitrary geometry; CSG modeling supports the intersection operation of CSG tree parent and child nodes, as well as the intersection-union-complement operation between surfaces of the highest order 4; the CSG tree node is divided into FSRs, and all FSRs are assigned a first FSR number; this first FSR number is a random number; the essence of the CSG tree node is the sequence of intersection points of the feature line and the FSR boundary; the intersection-union-complement operation maintains the intersection point calculation sequence as a tree-like relationship;

[0023] The incident point array generation unit is configured to generate N projection surfaces around the core and generate an incident point array on all projection surfaces; wherein... The angles between these N projection planes and the core are all different; all incident points generate a feature line perpendicular to the projection plane where the incident point is located.

[0024] The recursive feature line tracing unit is configured to construct a blank Segment list, starting from the root node of the CSG tree, and recursively tracing feature lines for all incident points, filling the blank Segment list with Segment data in sequence; the feature line tracing, based on the intersection point calculation sequence, combines the polynomial of the highest quartic surface and the feature line polynomial, transforming the intersection, union, and complement operations into an intersection point sequence solving operation;

[0025] The load balancing unit is configured to perform load balancing at the GPU layer and the GPU-internal thread layer. For GPU layer load balancing, the feature lines are grouped into a first feature line group based on their direction; consecutive sequence numbers are assigned to the feature lines within the first feature line group to obtain first feature line numbers; and feature lines are then round-robin allocated to GPUs based on the first feature line group and the first feature line numbers. For GPU-internal thread layer load balancing, feature lines with the same first FSR number that pass through the first FSR within the GPU are grouped into a second feature line group; consecutive sequence numbers are assigned to the feature lines within the second feature line group to obtain second feature line numbers; and feature lines are then greedily allocated to adjacent GPU-internal threads based on the second feature line numbers. The termination condition for this greedy grouping is that the number of segments in a GPU-internal thread is not less than a preset upper limit.

[0026] The first data transmission unit is configured to transmit feature line data, FSR data, and material data to each GPU.

[0027] The transport scan computation unit is configured to perform transport scan computation on each GPU; where transport scan computation refers to each GPU traversing the feature line and updating the angular flux of the local FSR.

[0028] The global FSR angle flux calculation unit is configured to calculate the global FSR angle flux; wherein, the global FSR angle flux is obtained through the full reduction operation of the GPU inter-GPU communication library NVSHMEM;

[0029] The fission moment and fission source calculation units are configured to calculate the fission moment and fission source on each GPU;

[0030] The second data transmission unit is configured to transmit the total fission source mass value to the CPU;

[0031] The convergence verification unit is configured to calculate the effective value of K and verify whether convergence has occurred. If the verification fails, the transport scan calculation, global FSR angular flux calculation, fission moment and fission source calculation, total fission source quality value transfer, K effective value calculation and verification will continue. If the verification succeeds, the simulation will end.

[0032] Thirdly, this disclosure provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to implement the neutron transport simulation method as described in any implementation of the first aspect.

[0033] Fourthly, this disclosure provides a non-transitory computer-readable storage medium storing computer program instructions for causing the computer to execute a neutron transport simulation method as described in any implementation of the first aspect.

[0034] Fifthly, this disclosure provides a computer program product, including a computer program that, when executed by a processor, implements the neutron transport simulation method as described in any of the implementations in the first aspect.

[0035] The content described in this section is not intended to identify key or important features of the embodiments of this disclosure, nor does it constitute a limitation on the scope of this disclosure.

[0036] Other features of this disclosure will be described in detail in the following description to aid understanding. Attached Figure Description

[0037] Figure 1 This is a CSG tree structure shown from the perspective of node type;

[0038] Figure 2 This is a flowchart of a neutron transport simulation method provided in one embodiment of the present disclosure;

[0039] Figure 3 This is a schematic diagram of the core geometry in one embodiment of this disclosure;

[0040] Figure 4 This is a schematic diagram of an intersection-and-complement operation in one embodiment of this disclosure;

[0041] Figure 5 This is a pseudocode diagram of a recursive feature line tracing method starting from the root node in one embodiment of this disclosure;

[0042] Figure 6 This is a schematic diagram of GPU layer load balancing in one embodiment of this disclosure;

[0043] Figure 7 This is a schematic diagram of the relevant data status before load balancing of the GPU thread layer in one embodiment of this disclosure;

[0044] Figure 8 This is a schematic diagram of the intermediate data status of the GPU thread layer load balancing in one embodiment of this disclosure;

[0045] Figure 9 This is a schematic diagram of the load balancing result of the GPU thread layer in one embodiment of this disclosure;

[0046] Figure 10 This is a flowchart of an embodiment of the present disclosure of a method for generating an incident point array by gradually increasing the incident point density;

[0047] Figure 11 This is a schematic diagram of the generation of the incident point array in one embodiment of this disclosure;

[0048] Figure 12 This is a schematic diagram of a two-stage FSR replacement method provided in an embodiment of the present disclosure;

[0049] Figure 13 This is a schematic diagram of the relevant data status before the two-stage FSR replacement in one embodiment of this disclosure;

[0050] Figure 14 This is a schematic diagram of the first-stage FSR replacement result in one embodiment of this disclosure;

[0051] Figure 15 This is a schematic diagram of the second-stage FSR replacement result in one embodiment of this disclosure;

[0052] Figure 16 This is a schematic diagram of the combined processing results of GPU layer and GPU in-thread layer load balancing and two-stage FSR replacement in one embodiment of this disclosure;

[0053] Figure 17 This is a schematic diagram of a neutron transport simulation device provided in an embodiment of this disclosure;

[0054] Figure 18 This is a schematic diagram of a neutron transport simulation electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0055] The present disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments provided below are merely exemplary. Furthermore, for the sake of brevity and clarity, common knowledge has been omitted from the description of the embodiments below.

[0056] In this document, terms such as "first," "second," and "third" are used only to distinguish identical or similar descriptive objects and are not intended to limit the specific order or sequence of the descriptive objects, nor are they used to limit the importance of the descriptive objects. At the same time, in order to enable those skilled in the art to clearly understand the technical solutions provided in this disclosure, expressions such as "red," "yellow," and "blue" are also used only to distinguish identical or similar descriptive objects and do not represent the color attributes possessed by the descriptive objects when this solution is actually deployed.

[0057] Figure 2 A flowchart of a neutron transport simulation method provided in one embodiment of this disclosure is shown, which specifically includes the following steps:

[0058] Step S201: Perform CSG modeling on the reactor core and construct a CSG tree.

[0059] The nodes of the CSG tree are divided into multiple FSRs by the highest quartic surface, and these FSRs are randomly numbered (first FSR number).

[0060] It should be noted that existing neutron transport simulation methods suffer from geometric constraints when modeling CSGs, limiting their application to quadrilateral cores. These geometric constraints can be categorized into radial (XY plane) and axial (Z-axis) constraints.

[0061] In the feature line tracing performed in neutron transport simulation, the target data are the FSR (Freeform Sequence) crossed by each feature line and the segment length formed by the feature line being divided by the FSR boundary. Therefore, in step S201, CSG modeling does not directly describe the geometric structure of the nodes; the constructed CSG tree is essentially a sequence of intersection point calculations. The so-called intersection-union-complement operation does not actually calculate the intersection lines of the surfaces, but rather maintains the intersection point calculation sequence as a tree-like relationship. In subsequent feature line tracing steps, based on the intersection point calculation sequence, by simultaneously solving the polynomials of the highest-order fourth-degree surface and the feature line polynomials, the intersection-union-complement operation can be transformed into an intersection point sequence solution operation.

[0062] Therefore, it should be understood that the geometric shapes (e.g., rectangles, hexagons, etc.) described in this embodiment and shown in the accompanying drawings are geometric mappings of CSG tree nodes, intended to make this disclosure easier to understand, and do not represent that CSG modeling directly describes the geometric construction of nodes.

[0063] For radial constraints, such as Figure 3As shown in Figure a, the quadrilateral core, due to its self-similarity, allows the boundaries of parent and child nodes to fit tightly together, thus it can be used as follows: Figure 3 The red Lattice shown in figure a is used for rapid representation. However, for hexagonal cores, such as... Figure 3 As shown in b, the boundaries of the parent and child nodes cannot fit tightly. The red grid and the green large hexagonal boundary together form 6 rhomboid regions. These 6 rhomboid boundaries need to be manually spliced ​​together using multiple planes, which makes the existing neutron transport simulation method unsuitable for hexagonal cores. Similarly, it is also unsuitable for other complex geometric cores.

[0064] In one embodiment of this disclosure, for such Figure 3 In the case of the hexagonal core shown in b, when performing feature line tracing, the intersection range of the large green hexagon of the parent node and the small red hexagon of the child node can be calculated according to the CSG tree traversal order, thus breaking the radial limitation of the geometric construction.

[0065] For axial constraints, when actually performing feature line tracing, a surface can be represented by a polynomial of the highest degree of four. Adding a direction (inside or outside the surface) to this surface can define a semi-three-dimensional spatial region. The complement operation is to reverse this direction. Multiple semi-three-dimensional spatial regions can be intersected and joined to represent any geometry.

[0066] After a feature line passes through the FSR, a sequence of intersection points can be obtained by simultaneously solving the polynomials of the highest quartic surface (FSR boundary) and the first-order polynomial of the feature line. The internal and external relationships between the feature line and the three-dimensional region of the half-space bounded by these surfaces will appear alternately, and it can be determined whether the intersection points at different positions on the feature line are contained in these multiple surface half-spaces.

[0067] When performing an intersection operation, intersection points that are inside the other surface half-space are retained, while intersection points that are outside the other surface half-space are excluded; when performing a union operation, intersection points that are inside the other surface half-space are excluded, while intersection points that are outside the other surface half-space are retained.

[0068] In one embodiment of this disclosure, the intersection point of the feature line with the two curved surfaces and the relationship between the feature line and the two curved surfaces in half-space are as follows: Figure 4 As shown, when performing the intersection operation, points 1b, 2b, 2c, and 1c are retained, while points 1a and 2a are excluded; when performing the union operation, points 1b, 2b, 2c, and 1c are excluded, while points 1a and 2a are retained. Based on the retained intersection points, the first-order polynomial of the feature lines, and the highest-order fourth-order surface polynomial, the target data for feature line tracing can be obtained, breaking the axial constraints of geometric construction.

[0069] Step S202: Generate N projection surfaces around the core and generate an array of incident points on the projection surfaces.

[0070] in, The angles between these N projection planes and the core are all different; each incident point generates a feature line perpendicular to the projection plane at that incident point.

[0071] Step S203: Construct a blank Segment list. Starting from the root node of the CSG tree, perform recursive feature line tracing on all incident points and fill the blank Segment list with the Segment data in sequence.

[0072] Characteristic line tracing involves calculating a sequence based on intersection points, combining the polynomials of the highest-order quartic surface and the characteristic line polynomials, and transforming the intersection, union, and complement operations into solving the intersection point sequence.

[0073] It should be noted that existing neutron transport simulation methods require a separate search for each segment on the feature line during feature line tracing, thus necessitating multiple calls to the CSG tree traversal and search functions.

[0074] This disclosure includes an embodiment of recursive feature line tracing pseudocode, as follows: Figure 5 As shown, different operations are performed on the constructed Segment list according to the type of node processed during the tracking process, so that the tracking of a feature line can be completed in one tree traversal, reducing the time complexity of the tracking process.

[0075] Step S204: Perform load balancing at the GPU layer and within the GPU thread layer.

[0076] It should be noted that existing neutron transport simulation methods are limited to simulating square cores due to geometric constraints, and their load balancing methods also employ a region decomposition approach specific to square regions. Therefore, this step aims to disclose a load balancing method applicable to cores with arbitrary geometries.

[0077] For GPU-layer load balancing, in one embodiment of this disclosure, the relationship between the feature line and the stack core is as follows: Figure 6 As shown, feature lines from different angles are first grouped (first feature line grouping). It should be understood that feature lines from the same projection plane have the same direction, resulting in... Figure 6 The four feature line groups shown.

[0078] For the blue feature line group, number them in the main order of the feature line incident point row (first feature line number), and allocate the feature lines to GPU1 and GPU2 in a polling manner with an interval of 1. The process for the other feature line groups is omitted.

[0079] It should be understood that for feature lines in the same direction and with adjacent numbers (first feature line numbers), the number of FSRs they pass through is similar, and the number of segments is also similar. Therefore, the GPU load balancing method provided in this disclosure embodiment can make the computing load between different GPUs similar.

[0080] For GPU-internal thread-level load balancing, in one embodiment of this application, a GPU, after undergoing GPU-level load balancing, comprises a total of 8 feature lines, with ID representing the feature line number. The FSR sequence (first FSR number sequence) traversed by each feature line is as follows: Figure 7 As shown. Figure 7 The ID numbers shown are only used to distinguish different feature lines here, and are not the first, second, or other feature line numbers mentioned in this article.

[0081] Will Figure 7 The feature lines that pass through the first FSR number (first FSR number) are grouped together (second feature line grouping), and adjacent sequence numbers (second feature line numbers) are assigned to the feature lines within the group. Thus, the processing result is as follows: Figure 8 As shown.

[0082] Feature lines are distributed using a greedy grouping method. The termination condition for greedy grouping is that the number of segments within a GPU thread is not less than a preset upper limit, which is set to 9. Feature lines are assigned to adjacent GPU threads in sequence (based on the second feature line numbering order), with TH representing the GPU thread. The allocation result is as follows. Figure 9 As shown.

[0083] It should be understood that feature lines that pass through the same first FSR number (first FSR number) are spatially similar, and the FSR sequences they pass through will also be similar. For example Figure 9 In the calculation, ID1-ID4 traverse similar FSR sequences, ID5 and ID6 traverse similar FSR sequences, and ID7 and ID8 traverse similar sequences. Therefore, this GPU-internal thread-level load balancing method can improve cache hit rate during computation, thereby accelerating the computation process.

[0084] The GPU layer and GPU in-thread layer load balancing method provided in this disclosure, while adapting to arbitrary geometric cores, also takes into account temporal locality.

[0085] Step S205: Transfer the feature line data, FSR data, and material data to the GPU.

[0086] Step S206: Each GPU performs transport scan calculation; wherein, transport scan calculation refers to each GPU traversing the feature line and updating the local FSR angular flux.

[0087] Step S207: Calculate the global FSR angular flux; wherein, the global FSR angular flux is obtained through the full reduction operation of the GPU inter-communication library NVSHMEM.

[0088] Step S208: Each GPU calculates the fission moment and fission source.

[0089] Step S209: Transfer the total fission source quality value to the CPU.

[0090] Step S210: Calculate the effective value of K and verify whether it converges; if the verification is negative, return to step S206; if the verification is positive, end the simulation.

[0091] Figure 10 This is a flowchart illustrating a method for generating an incident point array with progressively increasing incident point density, provided in one embodiment of this disclosure. Figure 2 The incident point array generation part in step S202 shown provides a specific implementation method. Figure 2 Without adjusting other steps, you can Figure 10 The steps in the above are replaced as a whole with the incident point array generation part in step S202 to obtain a new complete embodiment.

[0092] A method for generating an incident point array with progressively increasing incident point density includes the following steps:

[0093] Step S1001: Generate an array of incident points on the projection surface with a preset density.

[0094] Step S1002: Count the total number of FSRs nFSR_base crossed by the feature lines generated with the preset density.

[0095] Step S1003: Encrypt the incident point array according to a preset pattern.

[0096] Step S1004: Count the total number of FSRs crossed by all feature lines, nFSR_now.

[0097] Step S1005: Calculate delta_FSRs = nFSR_now - nFSR_base, and then set nFSR_base = nFSR_now;

[0098] Step S1006: Determine whether delta_FSRs is less than the preset delta_FSRs threshold. If yes, end the encryption. If no, set delta_FSRs to 0, continue to encrypt the incident point array according to the preset rule, recalculate delta_FSRs, and perform the determination again. The preset delta_FSRs threshold is greater than 0.

[0099] In one embodiment of this disclosure, the preset density is such that the row spacing and column spacing of the incident point array are both 1; the preset encryption rule is that in one encryption of the incident point array, the row spacing and column spacing of the incident point array are both halved. The incident point array generated in this embodiment is as follows: Figure 11 As shown, the red dots are the incident points generated in step S1001, the blue dots are the newly generated incident points after the first encryption, and the green dots are the newly generated incident points after the second encryption.

[0100] It should be noted that, with the number of FSRs and projection planes remaining unchanged, if each FSR is traversed by a feature line at the angle of each projection plane, increasing the number of feature lines will not improve the calculation accuracy, but will cause additional computational load. Therefore, existing neutron transport simulation methods have the problem of generating additional feature lines, resulting in a waste of computational resources.

[0101] The incident point array generation method for gradually increasing incident point density provided in this embodiment uses the change in the number of FSRs crossed by all feature lines after one encryption as feedback data and sets judgment conditions to end encryption in a timely manner. This reduces the generation of unnecessary feature lines while ensuring the accuracy of iterative solution, thereby saving computational resources.

[0102] Figure 12 This disclosure illustrates a two-stage FSR replacement method provided by an embodiment of the present disclosure, which can... Figure 12 The steps shown are considered as a whole. Figure 2 The steps S204 and S205 shown are performed to obtain a new complete embodiment.

[0103] Two-stage FSR replacement methods include:

[0104] The first stage of FSR replacement includes the following steps:

[0105] Step S1211: Assign consecutive sequence numbers to the FSRs within the leaf nodes of the CSG.

[0106] Step S1212: Reconnect the FSRs according to the subsequent traversal order of the CSG tree to obtain the second FSR number.

[0107] The second stage of FSR replacement includes the following steps:

[0108] Step S1221: Search for the longest feature line that passes through each FSR in the order of the second FSR number, and obtain the FSR sequence through which the longest feature line passes; where the longest feature line refers to the feature line with the most segments.

[0109] Step S1222: Maintain a global variable G and initialize it to 0, which is used to assign the third FSR number to the FSR.

[0110] Step S1223: Maintain a Boolean array with a total length equal to the total number of FSRs to record whether an FSR is assigned a third FSR number.

[0111] Step S1224: Based on the second FSR number and the FSR sequence through which the longest feature line passes, assign G values ​​to the FSRs sequentially to obtain the third FSR number; wherein, the G value increases by 1 each time it is assigned.

[0112] In one embodiment of this disclosure, such as Figure 13 As shown, the core contains four leaf nodes, namely the red rectangular node, yellow rectangular node, blue rectangular node and green rectangular node in the figure. Each leaf node is divided into four FSRs. With random numbering (first FSR number), the range of FSR numbers crossed by the feature line is 2, 14, 10, 12 and 6, and the average range is 8.8.

[0113] It should be noted that the FSR number range specifically refers to the difference between the maximum and minimum FSR numbers crossed by a feature line. The smaller the range, the more densely the FSRs crossed by the feature line are stored, and the easier it is to continuously access the FSR data during feature line tracing, resulting in better spatial locality of computation.

[0114] Assume that the leaf node traversal order in this embodiment is as follows: red rectangle node, yellow rectangle node, blue rectangle node, and green rectangle node.

[0115] In the first stage of FSR replacement, consecutive indices are assigned to the four FSRs within the four rectangular nodes: [1], [2], [3], and [4]. Then, these four consecutive indices are concatenated according to the actual traversal order to obtain the second FSR number. The processing result is as follows: Figure 14 As shown, the ranges of the FSR numbers (second FSR numbers) crossed by the feature line are 3, 8, 8, 7, and 1, and the average range decreases to 5.4.

[0116] In the second-stage FSR permutation, for the FSR with number (second FSR number) 1 ( Figure 14 The FSR (numbered 1) is crossed by two feature lines, Line 1 and Line 2. Line 1 has 2 segments, and Line 2 has 6 segments. Therefore, the longest feature line of this FSR is Line 2, and the FSR sequence crossed by this longest feature line is: 9, 1, 2, 3, 4, 5 (all second FSR numbers). Assigning a G value to the FSR according to this sequence is... Figure 14The third FSR is numbered 1 to 6. Following the order of the second FSR numbers, the above operation is performed on the remaining FSRs sequentially to obtain the third FSR number. When assigning the G value, a Boolean array is used to check whether the FSR has already been assigned a value, thus avoiding duplicate numbering. The process is omitted. The FSR replacement result in the second stage is as follows: Figure 15 As shown, the FSR numbers crossed by the feature line have ranges of 3, 5, 7, 5, and 1, with the average range decreasing to 4.2.

[0117] The embodiments disclosed herein reduce the range of FSR numbers crossed by the feature line from 8.8 to 4.2 through a two-stage FSR permutation, thereby improving the spatial locality of the calculation and accelerating the calculation process.

[0118] In another embodiment of this disclosure, Figure 12 The steps shown are considered as a whole. Figure 2 The process is executed between steps S204 and S205. After step S204, the feature lines in a GPU and the FSR sequences they pass through (the first FSR number sequence) are as follows: Figure 9 As shown, after performing a two-stage FSR replacement, the relevant data state within the GPU is as follows: Figure 16 As shown.

[0119] It should be understood that performing a two-stage FSR replacement based on load balancing at the GPU layer and the GPU-internal thread layer optimizes temporal and spatial locality, thus accelerating the computation process.

[0120] As a implementation of the above methods, this disclosure provides a neutron transport simulation device, such as... Figure 17 As shown, the neutron transport simulation device may include:

[0121] CSG modeling unit 1701 is configured to perform CSG modeling on the core and construct a CSG tree; wherein the core can be an arbitrary geometric core; CSG modeling supports the intersection operation of CSG tree parent and child nodes and the intersection-union-complement operation between surfaces of the highest order 4; the CSG tree node is divided into FSRs and each FSR is assigned a first FSR number; the first FSR number is a random number; the essence of the CSG tree node is the intersection point calculation sequence of the feature line and the FSR boundary; the intersection-union-complement operation maintains the intersection point calculation sequence as a tree relationship.

[0122] Incident point array generation unit 1702 is configured to generate N projection surfaces around the core and generate an incident point array on all projection surfaces; wherein... The angles between these N projection planes and the core are all different; all incident points generate a feature line perpendicular to the projection plane where the incident point is located.

[0123] The recursive feature line tracing unit 1703 is configured to construct a blank Segment list, starting from the root node of the CSG tree, and recursively tracing feature lines for all incident points, filling the blank Segment list with Segment data in sequence; the feature line tracing, based on the intersection point calculation sequence, combines the polynomial of the highest quartic surface and the feature line polynomial, transforming the intersection, union, and complement operations into an intersection point sequence solution operation.

[0124] Load balancing unit 1704 is configured to perform load balancing at the GPU layer and the GPU-internal thread layer. Specifically, for GPU layer load balancing, feature lines are grouped into a first feature line group based on their direction; consecutive sequence numbers are assigned to the feature lines within the first feature line group to obtain first feature line numbers; and feature lines are then round-robin allocated to GPUs based on the first feature line group and the first feature line numbers. For GPU-internal thread layer load balancing, feature lines with the same first FSR number that pass through the first FSR within the GPU are grouped into a second feature line group; consecutive sequence numbers are assigned to the feature lines within the second feature line group to obtain second feature line numbers; and feature lines are then greedily allocated to adjacent GPU-internal threads based on the second feature line numbers. The termination condition for this greedy grouping is that the number of segments in a GPU-internal thread is not less than a preset upper limit.

[0125] The first data transmission unit 1705 is configured to transmit feature line data, FSR data, and material data to each GPU.

[0126] The transport scan computing unit 1706 is configured to perform transport scan computing on each GPU; wherein, transport scan computing refers to each GPU traversing the feature line and updating the angular flux of the local FSR.

[0127] The global FSR angle flux calculation unit 1707 is configured to calculate the global FSR angle flux; wherein, the global FSR angle flux is obtained through the full reduction operation of the GPU inter-GPU communication library NVSHMEM;

[0128] The fission moment and fission source computing unit 1708 is configured to compute the fission moment and fission source for each GPU;

[0129] The second data transmission unit 1709 is configured to transmit the total fission source mass value to the CPU;

[0130] The convergence verification unit 1710 is configured to calculate the effective value of K and verify whether convergence has occurred; wherein, if the verification is negative, the transport scan calculation, global FSR angular flux calculation, fission moment and fission source calculation, total fission source quality value transfer, K effective value calculation and verification are continued; if the verification is positive, the simulation ends.

[0131] In one embodiment of the apparatus disclosed herein, the incident point array generation unit 1702 may be configured as an incident point array generation subunit that progressively increases the incident point density, and the incident point array generation subunit may be further configured to:

[0132] An array of incident points is generated on all projection surfaces at a preset density.

[0133] The total number of FSRs, nFSR_base, traversed by feature lines generated at a preset density.

[0134] All incident point arrays are encrypted according to a preset rule.

[0135] Calculate the total number of FSRs crossed by all characteristic lines, nFSR_now.

[0136] Calculate delta_FSRs = nFSR_now - nFSR_base, and then set nFSR_base = nFSR_now.

[0137] Determine whether delta_FSRs is less than the preset delta_FSRs threshold. If yes, end the encryption. If no, set delta_FSRs to 0, continue to encrypt all the incident point arrays according to the preset rule, recalculate delta_FSRs, and make the judgment again. The preset delta_FSRs threshold is greater than 0.

[0138] In one embodiment of the apparatus disclosed herein, an FSR replacement unit may be further included, the FSR replacement unit being configured to:

[0139] Assign consecutive sequence numbers to the FSRs within the leaf nodes of the CSG tree;

[0140] Reconnect the FSRs in the leaf nodes according to the subsequent traversal order of the CSG tree to obtain the second FSR number;

[0141] Following the second FSR numbering order, the longest feature line passing through each FSR is searched sequentially, and the FSR numbering sequence passed by the longest feature line is obtained; where the longest feature line refers to the feature line with the most segments;

[0142] Maintain a global variable G and initialize it to 0, which is used to assign a third FSR number to the FSR;

[0143] Maintain a boolean array with a total length equal to the total number of FSRs to record whether an FSR is assigned a third FSR number;

[0144] Based on the second FSR number and the FSR number sequence, the G value is assigned to each FSR in turn to obtain the third FSR number; the G value is incremented by 1 each time it is assigned.

[0145] This disclosure also provides an electronic device comprising:

[0146] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to implement the neutron transport simulation method described in any of the above embodiments.

[0147] This disclosure also provides a readable storage medium storing computer instructions that enable a computer to implement the neutron transport simulation method described in any of the above embodiments when executed.

[0148] This disclosure also provides a computer program product that, when executed by a processor, can implement the neutron transport simulation method described in any of the above embodiments.

[0149] Figure 18 A schematic block diagram of an example electronic device 1800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0150] like Figure 18 As shown, device 1800 includes a computing unit 1801, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 1802 or a computer program loaded from storage unit 1808 into random access memory (RAM) 1803. RAM 1803 may also store various programs and data required for the operation of device 1800. The computing unit 1801, ROM 1802, and RAM 1803 are interconnected via bus 1804. Input / output (I / O) interface 1805 is also connected to bus 1804.

[0151] Multiple components in device 1800 are connected to I / O interface 1805, including: input unit 1806, such as keyboard, mouse, etc.; output unit 1807, such as various types of monitors, speakers, etc.; storage unit 1808, such as disk, optical disk, etc.; and communication unit 1809, such as network card, modem, wireless transceiver, etc. Communication unit 1809 allows device 1800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0152] The computing unit 1801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any suitable processor, controller, microcontroller, etc. The computing unit 1801 performs the various methods and processes described above, such as the neutron transport simulation method. For example, in some embodiments, the neutron transport simulation method can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 1808. In some embodiments, part or all of the computer program can be loaded and / or installed on device 1800 via ROM 1802 and / or communication unit 1809. When the computer program is loaded into RAM 1803 and executed by the computing unit 1801, one or more steps of the neutron transport simulation method described above can be performed. Alternatively, in other embodiments, the computing unit 1801 may be configured to perform a neutron transport simulation method by any other suitable means (e.g., by means of firmware).

[0153] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0154] Program code used to implement the methods provided in this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0155] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory, read-only memory, erasable programmable read-only memory (EPROM), flash memory, optical fiber, compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0156] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a cathode ray tube (CRT) or liquid crystal display (LCD) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0157] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0158] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0159] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0160] Any changes made to the above embodiments by those skilled in the art without departing from the true spirit and scope of this disclosure should be included within the scope of protection covered by the claims. The scope of protection claimed by this invention is limited only by the claims.

Claims

1. A neutron transport simulation method, characterized in that, include: CSG modeling is performed on the core to construct a CSG tree; wherein the core can be an arbitrary geometric core; the CSG modeling supports the intersection operation of parent and child nodes of the CSG tree and the intersection-union-complement operation between surfaces of the highest order 4; the CSG tree nodes are divided into FSRs and each FSR is assigned a first FSR number; the first FSR number is a random number; the CSG tree node is essentially a sequence of intersection points of feature lines and FSR boundaries; the intersection-union-complement operation maintains the intersection point calculation sequence as a tree structure; N projection surfaces are generated around the core, and an array of incident points is generated on all of the projection surfaces; wherein, the The angles between the N projection planes and the core are all different; all the incident points generate a feature line perpendicular to the projection plane where the incident point is located. Construct a blank Segment list, starting from the root node of the CSG tree, and perform recursive feature line tracing on all the incident points, filling the Segment data into the blank Segment list in sequence; the feature line tracing is performed by combining the polynomial of the highest quartic surface and the feature line polynomial according to the intersection point calculation sequence, and transforming the intersection, union, and complement operation into an intersection point sequence solving operation. Load balancing is performed at the GPU layer and within the GPU thread layer. Specifically, for GPU layer load balancing, the feature lines are grouped into a first feature line group based on their direction; consecutive sequence numbers are assigned to the feature lines within the first feature line group to obtain first feature line numbers; and the feature lines are then round-robin allocated to the GPU based on the first feature line group and the first feature line numbers. For GPU thread layer load balancing, feature lines with the same first FSR number that pass through the first FSR within the GPU are grouped into a second feature line group; consecutive sequence numbers are assigned to the feature lines within the second feature line group to obtain second feature line numbers; and the feature lines are then greedily allocated to adjacent GPU threads based on the second feature line numbers. The greedy grouping terminates when the number of segments in the GPU thread is not less than a preset upper limit. Feature line data, FSR data, and material data are transferred to each GPU; Each GPU performs transport scan calculations; wherein, the transport scan calculations refer to each GPU traversing the feature line and updating the angular flux of the local FSR; Calculate the global FSR angular flux; wherein the global FSR angular flux is obtained through the full reduction operation of the GPU inter-communication library NVSHMEM; Each GPU calculates the fission moment and fission source; Transmit the total fission source quality value to the CPU; Calculate the effective value of K and verify whether it converges; wherein, if the verification is negative, continue with the transport scan calculation, the global FSR angular flux calculation, the fission moment and fission source calculation, the total fission source quality value transfer, the effective value of K calculation and the verification; if the verification is positive, the simulation ends.

2. The method according to claim 1, characterized in that, An array of incident points is generated on the projection plane, including: An array of incident points is generated on all the projection surfaces at a preset density; The total number of FSRs, nFSR_base, traversed by the feature lines generated at the preset density; All the aforementioned incident point arrays are encrypted according to a preset rule; Calculate the total number of FSRs crossed by all the aforementioned feature lines, nFSR_now; Calculate delta_FSRs = nFSR_now - nFSR_base, then set nFSR_base = nFSR_now; Determine whether delta_FSRs is less than a preset delta_FSRs threshold. If yes, end the encryption. If no, set delta_FSRs to 0, continue to encrypt all the incident point arrays according to the preset rule, recalculate delta_FSRs, and perform the determination again. The preset delta_FSRs threshold is greater than 0.

3. The method according to claim 2, characterized in that, include: The preset density is such that the incident point row spacing and incident point column spacing of the incident point array are both 1; The preset rule is to halve both the row spacing and column spacing of the incident points.

4. The method according to claim 1 or 2, characterized in that, include: Assign consecutive sequence numbers to the FSRs within the leaf nodes of the CSG tree; The second FSR number is obtained by reconnecting the FSRs in the leaf nodes according to the subsequent traversal order of the CSG tree. According to the second FSR numbering order, the longest feature line passing through each FSR is searched sequentially, and the FSR numbering sequence passed by the longest feature line is obtained; wherein, the longest feature line refers to the feature line with the most segments; Maintain a global variable G and initialize it to 0, which is used to assign a third FSR number to the FSR; Maintain a boolean array with a total length equal to the total number of FSRs, used to record whether an FSR is assigned the third FSR number; Based on the second FSR number and the FSR number sequence, the G value is assigned to the FSR in sequence to obtain the third FSR number; wherein the G value is increased by 1 each time it is assigned.

5. A neutron transport simulation device, comprising: The CSG modeling unit is configured to perform CSG modeling on the core and construct a CSG tree; wherein the core can be an arbitrary geometric core; the CSG modeling supports the intersection operation of the parent and child nodes of the CSG tree and the intersection-union-complement operation between surfaces of the highest order 4; the CSG tree nodes are divided into FSRs and each FSR is assigned a first FSR number; the first FSR number is a random number; the CSG tree node is essentially a sequence of intersection points of the feature line and the FSR boundary; the intersection-union-complement operation maintains the intersection point calculation sequence as a tree relationship; An incident point array generation unit is configured to generate N projection surfaces around the core and generate an incident point array on all of the projection surfaces; wherein, the The angles between the N projection planes and the core are all different; all the incident points generate a feature line perpendicular to the projection plane where the incident point is located. The recursive feature line tracing unit is configured to construct a blank Segment list, starting from the root node of the CSG tree, and recursively tracing feature lines for all incident points, filling the blank Segment list with Segment data in sequence; the feature line tracing, based on the intersection point calculation sequence, combines the polynomial of the highest quartic surface and the feature line polynomial to transform the intersection-union-complement operation into an intersection point sequence solving operation; The load balancing unit is configured to perform load balancing at the GPU layer and the GPU-internal thread layer. Specifically, the GPU layer load balancing involves grouping the feature lines into a first feature line group based on their direction; assigning consecutive sequence numbers to the feature lines within the first feature line group to obtain a first feature line number; and then round-robin allocating the feature lines to GPUs based on the first feature line group and the first feature line number. The GPU-internal thread layer load balancing involves grouping feature lines with the same first FSR number that pass through the first FSR within the GPU into a second feature line group; assigning consecutive sequence numbers to the feature lines within the second feature line group to obtain a second feature line number; and then greedily allocating the feature lines to adjacent GPU-internal threads based on the second feature line number. The greedy grouping terminates when the number of segments in the GPU-internal thread is not less than a preset upper limit. The first data transmission unit is configured to transmit feature line data, FSR data, and material data to each GPU. The transport scan computation unit is configured to perform transport scan computation on each GPU; wherein, the transport scan computation refers to each GPU traversing the feature line and updating the angular flux of the local FSR; A global FSR angle flux calculation unit is configured to calculate the global FSR angle flux; wherein, the global FSR angle flux is obtained through the full reduction operation of the GPU inter-GPU communication library NVSHMEM; The fission moment and fission source calculation units are configured to calculate the fission moment and fission source on each GPU; The second data transmission unit is configured to transmit the total fission source mass value to the CPU; The convergence verification unit is configured to calculate the effective value of K and verify whether convergence has occurred; wherein, if the verification is negative, the transport scan calculation, the global FSR angular flux calculation, the fission moment and fission source calculation, the total fission source quality value transfer, the effective value of K calculation and the verification are continued; if the verification is positive, the simulation ends.

6. The apparatus according to claim 5, wherein, The incident point array generation unit includes an incident point array generation subunit configured to progressively increase the incident point density, and the incident point array generation subunit is further configured to: An array of incident points is generated on all the projection surfaces at a preset density; The total number of FSRs, nFSR_base, traversed by the feature lines generated at the preset density; All the aforementioned incident point arrays are encrypted according to a preset rule; Calculate the total number of FSRs crossed by all the aforementioned feature lines, nFSR_now; Calculate delta_FSRs = nFSR_now - nFSR_base, then set nFSR_base = nFSR_now; Determine whether delta_FSRs is less than a preset delta_FSRs threshold. If yes, end the encryption. If no, set delta_FSRs to 0, continue to encrypt all the incident point arrays according to the preset rule, recalculate delta_FSRs, and perform the determination again. The preset delta_FSRs threshold is greater than 0.

7. The apparatus according to claim 5 or 6, characterized in that, It also includes a two-stage FSR permutation unit, which is configured to: Assign consecutive sequence numbers to the FSRs within the leaf nodes of the CSG tree; The second FSR number is obtained by reconnecting the FSRs in the leaf nodes according to the subsequent traversal order of the CSG tree. According to the second FSR numbering order, the longest feature line passing through each FSR is searched sequentially, and the FSR numbering sequence passed by the longest feature line is obtained; wherein, the longest feature line refers to the feature line with the most segments; Maintain a global variable G and initialize it to 0, which is used to assign a third FSR number to the FSR; Maintain a boolean array with a total length equal to the total number of FSRs, used to record whether an FSR is assigned the third FSR number; Based on the second FSR number and the FSR number sequence, the G value is assigned to the FSR in sequence to obtain the third FSR number; wherein the G value is increased by 1 each time it is assigned.

8. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to implement the neutron transport simulation method according to any one of claims 1-4.

9. A non-transitory computer-readable storage medium storing computer program instructions, the computer instructions being configured to cause the computer to perform the neutron transport simulation method according to any one of claims 1-4.

10. A computer program product comprising a computer program that, when executed by a processor, implements the neutron transport simulation method according to any one of claims 1-4.

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