A signal synchronization method, apparatus, device, and storage medium

Abstract

The application provides a signal synchronization method, device, equipment and storage medium, comprising: processing the obtained wideband radio frequency signal to obtain a first carrier frequency offset estimation value and a first phase-locked loop compensation result; determining a first feedback gain according to the first carrier frequency offset estimation value and the first phase-locked loop compensation result; processing the first feedback gain to obtain a second carrier frequency offset estimation value, and generating a second phase-locked loop compensation result according to the second carrier frequency offset estimation value; determining a second feedback gain according to the second carrier frequency offset estimation value and the second phase-locked loop compensation result; determining a first code loop compensation result and a first frequency-locked loop carrier compensation result according to the second feedback gain; demodulating and decoding the first code loop compensation result and the first frequency-locked loop carrier compensation result to obtain the electric text information; for eliminating most frequency dynamics while realizing high-precision phase tracking, and effectively isolating noise through a gain adaptive mechanism, significantly improving the locking speed and tracking stability.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of satellite signal synchronization, and particularly relates to a signal synchronization method, device, equipment and storage medium. BACKGROUND

[0002] The tracking algorithm of the spread spectrum signal of the existing scheme is mainly for capturing and tracking high-orbit or narrowband satellites, and is not completely applicable to low-orbit satellites. For low-orbit satellites, the Doppler shift of the signal carrier has high dynamic characteristics, and combined with carrier frequency hopping, it will cause severe Doppler shift, which seriously affects the stability and tracking accuracy of the carrier tracking loop. The large dynamic change of the Doppler frequency will cause the traditional carrier phase-locked loop (PLL) tracking to be unstable, and even lose lock. At the same time, the Doppler frequency shift is equivalent to introducing a frequency step signal at the input end of the carrier tracking loop, so that the carrier tracking loop continuously enters the transient response process of the frequency step, thereby causing the carrier tracking loop to be unstable, and even lose lock.

[0003] Secondly, in the traditional fixed loop gain design scheme, for different frequency domain steps, the output result of the phase discriminator is any value between 0 and 2π. Based on the output result of the phase discriminator, underconditioning will occur when the signal frequency difference is large, which greatly increases the lock time of the loop. If the lock time spans the sawtooth period of the phase discriminator output signal, false adjustment will occur, resulting in a cycle slip phenomenon in the entire adjustment process. Based on the output result of the phase discriminator, over-adjustment will occur when the signal frequency difference is small, resulting in intensified oscillation of the output signal, and eventually causing the loop to lose lock. SUMMARY

[0004] The present application provides a signal synchronization method, device, equipment and storage medium, which can eliminate most of the frequency dynamics while achieving high-precision phase tracking, effectively isolate noise through a gain adaptive mechanism, and significantly improve the lock speed and tracking stability.

[0005] In a first aspect, the present application provides a signal synchronization method, comprising:

[0006] processing the obtained wideband radio frequency signal to obtain a first carrier frequency offset estimation value and a first phase-locked loop compensation result;

[0007] determining a first feedback gain according to the first carrier frequency offset estimation value and the first phase-locked loop compensation result;

[0008] processing the first feedback gain to obtain a second carrier frequency offset estimation value, and generating a second phase-locked loop compensation result according to the second carrier frequency offset estimation value;

[0009] determining a second feedback gain according to the second carrier frequency offset estimation value and the second phase-locked loop compensation result;

[0010] determining a first code loop compensation result and a first frequency-locked loop carrier compensation result according to the second feedback gain;

[0011] demodulating and decoding the first code loop compensation result and the first frequency-locked loop carrier compensation result to obtain text information.

[0012] In one or more possible embodiments, the determining a first feedback gain according to the first carrier frequency offset estimation value and the first phase-locked loop compensation result comprises:

[0013] comparing the first carrier frequency offset estimation value with a carrier loop bandwidth to determine a first inter-frequency error;

[0014] comparing the first carrier frequency offset estimation value with the first phase-locked loop compensation result in sign to determine a first loop feedback direction;

[0015] determining a first feedback gain according to the first inter-frequency error and the first loop feedback direction.

[0016] In one or more possible embodiments, the processing the obtained wideband radio frequency signal to obtain a first carrier frequency offset estimation value and a first phase-locked loop compensation result comprises:

[0017] initializing a frequency-locked loop carrier NCO according to an initial carrier compensation result and an initial phase-locked loop compensation result;

[0018] determining an initial demodulation signal according to the wideband radio frequency signal and a first local signal generated by the frequency-locked loop carrier NCO;

[0019] determining a first despread signal according to the initial demodulation signal and an initial code loop compensation result, and generating a first integral clean result according to the first despread signal;

[0020] calculating a non-coherent accumulation result according to the first integral clean result, and obtaining time synchronization information according to the non-coherent accumulation result;

[0021] determining a first carrier frequency offset estimation value and a first phase-locked loop compensation result according to the time synchronization information.

[0022] In one or more possible embodiments, the processing the first feedback gain to obtain a second carrier frequency offset estimation value comprises:

[0023] compensating the wideband radio frequency signal according to the first feedback gain to generate a first demodulation signal;

[0024] code loop filtering the first feedback gain, and determining a second code loop compensation result according to the filtered first feedback gain and a unit pseudo code Doppler increment;

[0025] calculating a second despread signal according to the first demodulation signal and the second code loop compensation result, and accumulating the second despread signal to obtain a second integral wipe-off result;

[0026] generating a second carrier frequency offset estimation value according to the second integral wipe-off result.

[0027] In one or more possible embodiments, the compensating the wideband radio frequency signal according to the first feedback gain to generate a first demodulation signal comprises:

[0028] multiplying the first feedback gain by a unit carrier Doppler increment to obtain a carrier Doppler compensation value;

[0029] adding the carrier Doppler compensation value, an acquisition predicted Doppler frequency and a carrier frequency fixed frequency word offset to obtain a carrier compensation value;

[0030] determining a second frequency locked loop carrier compensation result according to the carrier compensation value and a terminal working clock frequency;

[0031] determining a second local signal according to the second frequency locked loop carrier compensation result;

[0032] mixing the second local signal and the wideband radio frequency signal to generate the first demodulation signal.

[0033] In one or more possible embodiments, the generating a second phase locked loop compensation result according to the second carrier frequency offset estimation value comprises:

[0034] phase rotating the second integral wipe-off result to obtain a third integral wipe-off result;

[0035] generating a carrier phase discrimination result according to the second carrier frequency offset estimation value and the third integral wipe-off result;

[0036] phase filtering the carrier phase discrimination result to generate the second phase locked loop compensation result.

[0037] In one or more possible embodiments, the determining the first code loop compensation result and the first frequency locked loop carrier compensation result according to the second feedback gain comprises:

[0038] generating the first code loop compensation result according to the second feedback gain and the second integral wipe-off result;

[0039] The second feedback gain is determined according to the second carrier frequency offset estimation value and the second phase-locked loop compensation result.

[0040] In one or more possible embodiments, the second feedback gain is determined according to the second carrier frequency offset estimation value and the second phase-locked loop compensation result, including:

[0041] The second inter-frequency error is determined by comparing the second carrier frequency offset estimation value with a carrier loop bandwidth.

[0042] The second loop feedback direction is determined by symbolically comparing the second carrier frequency offset estimation value with the second phase-locked loop compensation result.

[0043] The second feedback gain is determined according to the second inter-frequency error and the second loop feedback direction.

[0044] In a second aspect, the present application further provides a signal synchronization device, including:

[0045] A signal processing module is configured to process the acquired wideband radio frequency signal to obtain a first carrier frequency offset estimation value and a first phase-locked loop compensation result.

[0046] A first feedback gain determination module is configured to determine a first feedback gain according to the first carrier frequency offset estimation value and the first phase-locked loop compensation result.

[0047] An update module is configured to process the first feedback gain to obtain a second carrier frequency offset estimation value, and generate a second phase-locked loop compensation result according to the second carrier frequency offset estimation value.

[0048] A second feedback gain determination module is configured to determine a second feedback gain according to the second carrier frequency offset estimation value and the second phase-locked loop compensation result.

[0049] A compensation result determination module is configured to determine a first code loop compensation result and a first frequency-locked loop carrier compensation result according to the second feedback gain.

[0050] An electronic text information acquisition module is configured to demodulate and decode the first code loop compensation result and the first frequency-locked loop carrier compensation result to acquire electronic text information.

[0051] In a third aspect, the present application further provides an electronic device, including:

[0052] At least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute any one of the methods in the first aspect.

[0053] In a fourth aspect, the present application provides a computer storage medium storing a computer program for causing a computer to execute any one of the methods in the first aspect.

[0054] According to the signal synchronization method, device, equipment and storage medium provided in the present application, high-precision phase tracking can be realized while eliminating most frequency dynamics, and noise can be effectively isolated through a gain adaptive mechanism, thereby significantly improving locking speed and tracking stability. BRIEF DESCRIPTION OF DRAWINGS

[0055] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the present application and, do not limit the present application.

[0056] Figure 1 A signal synchronization module diagram according to an embodiment is provided;

[0057] Figure 2 A flowchart of a signal synchronization method according to an embodiment is provided;

[0058] Figure 3 A module diagram of a signal synchronization method according to an embodiment is provided;

[0059] Figure 4 A signal synchronization device diagram according to an embodiment is provided;

[0060] Figure 5 An electronic device diagram according to an embodiment is provided;

[0061] Figure 6 A computer storage medium diagram according to an embodiment is provided. DETAILED DESCRIPTION

[0062] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0063] It should be noted that the terms "first", "second", etc. in the description of the present disclosure and claims and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0064] In addition, in the description of the embodiments of the present application, unless otherwise specified, " / " represents the meaning of or, for example, A / B can represent A or B; "and / or" in the text only describes the relationship between the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0065] Low-orbit satellite refers to a man-made satellite running in an orbit about 300 kilometers to 2000 kilometers above the earth's surface. The "low" of low-orbit satellite is relative to medium-orbit satellite and high-orbit satellite. In order to overcome the earth's gravity and not fall into the atmosphere, low-orbit satellite must fly around the earth at a very high speed (about 7.8 kilometers per second). Relative to users on the ground, low-orbit satellite will quickly rise from the horizon, fly over the head, and then fall to the horizon on the other side. This high-speed relative motion produces a huge and rapidly changing "Doppler frequency offset". For a fixed point on the ground, the "visible time" (from rising to falling) of a low-orbit satellite is usually only a few minutes to tens of minutes, that is, the terminal device must complete the acquisition and stable tracking of the satellite signal in a very short time, otherwise the signal will be lost.

[0066] For the tracking algorithm of satellite spread spectrum signal, the prior art mainly captures and tracks high-orbit or narrowband satellites. For low-orbit satellites, the Doppler frequency agility caused by large Doppler frequency dynamics and carrier frequency hopping is the main factor affecting the characteristics of the spread spectrum carrier tracking loop. Large Doppler frequency dynamics will cause the traditional carrier phase-locked loop to be unstable or even lose lock. At the same time, the Doppler frequency agility is equivalent to introducing a frequency step signal at the input end of the carrier tracking loop, so that the carrier tracking loop continuously enters the transient response process of the frequency step, thereby causing the loop to be unstable or even lose lock.

[0067] In addition, in the traditional fixed loop gain design scheme, for different frequency steps, the output results of the phase detector are between any values. The same phase discriminator output signal, when the signal frequency difference is large, will occur under-regulation, which will increase the lock time of the loop. Further, when the lock time spans the sawtooth period of the phase discriminator output signal, false adjustment will occur, and the entire adjustment process will exhibit a cycle slip phenomenon. For the same phase discriminator output signal, when the signal frequency difference is small, over-regulation will occur, which will exacerbate the oscillation of the system output signal and cause the loop to lose lock.

[0068] The existing typical signal synchronization method, as shown in Figure 1 , shows a typical baseband signal tracking loop structure, which realizes continuous tracking of the input signal through the cooperative work of the carrier tracking loop and the code tracking loop; in the carrier tracking loop, the carrier loop discriminator calculates the error according to the phase-rotated signal, the error is smoothed by the carrier loop filter, and then drives the carrier loop NCO to adjust the output frequency, forming a closed-loop control; in the code tracking loop, the code loop discriminator estimates the code phase deviation through the processed signal, and then the deviation is filtered by the code loop filter to control the code loop NCO to adjust the code generation rate; the tracking jitter of the carrier loop will be directly transmitted to the code loop through the code NCO offset, affecting the code measurement accuracy; and the instability of the code loop will reduce the input signal quality of the carrier discriminator, which may cause a chain lock loss, secondly, the loop performance is limited by the fixed setting of the filter bandwidth: a wider bandwidth is needed to adapt to the dynamic environment, while a narrower bandwidth is needed to suppress noise, which makes it difficult for the traditional loop to maintain optimal performance in complex environments; in addition, under weak signal conditions, when the correlation peak is overwhelmed by noise, the discriminator output error increases significantly, which easily leads to tracking loss, and once the loss occurs, a long time is needed to re-establish tracking.

[0069] Based on the above problems, the present application provides a signal synchronization method applied to a terminal, as shown in Figure 2 , which comprises:

[0070] Step 201, processing the obtained wideband radio frequency signal to obtain a first carrier frequency offset estimation value and a first phase-locked loop compensation result;

[0071] In one or more possible embodiments, the present application is applied to a terminal, specifically to a signal receiving and processing module in the terminal, for realizing robust signal synchronization and demodulation under high dynamic and weak signal conditions, and providing accurate baseband signals for subsequent navigation information calculation or data communication; the above-mentioned wideband radio frequency signal is transmitted by a satellite, and after the terminal receives the wideband radio frequency signal, the wideband radio frequency signal is processed by a radio frequency front end to down-convert it to a digital intermediate frequency signal S n , and after processing the digital intermediate frequency signal S n , a first carrier frequency offset estimation value and a first phase-locked loop compensation result are output.

[0072] In one or more possible embodiments, the processing of the acquired wideband radio frequency signal to obtain the first carrier frequency offset estimation value and the first phase-locked loop compensation result comprises: initializing a frequency-locked loop carrier NCO according to an initial carrier compensation result and an initial phase-locked loop compensation result; determining an initial demodulation signal according to the wideband radio frequency signal and a first local signal generated by the frequency-locked loop carrier NCO; determining a first despread signal according to the initial demodulation signal and an initial code loop compensation result, and generating a first integral cleaning result according to the first despread signal; calculating a non-coherent accumulation result according to the first integral cleaning result, and obtaining time synchronization information according to the non-coherent accumulation result; determining the first carrier frequency offset estimation value and the first phase-locked loop compensation result according to the time synchronization information; since the first integral cleaning result is a complex signal (containing in-phase I and quadrature Q components), the phase will be randomly rotated due to the influence of the residual carrier frequency offset, in order to eliminate this phase uncertainty and extract stable signal power, it is necessary to take the modulus square (i.e. calculate I² + Q²) or take the absolute value operation for each integral cleaning result, which is used to convert the complex signal into a positive real number representing signal energy, so that the subsequent accumulation is not affected by the phase jump, then, the real energy values obtained in multiple code periods are accumulated to obtain the non-coherent accumulation result, the above accumulation process is essentially a signal energy accumulation and averaging, which can effectively improve the signal-to-noise ratio, so that the weak synchronization features stand out in the noise background; then, peak detection is performed on the non-coherent accumulation result sequence, the receiver slides on the local code phase, and the above non-coherent accumulation process is repeated at each possible phase offset point, when the phase of the local code is completely aligned with the spread spectrum code phase of the input signal, the despread effect is best, the signal energy is maximum, at this time, the corresponding non-coherent accumulation result will present a significant peak, the position of the peak indicates the accurate arrival time or frame boundary of the signal, thereby obtaining the time synchronization information; and generating a carrier frequency discrimination result between the first local signal and a digital intermediate frequency signal according to the time synchronization information

[0073] Step 202, determining a first feedback gain according to the first carrier frequency offset estimation value and the first phase-locked loop compensation result;

[0074] ​​​​​​​In one or more possible embodiments, the first carrier frequency offset estimation value is compared with a carrier loop bandwidth to determine a first inter-frequency error; the first carrier frequency offset estimation value is compared with the first phase-locked loop compensation result in sign to determine a first loop feedback direction; a first feedback gain is determined according to the first inter-frequency error and the first loop feedback direction; and the specific formula is as follows:

[0075]

[0076] In the present application, is taken as , is taken as , is taken as , and n represents a sampling time; is a carrier loop bandwidth, and sig represents a sign comparison result of the first carrier frequency offset estimation value and the first phase-locked loop compensation result ; if the sign comparison result of the first carrier frequency offset estimation value and the first phase-locked loop compensation result is the same, sig is positive, and if it is opposite, sig is negative; specifically, when it is determined that the absolute value of the first carrier frequency offset estimation value is greater than , and at the same time, it is determined that sig < 0, the following formula is used:

[0077]

[0078] As long as the determination that the absolute value of the first carrier frequency offset estimation value is greater than , and the determination that sig < 0 are not met at the same time, the following formula is used:

[0079]

[0080] The existing scheme provides insufficient correction ability for a large frequency step (large initial frequency offset) under a fixed gain, resulting in too small step length and slow convergence. The application provides a method for generating an inter-frequency error by comparing a carrier frequency offset estimation value with a preset loop bandwidth threshold to determine the size of the generated feedback gain. When the carrier frequency offset estimation value is large, the calculated feedback gain D(n) will significantly increase, which is equivalent to increasing the "total open loop gain" of the loop, making the frequency adjustment step length of the NCO larger, thereby quickly narrowing the frequency difference between the local carrier (generated by the frequency locked loop carrier NCO) and the input signal (wideband radio frequency signal transmitted by the satellite), effectively overcoming the under-regulation problem and greatly shortening the locking time. Under a fixed gain, when the frequency difference is very small, the same gain will be too large, resulting in the loop "overshooting" and producing damped oscillation or continuous oscillation near the balance point. Such oscillation will worsen the demodulation performance and, in severe cases, cause the loop to lose lock. When the carrier frequency offset estimation value decreases, the calculated feedback gain D(n) also decreases, at which time the loop enters the "fine tuning" mode, and the frequency adjustment step length of the NCO becomes very fine, improving the tracking stability and noise immunity. A cycle slip often occurs when the phase detector output of the phase-locked loop crosses the boundary of its linear range (e.g., from +π to -π). In the case of rapid frequency change or noise, a fixed high gain may "push" the phase to quickly cross the boundary, resulting in an incorrect 2π phase jump of the loop. The application solves the cycle slip problem by determining whether the sign of the carrier frequency offset estimation value is consistent with the sign of the phase-locked loop compensation result. If the signs are the same, it means that the frequency difference and the phase difference are in the same direction, and the loop is adjusting in the correct locking direction. If the signs are opposite, it means that the frequency difference and the phase difference are in opposite directions, and the loop is likely to be in the state of "overshooting" and backtracking, or on the edge of cycle slip. At this time, the adaptive module adjusts the feedback gain according to the feedback gain calculation formula, thereby effectively avoiding cycle slip.

[0081] Step 203: processing the first feedback gain to obtain a second carrier frequency offset estimation value, and generating a second phase-locked loop compensation result according to the second carrier frequency offset estimation value;

[0082] In one or more possible embodiments, the first feedback gain is first multiplied by a unit carrier Doppler increment to obtain a carrier Doppler compensation value; the carrier Doppler compensation value, an acquisition predicted Doppler frequency and a carrier frequency fixed frequency word offset are added to obtain a carrier compensation value; a second frequency locked loop carrier compensation result is calculated according to the carrier compensation value and a terminal working clock frequency ; and the second frequency locked loop carrier compensation result determining a second local signal; then mixing the second local signal and the wideband radio frequency signal (here, the wideband radio frequency signal is essentially a processed wideband radio frequency signal, that is, a digital intermediate frequency signal ) to generate a first demodulation signal; at the same time, code loop filtering the first feedback gain, and determining a second code loop compensation result according to the filtered first feedback gain and a unit pseudo code Doppler increment, specifically, calculating a pseudo code Doppler compensation value according to the filtered first feedback gain and the unit pseudo code Doppler increment, and then generating the second code loop compensation result according to the pseudo code Doppler compensation value, a code NCO nominal deviation and a terminal working clock frequency; after determining the second code loop compensation result, calculating a second despread signal according to the first demodulation signal and the second code loop compensation result, and accumulating the second despread signal to obtain a second integral wipeoff result.

[0083] In one or more possible embodiments, the second integral wipeoff result is processed by a frequency discriminator and a frequency locked loop filter to obtain a second carrier frequency offset estimation value, and at the same time, the second integral wipeoff result is phase-rotated to obtain a third integral wipeoff result; the mixed signal (the first demodulation signal) is not completely zero frequency, but has a very small and slowly changing residual frequency, which causes a key problem: the direction of the phase vector represented by the second integral wipeoff result will slowly rotate over time. The step of phase-rotation reverses the mathematical rotation of the second integral wipeoff result, which can actively offset the vector rotation effect caused by the residual frequency difference in the digital domain; after obtaining the third integral wipeoff result, the third integral wipeoff result and the second carrier frequency offset estimation value are processed by a phase discriminator to obtain a carrier phase discrimination result, and the carrier phase discrimination result is filtered by a phase locked loop filter to obtain a second phase locked loop compensation result.

[0084] In one or more possible embodiments, the second carrier frequency offset estimation value is used to assist in updating a phase locked loop NCO carrier generator, specifically, a digital control signal (the second carrier frequency offset estimation value) from the frequency locked loop that changes in real time is used to dynamically configure and drive the phase locked loop NCO carrier generator, so that the frequency of the output signal of the phase locked loop NCO carrier generator pre-approaches the data intermediate frequency signal.

[0085] In one or more possible embodiments, the total control word of the phase-locked loop carrier NCO = the phase-locked loop phase control word + (the frequency estimation value of the frequency-locked loop × the scaling factor); the specific auxiliary update process is as follows: the frequency-locked loop keeps working, and the frequency-locked loop loop filter outputs a smoothed and denoised second carrier frequency offset estimation value, which represents the remaining and relatively stable frequency difference between the current intermediate frequency signal and the frequency-locked loop carrier NCO; then, the second carrier frequency offset estimation value is informationally converted and scaled according to the scaling factor, the scaling factor is related to the phase accumulator bit width of the frequency-locked loop carrier NCO and the clock frequency of the field programmable gate array (FPGA), and the specific calculation formula is as follows:

[0086]

[0087] Wherein, K represents the calculated scaling factor, N represents the phase accumulator bit width of the frequency-locked loop carrier NCO, The clock frequency of the field programmable gate array (FPGA); the role of the scaling factor is to convert the second carrier frequency offset estimation value (i.e. the frequency estimation value of the frequency-locked loop) into a frequency control word increment that can be understood by the phase-locked loop carrier NCO; the scaled frequency-locked loop frequency control word is directly added to the phase control word output by the phase-locked loop loop filter to obtain the superimposed total control word, and then the phase-locked loop carrier NCO adjusts the frequency and phase of the output signal according to the superimposed total control word.

[0088] Step 204, determining a second feedback gain according to the second carrier frequency offset estimation value and the second phase-locked loop compensation result;

[0089] In one or more possible embodiments, the second carrier frequency offset estimation value is compared with the carrier loop bandwidth to determine a second inter-frequency error; the second carrier frequency offset estimation value is compared with the second phase-locked loop compensation result in terms of sign to determine a second loop feedback direction; the second feedback gain is determined according to the second inter-frequency error and the second loop feedback direction; the second feedback gain is generated in the same way as the first feedback gain, and the specific formula is not repeated here.

[0090] Step 205, determining a first code loop compensation result and a first frequency-locked loop carrier compensation result according to the second feedback gain;

[0091] In one or more possible embodiments, a second pseudo-code Doppler compensation value is generated according to the second feedback gain and the second integral clearing result, and then the first code loop compensation result is generated based on the second pseudo-code Doppler compensation value, the code NCO nominal deviation and the terminal working clock frequency; at the same time, the second feedback gain is first multiplied by the unit carrier Doppler increment to obtain a carrier Doppler compensation value; the carrier Doppler compensation value, the acquisition predicted Doppler frequency And the carrier frequency fixed frequency word offset The carrier compensation values ​​are added together to obtain the carrier compensation value; based on the carrier compensation value and the terminal operating clock frequency, the first frequency-locked loop carrier compensation result is calculated.

[0092] Step 206: Demodulate and decode the first code ring compensation result and the first frequency-locked ring carrier compensation result to obtain the message information.

[0093] In one or more possible embodiments, demodulation and decoding are performed based on the first code ring compensation result and the first frequency-locked ring carrier compensation result to generate compensated incoherent integral information and time information. Finally, the message information is decoded based on the incoherent integral information and time information.

[0094] This application also provides a structural schematic diagram of an example of a signal receiving and processing device, specifically as follows: Figure 3 As shown, it includes a phase-locked loop, a frequency-locked loop, and a feedback gain calculation module. The specific processing flow after receiving the broadband radio frequency signal transmitted by the satellite is as follows: First, the broadband radio frequency signal received by the terminal antenna is processed by the radio frequency front-end to output a digital intermediate frequency signal. Then, based on the digital intermediate frequency signal A first integral clearing result is generated; a first phase-locked loop (PLL) compensation result and a first carrier frequency offset estimate are generated based on the first integral clearing result; a first feedback gain is generated based on the first PLL compensation result and the first carrier frequency offset estimate; a carrier compensation result is generated based on the first feedback gain, the capture prediction Doppler frequency, and the carrier frequency fixed frequency word offset, thereby generating a carrier frequency offset compensated digital baseband signal integral clearing result (a second integral clearing result); a second carrier frequency offset estimate and a second PLL compensation result are generated based on the compensated digital baseband signal demodulation result; a code ring NCO compensation result is generated based on the second carrier frequency offset estimate, the second PLL compensation result, and the digital baseband signal; finally, demodulation and decoding are performed based on the carrier compensation result and the code ring compensation result to obtain message demodulation information.

[0095] According to the signal synchronization method provided in this application, a tracking structure consisting of a cascaded frequency-locked loop (FLL) and a phase-locked loop (PLL) is adopted. The FLL quickly eliminates the large dynamic Doppler frequency offset of the signal, while the PLL focuses on high-precision carrier phase tracking, effectively solving the problem of easy loss of lock-in in traditional PLLs under high-speed dynamic environments. The two loops use independent carrier generators, achieving noise isolation between the preceding and following stages and reducing mutual interference. In addition, a feedback gain adaptive adjustment module is introduced into the loop, which can dynamically optimize the loop gain according to the frequency offset and the frequency and phase discrimination symbols, significantly improving the locking speed and tracking stability of the loop. This overcomes the under-adjustment, over-adjustment, and cycle slip phenomena existing in fixed-gain designs, thereby ensuring the reliability and accuracy of signal synchronization in low-Earth orbit satellite broadband communication systems.

[0096] Corresponding to the signal synchronization method, the application further provides a signal synchronization device, as shown in the specific Figure 4 The device comprises:

[0097] The signal processing module 401 is configured to process the acquired wideband radio frequency signal to obtain a first carrier frequency offset estimation value and a first phase-locked loop compensation result.

[0098] The first feedback gain determination module 402 is configured to determine a first feedback gain according to the first carrier frequency offset estimation value and the first phase-locked loop compensation result.

[0099] The update module 403 is configured to process the first feedback gain to obtain a second carrier frequency offset estimation value, and generate a second phase-locked loop compensation result according to the second carrier frequency offset estimation value.

[0100] The second feedback gain determination module 404 is configured to determine a second feedback gain according to the second carrier frequency offset estimation value and the second phase-locked loop compensation result.

[0101] The compensation result determination module 405 is configured to determine a first code loop compensation result and a first frequency-locked loop carrier compensation result according to the second feedback gain.

[0102] The text information acquisition module 406 is configured to demodulate and decode the first code loop compensation result and the first frequency-locked loop carrier compensation result to acquire text information.

[0103] Since the device embodiment of the application corresponds to the method embodiment described above, for details not disclosed in the device embodiment, reference can be made to the method embodiment described above, which will not be described in detail in the application.

[0104] The application further provides an electronic device comprising at least one processor; and a memory connected in communication with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the signal synchronization method described above.

[0105] As shown in the specific Figure 5 The device comprises a processor 501, a memory 502, a communication interface 503 and a bus 504. The processor 501, the memory 502 and the communication interface 503 are connected to each other through the bus 504.

[0106] The processor 501 is configured to read instructions in the memory 502 and execute the instructions to enable the at least one processor to perform the signal synchronization method provided by the above embodiments.

[0107] The memory 502 is configured to store various instructions and programs of the signal synchronization method provided by the above embodiments.

[0108] Bus 504 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 Only one thick line is used to represent the bus in the figure, but it does not mean that there is only one bus or only one type of bus.

[0109] Processor 501 can be a central processing unit (CPU), a network processor (NP), a Graphic Processing Unit (GPU), or any combination of CPU, NP, and GPU. It can also be a hardware chip. The hardware chip can be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0110] In addition, the present application also provides a computer readable storage medium, such as Figure 6 As shown in the figure, the computer storage medium stores a computer program, and the computer program is used to make the computer execute any one of the above-mentioned methods.

[0111] The memory can include a readable medium in the form of a volatile memory, such as a random access memory (RAM) 601 and / or a cache memory 602, and can further include a read-only memory (ROM) 603.

[0112] The memory can also include a program / utility 605 having a set of (at least one) program modules 604, such as an operating system, one or more application programs, other program modules, and program data, each of which or a combination of which can include the implementation of a network environment.

[0113] Those skilled in the art will appreciate that embodiments of the present application can be readily used as software, hardware, or a combination of software and hardware. In one embodiment, embodiments of the present application can be implemented in software and / or firmware. In this embodiment, the software implementation can include a computer program product which can include one or more computer program elements having computer readable program code stored therein to carry out the various processes described herein. The computer program elements on the computer readable program code can be executed on a computer or a processor of a computer.

[0114] The present application is described in reference to the flow diagrams and / or block diagrams of the methods, apparatus (systems) and computer program products according to this application. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks. Figure 1 one or more functions specified in the flow diagram and / or block diagram block or blocks. Figure 1 one or more functions specified in the flow diagram and / or block diagram block or blocks.

[0115] These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instructions which implement the flow diagram and / or block diagram block or blocks. Figure 1 one or more functions specified in the flow diagram and / or block diagram block or blocks. Figure 1 one or more functions specified in the flow diagram and / or block diagram block or blocks.

[0116] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the flow diagram and / or block diagram block or blocks. Figure 1 one or more functions specified in the flow diagram and / or block diagram block or blocks. Figure 1 one or more functions specified in the flow diagram and / or block diagram block or blocks.

[0117] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their legal equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A signal synchronization method, characterized in that, include: The acquired broadband radio frequency signal is processed to obtain the first carrier frequency offset estimate and the first phase-locked loop compensation result; The first feedback gain is determined based on the first carrier frequency offset estimate and the first phase-locked loop compensation result, including: The first carrier frequency offset estimate is compared with the carrier loop bandwidth to determine the first inter-frequency error; The first carrier frequency offset estimate is compared with the first phase-locked loop compensation result by sign comparison to determine the first loop feedback direction; The first feedback gain is determined based on the first inter-frequency error and the first loop feedback direction; The first feedback gain is processed to obtain a second carrier frequency offset estimate, and a second phase-locked loop compensation result is generated based on the second carrier frequency offset estimate. Based on the second carrier frequency offset estimate and the second phase-locked loop compensation result, the second feedback gain is determined, including: The second carrier frequency offset estimate is compared with the carrier loop bandwidth to determine the second inter-frequency error; The second carrier frequency offset estimate is compared with the second phase-locked loop compensation result by sign comparison to determine the feedback direction of the second loop; The second feedback gain is determined based on the second inter-frequency error and the second loop feedback direction; The first code ring compensation result and the first frequency-locked ring carrier compensation result are determined based on the second feedback gain; The first code ring compensation result and the first frequency-locked ring carrier compensation result are demodulated and decoded to obtain the message information.

2. The method according to claim 1, characterized in that, The process of processing the acquired broadband radio frequency signal to obtain the first carrier frequency offset estimate and the first phase-locked loop compensation result includes: The frequency-locked loop carrier NCO is initialized based on the initial carrier compensation results and the initial phase-locked loop compensation results; The initial demodulation signal is determined based on the broadband radio frequency signal and the first local signal generated by the frequency-locked loop carrier NCO; The first despread signal is determined based on the initial demodulation signal and the initial code ring compensation result, and the first integral clearing result is generated based on the first despread signal; Calculate the incoherent accumulation result based on the first integral clearing result, and obtain time synchronization information based on the incoherent accumulation result; The estimated value of the first carrier frequency offset and the compensation result of the first phase-locked loop are determined based on the time synchronization information.

3. The method according to claim 1, characterized in that, The step of processing the first feedback gain to obtain the second carrier frequency offset estimate includes: The broadband radio frequency signal is compensated based on the first feedback gain to generate a first demodulated signal; The first feedback gain is subjected to code ring filtering, and the second code ring compensation result is determined based on the filtered first feedback gain and the unit pseudocode Doppler enhancement. The second despread signal is calculated and generated based on the first demodulated signal and the second code ring compensation result, and the second despread signal is accumulated to obtain the second integral clearing result; The second carrier frequency offset estimate is generated based on the second integral clearing result.

4. The method according to claim 3, characterized in that, The step of compensating the broadband radio frequency signal according to the first feedback gain to generate the first demodulated signal includes: Multiply the first feedback gain by the unit carrier Doppler boost to obtain the carrier Doppler compensation value; The carrier Doppler compensation value, the acquisition prediction Doppler frequency, and the carrier frequency fixed frequency word offset are added together to obtain the carrier compensation value. The second frequency-locked loop carrier compensation result is determined based on the carrier compensation value and the terminal operating clock frequency. The second local signal is determined based on the second frequency-locked loop carrier compensation result; The second local signal and the broadband radio frequency signal are mixed to generate a first demodulated signal.

5. The method according to claim 3, characterized in that, The step of generating a second phase-locked loop compensation result based on the second carrier frequency offset estimate includes: The second integral clearing result is phase-rotated to obtain the third integral clearing result; Based on the second carrier frequency offset estimate and the third integral clearing result, a carrier phase discrimination result is generated; Phase filtering is performed on the carrier phase discrimination result to generate a second phase-locked loop compensation result.

6. The method according to claim 3, characterized in that, The step of determining the first code ring compensation result and the first frequency-locked loop carrier compensation result based on the second feedback gain includes: The first code ring compensation result is generated based on the second feedback gain and the second integral clearing result; The second feedback gain is processed by the frequency-locked loop carrier NCO to generate the first frequency-locked loop carrier compensation result.

7. A signal synchronization device, characterized in that, include: The signal processing module is used to process the acquired broadband radio frequency signal to obtain the first carrier frequency offset estimate and the first phase-locked loop compensation result; The first feedback gain determination module is used to determine the first feedback gain based on the first carrier frequency offset estimate and the first phase-locked loop compensation result, including: The first carrier frequency offset estimate is compared with the carrier loop bandwidth to determine the first inter-frequency error; The first carrier frequency offset estimate is compared with the first phase-locked loop compensation result by sign comparison to determine the first loop feedback direction; The first feedback gain is determined based on the first inter-frequency error and the first loop feedback direction; The update module is used to process the first feedback gain to obtain a second carrier frequency offset estimate, and generate a second phase-locked loop compensation result based on the second carrier frequency offset estimate. The second feedback gain determination module is used to determine the second feedback gain based on the second carrier frequency offset estimate and the second phase-locked loop compensation result, including: The second carrier frequency offset estimate is compared with the carrier loop bandwidth to determine the second inter-frequency error; The second carrier frequency offset estimate is compared with the second phase-locked loop compensation result by sign comparison to determine the feedback direction of the second loop; The second feedback gain is determined based on the second inter-frequency error and the second loop feedback direction; The compensation result determination module is used to determine the first code ring compensation result and the first frequency-locked loop carrier compensation result based on the second feedback gain; The message information acquisition module is used to demodulate and decode the first code ring compensation result and the first frequency-locked ring carrier compensation result to acquire message information.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.

9. A computer storage medium, characterized in that, The computer storage medium stores a computer program that causes the computer to perform any one of the methods claimed in claims 1-6.

Images