A gate system for a plasma etching system and a plasma etching system

Abstract

The application discloses a grid system for a plasma etching system and the plasma etching system, and belongs to the field of integrated circuit manufacturing, and comprises grid meshes arranged in sequence on the side of a discharge outlet of a nearby discharge chamber, an Nth intermediate grid mesh, and a grid mesh on the side of a nearby dry etching component, each grid mesh comprises a substrate, a plurality of grid mesh holes are uniformly distributed on the substrate, a first film layer with low surface energy and low sputtering yield is arranged on the outer surface of the substrate, and the inner wall of each grid mesh hole is provided with a second film layer with low surface energy and low sputtering yield; N is an integer greater than or equal to 0. The application can delay the grid mesh loss and delay the adsorption pollution on the surface of the grid mesh.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and more specifically, to a gate system and a plasma etching system for use in a plasma etching system. Background Technology

[0002] Ion beam processing is one of the important processes in the semiconductor manufacturing field. The ion source is the core of the ion beam processing system. It is formed by pressurizing the main cathode at the upstream end of the discharge chamber, ionizing the inert gas in the discharge chamber into plasma through glow discharge, and then extracting the positively charged ion beam through the ion optical system to form an ion beam source with high speed, high energy and directional distribution, which is used for surface etching of relevant materials and components. A crucial functional component in forming a specific ion beam source is the grid system, the core of the ion thruster. It typically consists of two or three precision-machined grid layers: a screen grid (closer to the discharge chamber side, usually grounded or with a low positive bias, working with the chamber wall to confine the plasma within the chamber while allowing some ions to pass through), an accelerating grid (applying a very high negative voltage, forming a powerful electrostatic lens between the screen grid and the accelerating grid, accelerating the passing cations to extremely high speeds, generating thrust), and a decelerating grid (optional, usually part of a three-grid system, typically grounded or with a small positive bias; its main function is to block electrons emitted by the accelerated high-speed ion stream neutralizer, preventing electron backflow and bombardment of the accelerating grid, thus protecting the accelerating grid and further collimating the ion beam). Whether the grid system consists of a screen grid and an accelerating grid, or a screen grid, accelerating grid, and decelerating grid, all provide electrostatic confinement, ion acceleration, and ion beam collimation to ultimately provide an ion source with a specific emission direction or ion distribution for etching the target object.

[0003] In practical applications, the grid surface near the discharge chamber is continuously bombarded by the ion source, which wears down or etches the grid, reducing the lifespan of the grid system and negatively impacting alignment or ion spatial distribution. This further shortens the lifespan, potentially requiring more frequent replacements or adjustments to the grid system, affecting its stable operation. Additionally, the area near the etched material or component (the ion beam exit end) is often contaminated by substances sputtered from the etching process. These etched materials adhere to the grid surface, and continuous deposition alters the ion beam quality or distribution. Furthermore, the adsorbed material may be difficult to remove, further impacting grid maintenance and causing slag contamination during system operation. For example, in ion etching equipment using this grid system to process thin-film circuits, the ion beam etches the thin-film coating on the substrate surface. The coating material adheres to the grid surface, and the etched coating may contain precious metals. This raises questions about how to recover these precious metals, how to extend the continuous operating time of the grid system, and how to avoid the contamination caused by slag during etching.

[0004] The candidate materials for the gate system's grid must first meet the requirements of being able to conduct electricity and heat (such as stainless steel, tungsten, tantalum, molybdenum, etc.). Considering the relevant factors such as machinability and maintainability, molybdenum is preferred as the material for processing and manufacturing the gate system's grid.

[0005] Therefore, based on the following problems existing in the application of the gate system, the gate facing the discharge chamber side is easily bombarded by ions, resulting in rapid wear and consumption; the gate surface facing the ion source emission side is easily contaminated by the adsorption of etched emission materials; and precious metals adsorbed onto the gate are difficult to recover (especially since precious metals directly deposited on the molybdenum gate surface have relatively strong adhesion and are prone to adhesion, resulting in frequent disassembly, cleaning and maintenance of the gate system after contamination on the gate surface, and it is difficult to collect relatively high purity precious metal materials).

[0006] The above background information is provided to facilitate understanding of the present invention and is not intended to be publicly known technology disclosed to the general public prior to the application of this invention. Summary of the Invention

[0007] To address the aforementioned problems, the present invention provides a gate system for a plasma etching system, which can delay gate loss and delay adsorption contamination on the gate surface.

[0008] The technical solution is: a gate system for a plasma etching system, comprising a gate mesh adjacent to the discharge outlet side of the discharge chamber, ... an Nth intermediate gate mesh and a gate mesh adjacent to the dry etching component side arranged in sequence. Each gate mesh includes a substrate, on which a plurality of gate mesh holes are uniformly distributed. A first low surface energy and low sputtering yield film layer is disposed on the outer surface of the substrate, and a second low surface energy and low sputtering yield film layer is disposed on the inner wall of each gate mesh hole; N is an integer greater than or equal to 0.

[0009] This invention reduces ion bombardment loss on the discharge chamber side and slows down adsorption and contamination of etched material on the ion emission side by setting a film material with low surface energy and low sputtering yield on the surface of the existing grid and the inner wall of the grid holes. Furthermore, it facilitates the concentrated collection of etched material deposited on the surface.

[0010] Alternatively, N=0 or N=1.

[0011] Optionally, the substrate is made of one of stainless steel, tungsten, tantalum, or molybdenum.

[0012] Optionally, the material of the first low surface energy and low sputtering yield film layer is graphite or zirconium boride, and the material of the second low surface energy and low sputtering yield film layer is graphite or zirconium boride.

[0013] Optionally, the thickness of the first low surface energy and low sputtering yield film layer is 1000nm~25000nm, and the thickness of the second low surface energy and low sputtering yield film layer is 1000nm~25000nm.

[0014] Optionally, the first low surface energy and low sputtering yield film layer and the second low surface energy and low sputtering yield film layer are deposited by magnetron sputtering, electron beam evaporation or chemical vapor deposition.

[0015] Optionally, a first underlayer is provided between the outer surface of the substrate and the first low surface energy and low sputtering yield film layer, and a second underlayer is provided between the second low surface energy and low sputtering yield film layer and the inner wall of the gate hole.

[0016] Optionally, the material of the first substrate is Ti or Cr, and the material of the second substrate is Ti or Cr.

[0017] Optionally, the thickness of the first substrate layer is 20nm~350nm, and the thickness of the second substrate layer is 20nm~350nm.

[0018] Optionally, the first low surface energy and low sputtering yield film, the second low surface energy and low sputtering yield film, the first underlayer and the second underlayer are deposited by magnetron sputtering, electron beam evaporation or chemical vapor deposition.

[0019] Optionally, the further away from the discharge outlet of the discharge chamber, the thicker the second low surface energy and low sputtering yield film.

[0020] The present invention also provides a plasma etching system.

[0021] A plasma etching system includes a working chamber with an opening on the chamber wall that communicates with a plasma generating chamber. A gate system and a dry etching component are installed inside the working chamber. The gate system is located between the opening communicating with the plasma generating chamber and the dry etching component. The gate system is the aforementioned gate system for a plasma etching system.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0023] This invention reduces ion bombardment loss on the discharge chamber side and slows down adsorption and contamination of etched material on the ion emission side by setting a film material with low surface energy and low sputtering yield on the surface of the existing grid. Furthermore, it facilitates the concentrated collection of etched material deposited on the surface. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic top view of the gate system of the present invention;

[0026] Figure 2 This is a schematic diagram of the gate mesh portion of the gate system of the present invention;

[0027] Figure 3 This is a schematic diagram of the substrate, film layer, and underlayer structure of the present invention;

[0028] Figure 4 A schematic diagram of the inner wall of the grid mesh, the film layer, and the underlayer structure;

[0029] Figure 5 This is a schematic diagram of the plasma etching system structure of the present invention;

[0030] Explanation of reference numerals in the attached figures: 1. Grid near the discharge outlet side of the discharge chamber; 2. Grid near the dry etching component side; 3. Substrate; 4. Grid hole; 5. First low surface energy and low sputtering yield film layer; 6. Second low surface energy and low sputtering yield film layer; 7. First underlayer layer; 8. Second underlayer layer; 9. Working chamber; 10. Port communicating with the plasma generation chamber; 11. Gate system; 12. Dry etching component. Detailed Implementation

[0031] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, an indirect connection via an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0032] In the description of this invention, it should be understood that the terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In the description of this invention, "a plurality of" means two or more, unless otherwise precisely specified.

[0033] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] Please refer to Figures 1-4 , Figure 1 This is a schematic top view of the gate system of the present invention. Figure 2 This is a schematic diagram of the gate mesh portion of the gate system of the present invention. Figure 3 This is a schematic diagram of the substrate, film layer, and underlayer structure of the present invention. Figure 4 This is a schematic diagram of the inner wall of the grid mesh, the film layer, and the underlayer structure of the present invention.

[0036] A gate system includes a gate 1 near the discharge outlet side of a discharge chamber and a gate 2 near the dry etching component side. Each gate includes a substrate 3, on which a plurality of gate holes 4 are uniformly distributed. A first low surface energy and low sputtering yield film layer 5 is disposed on the outer surface of the substrate 3, and a second low surface energy and low sputtering yield film layer 6 is disposed on the inner wall of each gate hole 4.

[0037] By setting a first low surface energy and low sputtering yield film layer 5 and a second low surface energy and low sputtering yield film layer 6, the loss of the gate 1 near the discharge outlet side of the discharge chamber and the adsorption contamination on the surface of the gate 2 near the dry etching component side can be delayed during operation, so that the gate system can be kept in a continuous and stable working state. Furthermore, due to the delay in the adsorption contamination on the surface of the gate 2 near the dry etching component side, the precious metals etched from the dry etching component can be easily deposited at the bottom of the working chamber, which is convenient for the recovery of precious metals.

[0038] In one or more embodiments of the present invention, the substrate 3 is made of stainless steel, tungsten, tantalum, or molybdenum, preferably molybdenum.

[0039] In one or more embodiments of the present invention, the material of the first low surface energy and low sputtering yield film layer 5 is graphite or zirconium boride, and the material of the second low surface energy and low sputtering yield film layer 6 is graphite or zirconium boride.

[0040] In one or more embodiments of the present invention, the thickness of the first low surface energy and low sputtering yield film 5 is 1000 nm to 25000 nm, and the thickness of the second low surface energy and low sputtering yield film 6 is 1000 nm to 25000 nm.

[0041] In one or more embodiments of the present invention, in order to enable the first low surface energy and low sputtering yield film layer 5 to be firmly attached to the surface of the substrate 3, and the second low surface energy and low sputtering yield film layer 6 to be firmly attached to the inner wall of the gate hole 4, a first underlayment 7 is provided between the outer surface of the substrate 3 and the first low surface energy and low sputtering yield film layer 5, and a second underlayment 8 is provided between the second low surface energy and low sputtering yield film layer 6 and the inner wall of the gate hole 4.

[0042] In one or more embodiments of the present invention, the material of the first base layer 7 is Ti or Cr, and the material of the second base layer 8 is Ti or Cr.

[0043] In one or more embodiments of the present invention, the thickness of the first substrate 7 is 20nm~350nm, and the thickness of the second substrate 8 is 20nm~350nm.

[0044] In one or more embodiments of the present invention, the first low surface energy and low sputtering yield film layer 5, the second low surface energy and low sputtering yield film layer 6, the first underlayer 7 and the second underlayer 8 are deposited by magnetron sputtering, electron beam evaporation or chemical vapor deposition.

[0045] In one or more embodiments of the present invention, in order to further extend the operating lifetime of the gate system, the thickness of the second low surface energy and low sputtering yield film 6 of the gate 2 adjacent to the dry etching component side is greater than the thickness of the second low surface energy and low sputtering yield film 6 of the first low surface energy and low sputtering yield film 5.

[0046] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the plasma etching system structure of the present invention.

[0047] A plasma etching system includes a working chamber 9, with an opening 10 on the wall of the working chamber 9 communicating with a plasma generating chamber. A gate system 11 and a dry etching component 12 are installed in the working chamber 9. The gate system 11 is located between the opening 10 communicating with the plasma generating chamber and the dry etching component 12. The gate system 11 is the gate system of the present invention.

[0048] Plasma from the plasma generation chamber collides with the dry etching component 12 after passing through the gate system 11, and dry etching off the noble metal on the dry etching component 12.

[0049] In this invention, the plasma can be, for example, Ar+, F-, etc., with Ar+ being preferred.

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A plasma etching system, comprising a working chamber, wherein an opening communicating with a plasma generating chamber is formed on the wall of the working chamber, a gate system and a dry etching component are installed inside the working chamber, the gate system being located between the opening communicating with the plasma generating chamber and the dry etching component, characterized in that, The gate system includes a gate mesh arranged sequentially on the discharge outlet side of the discharge chamber, ... the Nth intermediate gate mesh, and a gate mesh on the dry etching component side. Each gate mesh includes a substrate with a plurality of gate mesh holes uniformly distributed on it. The outer surface of the substrate is provided with a first low surface energy and low sputtering yield film layer, and the inner wall of each gate mesh hole is provided with a second low surface energy and low sputtering yield film layer; N is an integer greater than or equal to 0. The first low surface energy and low sputtering yield film layer and the second low surface energy and low sputtering yield film layer reduce the adsorption and contamination of the etched material on the ion emission side, which facilitates the concentrated collection of the etched material deposited on the surface. The farther away from the discharge outlet of the discharge chamber, the thicker the film with the second lowest surface energy and the lowest sputtering yield. The thickness of the first low surface energy and low sputtering yield film is 1000nm~25000nm, and the thickness of the second low surface energy and low sputtering yield film is 1000nm~25000nm.

2. The plasma etching system according to claim 1, characterized in that, N=0 or N=1.

3. The plasma etching system according to claim 1, characterized in that, The substrate is made of one of stainless steel, tungsten, tantalum, or molybdenum; and / or The first low surface energy and low sputtering yield film is made of graphite or zirconium boride, and the second low surface energy and low sputtering yield film is made of graphite or zirconium boride.

4. The plasma etching system according to claim 1, characterized in that, The first low surface energy and low sputtering yield film layer and the second low surface energy and low sputtering yield film layer are formed by magnetron sputtering, electron beam evaporation or chemical vapor deposition.

5. The plasma etching system according to claim 1, characterized in that, A first underlayer is provided between the outer surface of the substrate and the first low surface energy and low sputtering yield film layer, and a second underlayer is provided between the second low surface energy and low sputtering yield film layer and the inner wall of the gate hole.

6. The plasma etching system according to claim 5, characterized in that, The first substrate material is Ti or Cr, the second substrate material is Ti or Cr; and / or The thickness of the first layer is 20nm~350nm, and the thickness of the second layer is 20nm~350nm.

7. The plasma etching system according to claim 5, characterized in that, The first low surface energy and low sputtering yield film layer, the second low surface energy and low sputtering yield film layer, the first underlayer and the second underlayer are deposited by magnetron sputtering, electron beam evaporation or chemical vapor deposition.

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