A method and system for correcting data errors in network transmission terminals

Abstract

This application proposes a method and system for correcting data errors in network transmission terminals, relating to the field of data transmission error correction technology. The method includes: monitoring the operating status of the internal data bus of an industrial control terminal, obtaining bus load indicators and memory access indicators; assessing whether there is a risk of signal crosstalk on the internal data bus based on the bus load indicators and memory access indicators; when a risk of signal crosstalk exists, applying error coding optimized for consecutive bit errors to the data packet to be received, obtaining the target data packet; storing the bus load status information at the time of data packet reception as a correction context along with the target data packet; and when performing error correction on the target data packet containing the correction context, enabling a decoding algorithm optimized for consecutive bit errors based on the correction context. This application can improve the reliability of data transmission in industrial control terminals and reduce the data error rate at the application layer.

Description

Technical Field

[0001] This application relates to the field of data transmission error correction technology, and in particular to a method and system for correcting data errors in network transmission terminals. Background Technology

[0002] In modern industrial production, the reliability of data transmission is crucial to ensuring smooth, accurate, and safe production processes. With the increasing prevalence of smart manufacturing concepts, industrial control terminals, as core nodes, need to process high-speed data streams from numerous sensors and actuators. This data often demands extremely high real-time performance; any data error can lead to serious production accidents or economic losses. Traditional error correction methods typically focus on addressing random bit errors occurring in the transmission link. However, when the system faces high loads and resource contention, certain special types of errors may arise that are difficult for existing methods to handle effectively.

[0003] However, when the system writes new data packets to the congested buffer at an extreme rate to cope with the continuous influx of data, the internal data bus operates under high load for extended periods. This high-frequency, parallel signal transmission exacerbates crosstalk between adjacent data lines on the bus. Crosstalk is an electromagnetic interference phenomenon that occurs when multiple signal lines transmit data in parallel. When a rapidly changing electrical signal on one line generates an electromagnetic field, this field can induce unwanted voltages or currents on adjacent lines through capacitive or inductive coupling. If this induced pulse is strong enough and happens to occur within the effective window of the receiving end's sampling clock, it can cause a single, normally correct bit to be incorrectly flipped. In extreme cases, especially when multiple data lines switch at high frequencies simultaneously, this crosstalk effect becomes more pronounced, even affecting several neighboring bits, thus transforming an isolated, easily correctable single-bit error into a series of continuous, sudden errors that are difficult to handle with traditional correction methods. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a method and system for correcting data errors in network transmission terminals, aiming to improve the reliability of data transmission in industrial control terminals and reduce the data error rate at the application layer.

[0005] In a first aspect, an embodiment of this application provides a method for correcting data errors in a network transmission terminal, comprising:

[0006] Monitor the operating status of the internal data bus of the industrial control terminal and obtain bus load indicators and memory access indicators;

[0007] Based on the bus load metrics and memory access metrics, assess whether there is a risk of signal crosstalk on the internal data bus;

[0008] When the signal crosstalk risk exists, error coding optimized for consecutive bit errors is applied to the data packet to be received to obtain the target data packet;

[0009] The bus load status information at the time of data packet reception is used as the correction context and stored together with the target data packet;

[0010] When performing error correction on the target data packet storing the correction context, a decoding algorithm optimized for consecutive bit errors is enabled based on the correction context.

[0011] According to some embodiments of this application, when the signal crosstalk risk exists, applying error coding optimized for consecutive bit errors to the data packet to be received to obtain the target data packet includes:

[0012] The transient voltage value, instantaneous current consumption, and power transmission path of the transceiver of the internal data bus are collected.

[0013] Based on the transient voltage value and the instantaneous current consumption, assess whether there is a risk of abnormal power supply in the power transmission path;

[0014] When the aforementioned power supply abnormality risk exists, a power supply abnormality risk identifier is generated;

[0015] Based on the power supply anomaly risk indicator, error coding optimized for consecutive bit errors is applied to the data packet to be received, resulting in the target data packet.

[0016] According to some embodiments of this application, storing the bus load state information at the time of data packet reception as a correction context along with the target data packet includes:

[0017] Monitor the read / write error rate, bit flip rate, and access latency of the memory region storing the correction context;

[0018] Based on the read / write error rate, the bit flip rate, and the access latency, a memory anomaly risk identifier is generated;

[0019] The memory anomaly risk identifier and the bus load status information at the time of data packet reception are used as the correction context and stored together with the target data packet.

[0020] According to some embodiments of this application, when performing error correction on the target data packet storing a correction context, enabling a decoding algorithm optimized for consecutive bit errors based on the correction context includes:

[0021] Analyze the actual error bit distribution pattern of the target data packet;

[0022] Compare the actual error bit distribution pattern with the error pattern indicated by the correction context;

[0023] When the actual error bit distribution pattern is inconsistent with the error pattern indicated by the correction context, the hybrid decoding algorithm is started, and the parameters of the hybrid decoding algorithm are adjusted according to the actual error bit distribution pattern.

[0024] When the actual error bit distribution pattern matches the error pattern indicated by the correction context, a decoding algorithm optimized for consecutive bit errors is enabled.

[0025] According to some embodiments of this application, when the signal crosstalk risk exists, applying error coding optimized for consecutive bit errors to the data packet to be received to obtain the target data packet includes:

[0026] Continuously monitor the utilization of the internal data bus and memory access latency;

[0027] Calculate the current signal crosstalk risk level based on the utilization rate and the memory access latency;

[0028] Based on the signal crosstalk risk level, the error correction capability parameters of the error coding optimized for continuous bit errors are adjusted to obtain the target error correction capability parameters;

[0029] Based on the target error correction capability parameters, error coding optimized for consecutive bit errors is applied to the data packets to be received to obtain the target data packets.

[0030] According to some embodiments of this application, adjusting the error correction capability parameters of the error coding optimized for continuous bit errors based on the signal crosstalk risk level to obtain the target error correction capability parameters includes:

[0031] Obtain the computational resource utilization and power consumption of the encoding engine;

[0032] Based on the signal crosstalk risk level, the computing resource utilization rate, the power consumption, and the preset resource consumption threshold, the error correction capability parameters of the error coding optimized for continuous bit errors are adjusted to obtain the target error correction capability parameters.

[0033] According to some embodiments of this application, adjusting the error correction capability parameters of the error coding optimized for continuous bit errors based on the signal crosstalk risk level to obtain the target error correction capability parameters includes:

[0034] Monitor the rate of change of the signal crosstalk risk level;

[0035] When the rate of change exceeds a preset threshold, the encoding engine is triggered to enter a fast response mode;

[0036] In the fast response mode, computing resources are prioritized for adjusting the error correction capability parameters;

[0037] Based on the signal crosstalk risk level and the computing resources, the error correction capability parameters of the error coding optimized for continuous bit errors are adjusted to obtain the target error correction capability parameters.

[0038] According to some embodiments of this application, obtaining the computational resource utilization rate of the encoding engine includes:

[0039] Obtain the instruction cycle count and memory access count when an independent hardware thread and logic processing unit executes encoding operations;

[0040] Obtain the encoding tasks and non-encoding tasks, and only perform statistics on the resource consumption of the encoding tasks to obtain the resource consumption of the encoding tasks;

[0041] The computational resource utilization rate of the encoding engine is calculated based on the number of instruction cycles, the number of memory accesses, and the resource consumption of the encoding task.

[0042] According to some embodiments of this application, obtaining the power consumption of the encoding engine includes:

[0043] Obtain the encoding task and non-encoding tasks, and only count the power consumption of the encoding task to obtain the power consumption of the encoding task;

[0044] Obtain the instantaneous current and voltage of the encoding task;

[0045] The power consumption of the encoding engine is calculated based on the instantaneous current and voltage of the encoding task and the power consumption of the encoding task.

[0046] Secondly, embodiments of this application provide a network transmission terminal data error correction system, comprising:

[0047] The acquisition module is used to monitor the operating status of the internal data bus of the industrial control terminal and acquire bus load indicators and memory access indicators.

[0048] The evaluation module is used to evaluate whether there is a risk of signal crosstalk on the internal data bus based on the bus load index and the memory access index.

[0049] The encoding module is used to apply error coding optimized for consecutive bit errors to the data packet to be received when the signal crosstalk risk exists, so as to obtain the target data packet;

[0050] The storage module is used to store the bus load status information at the time of receiving the data packet as a correction context, together with the target data packet;

[0051] The correction module is used to enable a decoding algorithm optimized for consecutive bit errors based on the correction context when performing error correction on the target data packet storing the correction context.

[0052] This application discloses a data error correction method for network transmission terminals. By monitoring the operating status of the internal data bus of an industrial control terminal, bus load indicators and memory access indicators are obtained, and signal crosstalk risk is assessed accordingly. When signal crosstalk risk exists, error coding optimized for consecutive bit errors is applied to the incoming data packets, and the bus load status information at the time of data packet reception is stored as the correction context. During error correction, a decoding algorithm optimized for consecutive bit errors is activated based on the correction context. This method effectively solves the problems in existing technologies where, under high load and high-concurrency data flow impacts, internal data bus signal crosstalk causes consecutive bit errors in industrial control terminals, and traditional error correction methods suffer from low efficiency and insufficient error correction capabilities in handling such errors. By dynamically assessing internal system risks and specifically optimizing error coding and decoding strategies, this application significantly improves the reliability of data transmission in industrial control terminals, reduces the data error rate at the application layer, and ensures the continuity of production operations and the accuracy of data.

[0053] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0054] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0055] Figure 1 A flowchart illustrating a network transmission terminal data error correction method provided in one embodiment of this application;

[0056] Figure 2 This is a schematic diagram of a network transmission terminal data error correction system provided in one embodiment of this application. Detailed Implementation

[0057] To make the objectives, technical methods, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0058] It should be noted that the meaning of "multiple" (or "more than") in the description of the embodiments of this application refers to two or more, and "greater than," "less than," "exceeding," etc. are understood to exclude the number itself, while "above," "below," "within," etc. are understood to include the number itself. If "first," "second," etc. are used in the description, they are only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or the order of the technical features indicated.

[0059] Based on the above, this application proposes a method and system for correcting data errors in network transmission terminals, aiming to improve the reliability of data transmission in industrial control terminals and reduce the data error rate at the application layer.

[0060] See Figure 1 , Figure 1 This is a flowchart illustrating a network transmission terminal data error correction method according to an embodiment of this application. The embodiment includes, but is not limited to, steps S110 to S130, which will be described in detail below.

[0061] S110. Monitor the operating status of the internal data bus of the industrial control terminal and obtain bus load indicators and memory access indicators.

[0062] S120. Based on bus load indicators and memory access indicators, assess whether there is a risk of signal crosstalk on the internal data bus;

[0063] S130. When there is a risk of signal crosstalk, apply error coding optimized for consecutive bit errors to the data packet to be received to obtain the target data packet.

[0064] S140. The bus load status information at the time of data packet reception is used as the correction context and stored together with the target data packet;

[0065] S150. When performing error correction on a target data packet that stores a correction context, enable a decoding algorithm optimized for consecutive bit errors based on the correction context.

[0066] It should be noted that "industrial control terminal" refers to devices used for data acquisition, processing, control, and communication in industrial automation and control systems, such as programmable logic controllers (PLCs), field controllers in distributed control systems (DCS), and industrial PCs. These terminals typically include one or more processors, memory, a data bus, and various input / output interfaces for data interaction with sensors, actuators, and other control units. "Internal data bus" refers to the high-speed communication channel within the industrial control terminal used to connect components such as processors, memory, and peripherals, such as the PCIe bus and AMBA bus. "Signal crosstalk risk" refers to the possibility of mutual interference between adjacent signal lines due to electromagnetic coupling when the internal data bus is under high load. This interference may lead to data transmission errors, especially consecutive bit errors. "Consecutive bit error optimization" refers to the design of error encoding and decoding algorithms that specifically consider the characteristics of consecutive or locally concentrated erroneous bits in data packets to improve the error correction capability for such errors.

[0067] In one embodiment, the operating status of the internal data bus of the industrial control terminal is monitored to obtain bus load indicators and memory access indicators. Bus load indicators reflect the busyness of the data bus; for example, they can be obtained by measuring the data bus utilization, data throughput, or transmission queue depth. For instance, a hardware monitoring unit can be configured to statistically analyze the ratio of effective data transmission volume to total transmission capacity per unit time, thereby obtaining the bus utilization rate. Memory access indicators reflect the pressure on the memory system; for example, they can be obtained by measuring memory access latency, memory bandwidth utilization, or memory controller queue length. Next, based on the obtained bus load and memory access indicators, the presence of signal crosstalk risk on the internal data bus is assessed. The assessment process can be based on preset thresholds or models. For example, when the bus utilization rate consistently exceeds 80% and the memory access latency exceeds 100 nanoseconds, a high risk of signal crosstalk can be considered. As another assessment method, a machine learning-based model can be established. This model predicts the signal crosstalk risk in the current state by learning the relationship between historical data bus operating states and actual error occurrences. For example, the model can take real-time monitored bus load and memory access metrics as input and output a risk score between 0 and 1, with a higher score indicating a greater risk. Furthermore, when crosstalk risk exists, error coding optimized for consecutive bit errors is applied to the incoming data packet to obtain the target data packet. This means the system dynamically adjusts the error coding strategy based on the evaluation results. For example, Reed-Solomon codes or low-density parity-check codes (LDPC codes), which have strong error correction capabilities for consecutive bit errors, can be used. Specifically, when crosstalk risk is detected, the coding module can select a coding scheme with higher error correction capabilities from a pre-set coding scheme library. Next, the bus load status information at the time of data packet reception is used as a correction context and stored along with the target data packet. Storing the correction context provides additional information for subsequent decoding, assisting the decoding algorithm in more accurate error correction. Finally, when performing error correction on the target data packet with the stored correction context, a decoding algorithm optimized for consecutive bit errors is activated based on the correction context. This means the selection and parameter adjustment of the decoding algorithm are guided by the correction context. For example, when the correction context indicates a high risk of signal crosstalk during reception, the decoding module will prioritize the use of decoding algorithms specifically designed to handle consecutive bit errors, such as a Viterbi-based decoder or an iterative decoder.

[0068] It should be noted that collecting transient voltage and instantaneous current consumption of the transceiver on the internal data bus, as well as the power transmission path, refers to deploying voltage and current sensors near the transceiver on the internal data bus of the industrial control terminal to monitor voltage fluctuations and current consumption in real time during data transmission. Simultaneously, the physical characteristics and connection status of the power transmission path are analyzed to identify potential power supply weaknesses. The purpose is to obtain real-time, fine-grained data on the power supply status, providing a basis for subsequent risk assessment. Assessing whether there is a power supply anomaly risk in the power transmission path based on transient voltage and instantaneous current consumption can be understood as analyzing the collected transient voltage and instantaneous current consumption data. For example, when the voltage value drops significantly within a short period or the current consumption shows abnormal spikes, combined with preset thresholds or pattern recognition algorithms, it can be determined whether there are abnormalities such as unstable power supply, voltage drops, or current overload in the power transmission path. The purpose is to identify potential data error risks caused by power supply problems.

[0069] In one embodiment, an industrial control terminal is transmitting data at high speed via an internal data bus. At a certain moment, a sudden change in the external load causes a transient voltage drop on the power transmission path. At this time, the system uses sensors deployed near the transceiver to collect the transient voltage value and instantaneous current consumption of the transceiver in real time. For example, if a voltage drop from 5V to 4.5V is detected within microseconds, and abnormal fluctuations in instantaneous current consumption are observed, the system will assess the risk of a power supply anomaly based on a preset threshold. Therefore, even if a power supply anomaly causes continuous data bit flipping, the received data packets can be effectively corrected through subsequent decoding, thus ensuring the accuracy of industrial control data and the stable operation of the system.

[0070] It should be noted that monitoring the read / write error rate, bit flip rate, and access latency of the memory region in the storage correction context refers to acquiring the operational status parameters of the memory region in real time or periodically through the memory controller or a dedicated hardware monitoring unit. The read / write error rate can be understood as the ratio of the number of failed memory read / write operations to the total number of operations within a certain period. The bit flip rate refers to the frequency of accidental flips of bits stored in memory, and the access latency represents the time interval from issuing a memory access request to the actual availability of data. These indicators directly reflect the health and stability of the memory. Generating a memory anomaly risk identifier based on the read / write error rate, bit flip rate, and access latency can be understood as comprehensively judging whether memory anomalies exist based on preset thresholds or models. For example, when any one of the read / write error rate, bit flip rate, or access latency exceeds a preset safety threshold, it can be determined that there is a memory anomaly risk, and a corresponding memory anomaly risk identifier is generated. This identifier can be a Boolean value, a risk level, or a structure containing specific anomaly information.

[0071] In one embodiment, suppose an industrial control terminal receives a data packet while its internal data bus is under high load. Simultaneously, the memory region storing the data packet and correction context also detects a high bit flip rate and access latency. First, the system monitors the bus load and memory access metrics and assesses a risk of signal crosstalk. Then, error coding optimized for consecutive bit errors is applied to the incoming data packet to obtain the target data packet. The system monitors the memory region storing the target data packet and correction context. For example, the memory controller records that in the past minute, this memory region experienced 10 bit flips, and the average access latency increased from the normal 50 nanoseconds to 150 nanoseconds. Based on preset thresholds (e.g., bit flip rate exceeding 5 times / minute, access latency exceeding 100 nanoseconds), the system determines that there is an abnormal risk in the memory and generates a memory abnormal risk flag, for example, setting it to "high memory risk". Subsequently, this "high memory risk" flag is integrated with the bus load status information at the time of data packet reception (e.g., "high bus load") to form a correction context containing both "high bus load" and "high memory risk". This extended correction context is then stored along with the target data packet. When error correction of the target data packet is required, the decoding algorithm reads this correction context, which contains information on "high bus load" and "high memory risk." Based on the "high bus load," the decoding algorithm anticipates the potential presence of consecutive bit errors in the data packet; while based on the "high memory risk," particularly the "high bit flip rate," the decoding algorithm further anticipates that the data packet may also be affected by random bit errors after storage. Therefore, the decoding algorithm can employ a hybrid decoding strategy, such as first attempting to correct consecutive bit errors and then performing secondary correction for random bit errors, or adjusting decoding parameters to more effectively handle mixed error patterns.

[0072] It should be noted that analyzing the actual error bit distribution pattern of the target data packet refers to identifying the erroneous bits in the data packet after receiving it, using specific error detection mechanisms (such as Cyclic Redundancy Check (CRC), checksums, etc.), and further analyzing the spatial distribution characteristics of these erroneous bits, such as whether they appear in a concentrated manner (continuous errors) or dispersedly (random errors), as well as the length and density of the errors. The purpose is to obtain the most accurate current error status of the data packet. Comparing the actual error bit distribution pattern with the error pattern indicated by the correction context can be understood as comparing the actual error bit distribution pattern of the target data packet obtained through analysis with the expected or inferred error pattern contained in the correction context. The error pattern indicated by the correction context is usually inferred based on environmental factors such as bus load status information at the time of data packet reception; for example, high bus load may indicate continuous bit errors. The purpose of this comparison is to determine whether the actual error situation matches the environmental prediction.

[0073] In one embodiment, it is assumed that at a certain moment, the bus load and memory access metrics of the internal data bus of the industrial control terminal indicate a high risk of signal crosstalk, thus the correction context indicates that consecutive bit errors may occur. Based on this, the system applies error coding optimized for consecutive bit errors to the incoming data packet. However, when the target data packet is received, analysis of its actual error bit distribution pattern reveals that although errors exist, they are not typical consecutive bit errors, but rather exhibit more dispersed random error characteristics, possibly caused by instantaneous voltage fluctuations or other non-bus crosstalk factors. At this point, the actual error bit distribution pattern is inconsistent with the consecutive bit error pattern indicated by the correction context. Simultaneously, based on the detected dispersed random error pattern, the parameters of the hybrid decoding algorithm are adjusted, for example, by increasing the number of iterations of the LDPC code or adjusting its parity check matrix, to more effectively correct these randomly distributed errors. If the actual error pattern is indeed a consecutive bit error, consistent with the correction context, a decoding algorithm specifically optimized for consecutive bit errors is activated.

[0074] It's important to note that continuously monitoring the utilization of the internal data bus and memory access latency refers to acquiring the real-time busy level of the internal data bus and the time required for data access in memory per unit of time. Bus utilization reflects the data transmission load of the bus, while memory access latency may indicate congestion in the memory controller or bus links; both are closely related to the probability and severity of signal crosstalk. Calculating the current signal crosstalk risk level based on utilization and memory access latency can be understood as using a preset algorithm or model, taking the monitored bus utilization and memory access latency as input, and outputting a quantified risk level. For example, multiple risk thresholds can be set to divide the risk level into low, medium, and high levels, or a continuous risk score can be calculated. The risk level aims to accurately reflect the degree of signal crosstalk threat in the current bus environment. Adjusting the error correction capability parameters of the error coding optimized for continuous bit errors based on the signal crosstalk risk level to obtain the target error correction capability parameters refers to dynamically changing the redundancy or error correction strength of the error coding scheme based on the calculated risk level. For example, when the risk level is high, the redundant bits in the encoding can be increased to improve its error correction capability; when the risk level is low, the redundancy can be appropriately reduced to decrease encoding overhead. Error correction capability parameters may include, but are not limited to, encoding rate, codeword length, and number of parity bits. Furthermore, applying error coding optimized for consecutive bit errors to the data packet to be received, based on the target error correction capability parameters, to obtain the target data packet refers to applying the adjusted error correction capability parameters to the actual encoding process.

[0075] In one embodiment, it is assumed that in an industrial control terminal, the utilization rate of the internal data bus during normal operation is typically below 50%, and the memory access latency is below 100 nanoseconds. When the bus utilization rate is detected to consistently exceed 70% and the memory access latency exceeds 200 nanoseconds, the system determines the signal crosstalk risk level to be "moderate." At this time, the error correction capability parameters of the error coding are adjusted, for example, from a scheme with a coding rate of 1 / 2 to a scheme with a coding rate of 1 / 3, to increase redundancy. If the bus utilization rate is further detected to be close to 90% and the memory access latency exceeds 500 nanoseconds, the system will raise the risk level to "high" and further adjust the error correction capability parameters, for example, adopting a scheme with a coding rate of 1 / 4, to provide stronger error correction capability. Conversely, when the bus load and memory access latency return to normal levels, the risk level will decrease, and the error correction capability parameters will be adjusted back to a scheme with lower redundancy to save resources.

[0076] It's important to note that the system acquires the computational resource utilization and power consumption of the encoding engine. Computational resource utilization refers to the proportion of computing resources, such as processor time and memory bandwidth, consumed by the encoding engine when performing error encoding operations. Power consumption refers to the electrical energy consumed by the encoding engine during operation. These metrics can be collected in real-time using hardware sensors, operating system APIs, or dedicated monitoring tools. Next, based on the signal crosstalk risk level, computational resource utilization, power consumption, and preset resource consumption thresholds, the error correction capability parameters for error encoding optimized for consecutive bit errors are adjusted to obtain the target error correction capability parameters. The preset resource consumption thresholds can be set according to the specific hardware configuration, performance requirements, and power consumption budget of the industrial control terminal. For example, the CPU utilization can be set to no more than 80%, and the power consumption to no more than a certain number of watts. During the adjustment process, the system comprehensively evaluates the current signal crosstalk risk level's demand for error correction capability, while also considering whether the current computational resource utilization and power consumption of the encoding engine are close to or have exceeded the preset resource consumption thresholds. For example, when the risk level of signal crosstalk is high, the system tends to increase the error correction capability parameter; however, if the computing resource utilization or power consumption of the encoding engine is close to or exceeds the threshold, the system may moderately reduce the increase of the error correction capability parameter, or even maintain the existing parameter or slightly reduce it in extreme cases, in order to avoid system overload.

[0077] In one embodiment, it is assumed that the internal data bus of the industrial control terminal continuously monitors a moderately high level of signal crosstalk risk. The system might tend to increase the error correction capability parameter of the error coding optimized for consecutive bit errors by one level. However, in the scheme of this application, before making this adjustment, the system first obtains the current computing resource utilization and power consumption of the encoding engine. If the computing resource utilization of the encoding engine has reached a preset threshold (e.g., 85%) and the power consumption is close to its maximum allowable value, then even if the signal crosstalk risk level is high, the system may not increase the error correction capability parameter by a full level, but instead choose to increase it by half a level, or prioritize maintaining system stability while ensuring basic error correction capability. For example, the system can make a comprehensive judgment based on a preset decision matrix or adaptive algorithm: when the signal crosstalk risk level is "high" and the resource utilization is "low", the error correction capability parameter is increased by 2 units; when the signal crosstalk risk level is "high" but the resource utilization is "high", the error correction capability parameter is increased by only 1 unit, or even remains unchanged, to avoid system overload. Conversely, if the signal crosstalk risk level is medium, but the computational resource utilization and power consumption of the encoding engine are very low, far below the preset threshold, the system may slightly increase the error correction capability parameters to provide additional redundancy protection without significantly increasing the resource burden.

[0078] It should be noted that the rate of change of the monitored signal crosstalk risk level refers to the system continuously tracking the numerical value of the signal crosstalk risk level and calculating its change or trend within a unit of time. For example, the rate of change can be obtained by performing differential operations, moving averages, or trend analysis on continuously collected risk level data. The purpose is to identify whether the risk level is rapidly rising or falling, so that the system can predict potential risk evolution trends. When the rate of change exceeds a preset threshold, the encoding engine is triggered to enter a fast response mode. The preset threshold can be set based on factors such as the specific application scenario of the industrial control terminal, the requirements for data transmission reliability, and the system's acceptable resource overhead. For example, when the risk level rises by more than a certain percentage or absolute value in a short period of time, the rate of change is considered to have exceeded the threshold. Fast response mode refers to a high-priority, high-efficiency working state that the encoding engine enters to cope with urgent or rapidly changing risk situations. In this mode, the system temporarily adjusts its internal scheduling strategy and resource management mechanism to ensure that adjustments to the error correction capability parameters can be completed quickly. In fast response mode, computing resources are prioritized for adjusting the error correction capability parameters. This means the system will assign higher priority to computing resources such as processor cores, memory bandwidth, and cache space for tasks that perform error correction parameter adjustment, ensuring these tasks can obtain the necessary computing power in a timely manner and avoiding delays caused by resource contention. The aim is to shorten the response time for parameter adjustments, enabling the system to adapt to new risk levels more quickly.

[0079] In one embodiment, it is assumed that in an industrial control terminal, the signal crosstalk risk level of the internal data bus is typically maintained at a low level during normal operation. However, due to a sudden increase in external electromagnetic interference or a sudden surge in a high-priority task, the bus load and memory access metrics rise sharply within a very short time, causing the signal crosstalk risk level to rapidly increase from level 2 to level 5 (assuming risk levels are divided into 1-10). At this time, the system continuously monitors the rate of change of the signal crosstalk risk level. For example, if the risk level increases from level 2 to level 5 within 100 milliseconds, the rate of change (level 3 / 100 milliseconds) exceeds a preset threshold (e.g., level 1 / 100 milliseconds). Once this situation is detected, the encoding engine is immediately triggered to enter a fast response mode. In fast response mode, the system scheduler prioritizes allocating CPU time slices, memory bandwidth, and other computing resources to computational tasks responsible for adjusting error correction capability parameters. For example, parameter adjustment tasks that might have previously needed to wait for other low-priority tasks to complete can now be executed immediately by preempting resources. Because computing resources are prioritized, the encoding engine can quickly calculate and apply a stronger error correction parameter based on the current crosstalk risk level, which has risen to level 5, and the available computing resources. For example, it can adjust the encoding from BCH(63,51) to BCH(63,45) to enhance the ability to correct consecutive bit errors. The entire adjustment process is completed in a very short time, ensuring that incoming data packets are adequately protected during the transient process of rapidly increasing crosstalk risk, effectively avoiding data errors that may be caused by response delays.

[0080] It's important to clarify that coding tasks refer to computational and data processing activities related to error coding, such as the execution of coding algorithms and the management of data buffers. Non-coding tasks, on the other hand, refer to other background processes or applications in the system unrelated to error coding. By distinguishing between coding and non-coding tasks and only statistically analyzing the resource consumption of coding tasks, the accuracy of computational resource utilization can be ensured, avoiding interference from non-coding tasks in the evaluation of coding engine resource utilization. Coding task resource consumption can include various resource indicators such as CPU time, memory bandwidth, and cache usage. The computational resource utilization rate of the coding engine is calculated by comprehensively analyzing the number of instruction cycles, memory accesses, and coding task resource consumption. For example, a weighted average, a statistical method based on performance counters, or a preset computational model can be used to obtain the final utilization rate value. The purpose is to provide a quantitative indicator to accurately reflect the actual degree of utilization of system computational resources by the coding engine within a specific time period.

[0081] This application's solution, by refining the process of obtaining computational resource utilization, can more accurately quantify the actual resource requirements of the encoding engine. By separately counting the number of instruction cycles and memory accesses when independent hardware threads and logic processing units execute encoding operations, the resource consumption details of encoding operations can be captured from the underlying hardware level. Simultaneously, by distinguishing between encoding tasks and non-encoding tasks and only statistically analyzing the resource consumption of encoding tasks, interference from other system activities on the evaluation of encoding engine resource utilization is effectively eliminated, thus ensuring the purity and accuracy of the computational resource utilization data. This provides more reliable and refined input data for subsequently adjusting the error correction capability parameters of the erroneous encoding based on the signal crosstalk risk level.

[0082] It's important to note that obtaining power consumption data for both encoding and non-encoding tasks, and only statistically analyzing the power consumption of encoding tasks, is crucial for accurately assessing the actual power consumption of the encoding engine. This requires distinguishing the power consumption generated by encoding operations from that of other non-encoding tasks within the system. Specifically, the task scheduler or power monitoring module can identify the currently executing task type, and power consumption statistics can be performed only on tasks related to packet encoding. This aims to prevent the power consumption of non-encoding tasks from interfering with the power consumption assessment of the encoding engine, thus obtaining more accurate power consumption data. Obtaining the instantaneous current and voltage of the encoding task involves using sensors integrated into the encoding engine or its power supply path to measure the instantaneous current and voltage during the encoding task's execution in real time. For example, high-precision current and voltage sensors can be used to capture dynamic changes in power consumption. This provides real-time, fundamental electrical parameters for subsequent power consumption calculations. Calculating the power consumption of the encoding engine based on the instantaneous current and voltage of the encoding task and its power consumption involves comprehensively analyzing or calibrating the statistically obtained power consumption of the encoding task with the power consumption calculated from the instantaneous current and voltage. The product of instantaneous current and voltage provides real-time instantaneous power, while the statistically obtained power consumption of the encoding task may be an average or cumulative value over a period of time. By combining these two types of data, the actual power consumption of the encoding engine when performing encoding tasks can be calculated more comprehensively and accurately.

[0083] See Figure 2 , Figure 2 This is a schematic diagram of a network transmission terminal data error correction system provided in one embodiment of this application. The network transmission terminal data error correction system 200 includes:

[0084] The acquisition module 210 is used to monitor the operating status of the internal data bus of the industrial control terminal and acquire bus load indicators and memory access indicators.

[0085] Evaluation module 220 is used to evaluate whether there is a risk of signal crosstalk on the internal data bus based on bus load indicators and memory access indicators;

[0086] Encoding module 230 is used to apply error coding optimized for consecutive bit errors to the data packet to be received when there is a risk of signal crosstalk, so as to obtain the target data packet;

[0087] Storage module 240 is used to store the bus load status information at the time of data packet reception as a correction context, together with the target data packet;

[0088] The correction module 250 is used to enable a decoding algorithm optimized for consecutive bit errors based on the correction context when performing error correction on a target data packet that stores the correction context.

[0089] When industrial control terminals operate under high loads, signal crosstalk may occur on their internal data buses, causing consecutive bit errors in data packets during transmission. Traditional error correction methods often struggle to effectively handle such errors. To address this issue, the acquisition module in this application first monitors bus load and memory access metrics in real time to perceive the operating status of the data bus. These metrics quantify the bus's activity level and memory system pressure, providing a data foundation for subsequent risk assessment. Subsequently, the assessment module evaluates the presence of signal crosstalk risk on the internal data bus based on these real-time acquired metrics. This assessment mechanism allows the system to predict potential error types and severity, rather than passively waiting for errors to occur. Once a signal crosstalk risk is detected, the encoding module immediately takes preventative measures, applying error coding optimized for consecutive bit errors to the incoming data packets. This encoding method enhances the data packets' resistance to consecutive bit errors by introducing additional redundancy information, thus providing stronger protection before the data packets reach the receiving end. After the data packets are received and encoded, the storage module stores the bus load status information at the time of data packet reception as the correction context, along with the target data packet. This correction context is crucial; it records the "environmental information" of the data packet at the time of reception, providing valuable clues for subsequent error correction. For example, if the correction context indicates that the data packet was received under conditions of extreme bus congestion and high risk of signal crosstalk, the correction module can predict the potential presence of consecutive bit errors during subsequent decoding and select a more suitable decoding strategy accordingly. Ultimately, when performing error correction on a target data packet storing the correction context, the correction module activates a decoding algorithm optimized for consecutive bit errors based on the correction context. This means the decoding process is no longer blind but targeted. By utilizing the correction context, the correction module can more intelligently select or adjust the decoding algorithm, for example, prioritizing decoders with stronger error correction capabilities for consecutive bit errors, or adjusting the parameters of the decoding algorithm to better adapt to the current error mode. This context-aware decoding strategy significantly improves the efficiency and accuracy of error correction, especially when dealing with consecutive bit errors caused by signal crosstalk.

[0090] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0091] The foregoing has provided a detailed description of the preferred embodiments of this application. However, this application is not limited to the above-described embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined in this application.

Claims

1. A method for correcting errors in data transmitted by a network terminal, characterized in that, The method comprises the following steps: monitoring the running state of the internal data bus of the industrial control terminal, obtaining a bus load index and a memory access index; evaluating whether there is a signal crosstalk risk on the internal data bus according to the bus load index and the memory access index; when the signal crosstalk risk exists, applying error coding optimized for consecutive bit error to a data packet to be received to obtain a target data packet; storing the bus load state information when the data packet is received as a correction context together with the target data packet; when error correction is performed on the target data packet with the correction context stored, enabling a decoding algorithm optimized for consecutive bit error according to the correction context.

2. The method of claim 1, wherein, The method comprises the following steps: collecting the transient voltage value and the instantaneous current consumption of the transceiver of the internal data bus and the power transmission path; evaluating whether there is a power supply abnormality risk on the power transmission path according to the transient voltage value and the instantaneous current consumption; when the power supply abnormality risk exists, generating a power supply abnormality risk identifier; according to the power supply abnormality risk identifier, applying error coding optimized for consecutive bit error to a data packet to be received to obtain a target data packet.

3. The method of claim 1, wherein, The method comprises the following steps: monitoring the read-write error rate, bit flip rate and access delay of the memory area storing the correction context; generating a memory abnormality risk identifier according to the read-write error rate, bit flip rate and access delay; storing the memory abnormality risk identifier and the bus load state information when the data packet is received as a correction context together with the target data packet.

4. The method of claim 1, wherein, The method comprises the following steps: analyzing the actual error bit distribution mode of the target data packet; comparing the actual error bit distribution mode with the error mode indicated by the correction context; when the actual error bit distribution mode is inconsistent with the error mode indicated by the correction context, starting a hybrid decoding algorithm and adjusting the parameters of the hybrid decoding algorithm according to the actual error bit distribution mode; when the actual error bit distribution mode is consistent with the error mode indicated by the correction context, enabling a decoding algorithm optimized for consecutive bit error.

5. The method of claim 1, wherein, The method comprises the following steps: continuously monitoring the utilization rate of the internal data bus and the memory access delay; according to the utilization rate and the memory access delay, calculating the current signal crosstalk risk level; according to the signal crosstalk risk level, adjusting the error correction capability parameter of the error coding optimized for consecutive bit error to obtain a target error correction capability parameter; According to the target error correction capability parameter, error coding optimized for consecutive bit error is applied to the data packet to be received, to obtain a target data packet.

6. The method of claim 5, wherein, The target error correction capability parameter is obtained by adjusting the error correction capability parameter of the error coding optimized for consecutive bit error according to the signal crosstalk risk level. The computing resource occupancy and power consumption of the encoding engine are obtained. The target error correction capability parameter is obtained by adjusting the error correction capability parameter of the error coding optimized for consecutive bit error according to the signal crosstalk risk level, the computing resource occupancy, the power consumption, and a preset resource consumption threshold.

7. The method of claim 6, wherein, The target error correction capability parameter is obtained by adjusting the error correction capability parameter of the error coding optimized for consecutive bit error according to the signal crosstalk risk level. The change rate of the signal crosstalk risk level is monitored. When the change rate exceeds a preset threshold, the encoding engine is triggered to enter a fast response mode. In the fast response mode, computing resources for adjusting the error correction capability parameter are preferentially allocated. The target error correction capability parameter is obtained by adjusting the error correction capability parameter of the error coding optimized for consecutive bit error according to the signal crosstalk risk level and the computing resources.

8. The method of claim 6, wherein, The computing resource occupancy of the encoding engine is obtained by: The number of instruction cycles and the number of memory accesses when the independent hardware thread and the logical processing unit perform the encoding operation are obtained. The encoding task and non-encoding task are obtained, and only the resource consumption of the encoding task is counted to obtain the encoding task resource consumption. The computing resource occupancy of the encoding engine is obtained by calculating the number of instruction cycles, the number of memory accesses, and the encoding task resource consumption.

9. The method of claim 6, wherein, The power consumption of the encoding engine is obtained by: The encoding task and non-encoding task are obtained, and only the power consumption of the encoding task is counted to obtain the encoding task power consumption. The instantaneous current and voltage of the encoding task are obtained. The power consumption of the encoding engine is obtained by calculating the instantaneous current and voltage of the encoding task and the encoding task power consumption.

10. A network transmission terminal data error correction system, characterized by, The running state of the internal data bus of the industrial control terminal is monitored to obtain a bus load index and a memory access index. Whether the internal data bus has a signal crosstalk risk is evaluated according to the bus load index and the memory access index. When the signal crosstalk risk exists, error coding optimized for consecutive bit error is applied to the data packet to be received to obtain a target data packet. The bus load state information when the data packet is received is stored as a correction context together with the target data packet. When error correction is performed on the target data packet with the correction context stored, a decoding algorithm optimized for consecutive bit error is enabled according to the correction context. ​

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