DMA out-of-order arbitration system supporting multiple encryption algorithms

Abstract

The invention discloses a DMA (Direct Memory Access) out-of-order arbitration system supporting multiple encryption algorithms. The DMA out-of-order arbitration system comprises a DMA controller, a plurality of downlink FIFOs (First In First Out), a plurality of encryption algorithm modules, a plurality of uplink FIFOs and an arbitration module, wherein each DMA channel is respectively and correspondingly connected with one downlink FIFO (First In First Out), and each downlink FIFO corresponds to one or more encryption algorithm modules; each encryption algorithm module is correspondingly connected with one uplink FIFO, and each uplink FIFO corresponds to one or more DMA channels; and the arbitration module is connected with each uplink FIFO and is used for carrying out sequential arbitration judgment on the encrypted data packets in each uplink FIFO and sending the data packets meeting the sequential arbitration judgment in the uplink FIFO to a target end. Therefore, during downlink transmission, the ordered, reliable and efficient transmission of the data under the multi-algorithm scene is realized through a double-layer architecture of configuring the exclusive downlink FIFO for the channel and configuring the exclusive uplink FIFO for the encryption algorithm module in combination with sequence number identification and sequence arbitration judgment.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a DMA out-of-order arbitration system that supports multiple encryption algorithms. Background Technology

[0002] Traditional DMA has significant limitations in scenarios combining multiple encryption algorithms and multiple channels, failing to meet the requirements for simultaneous operation. This limitation primarily stems from deficiencies in the architecture design and adaptation logic of existing technical solutions.

[0003] Specifically, it cannot support multiple encryption algorithms working simultaneously. The lack of an architecture adapted to the differences in algorithm latency leads to data out-of-order processing or inefficiency. It also cannot support multiple channels working simultaneously. The lack of channel isolation and dedicated processing design in the architecture results in data conflicts or loss across multiple channels. Summary of the Invention

[0004] In view of the above problems, the present invention provides a DMA out-of-order arbitration system that supports multiple encryption algorithms, which is used to solve the problems of out-of-order data transmission, data loss and low efficiency of DMA data transmission when multiple encryption algorithms are used in parallel.

[0005] According to a first aspect of the present invention, a DMA out-of-order arbitration system supporting multiple encryption algorithms is provided, including a DMA controller, multiple downlink FIFOs, multiple encryption algorithm modules, multiple uplink FIFOs, and an arbitration module;

[0006] The DMA controller is used to implement downlink and uplink data transmission control; each DMA channel is connected to a corresponding downlink FIFO, each downlink FIFO corresponds to one or more encryption algorithm modules, and the downlink FIFO is used to store data packets sent by the corresponding DMA channel;

[0007] Each encryption algorithm module is connected to an uplink FIFO, and each uplink FIFO corresponds to one or more DMA channels. The encryption algorithm module is used to encrypt the sent data packets to obtain encrypted data packets, and the uplink FIFO is used to store the encrypted data packets sent by the corresponding encryption algorithm module.

[0008] The arbitration module is connected to each uplink FIFO and is used to perform sequential arbitration judgment on the encrypted data packets in each uplink FIFO, and send the data packets in the uplink FIFO that meet the sequential arbitration judgment to the target end.

[0009] Optionally, the DMA controller is further configured to:

[0010] Receive downlink data control instructions sent by the processor; the downlink data control instructions include address information and data transmission information;

[0011] Based on the downlink data control command, the target channel and target encryption algorithm module corresponding to the downlink transmission of the data packet are determined;

[0012] After the control data packets are stored sequentially in the downlink FIFO corresponding to the target channel, they are sent to the target encryption module for encryption processing.

[0013] Optionally, the DMA controller is further configured to:

[0014] Before being sent to the target encryption module for encryption, each data packet is assigned a sequence number to mark the original transmission order of the data packets.

[0015] Optionally, the DMA controller is further configured to:

[0016] Receive uplink data control instructions sent by the processor; the uplink data control instructions include address information and data transmission information;

[0017] Based on the uplink data control command, determine the target channel and target terminal corresponding to the uplink transmission of the encrypted data packet;

[0018] The encrypted data packets are stored sequentially into the uplink FIFO corresponding to the target encryption algorithm module.

[0019] Optionally, the arbitration module is further configured to:

[0020] Iterate through all the encrypted data packets in the uplink FIFO, group each encrypted data packet according to the transmission channel, and determine whether the sequence number identifiers of each encrypted data packet in the same channel are consecutive.

[0021] If the sequence numbers of the encrypted data packets in the same channel are consecutive, then the encrypted data packets in the same channel will be transmitted upstream to the corresponding channel in sequence.

[0022] Optionally, the system further includes a backpressure module, which is configured to:

[0023] When the arbitration module determines that the sequence numbers of the encrypted data packets in the same channel are not consecutive, it suspends the uplink transmission corresponding to that channel.

[0024] Optionally, the backpressure module is configured as follows:

[0025] When the arbitration module determines that the sequence numbers of the encrypted data packets in the same channel are consecutive, it continues to transmit the data packets sequentially to the corresponding channel.

[0026] Optionally, the processor is a GPU.

[0027] Optionally, the processor is a CPU.

[0028] The above-described one or more technical solutions in the embodiments of this specification have at least the following technical effects:

[0029] This specification provides a DMA out-of-order arbitration system supporting multiple encryption algorithms, comprising a DMA controller, multiple downlink FIFOs, multiple encryption algorithm modules, multiple uplink FIFOs, and an arbitration module. The DMA controller is used to implement downlink and uplink data transmission control. Each DMA channel is connected to a corresponding downlink FIFO, and each downlink FIFO corresponds to one or more encryption algorithm modules. The downlink FIFO stores data packets sent by the corresponding DMA channel. Each encryption algorithm module is connected to a corresponding uplink FIFO, and each uplink FIFO corresponds to one or more DMA channels. The encryption algorithm module encrypts the sent data packets to obtain encrypted data packets, and the uplink FIFO stores the encrypted data packets sent by the corresponding encryption algorithm module. The arbitration module is connected to each uplink FIFO and performs order arbitration judgment on the encrypted data packets in each uplink FIFO, sending the data packets in the uplink FIFOs that satisfy the order arbitration judgment to the target end. Thus, by configuring a dedicated downlink FIFO for the channel and a dedicated uplink FIFO for the encryption algorithm module in a two-layer architecture during downlink transmission, combined with sequence number identification and order arbitration judgment, orderly, reliable and efficient data transmission in multi-algorithm scenarios can be achieved.

[0030] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0031] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0032] Figure 1 A schematic diagram of a DMA out-of-order arbitration system supporting multiple encryption algorithms is shown in an embodiment of the present invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0034] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0035] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0036] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "setup," "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0037] Traditional DMA has significant limitations in scenarios combining multiple encryption algorithms and multiple channels, failing to meet the requirements for simultaneous operation. This limitation primarily stems from deficiencies in the architecture design and adaptation logic of existing technical solutions.

[0038] 1. Inability to support multiple encryption algorithms working simultaneously. Due to a lack of design to adapt to differences in algorithm execution time, data may become out of order or inefficient. Specifically:

[0039] Encryption algorithms have inherent differences. The computational complexity and processing speed of different encryption algorithms (such as AES, SM4, and DES) are completely different (for example, AES-128 may only take 10ns to encrypt 1KB of data due to its simple algorithm structure; while some high-strength custom algorithms may take 50ns).

[0040] In existing technologies, DMA typically designs only one data transmission link, and all encrypted data from all encryption algorithms are transmitted back through the same link.

[0041] Hypothetical scenario: DMA transmits two sets of data simultaneously. Data A is encrypted with AES (faster), and data B is encrypted with SM4 (slower). Originally, A should be transmitted before B. However, because AES is faster, data A will be encrypted and transmitted back via DMA ahead of time, while data B is still being encrypted. If DMA directly transmits the already-ready data A, subsequent data B will be transmitted after A after completion, seemingly in an ordered order. However, if multiple sets of data are transmitted alternately (e.g., A1, B1, A2, B2), an out-of-order sequence of A1, A2, B1, B2 will occur.

[0042] Existing technology is also unable to identify which data belongs to which original sequence, and can only transmit data in the order of encryption completion, which ultimately leads to data disorder when multiple algorithms are running in parallel, making it impossible to restore the original order.

[0043] Second, it cannot support simultaneous operation of multiple channels. Due to the lack of channel isolation and dedicated processing design in the architecture, data conflicts or loss occur between multiple channels, as detailed below:

[0044] The essence of a channel is a data transmission link: it can be understood as multiple parallel data lines. For example, in an embedded system, channel 1 transmits video data captured by a camera, channel 2 transmits temperature data captured by a sensor, and channel 3 transmits control commands input by the user. Multiple channels working simultaneously are used to improve data transmission efficiency.

[0045] To save hardware resources, current technologies often adopt a single FIFO + single link design, where data from all channels is crammed into the same FIFO (data buffer) waiting to be transmitted.

[0046] This can lead to data confusion, with video data from channel 1 and temperature data from channel 2 mixed together in the FIFO. The DMA cannot distinguish which data belongs to which channel, resulting in incorrect data attribution during subsequent processing (such as decoding temperature data as video data).

[0047] It can also cause transmission blockage. If the amount of data in a certain channel is too large (such as video data), it will fill the entire FIFO, causing data in other channels to be unable to be written, resulting in channel starvation (for example, temperature data cannot be transmitted, causing the system to be unable to monitor the temperature).

[0048] Existing technologies do not configure dedicated algorithm registers and dedicated downlink FIFOs for each channel, making it impossible to predefine which algorithm to use to encrypt data for a particular channel, nor can they isolate data from different channels, thus failing to support stable operation of multiple channels simultaneously.

[0049] It's important to note that the limitation of existing technologies is not that they are unusable, but rather that they are not suitable for complex scenarios. Existing technologies are not entirely incapable of supporting multiple algorithms or multiple channels, but they can only be used in low-complexity scenarios without parallel requirements.

[0050] For example, a single channel with multiple algorithms: if the system does not need to use multiple algorithms at the same time, but instead uses AES first and then switches to SM4, traditional DMA can be implemented by reconfiguring the algorithm parameters in software, but the switching process will interrupt data transmission, which is extremely inefficient.

[0051] For example, multi-channel + single algorithm: if all channels use the same algorithm (such as using AES), and the data volume is small and there is no real-time requirement, traditional DMA can barely work. However, once the data volume increases or there is a real-time requirement (such as industrial control and communication equipment), out-of-order and data loss problems will occur.

[0052] Based on the above situation, combined with Figure 1 As shown, this embodiment of the invention provides a DMA out-of-order arbitration system supporting multiple encryption algorithms, including a DMA controller, multiple downlink FIFOs, multiple encryption algorithm modules, multiple uplink FIFOs, and an arbitration module;

[0053] The DMA controller is used to implement downlink and uplink data transmission control; each DMA channel is connected to a corresponding downlink FIFO, each downlink FIFO corresponds to one or more encryption algorithm modules, and the downlink FIFO is used to store data packets sent by the corresponding DMA channel;

[0054] Each encryption algorithm module is connected to an uplink FIFO, and each uplink FIFO corresponds to one or more DMA channels. The encryption algorithm module is used to encrypt the sent data packets to obtain encrypted data packets, and the uplink FIFO is used to store the encrypted data packets sent by the corresponding encryption algorithm module.

[0055] The arbitration module is connected to each uplink FIFO and is used to perform sequential arbitration judgment on the encrypted data packets in each uplink FIFO, and send the data packets in the uplink FIFO that meet the sequential arbitration judgment to the target end.

[0056] Optionally, the DMA controller is further configured to:

[0057] Receive downlink data control instructions sent by the processor; the downlink data control instructions include address information and data transmission information;

[0058] Based on the downlink data control command, the target channel and target encryption algorithm module corresponding to the downlink transmission of the data packet are determined;

[0059] After the control data packets are stored sequentially in the downlink FIFO corresponding to the target channel, they are sent to the target encryption module for encryption processing.

[0060] Optionally, the DMA controller is further configured to:

[0061] Before being sent to the target encryption module for encryption, each data packet is assigned a sequence number to mark the original transmission order of the data packets.

[0062] Optionally, the DMA controller is further configured to:

[0063] Receive uplink data control instructions sent by the processor; the uplink data control instructions include address information and data transmission information;

[0064] Based on the uplink data control command, determine the target channel and target terminal corresponding to the uplink transmission of the encrypted data packet;

[0065] The encrypted data packets are stored sequentially into the uplink FIFO corresponding to the target encryption algorithm module.

[0066] Optionally, the arbitration module is further configured to:

[0067] Iterate through all the encrypted data packets in the uplink FIFO, group each encrypted data packet according to the transmission channel, and determine whether the sequence number identifiers of each encrypted data packet in the same channel are consecutive.

[0068] If the sequence numbers of the encrypted data packets in the same channel are consecutive, then the encrypted data packets in the same channel will be transmitted upstream to the corresponding channel in sequence.

[0069] Optionally, the system further includes a backpressure module, which is configured to:

[0070] When the arbitration module determines that the sequence numbers of the encrypted data packets in the same channel are not consecutive, it suspends the uplink transmission corresponding to that channel.

[0071] Optionally, the backpressure module is configured as follows:

[0072] When the arbitration module determines that the sequence numbers of the encrypted data packets in the same channel are consecutive, it continues to transmit the data packets sequentially to the corresponding channel.

[0073] In this embodiment, the DMA controller is the command center for data transmission, responsible for receiving processor instructions and controlling the flow of data between the DMA channel, FIFO, and encryption module. The DMA channel is a dedicated link for data transmission, with each channel corresponding to an independent data transmission path to avoid data from different sources being mixed up. The FIFO (First-In, First-Out) is a temporary buffer for data, storing data according to a first-in, first-out rule to avoid data loss due to differences in device processing speed. The downlink FIFO is used to temporarily store the raw data to be encrypted, while the uplink FIFO is used to temporarily store the encrypted ciphertext data. The encryption algorithm module is the processing unit that implements data encryption, supporting a specific encryption algorithm (such as the AES module or SM4 module), receiving the raw data from the downlink FIFO, and outputting the encrypted ciphertext.

[0074] In this embodiment, the processor can be a CPU or a GPU. Downlink transmission control refers to receiving downlink data control instructions from the processor. These instructions typically include the data source address, data length, target encryption algorithm type, and DMA channel number. After parsing the instructions, a channel and algorithm mapping table is obtained (e.g., DMA channel 1 is bound to the SM4 algorithm, DMA channel 2 is bound to the AES algorithm). Based on this mapping table, the original data packets are read from the memory (e.g., RAM, sensor data register) and transmitted to the corresponding downlink FIFO along the channel-specific path.

[0075] In this embodiment, uplink transmission control can be understood as receiving uplink data control instructions (including the target address of encrypted data packets and the corresponding encryption algorithm number) issued by the processor, parsing them, generating an algorithm-target mapping table (e.g., AES algorithm encrypted data is transmitted back to memory address 0x20000000, SM4 algorithm encrypted data is transmitted back to memory address 0x30000000); monitoring the data readiness status of each uplink FIFO in real time (judged by FIFO full / empty signals); after the arbitration module completes the order judgment, controlling the encrypted data packets that meet the conditions to be transmitted to the target end according to the algorithm-specific path, and simultaneously feeding back the uplink transmission progress to the processor (e.g., the number of bytes transmitted and the number of bytes remaining).

[0076] In this embodiment, 8-32 independent DMA channels are supported (which can be flexibly configured according to business scenarios, such as 8 channels for smart bracelet scenarios and 32 channels for industrial control scenarios). Hardware isolation design is adopted between channels (independent address bus and data bus) to avoid the data transmission abnormality of one channel from affecting other channels. The channel transmission rate can reach up to 1GB / s, which can adapt to different data volume requirements from 16 bytes (heart rate data) to 4KB (batch data of industrial sensors).

[0077] The downlink FIFO (First In First Out queue) adopts a physical isolation design of one FIFO per channel. Each FIFO is an independent hardware storage unit. Its core function is to temporarily store the original data to be encrypted and balance the speed difference between the DMA channel and the encryption algorithm module.

[0078] Specifically, the downlink FIFO and DMA channel are bound one-to-one (e.g., DMA channel 1 is only connected to downlink FIFO 1, and DMA channel 2 is only connected to downlink FIFO 2). The input of each downlink FIFO is connected to the downlink control submodule of the DMA controller via the AXI4-Lite bus, and the output is connected to multiple encryption algorithm modules (e.g., downlink FIFO 1 can be connected to AES, SM4, and DES algorithm modules, allowing the channel data to select the encryption algorithm as needed).

[0079] For example, the stored data packets can adopt a header + payload structure. The header contains a 32-bit channel identifier (corresponding to the DMA channel number) and a 32-bit data length (the number of bytes in the data packet payload). The payload is the original plaintext data, ensuring that the subsequent encryption algorithm module can quickly identify the data channel and data size without additional parsing instructions.

[0080] In this embodiment, the encryption algorithm module is the core processing unit for the system to implement data security encryption. It adopts a parallel design of one algorithm and one hardware core, supports mainstream symmetric encryption algorithms, and can be flexibly expanded according to business security requirements.

[0081] For example, it integrates hardware cores for three industrial-grade encryption algorithms: AES-128 / 256, SM4, and DES by default. Each algorithm core adopts a pipelined architecture (e.g., the AES core uses a 4-stage pipeline), with an encryption rate of up to 2GB / s (AES-128 algorithm encrypts 1KB of data in only 0.5μs). It supports dynamic configuration of algorithm parameters (e.g., the AES core can switch between ECB / CBC / GCM working modes via registers, and the SM4 core can switch between encryption / decryption modes) to meet the security needs of different scenarios (e.g., financial data uses AES-256 CBC mode, and IoT data uses SM4 ECB mode).

[0082] Each encryption algorithm module's input can be connected to 1-8 downlink FIFOs (e.g., the AES module can receive downlink FIFO data from DMA channels 1-8, supporting multi-channel data sharing for encryption with the same algorithm), and its output is connected to a unique corresponding uplink FIFO (e.g., the AES module only connects to uplink FIFO1, and the SM4 module only connects to uplink FIFO2), ensuring that the encrypted data is temporarily stored according to the algorithm's dedicated path and avoiding ciphertext confusion between different algorithms.

[0083] The uplink FIFO is forcibly bound to the encryption algorithm module in a one-to-one manner. Its core function is to temporarily store the encrypted ciphertext data, balance the speed difference between the encryption algorithm module and the arbitration module, and provide a data storage carrier for subsequent sequential arbitration.

[0084] Specifically, the input of each uplink FIFO is connected to a unique corresponding encryption algorithm module (e.g., uplink FIFO1 only receives ciphertext data from the AES module, and uplink FIFO2 only receives ciphertext data from the SM4 module), and the output is connected to the arbitration module, which supports the arbitration module to read the encrypted data packets of each uplink FIFO in a polling order.

[0085] The uplink FIFO and downlink FIFO adopt the same asynchronous architecture, with a depth configuration range of 128-4096 bytes. It supports full threshold interruption (notifying the arbitration module to read the FIFO data first to avoid ciphertext overflow) and empty threshold interruption (notifying the encryption algorithm module to pause writing to avoid empty write). The stored ciphertext data packets adopt an extended header + payload structure. The header adds a 32-bit sequence number identifier (pkt_id, marking the original transmission order) and a 32-bit algorithm identifier (corresponding to the encryption algorithm number) to the downlink data packet header, providing key information for the arbitration module's channel grouping and order determination.

[0086] The uplink FIFO adopts an algorithm-level isolation design, and the storage units of different uplink FIFOs are physically independent (e.g., the storage particles of uplink FIFO1 are completely separated from those of uplink FIFO2). Even if a data error occurs in one uplink FIFO (e.g., bit flip), it will not affect the encrypted storage of other FIFOs, thus ensuring data security.

[0087] In this embodiment, the arbitration module is the core unit for resolving the out-of-order problem caused by the time difference of multiple algorithms. It can be designed with hardware logic circuits and dynamic judgment algorithms, and has the ability to perform multiple FIFO traversal, channel grouping, sequence verification, and data scheduling.

[0088] Specifically, the arbitration module is connected to all uplink FIFOs (it can read the ciphertext data header information of 16 uplink FIFOs at the same time), and its output is connected to the uplink control submodule of the DMA controller. It sends the ciphertext data that meets the order conditions to the DMA controller, and then the DMA controller transmits it to the target end.

[0089] The arbitration module employs a hybrid arbitration strategy combining round-robin and priority-based methods. The specific process is as follows:

[0090] Step 1: Traverse all uplink FIFOs in the order of their numbers (e.g., FIFO1→FIFO2→FIFO3…), read the channel identifier and sequence number identifier (pkt_id) of the encrypted data packets to be transmitted in each FIFO, and generate a FIFO-channel-pkt_id mapping table;

[0091] Step 2: Group the encrypted data packets according to the channel identifier (e.g., group all data packets containing the channel 1 identifier into one group and those containing the channel 2 identifier into another group) to ensure that data packets from the same channel are processed centrally.

[0092] Step 3: Sort each group of data packets by pkt_id in ascending order, and determine whether the current smallest pkt_id is consecutive (e.g., if channel 1 currently has ready pkt_id = 1 and 3, and the missing pkt_id = 2, then it is determined to be non-consecutive; if the ready pkt_id = 1, 2 and 3, then it is determined to be consecutive).

[0093] Step 4: Prioritize data packets with consecutive sequence numbers and high channel priority (channel priority can be configured by the processor, such as in industrial control scenarios where the device status data channel has a higher priority than the log data channel), send them to the DMA controller, and update the already transmitted pkt_id record table at the same time (to avoid duplicate transmission).

[0094] The pipelined decision architecture is adopted, which processes the four steps of traversal, grouping, sorting and decision in parallel (e.g., while judging the order of data packets in channel 1, the FIFO data of channel 2 is traversed). The arbitration response latency is controlled within 10μs, which meets the needs of latency-sensitive scenarios such as industrial control and real-time communication.

[0095] In this embodiment, the backpressure module acts as an anomaly protection unit for system data transmission. It interacts in real time with the arbitration module and DMA controller via a hardware signal link. Its core function is to quickly block uplink transmission when data sequence numbers are discontinuous, preventing out-of-order data from flowing into the target end. When the arbitration module determines that the sequence number identifier of encrypted data packets in the same channel is discontinuous (e.g., channel 1 is missing pkt_id=2), it immediately sends an out-of-order trigger signal to the backpressure module. The signal contains key information such as the channel number and the missing sequence number, ensuring that the backpressure module accurately locates the abnormal channel. After receiving the signal, the backpressure module generates a backpressure control signal and sends it to the uplink transmission control subunit of the corresponding channel in the DMA controller. Upon receiving the signal, the DMA controller immediately stops reading data from the corresponding uplink FIFO and simultaneously sends a transmission pause notification to the target end (e.g., memory) to prevent storage chaos caused by receiving discontinuous data.

[0096] The backpressure module will continuously monitor the arbitration module's judgment result. Before the sequence number identifier is detected to be restored to continuity, it will maintain the backpressure state and prohibit the uplink transmission restart of the corresponding channel to prevent abnormal data from being missed.

[0097] When the arbitration module detects that the sequence numbers of encrypted data packets on the same channel are consecutive (e.g., the missing pkt_id=2 in channel 1 has been filled in, and the sequence number is 1→2→3), it sends a normal sequence recovery signal to the backpressure module. After receiving the signal, the backpressure module immediately generates a backpressure release signal and synchronizes it to the DMA controller. After receiving the release signal, the DMA controller quickly restarts the uplink transmission of the corresponding channel, reads the encrypted data packets from the uplink FIFO in sequence number order, and continues to transmit to the target end. When resuming transmission, the DMA controller will directly start transmitting from the subsequent consecutive sequence number (pkt_id=2) based on the previously recorded transmitted sequence number (e.g., pkt_id=1 has been transmitted in channel 1), without retransmitting the completed part, avoiding data redundancy and ensuring transmission efficiency.

[0098] In summary, the DMA out-of-order arbitration system supporting multiple encryption algorithms provided in this specification includes a DMA controller, multiple downlink FIFOs, multiple encryption algorithm modules, multiple uplink FIFOs, and an arbitration module. The DMA controller is used to implement downlink and uplink data transmission control. Each DMA channel is connected to a corresponding downlink FIFO, and each downlink FIFO corresponds to one or more encryption algorithm modules. The downlink FIFO stores data packets sent by the corresponding DMA channel. Each encryption algorithm module is connected to a corresponding uplink FIFO, and each uplink FIFO corresponds to one or more DMA channels. The encryption algorithm module encrypts the sent data packets to obtain encrypted data packets. The uplink FIFO stores the encrypted data packets sent by the corresponding encryption algorithm module. The arbitration module is connected to each uplink FIFO and is used to perform order arbitration judgment on the encrypted data packets in each uplink FIFO, and send the data packets in the uplink FIFO that satisfy the order arbitration judgment to the target end. Thus, by configuring a dedicated downlink FIFO for the channel and a dedicated uplink FIFO for the encryption algorithm module in a two-layer architecture during downlink transmission, combined with sequence number identification and order arbitration judgment, orderly, reliable and efficient data transmission in multi-algorithm scenarios can be achieved.

[0099] The above are merely various embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A DMA out-of-order arbitration system supporting multiple encryption algorithms, characterized in that, It includes a DMA controller, multiple downlink FIFOs, multiple encryption algorithm modules, multiple uplink FIFOs, and an arbitration module; The DMA controller is used to implement downlink and uplink data transmission control; each DMA channel is connected to a corresponding downlink FIFO, each downlink FIFO corresponds to one or more encryption algorithm modules, and the downlink FIFO is used to store data packets sent by the corresponding DMA channel; Each encryption algorithm module is connected to an uplink FIFO, and each uplink FIFO corresponds to one or more DMA channels. The encryption algorithm module is used to encrypt the sent data packets to obtain encrypted data packets, and the uplink FIFO is used to store the encrypted data packets sent by the corresponding encryption algorithm module. The arbitration module is connected to each uplink FIFO and is used to perform sequential arbitration judgment on the encrypted data packets in each uplink FIFO, and send the data packets in the uplink FIFO that meet the sequential arbitration judgment to the target end.

2. The DMA out-of-order arbitration system supporting multiple encryption algorithms according to claim 1, characterized in that, The DMA controller is also configured to: Receive downlink data control instructions sent by the processor; the downlink data control instructions include address information and data transmission information; Based on the downlink data control command, the target channel and target encryption algorithm module corresponding to the downlink transmission of the data packet are determined; After the control data packets are stored sequentially in the downlink FIFO corresponding to the target channel, they are sent to the target encryption module for encryption processing.

3. The DMA out-of-order arbitration system supporting multiple encryption algorithms according to any one of claims 2, characterized in that, The DMA controller is also configured to: Before being sent to the target encryption module for encryption, each data packet is assigned a sequence number to mark the original transmission order of the data packets.

4. The DMA out-of-order arbitration system supporting multiple encryption algorithms according to claim 3, characterized in that, The DMA controller is also configured to: Receives uplink data control instructions sent by the processor; the uplink data control instructions include address information and data transmission information; Based on the uplink data control command, determine the target channel and target terminal corresponding to the uplink transmission of the encrypted data packet; The encrypted data packets are controlled to be stored sequentially into the uplink FIFO corresponding to the target encryption algorithm module.

5. The DMA out-of-order arbitration system supporting multiple encryption algorithms according to claim 4, characterized in that, The arbitration module is also configured to: Iterate through all the encrypted data packets in the uplink FIFO, group each encrypted data packet according to the transmission channel, and determine whether the sequence number identifiers of each encrypted data packet in the same channel are consecutive. If the sequence numbers of the encrypted data packets in the same channel are consecutive, then the encrypted data packets in the same channel will be transmitted upstream to the corresponding channel in sequence.

6. The DMA out-of-order arbitration system supporting multiple encryption algorithms according to claim 5, characterized in that, The system also includes a backpressure module, which is configured to: When the arbitration module determines that the sequence numbers of the encrypted data packets in the same channel are not consecutive, it suspends the uplink transmission corresponding to that channel.

7. The DMA out-of-order arbitration system supporting multiple encryption algorithms according to claim 6, characterized in that, The back pressure module is configured as follows: When the arbitration module determines that the sequence numbers of the encrypted data packets in the same channel are consecutive, it continues to transmit the data packets sequentially to the corresponding channel.

8. The DMA out-of-order arbitration system supporting multiple encryption algorithms according to claim 1, characterized in that, The processor is a GPU.

9. The DMA out-of-order arbitration system supporting multiple encryption algorithms according to claim 1, characterized in that, The processor is a CPU.

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