A control method, a communication system, a device, and a storage medium

Abstract

The application discloses a control method, a communication system, a device and a storage medium. The method comprises the following steps: detecting the start and end of a data frame in a state in which a physical layer communication chip (PHY) continuously works; starting a data link processing (DLP) circuit when the start of the data frame is detected; and closing the DLP circuit after the end of the data frame is detected and the DLP circuit completes processing of the current data frame. The method effectively reduces the useless power consumption of the DLP during an idle period of the communication system and a minimum interval period between continuous communication frames, retains the real-time capability for random burst transmission, solves the defect of power waste, and is suitable for industrial scenes with requirements for power consumption or heat generation.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a control method, communication system, device and storage medium. Background Technology

[0002] In Ethernet communication architecture, the lowest layer of the protocol includes the Physical Layer (PHY) and the Data Link Layer. The PHY is responsible for the physical transmission of data and clock extraction, while the Data Link Layer undertakes core processing tasks such as data frame verification, format conversion, and link management. To meet the real-time requirements of industrial Ethernet, existing technical solutions generally use hardware circuits (Data Link Process, DLP) to process the data link layer. Compared to software processing via CPU, DLP circuits not only process data faster but also significantly reduce processing latency, ensuring that data can be prepared and transmitted to the receiving end in a short time, meeting the low-latency requirements of real-time scenarios.

[0003] However, existing real-time industrial Ethernet solutions suffer from significant power consumption waste. Because industrial Ethernet needs to handle random bursts of transmission demands, existing technologies mandate that the PHY and DLP circuits remain continuously operational to avoid data loss or response delays due to hardware startup latency. This means the DLP circuits continue running even when the communication system is mostly idle or when there is a minimum interval between adjacent data frames as specified by the protocol during continuous communication. While this design ensures real-time performance, it generates substantial amounts of unnecessary power consumption, especially in industrial scenarios with strict limitations on power consumption and device heat generation, such as outdoor low-power monitoring equipment and battery-powered industrial sensor nodes. This power consumption waste has become a key bottleneck restricting system endurance and stability. Summary of the Invention

[0004] In view of the above problems, this application provides a control method, a communication system, a device and a storage medium.

[0005] The embodiments of this application disclose the following technical solutions:

[0006] The first aspect of this application provides a control method, including:

[0007] While the physical layer communication chip (PHY) is continuously working, the start and end of data frames are detected;

[0008] When the start of a data frame is detected, the data link processing (DLP) circuit is activated.

[0009] When the end of a data frame is detected and the DLP circuit has finished processing the current data frame, the DLP circuit is turned off.

[0010] In one possible implementation, the method further includes:

[0011] If the continuous processing time required by the DLP circuit after the end of the data frame is greater than the minimum interval time between two adjacent data frames, the idle time of the communication link is detected to be greater than the preset interval time threshold.

[0012] When the idle time is detected to be greater than the preset interval time threshold, the DLP circuit is turned off.

[0013] In one possible implementation, the step of shutting down the DLP circuit after detecting the end of a data frame and after the DLP circuit has completed processing the data frame includes:

[0014] When the end of a data frame is detected, a delay signal is sent to the DLP circuit. The delay signal is used to reserve time for the DLP circuit to complete the subsequent processing of the current data frame.

[0015] Real-time detection of the processing status of the DLP circuit for the current data frame;

[0016] Once it is detected that the DLP circuit has completed all processing of the current data frame, the DLP circuit is turned off.

[0017] In one possible implementation, disabling the DLP circuit includes cutting off the clock signal supplied to the DLP circuit or turning off the enable terminal of the DLP circuit.

[0018] In one possible implementation, shutting down the DLP circuit includes reducing or shutting down the power supply to at least a portion of the DLP circuit.

[0019] In one possible implementation, activating the DLP circuit when the start of a data frame is detected includes:

[0020] When the start of a data frame is detected, the DLP circuit is activated during the wake-up time of the DLP circuit, which is the buffering time required for data to be transmitted from the PHY to the DLP through the first-in-first-out buffer.

[0021] In one possible implementation, the method further includes:

[0022] Retrieve historical communication information;

[0023] Based on the historical communication information, the arrival time pattern of data frames is determined;

[0024] Based on the arrival time pattern information of the data frames, predict the estimated arrival time of the next data frame;

[0025] The DLP circuit is activated during a pre-wake-up period prior to the expected arrival time, the pre-wake-up period including at least the wake-up preparation time of the DLP circuit.

[0026] This application provides a control system in embodiment two, including:

[0027] Physical layer communication chip (PHY);

[0028] Data link processing (DLP) circuitry;

[0029] The frame start / end detection circuit is used to execute the control method described in the first aspect above.

[0030] A third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, it implements the control method described in the first aspect above.

[0031] A fourth aspect of this application provides a computer-readable storage medium storing instructions that, when executed on a terminal device, cause the terminal device to perform the control method described in the first aspect above.

[0032] Compared with the prior art, this application has the following beneficial effects:

[0033] To address the technical shortcomings of existing technologies where continuous operation of the PHY and DLP circuits leads to excessive power consumption, this application adopts a control logic that allows the PHY to operate continuously while the DLP is started and stopped on demand. On the one hand, the PHY is kept continuously operational to meet the real-time requirements of asynchronous industrial Ethernet communication for clock extraction and data reception, avoiding data loss or response delays caused by low PHY power consumption. On the other hand, by detecting the start and end of data frames, the DLP circuit is only activated during the data frame transmission and processing phases, and immediately deactivated after the frame ends and the DLP completes processing. This effectively reduces the useless power consumption of the DLP during idle periods of the communication system and during the minimum inter-frame interval of continuous communication. It retains the real-time capability to handle random burst transmissions while solving the problem of wasted power consumption, making it suitable for industrial scenarios where power consumption or heat generation is a concern. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A schematic diagram of interaction logic provided for an embodiment of this application;

[0036] Figure 2 A flowchart of a control method provided in an embodiment of this application;

[0037] Figure 3 This is a structural diagram of a control system provided in an embodiment of this application. Detailed Implementation

[0038] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0039] To facilitate understanding of the technical solutions provided in the embodiments of this application, the technical terms involved in the embodiments of this application will be explained below.

[0040] The Physical Layer (PHY) chip is the core implementation unit of the lowest physical layer of the Ethernet protocol, responsible for physical data transmission and clock extraction. In consumer Ethernet, the PHY has low-power modes such as EEE (Energy Efficient Ethernet), but industrial Ethernet, due to real-time requirements (such as EtherCAT and ProfinetIRT protocols), prohibits the use of its low-power modes. This is because Ethernet is an asynchronous communication network, and the PHY needs to continuously receive data frames to extract and update its local clock (ensuring synchronization with the communication node's clock). If it enters low-power mode, the excessive time spent extracting the clock can lead to data loss or response delays. The document clearly states that the PHY must always be operational, independently controlled only by the DLP circuit, and is the fundamental hardware unit ensuring the real-time performance of industrial Ethernet.

[0041] A First-In-First-Out (FIFO) buffer is a common data buffer in digital system design used to handle data transfer between different clock domains. It effectively solves the problem of data read / write speed mismatch caused by different clock signals, enabling asynchronous data transfer and buffering operations.

[0042] To address the aforementioned issues, this application embodiment significantly reduces the power consumption of the communication system while ensuring the real-time performance of industrial Ethernet by independently controlling the PHY and DLP circuits. On one hand, the PHY is kept constantly operational to meet the requirements of asynchronous Ethernet communication, which necessitates continuous clock extraction and updates to prevent data loss and ensure rapid response, thus adapting to real-time protocol scenarios. On the other hand, by utilizing a frame start / end detection circuit, the DLP circuit is only activated when the start of a data frame is detected, and deactivated after the frame ends and the DLP completes data processing. This effectively reduces the wasted power consumption of the DLP during system idle periods and the minimum inter-frame interval during continuous communication. Furthermore, the DLP shutdown method can be selected based on real-time requirements, allowing for immediate wake-up to adapt to high real-time scenarios (clock shutdown / enablement) or deep power reduction to adapt to low real-time scenarios (partial power reduction / shutdown). Ultimately, this achieves the goal of "saving power without sacrificing performance," solving the problem of power waste caused by continuous PHY and DLP operation in existing technologies and meeting the needs of various industrial scenarios with requirements for power consumption and heat dissipation.

[0043] It should be noted that the control method, communication system, device, and medium provided in this application can be applied to the field of computer technology. The above are merely examples and do not limit the application field of the control method, communication system, device, and medium provided in this application. Furthermore, the embodiments of this application may not limit the executing entity of the control; for example, the control method of the embodiments of this application can be applied to data processing devices such as terminal devices or servers. The terminal device can be an electronic device such as a computer or a personal digital assistant (PDA). The server can be a standalone server, a cloud server, or a cluster server composed of multiple servers.

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0045] See Figure 1 , Figure 1This is a schematic diagram of an interactive logic provided in an embodiment of this application. The various parts are combined to form the physical layer communication chip / physical layer communication module (PHY) provided in this embodiment of the application. The PHY is responsible for continuously transmitting data frames. The frame start and end detection module monitors the data frames transmitted by the PHY in real time and identifies their start and end states. When the start of a data frame is detected, the module generates an enable signal (Enable) to turn on the DLP circuit and enable it to process the data frame. This enables on-demand control of the DLP circuit, which can reduce unnecessary power consumption of the DLP circuit while ensuring data processing.

[0046] The following embodiment illustrates a control method provided in this application. See also: Figure 2 ,Should Figure 2 A flowchart of a control method provided in this application embodiment, the method comprising:

[0047] S101. While the physical layer PHY is continuously working, detect the start and end of the data frame.

[0048] In industrial Ethernet or other communication systems, data is transmitted in frames, each containing valid data and possible control information. Frame start / end detection circuits accurately determine the start and end times of data frames by analyzing specific patterns or flags in the data stream.

[0049] The data frame detection can be performed by either a frame start / end detection module or a frame start / end detection circuit.

[0050] For example, the start of a data frame can be detected by identifying the preamble and start-of-frame delimiter of the Ethernet frame. Once this specific bit sequence is identified, the start of a new data frame is determined. The end of a data frame is determined by detecting the inter-frame interval or the disappearance of the carrier sense signal after the frame. When the data stream returns to an idle state and continues for more than a certain period of time, the current frame is determined to have ended.

[0051] The DLP circuit provides precise trigger signals for turning on S102a and turning off S102b. Only by accurately identifying the start and end of the data frame can we ensure that the DLP only works during the time when data needs to be processed. This avoids wasting power consumption due to the DLP being turned on by mistake or losing data due to the DLP being turned off by mistake. This is the basic guarantee for saving power consumption without sacrificing performance.

[0052] S102a. When the start of a data frame is detected, the data link processing (DLP) circuit is activated.

[0053] Enables on-demand power supply. The DLP circuit is only awakened when data processing is actually needed, thus eliminating its static and dynamic power consumption during idle periods. Upon detecting the start of a frame, an enable signal, such as a high-level pulse, is immediately output to the DLP circuit's control unit. The enable signal restores the clock signal to the DLP circuit and unlocks it, transitioning it from a static power consumption state to a dynamic operating state.

[0054] S102b: When the end of the data frame is detected and the DLP circuit has completed processing of the current data frame, the DLP circuit is turned off.

[0055] When the frame start / end detection circuit / module detects the end of a data frame, it does not immediately shut down the DLP circuit. Instead, it waits for the DLP circuit to complete all processing of the current data frame. This step ensures data integrity and processing accuracy, avoiding data loss or processing errors caused by prematurely shutting down the DLP circuit. Once the DLP circuit has finished processing, the frame start / end detection circuit generates a control signal again to shut down the DLP circuit or reduce its power supply to minimize unnecessary power consumption. This dynamic management method effectively reduces system power consumption while meeting real-time requirements.

[0056] In one possible implementation, the step of shutting down the DLP circuit after detecting the end of a data frame and after the DLP circuit has completed processing the data frame includes: sending a delay signal to the DLP circuit when the end of the data frame is detected, the delay signal being used to reserve time for the DLP circuit to complete subsequent processing of the current data frame; real-time detection of the processing status of the DLP circuit on the current data frame; and shutting down the DLP circuit after detecting that the DLP circuit has completed all processing of the current data frame.

[0057] When the start / end of frame detection circuit detects the end of a data frame, it does not immediately trigger the shutdown operation of the DLP circuit. Instead, it first sends a delay signal to the DLP circuit. This delay signal allows the DLP circuit sufficient time to complete subsequent processing of the current data frame, such as verification, error correction, and data forwarding. By setting a reasonable delay time, it ensures that the DLP circuit can completely and accurately process the current data frame before shutting down, avoiding data loss or processing errors caused by premature shutdown.

[0058] While sending the delay signal, the system initiates a real-time monitoring mechanism for the DLP circuit's processing status. This mechanism monitors the DLP circuit's internal status register, busy / idle flags, or specific completion signals to track the DLP circuit's progress in processing the current data frame. The purpose of real-time monitoring is to accurately determine when the DLP circuit has completed all processing of the current data frame, thus providing an accurate basis for subsequent shutdown operations.

[0059] Once the DLP circuit has completed processing of the current data frame, the system immediately generates a control signal to shut it down. The specific method for shutting down the DLP circuit can be cutting off its clock signal, disabling the enable pin, or reducing its power supply voltage, depending on the system's actual needs and design considerations. By promptly shutting down the DLP circuit, the system can effectively reduce power consumption during idle periods, improving overall energy efficiency. Furthermore, since the shutdown operation is performed after confirming that the DLP circuit has completed all processing, it will not affect the system's real-time performance or data integrity.

[0060] In one possible implementation, disabling the DLP circuit includes cutting off the clock signal supplied to the DLP circuit or turning off the enable terminal of the DLP circuit.

[0061] The clock-off function cuts off the clock signal to the DLP circuit, stopping its logic operations, but the register contents remain unchanged. This significantly reduces power consumption, and wake-up only requires re-enabling the clock, with no additional delay.

[0062] The clock refers to the timing reference signal required for the DLP to operate as a hardware circuit. All dynamic operations within the DLP, such as register data interaction, arithmetic unit logic operations, and data reception and transmission, rely on the clock signal to execute sequentially. Specifically, by cutting off the clock signal supplied to the DLP circuit through a frame start / end detection circuit or a corresponding control unit, the DLP is prevented from performing any dynamic data processing operations, thus entering a low-power state.

[0063] Enable refers to the working permission control function of the DLP circuit, corresponding to the enable terminal (or enable interface) on the DLP hardware. This port receives the control signal sent by the frame start / end detection circuit. Only when the enable signal is in a valid state, such as a specific high / low level, is the DLP circuit allowed to perform core operations such as data reception and data link layer processing, according to the hardware design definition. Conversely, disabling the enable means that the frame start / end detection circuit outputs an invalid enable signal, such as a level opposite to the valid state, cutting off the working permission of the DLP circuit and causing the DLP to stop its core functions and enter a low-power state.

[0064] Because Industrial Ethernet has extremely high real-time requirements for data response, if the DLP circuit enters a deep sleep or complete power-off state, it needs to undergo a complex initialization process upon waking, such as clock synchronization and register reset, which will cause significant delays. However, turning off the clock or enable signal is a shallow sleep mode, which only suspends the circuit function but retains its configuration state. Upon waking, it does not need to be reinitialized and can resume operation immediately, meeting real-time requirements.

[0065] In one possible implementation, shutting down the DLP circuit includes reducing or shutting down the power supply to at least a portion of the DLP circuit.

[0066] Reducing the power supply refers to lowering the operating voltage applied to the DLP circuit (or a portion thereof) by adjusting the power management unit. The circuit can still maintain its basic state in the buck state, but dynamic power consumption and static leakage power consumption will decrease significantly.

[0067] Turning off the power supply refers to completely cutting off the power flowing to the DLP circuit (or a part thereof) by controlling the power switch. This is the most thorough way to save energy, reducing the power consumption of that part of the circuit to almost zero.

[0068] In one possible implementation, activating the DLP circuit when the start of a data frame is detected includes: activating the DLP circuit during its wake-up time when the start of a data frame is detected, wherein the wake-up time of the DLP circuit is the buffering time required for data to be transmitted from the PHY to the DLP through the first-in-first-out buffer.

[0069] The disadvantage of the above-mentioned method of reducing or turning off the power supply is that wake-up takes time and cannot be done immediately. This embodiment solves the contradiction between wake-up delay and real-time requirements by using FIFO buffering delay between PHY and DLP.

[0070] Data transmission from PHY to DLP is asynchronous and requires temporary data storage via FIFO. That is, PHY first writes the received data into FIFO, and DLP then reads the data from FIFO for processing. During this process, the temporary storage of data in FIFO will generate an inherent delay. The duration of the delay depends on the depth of FIFO and the data transmission rate, and can be preset through hardware design.

[0071] The inherent delay of the FIFO is matched with the wake-up delay of the DLP, so that the wake-up operation of the DLP starts synchronously with the process of the PHY writing data to the FIFO. When the frame start end detection circuit detects the start of a data frame, it immediately triggers the power recovery and wake-up process of the DLP. During the time period when the DLP completes the wake-up, the PHY has written some or all of the data to the FIFO. After the DLP is woken up, the data can be read directly from the FIFO for processing without waiting for new data transmission. Thus, the FIFO's buffer delay offsets the DLP's wake-up delay, avoiding data loss or processing lag, and achieving a seamless connection between wake-up and data processing without introducing additional delay.

[0072] In one possible implementation, if the DLP was previously shut down using a low-power method suitable for high real-time scenarios (clock off / enable off), when it is turned on again, only the clock supply needs to be restored and the enable pin needs to be set. The DLP can respond immediately and enter the working state without wake-up delay.

[0073] In one possible implementation, if the continuous processing time required by the DLP circuit after the end of a data frame is greater than the minimum interval between two adjacent data frames, the idle time of the communication link is detected to be greater than a preset interval time threshold; when the idle time is detected to be greater than the preset interval time threshold, the DLP circuit is turned off.

[0074] In industrial Ethernet communication, even when data is transmitted continuously, there is an inherent shortest idle time between two adjacent data frames, which is the minimum interval between two adjacent data frames. After a data frame ends, the DLP needs additional working time to complete the subsequent processing of that frame, such as data verification and signal conversion.

[0075] Post-frame processing time in DLP refers to the time required for the DLP circuit to complete the frame termination work after the data frame transmission ends, such as data verification, format conversion, and transmission of processing results to subsequent modules. This time is inherent to the characteristics of DLP hardware. Minimum interval between adjacent frames refers to the shortest idle time that must be maintained between consecutively transmitted adjacent data frames, as specified by the Industrial Ethernet protocol, to avoid frame collisions.

[0076] Therefore, the frame start and end detection circuit needs to switch its function from judging based on the frame end time to judging based on whether the idle time exceeds a specific interval. By judging the DLP idle window, it ensures that all necessary work has been completed when the DLP is closed, while avoiding wasted power consumption.

[0077] When the idle time of the communication link is detected to be greater than a preset interval threshold, a control signal is generated to shut down the DLP circuit. This ensures that the DLP circuit does not consume power during idle periods, further reducing system power consumption. The specific method for shutting down the DLP circuit can be to disable its clock signal, disable its enable signal, or reduce the power supply, depending on the system's trade-off between wake-up time and power saving.

[0078] In one possible implementation, historical communication data is statistically analyzed to obtain the arrival time pattern of data frames; based on the arrival time pattern, the expected arrival time of the next data frame is predicted; and within a pre-wake-up time before the expected arrival time, the DLP circuit is activated, wherein the pre-wake-up time includes at least the wake-up preparation time of the DLP circuit.

[0079] During operation, the system continuously or periodically records the timestamps of data frame arrivals. This data is stored in a specific register, buffer, or small memory area.

[0080] The first type is periodicity. In scenarios such as periodic sensor data reporting and PLC (Programmable Logic Controller) cyclic communication, data frames arrive at fixed or nearly fixed time intervals. For example, a data frame will inevitably arrive every 10 milliseconds. The pattern can be expressed as: the estimated arrival time of the next frame (T_p) = the arrival time of the previous frame (T_n) + the fixed period (C).

[0081] The second type is the bursty pattern. In some applications, although data frames are not strictly periodic, they tend to arrive within a specific time window. For example, after a certain delay following the issuance of a control command, a batch of data will always return. The pattern can be represented as: within the [X,Y] time window after event A is triggered, there is a high probability of receiving data frames. This transforms communication behavior from "random" to "predictable," providing data support for subsequent pre-wake-up.

[0082] The prediction methods can include the following two:

[0083] Simple periodicity prediction: Estimated arrival time T_p = T_n + C, where T_n is the arrival time of the last frame and C is the statistically obtained average period. Weighted average prediction: Uses a weighted average of the most recent periods to account for minor period fluctuations. For example: T_p = T_n + (0.5*C_{n-1} + 0.3*C_{n-2} + 0.2*C_{n-3}). Transforming historical data into accurate predictions of future events is the basis for triggering pre-wake operations.

[0084] At the time point T_p-T_wake (T_wake being the pre-wake time), a control signal to enable the DLP circuit is issued, instead of waiting until the actual start of a data frame is detected. The pre-wake time T_wake includes at least the "wake-up preparation time" required for the DLP circuit to recover from its current low-power state to its normal operating state.

[0085] T_wake is a dynamic value that depends on the depth to which the DLP circuit was shut down in the previous stage. In one possible implementation: the arrival time pattern includes periodic arrival intervals or burst arrival time windows for data frames; the pre-wake time is dynamically adjusted according to different shutdown modes of the DLP circuit; wherein, if the DLP circuit is in a state of clock off or enable, the pre-wake time is set to zero or a first threshold; if the DLP circuit is in a state of reduced or off power supply, the pre-wake time is set to a second threshold, the second threshold being greater than the first threshold and at least equal to the full wake-up time required for the DLP circuit to recover from a deep sleep state to a normal operating state.

[0086] Scenario 1 illustrates immediate response in shallow sleep mode. In this scenario, the DLP is either clock-off or enabled. The pre-wake time is set to zero or a first threshold (T1). This "shallow sleep" mode has an extremely short wake-up latency (typically within a few clock cycles). Therefore, the system does not need to wake it up long in advance. Setting it to zero means that the existing detection-based immediate-on mechanism can be relied upon entirely, achieving a near-zero latency response. T1 can be a very small design margin to handle extremely minor circuit response delays.

[0087] In this scenario, the primary function of the prediction mechanism is no longer early wake-up, but rather to confirm that "even if early wake-up occurs, it will not result in significant power wastage," because DLP may have just been turned off during the frame interval. This optimizes behavior during extremely short idle intervals.

[0088] Scenario 2 involves early wake-up from deep sleep mode. In this scenario, the DLP is in a state of reduced or shut-off power supply. The pre-wake-up time is set to a second threshold (T2), where T2 > T1, and T2 ≥ the full wake-up time. Wake-up from "deep sleep" mode (e.g., power off) requires a relatively long time, involving power rail establishment, internal register initialization, and clock stabilization. The full wake-up time is a fixed value determined by the hardware circuit characteristics. This solution mandates that the pre-wake-up time must cover this hardware requirement. It allows the system to boldly adopt the most power-efficient shutdown mode during long idle periods because the prediction mechanism ensures sufficient time to safely wake the DLP from "deep sleep," ensuring that the DLP is fully ready when data frames arrive. This mitigates the cost of deep sleep power reduction (wake-up latency) through intelligent prediction.

[0089] This resolves the fundamental contradiction between deep power reduction and real-time performance, allowing the system to boldly use the most energy-efficient method—power-off—to shut down the DLP during communication intervals. The system can predict the arrival of the next data frame in advance and wake up the DLP sufficiently beforehand, ensuring the DLP is ready when data arrives, achieving "zero-wait" processing. The system is no longer a simple start / stop logic but intelligently selects the most power-saving method based on the communication mode (periodic or bursty), while ensuring no performance loss through a predictive mechanism. This makes the invention applicable not only to completely random and bursty communication scenarios but also demonstrates a power consumption advantage far exceeding traditional responsive solutions when handling the numerous periodic communications prevalent in industrial settings, resulting in more significant and outstanding technical effects.

[0090] The above are some specific implementations of the control method provided in the embodiments of this application. Based on this, this application also provides a corresponding control system. The system provided in the embodiments of this application will be described below from the perspective of functional modularity. Figure 3 This is a structural diagram of a control system provided in an embodiment of this application.

[0091] The system includes:

[0092] The detection unit 110 is used to detect the start and end of data frames while the physical layer communication chip PHY is continuously working.

[0093] The enabling unit 111 is used to enable the data link processing (DLP) circuit when the start of a data frame is detected.

[0094] The shutdown unit 112 is used to shut down the DLP circuit when the end of the data frame is detected and the DLP circuit has completed processing the current data frame.

[0095] This application also provides a corresponding communication system, including: a physical layer communication chip (PHY); a data link processing (DLP) circuit; and a frame start / end detection circuit, used to execute the control method provided in this application.

[0096] In other words, the communication system combines the physical layer communication chip PHY, the data link processing DLP circuit, and a frame start and end detection circuit with intelligent decision-making capabilities, thereby materializing the control method provided in the embodiments of this application at the hardware level.

[0097] This application also provides corresponding devices and computer storage media for implementing the control scheme provided in this application.

[0098] The device includes a memory and a processor. The memory is used to store instructions or code, and the processor is used to execute the instructions or code to cause the device to perform the control method described in any embodiment of this application.

[0099] The computer storage medium stores code, and when the code is executed, the device running the code implements the control method described in any embodiment of this application.

[0100] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems or apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0101] It should be understood that in this application, "at least one" refers to one or more items, and "more" refers to two or more items. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one" or similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, "at least one" of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple.

[0102] It should be understood that the terms center, longitudinal, transverse, up, down, front, back, left, right, vertical, horizontal, top, bottom, inside, outside, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0103] It should be noted that, unless otherwise explicitly specified and limited, the terms installation, connection, and linking should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0104] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the statement "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0105] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0106] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A control method, characterized in that, include: While the physical layer communication chip (PHY) is continuously working, the start and end of data frames are detected; When the start of a data frame is detected, the data link processing (DLP) circuit is activated. When the end of a data frame is detected and the DLP circuit has finished processing the current data frame, the DLP circuit is turned off. The step of activating the data link processing (DLP) circuit when the start of a data frame is detected includes: When the frame start / end detection circuit detects the start of a data frame, it triggers the power recovery and wake-up process of the DLP. During the wake-up period of the DLP, the PHY writes some or all of the data into the FIFO. After the DLP wake-up is complete, the data is read from the FIFO for processing, so as to offset the wake-up delay of the DLP by the buffer delay of the FIFO. The method further includes: Statistical analysis of historical communication data is used to obtain the arrival time pattern of data frames, which includes the periodic arrival interval or the time window of sudden arrival of data frames. Based on the arrival time pattern, predict the estimated arrival time of the next data frame; During a pre-wake-up period prior to the estimated arrival time, the data link processing (DLP) circuit is activated, wherein the pre-wake-up period includes at least the wake-up preparation time of the DLP circuit. The pre-wake-up time is dynamically adjusted according to different shutdown modes of the DLP circuit: if the DLP circuit is in a state of clock off or enable, the pre-wake-up time is set to zero or a first threshold; if the DLP circuit is in a state of reduced or turned off power supply, the pre-wake-up time is set to a second threshold, the second threshold being greater than the first threshold and at least equal to the full wake-up time required for the DLP circuit to recover from deep sleep state to normal working state.

2. The method according to claim 1, characterized in that, The method further includes: If the continuous processing time required by the DLP circuit after the end of the data frame is greater than the minimum interval time between two adjacent data frames, then it is detected whether the idle time of the communication link is greater than the preset interval time threshold. When the idle time is detected to be greater than the preset interval time threshold, the DLP circuit is turned off.

3. The method according to claim 1, characterized in that, The step of shutting down the DLP circuit after detecting the end of a data frame and after the DLP circuit has completed processing the current data frame includes: When the end of a data frame is detected, a delay signal is sent to the DLP circuit. The delay signal is used to reserve time for the DLP circuit to complete the subsequent processing of the current data frame. Real-time detection of the processing status of the DLP circuit for the current data frame; Once it is detected that the DLP circuit has completed all processing of the current data frame, the DLP circuit is turned off.

4. The method according to claim 1, characterized in that, The shutdown of the DLP circuit includes cutting off the clock signal supplied to the DLP circuit or turning off the enable terminal of the DLP circuit.

5. The method according to claim 1, characterized in that, The shutdown of the DLP circuit includes reducing or shutting down the power supply to at least a portion of the DLP circuit.

6. A communication system, characterized in that, include: Physical layer communication chip (PHY); Data link processing (DLP) circuitry; A frame start / end detection circuit is used to execute the control method as described in any one of claims 1-5.

7. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the control method as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on a terminal device, cause the terminal device to perform the control method as described in any one of claims 1-5.

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