DUT test result processing methods, error memory, digital boards and testing machines

Abstract

This application relates to a DUT test result processing method, an error memory, a digital board, and a test machine. The method includes: capturing comparison data sampled from N signal lines, where each signal line corresponds to leading-edge comparison data and trailing-edge comparison data, and N is a natural number greater than 0; filtering the comparison data corresponding to the N signal lines to extract error data and the addresses of the error data; comparing the addresses of the error data and generating a time-sharing flag signal based on the address comparison result and the number of signal lines N; concatenating the error data, the addresses of the error data, and the time-sharing flag signal, and storing the concatenated data in a first storage unit; and sending the error data and the addresses of the error data in the first storage unit to a second storage unit in time-sharing order according to the time-sharing flag signal. This method saves the time for sending and storing error data and improves the processing efficiency of DUT test results.

Description

Technical Field

[0001] This application relates to the field of testing technology, and in particular to a method for processing DUT test results, an error memory, a digital board, and a testing machine. Background Technology

[0002] When a test machine performs tests on a Device Under Test (DUT), it inputs a stimulus signal to the DUT and acquires the response signal output by the DUT. The test machine then compares the acquired response signal with the expected signal. If the response signal does not match the expected signal, it outputs error data and the address of the error data, which is transmitted to the Address Fail Memory (AFM) to assess whether the DUT is functionally qualified. In related technologies, during DUT testing, all error data acquired within the same sampling period must be sequentially stored in a specific memory space in the AFM. However, the AFM processes each error data independently; that is, a single clock cycle can only process one external input address and data, resulting in a bottleneck in its operating efficiency.

[0003] Currently, there is no effective solution to the problem of low efficiency in processing DUT test results in related technologies. Summary of the Invention

[0004] Therefore, it is necessary to provide a DUT test result processing method, error memory, digital board, and test machine that can improve the efficiency of DUT test result processing in addressing the above-mentioned technical problems.

[0005] Firstly, this application provides a method for processing DUT test results, including:

[0006] The comparison data is captured based on samples from N signal lines, and the comparison data corresponding to each signal line includes leading edge comparison data and trailing edge comparison data; where N is a natural number greater than 0;

[0007] The comparison data corresponding to the N signal lines are filtered to extract the erroneous data and the address of the erroneous data;

[0008] The addresses of the erroneous data are compared, and a time-lapse flag signal is generated based on the address comparison result and the number of signal lines N.

[0009] The error data, the address of the error data, and the time stamp signal are spliced ​​together, and the spliced ​​data is stored in the first storage unit.

[0010] According to the time-sharing flag signal, the erroneous data and the address of the erroneous data in the first storage unit are sent to the second storage unit in time-sharing order.

[0011] In some embodiments, the addresses of the erroneous data are compared, and a time-lapse flag signal is generated based on the address comparison result and the number N of the signal lines, including:

[0012] Compare whether the addresses corresponding to the leading edge error data and the trailing edge error data of the same signal line are the same;

[0013] Compare whether the addresses corresponding to the leading edge error data or the trailing edge error data are the same between different signal lines;

[0014] The time-sharing flag signal is generated based on the address comparison result and the number N of the signal lines.

[0015] In some embodiments, comparing whether the addresses corresponding to the leading edge error data or the trailing edge error data are the same between different signal lines includes:

[0016] Identify at least two signal lines whose addresses correspond to the leading edge error data and the trailing edge error data under the same signal line;

[0017] Compare whether the addresses corresponding to the leading edge error data or the trailing edge error data are the same between the at least two signal lines.

[0018] In some embodiments, the step-by-step flag signal is generated based on the address comparison result and the number N of signal lines, including:

[0019] Based on the address comparison result and the number of signal lines N, the time-sharing flag signal is generated by looking up a table; wherein the address comparison result includes one of the following:

[0020] First comparison result: The addresses of the leading edge error data and the trailing edge error data obtained under the same signal line are the same, while the addresses of the leading edge error data or the trailing edge error data obtained between different signal lines are different;

[0021] Second comparison result: The addresses of the leading edge error data and the trailing edge error data obtained under the same signal line are the same, and the addresses of the leading edge error data or the trailing edge error data obtained under some different signal lines are also the same;

[0022] The third comparison result is that the addresses of the leading edge error data and the trailing edge error data obtained under the same signal line are the same, and the addresses of the leading edge error data or the trailing edge error data obtained under all different signal lines are also the same.

[0023] Fourth comparison result: A comparison result other than the first comparison result, the second comparison result, and the third comparison result.

[0024] In some embodiments, the second storage unit includes a first storage section and a second storage section. According to the time-sharing flag signal, the erroneous data and the address of the erroneous data in the first storage unit are sent to the second storage unit in time-sharing order, including:

[0025] Based on the batch flag signal, the first erroneous data and the address of the first erroneous data belonging to the same batch are determined. The first erroneous data sent in the same batch are ORed together and stored in the first storage unit. The address of one of the first erroneous data sent in the same batch is stored in the second storage unit.

[0026] In some embodiments, the first erroneous data sent in the same photo is ORed and then stored in the first storage unit, including:

[0027] Determine whether the address of the first erroneous data captured in the current scan is the same as the address of the already stored erroneous data;

[0028] If they are determined to be the same, the first error data of the current photo is ORed with the stored error data and then stored in the first storage unit, and the address of the first error data sent in the current photo is discarded.

[0029] If the data is determined to be different, the first erroneous data is stored in the remaining free address of the first storage unit.

[0030] In some embodiments, the comparison data corresponding to the N signal lines is filtered to extract the corresponding error data and the address of the error data, including:

[0031] Select the preprocessing mode to perform format conversion on the comparison data corresponding to the N signal lines, and obtain the converted comparison data corresponding to the N signal lines;

[0032] According to the preset mapping function, the converted comparison data and captured address data corresponding to the N signal lines are used as input to obtain the mapped comparison data and mapped address corresponding to the N signal lines. The mapped comparison data and the mapped address are in one-to-one correspondence. The mapped comparison data corresponding to each signal line includes the mapped leading edge comparison data and the mapped trailing edge comparison data.

[0033] The mapped comparison data corresponding to N signal lines is filtered and selected to obtain the erroneous data and the address of the erroneous data.

[0034] In some embodiments, after sending the erroneous data and the address of the erroneous data in the first storage unit to the second storage unit according to the time-sharing flag signal, the method further includes:

[0035] The error data and its address in the second storage unit are synchronously cached in the third storage unit;

[0036] When the third storage unit is not empty, a read enable signal is sent to the third storage unit, causing the third storage unit to output the erroneous data;

[0037] The error data is stored in the fourth storage unit according to the address of the corresponding error data.

[0038] In some embodiments, the error data is stored in the fourth storage unit according to the address of the corresponding error data, including:

[0039] Determine whether the address of the currently read erroneous data is the same as the address of the erroneous data already stored in the fourth storage unit;

[0040] If they are determined to be the same, the currently read error data is ORed with the already stored error data and then stored in the fourth storage unit;

[0041] If the data is determined to be different, the currently read erroneous data is stored in the remaining free address of the fourth storage unit according to the address of the corresponding erroneous data.

[0042] Secondly, this application provides an error storage device, including: a capture module, the capture module including: a processing unit, a first storage unit and a second storage unit, the processing unit, the first storage unit and the second storage unit being connected in sequence;

[0043] The processing unit executes the DUT test result processing method described in the first aspect above, concatenates the error data, the address of the error data, and the time-sharing flag signal, stores the concatenated data in the first storage unit, and sends the error data and the address of the error data in the first storage unit to the second storage unit cache according to the time-sharing flag signal.

[0044] In some embodiments, the processing unit includes a preprocessing mode selection module, a mapping module, and a filtering module connected in sequence;

[0045] The preprocessing mode selection module is used to receive comparison data corresponding to N signal lines, and to perform format conversion on the comparison data corresponding to the N signal lines to obtain the converted comparison data corresponding to the N signal lines.

[0046] The mapping module is used to take the converted comparison data and captured address data corresponding to the N signal lines as input to obtain the mapped comparison data and mapped address corresponding to the N signal lines. The mapped comparison data and the mapped address are in one-to-one correspondence. The mapped comparison data corresponding to each signal line includes mapped leading edge comparison data and mapped trailing edge comparison data.

[0047] The filtering module is connected to the first storage unit and is used to filter and compare the mapped data corresponding to the N signal lines to obtain the error data and the address of the error data.

[0048] In some embodiments, the processing unit further includes a state machine, the two ends of which are connected to the first storage unit and the second storage unit respectively, for sending the error data and the address of the error data in the first storage unit to the second storage unit cache according to the time-sharing flag signal.

[0049] In some embodiments, the second storage unit includes: a first storage section and a second storage section;

[0050] The first storage unit is used to store the error data;

[0051] The second storage unit is used to store the address of the error data.

[0052] In some embodiments, the error memory further includes: a third storage unit and a data selection module, wherein the input of the third storage unit is connected to the output of the second storage unit, and the input of the data selection module is connected to the output of the third storage unit;

[0053] The third storage unit is used to cache the error data and the address of the error data in the second storage unit;

[0054] The data selection module is used to send a read enable signal to the third storage unit when the third storage unit is not empty, so that the third storage unit outputs the erroneous data to the fourth storage unit.

[0055] In some embodiments, the error storage further includes a master control parsing module and an access processing module. The access processing module is connected to the data selection module. The master control parsing module is used to receive and parse input master control configuration instructions. The access processing module is used to receive the master control configuration instructions and access the fourth storage unit through the data selection module.

[0056] Thirdly, embodiments of this application provide a digital board, including: a vector generator, a timing processor, and an error memory;

[0057] The vector generator is used to output test sequence data and expected data of N signal lines to the timing processor, and to output address data to the error memory.

[0058] The timing processor is used to shape the test sequence data of the N signal lines, output the excitation signals corresponding to the N signal lines to the device under test, acquire the sampling data of the N signal lines, and compare the sampling data under each signal line with the expected data to generate comparison data based on the sampling of the N signal lines.

[0059] The error memory captures the comparison data sampled from the N signal lines, captures the address data, and executes the DUT test result processing method described in the first aspect above to store the error data in the fourth storage unit.

[0060] Fourthly, embodiments of this application provide a testing machine, including: a host computer and the digital board described in the third aspect above, wherein the host computer and the digital board are connected;

[0061] The host computer is used to send the test sequence to the digital board.

[0062] The digital board is used to test the device under test according to the test sequence and generate test results.

[0063] The aforementioned DUT test result processing method, error memory, digital board, and tester, for error data corresponding to multiple signal lines, achieve phased transmission and storage by determining whether their addresses are the same, saving error data transmission and storage time and improving the processing efficiency of DUT test results. Furthermore, error data belonging to the same phase are stored sequentially, saving storage space. Attached Figure Description

[0064] Figure 1 This is a schematic diagram of the test machine in one embodiment;

[0065] Figure 2 This is a schematic diagram of the structure of a digital board in one embodiment;

[0066] Figure 3 This is a schematic diagram of the capture module in one embodiment;

[0067] Figure 4 This is a flowchart illustrating a method for processing DUT test results in one embodiment;

[0068] Figure 5 This is a schematic diagram of the capture module in another embodiment;

[0069] Figure 6 This is a schematic diagram of the capture module in another embodiment;

[0070] Figure 7 This is a schematic diagram of the error memory structure in one embodiment;

[0071] Figure 8 This is a schematic diagram of the structure of a digital board in another embodiment;

[0072] Figure 9 This is a schematic diagram of the error memory structure in another embodiment;

[0073] Figure 10 This is a flowchart illustrating the DUT test result processing method in another embodiment.

[0074] Figure Descriptions: 1. Host Computer; 2. Digital Board; 21. Vector Generator; 22. Timing Processor; 23. Error Memory; 231. Capture Module; 232. Data Selection Module; 233. Main Control Parsing Module; 234. Access Processing Module; C. Processing Unit; C1. State Machine; C2. Preprocessing Mode Selection Module; C3. Mapping Module; C4. Filtering Module; M1. First Storage Unit; M2. Second Storage Unit; M3. Third Storage Unit; M4. Fourth Storage Unit; M21. First Storage Section; M22. Second Storage Section. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0076] Unless otherwise defined, the technical or scientific terms used in this application shall have the general meaning understood by one of ordinary skill in the art to which this application pertains. Words such as “a,” “an,” “an,” “the,” “the,” and “these” used in this application do not indicate quantitative limitation and may be singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps or modules (units) is not limited to the listed steps or modules (units) but may include steps or modules (units) not listed, or may include other steps or modules (units) inherent to these processes, methods, products, or devices. Words such as “connected,” “linked,” and “coupled” used in this application are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. Normally, the character " / " indicates that the objects before and after it are in an "or" relationship. The terms "first," "second," "third," etc., used in this application are merely to distinguish similar objects and do not represent a specific order of objects.

[0077] In one embodiment, Figure 1 A schematic diagram of a test machine is provided. The test machine includes a host computer 1 and a digital board 2, which are connected. The host computer 1 is used to send test sequences to the digital board 2. The digital board 2 is used to test the device under test according to the test sequences and generate test results.

[0078] The host computer 1 can be a device with computing capabilities, such as a computer, an FPGA (Field-Programmable Gate Array), or a combination of a computer and an FPGA.

[0079] Figure 2The diagram shows the structure of digital board 2, which includes a vector generator 21, a timing processor 22, and an error memory 23. The vector generator 21 outputs test sequence data and expected data for N signal lines to the timing processor 22, and outputs address data to the error memory 23. The timing processor 22 shapes the test sequence data for the N signal lines, outputs the corresponding excitation signals for the N signal lines to the device under test (DUT), acquires the sampled data for the N signal lines, and compares the sampled data for each signal line with the expected data to generate comparison data based on the N signal line samples. The error memory 23 captures the comparison data from the N signal line samples, captures the address data, and executes the DUT test result processing method to store the error data in the fourth storage unit M4 (see reference). Figure 7 , Figure 8 or Figure 9 ).

[0080] In some embodiments, the error storage 23 includes a capture module 231. Figure 3 The capture module 231, as shown in the schematic diagram, includes a processing unit C, a first storage unit M1, and a second storage unit M2, which are connected sequentially. The processing unit C executes a DUT test result processing method to concatenate error data, the address of the error data, and a time-sharing flag signal. The concatenated data is stored in the first storage unit M1, and the error data and its address in the first storage unit M1 are sent to the second storage unit M2 for buffering according to the time-sharing flag signal. In this embodiment, the first storage unit M1 can be a FIFO (First In First Out) memory, and the second storage unit M2 can be a RAM (Random Access Memory). The processing unit C may include a state machine C1, which is connected to the first storage unit M1 and the second storage unit M2 respectively. The state machine C1 is used to send the error data and its address in the first storage unit M1 to the second storage unit M2 for buffering according to the time-sharing flag signal. In this embodiment, the error data refers to the error data of the acquired N signal lines.

[0081] Figure 4 This is a flowchart of a DUT test result processing method according to this embodiment. The method is applied to the error memory capture module and includes the following steps:

[0082] Step S101: Capture comparison data based on N signal lines. The comparison data corresponding to each signal line includes leading edge comparison data and trailing edge comparison data.

[0083] Where N is a natural number greater than 0, the data of the corresponding pin of the device under test are sampled for each signal line in the same sampling period to obtain the leading edge sampling data and trailing edge sampling data of N signal lines. The leading edge sampling data and trailing edge sampling data of N signal lines are compared with the expected data to obtain the corresponding leading edge comparison data and trailing edge comparison data.

[0084] In the error memory 23, the capture module 231 processes the comparison data sampled based on N signal lines in parallel. Taking the 2-way mode (2 signal lines) as an example, the comparison data sampled based on signal line A includes A''0 and A''1, and the comparison data sampled based on signal line B includes B''0 and B''1. For each sampling period, the timing processor 22 acquires the sampling data of N signal lines. Correspondingly, the timing processor 22 acquires the leading edge sampling data A'0 obtained by sampling signal line A at the leading edge sampling time, and the timing processor 22 acquires the trailing edge sampling data A'1 obtained by sampling signal line A at the trailing edge sampling time; similarly, the timing processor 22 acquires the leading edge sampling data B'0 obtained by sampling signal line B at the leading edge sampling time, and the timing processor 22 acquires the trailing edge sampling data B'1 obtained by sampling signal line B at the trailing edge sampling time.

[0085] The leading edge sampling data and trailing edge sampling data are compared with the expected data to obtain the corresponding leading edge comparison data and trailing edge comparison data, namely, the leading edge comparison data A''0 and trailing edge comparison data A''1 for signal line A, and the leading edge comparison data B''0 and trailing edge comparison data B''1 for signal line B.

[0086] Step S102: Filter the comparison data corresponding to the N signal lines to extract the erroneous data and the address of the erroneous data.

[0087] You can directly filter out non-zero data from the comparison data corresponding to the N signal lines to obtain the error data. Alternatively, you can first convert the format of the comparison data corresponding to the N signal lines to obtain the converted comparison data corresponding to the N signal lines, and then filter out non-zero data from the converted comparison data corresponding to the N signal lines to obtain the error data.

[0088] In some embodiments, such as Figure 5 As shown, the processing unit C includes a state machine C1, as well as a preprocessing mode selection module C2, a mapping module C3, and a filtering module C4 connected in sequence.

[0089] The preprocessing mode selection module C2 is used to receive comparison data corresponding to N signal lines, and to perform format conversion on the comparison data corresponding to N signal lines to obtain the converted comparison data corresponding to N signal lines.

[0090] The mapping module C3 is used to take the converted comparison data and captured address data corresponding to N signal lines as input to obtain the mapped comparison data and mapped address corresponding to the N signal lines. The mapped comparison data and the mapped address are in one-to-one correspondence. The mapped comparison data corresponding to each signal line includes the mapped leading edge comparison data and the mapped trailing edge comparison data.

[0091] The filtering module C4 is connected to the first storage unit M1 and is used to filter and compare the data corresponding to the mapping of N signal lines to obtain the erroneous data and the address of the erroneous data.

[0092] In this embodiment, preprocessing modes, such as MM mode, FT mode, FZ mode, and FO mode, can be pre-configured in the preprocessing mode selection module C2 to convert the format of the comparison data corresponding to N signal lines, obtaining the data that needs to be used, so as to ultimately determine what kind of comparison data is erroneous data. The preprocessing modes are as follows:

[0093] MM mode: Only stores comparison data marked with a Mark;

[0094] FT mode: Directly stores comparison data;

[0095] FZ mode: Expects data to be inverted and compared before storage;

[0096] FO mode: Expected data and comparison data are processed and then stored.

[0097] Taking the 2WAY mode (2 signal lines) as an example, the comparison data corresponding to signal line A and signal line B are filtered. If both are non-zero data, the error data corresponding to signal line A is: leading edge error data A0 and trailing edge error data A1; the error data corresponding to signal line B is: leading edge error data B0 and trailing edge error data B1.

[0098] Step S103: Compare the addresses of the erroneous data, and generate a time-lapse flag signal based on the address comparison result and the number of signal lines N.

[0099] The error data consists of the error data from the N signal lines acquired, and the address of the corresponding error data corresponds to the error data.

[0100] Compare whether the addresses corresponding to the leading edge error data and the trailing edge error data of the same signal line are the same; compare whether the addresses corresponding to the leading edge error data or the trailing edge error data of different signal lines are the same; generate a time-sequence flag signal based on the address comparison results and the number of signal lines N.

[0101] Taking 2-way mode as an example, with error data A0, A1, B0, and B1, the error data corresponding to signal line A are: leading edge error data A0 and trailing edge error data A1; the error data corresponding to signal line B are: leading edge error data B0 and trailing edge error data B1. There are three possible scenarios:

[0102] Case 1: If the addresses of A0, A1, B0, and B1 are the same, then based on the address comparison result and the number of signal lines 2, a batch flag signal 11 is generated, indicating that the erroneous data A0, A1, B0, and B1 belong to the first erroneous data of the same batch. The processing unit needs to spend one clock cycle to send the current batch of erroneous data (the first erroneous data of the same batch) from the first storage unit M1 to the second storage unit M2. One clock cycle is one clock cycle of the local clock of the error memory.

[0103] Case 2: If A0 and A1 have the same address, and B0 and B1 have the same address, and A0 is not equal to B0, then based on the address comparison result and the number of signal lines 2, a time-sharing flag signal 01 is generated, indicating that A0 and A1 belong to the first erroneous data of the same time, and B0 and B1 belong to the first erroneous data of the same time. The processing unit needs to use two clock cycles to send the first erroneous data in the first storage unit to the second storage unit M2 in batches.

[0104] Case 3: If the addresses A0, A1, B0, and B1 are all different, then based on the address comparison result and the number of signal lines 2, a batch flag signal 00 is generated, indicating that A0, A1, B0, and B1 are respectively the first erroneous data. For the current batch of erroneous data, the processing unit needs to use four clock cycles to send the first erroneous data in the first storage unit to the second storage unit M2 in batches.

[0105] Therefore, in 4WAY mode, if there are erroneous data A0, A1, B0, B1, C0, C1, D0, and D1, that is, erroneous data corresponding to signal line A includes A0 and A1, erroneous data corresponding to signal line B includes B0 and B1, erroneous data corresponding to signal line C includes C0 and C1, and erroneous data corresponding to signal line D includes D0 and D1, there are four possible scenarios:

[0106] Case 1: If the addresses of A0, A1, B0, B1, C0, C1, D0, and D1 are the same, the time-sharing flag signal 111 indicates that the erroneous data A0, A1, B0, B1, C0, C1, D0, and D1 belong to the first erroneous data of the same time-sharing unit. The processing unit needs to spend one time-sharing clock cycle to send the first erroneous data of the first storage unit M1 to the second storage unit M2.

[0107] Case 2: If the addresses A0, A1, B0, B1, C0, C1, D0, and D1 can be classified into two groups, the time-sharing flag signal 011 indicates that there are two groups of first erroneous data in the same time step. The processing unit needs to use two time steps to send the first erroneous data in the first storage unit to the second storage unit M2 in batches.

[0108] Case 3: If the addresses A0, A1, B0, B1, C0, C1, D0, and D1 can be classified into four groups during the address comparison, the time-sharing flag signal 001 indicates that there are four groups of first erroneous data in the same time step. The processing unit needs to use four time steps to send the first erroneous data in the first storage unit to the second storage unit M2 in batches.

[0109] Case 4: If the addresses of A0, A1, B0, B1, C0, C1, D0, and D1 are all different, the time-sharing flag signal 000 indicates that there are eight groups of first erroneous data in the same time step. The processing unit needs to use eight time steps to send the first erroneous data in the first storage unit to the second storage unit M2 in batches.

[0110] Step S104: The error data, the address of the error data, and the time stamp signal are spliced ​​together, and the spliced ​​data is stored in the first storage unit M1.

[0111] Step S105: Based on the time-sharing flag signal, the error data and the address of the error data in the first storage unit M1 are sent to the second storage unit M2.

[0112] When the first storage unit M1 is not empty, the written erroneous data and its address are read. Based on the flag signal, the erroneous data and its address are stored in the second storage unit M2, either in one, two, or other time increments. Specifically, the first erroneous data sent in the same time increment is ORed and then stored in the second storage unit M2. Correspondingly, the address of one of the first erroneous data sent in the same time increment is also synchronously stored in the second storage unit M2 to ensure that the erroneous data and its address correspond. Taking the 2-way mode as an example, there are three cases:

[0113] Case 1: If the time-sharing flag signal is 11, that is, when writing in one time, the data after ORing the first error data A0, A1, B0, B1 is stored in the second storage unit M2, and one of the addresses of the first error data A0, A1, B0, B1 is stored in the second storage unit M2.

[0114] Case 2: If the time-sharing flag signal is 01, that is, when writing in two time-sharing phases, the data after ORing the first error data A0 and A1, the data after ORing the first error data B0 and B1 are stored in the second storage unit M2, the address of the first error data A0 or A1 is stored in the second storage unit M2, and the address of the first error data B0 or ​​B1 is stored in the second storage unit M2.

[0115] Case 3: If the step-by-step flag signal is 00, that is, when writing in four steps, the error data A0, A1, B0, and B1 are stored in the second storage unit M2 in sequence, and the addresses of A0, A1, B0, and B1 are stored in the second storage unit M2 in sequence. That is, A0, A1, B0, and B1 are respectively used as the first error data.

[0116] In steps S101 to S105 above, for erroneous data corresponding to multiple signal lines, the system determines whether their addresses are the same, enabling phased transmission and storage. This saves time in transmitting and storing erroneous data and improves the processing efficiency of DUT test results. Furthermore, the first erroneous data belonging to the same phase is stored sequentially, saving storage space.

[0117] In some embodiments, Figure 6 Another schematic diagram of the capture module is provided, wherein the second storage unit M2 includes: a first storage section M21 and a second storage section M22; wherein the first storage section M21 is used to store error data; and the second storage section M22 is used to store the address of the error data. In the above step S105, the first error data and the address of the first error data belonging to the same batch can be determined according to the batch flag signal. The first error data sent in the same batch are ORed and stored in the first storage section M21, and the address of one of the first error data sent in the same batch is stored in the second storage section M22. The storage of the first error data and the address of the first error data are performed synchronously, so that the addresses of the error data stored in the first storage section M21 and the error data stored in the second storage section M22 correspond. In this embodiment, the first storage section M21 can be RAM (Random Access Memory), and the second storage section M22 can be a register.

[0118] Taking the 2-way model as an example, there are three scenarios:

[0119] Case 1: If the time-sharing flag signal is 11, that is, when writing in one time, the value of the OR operation of the first error data A0, A1, B0, B1 is stored in the first storage unit M21, and the address of one of the first error data A0, A1, B0, B1 is stored in the second storage unit M22.

[0120] Case 2: If the time-sharing flag signal is 01, that is, when writing in two time-sharing phases, the value after ORing the first error data A0 and A1, the value after ORing the first error data B0 and B1 are stored in the first storage unit M21, and the address of the first error data A0 or A1 is stored in the second storage unit M22, and the address of the first error data B0 or ​​B1 is stored in the second storage unit M22.

[0121] Case 3: If the step-by-step flag signal is 00, that is, when writing in four steps, the error data A0, A1, B0, and B1 are stored in the first storage unit M21 in sequence, and the addresses of the error data A0, A1, B0, and B1 are stored in the second storage unit M22 in sequence, where A0, A1, B0, and B1 are respectively used as the first error data.

[0122] In some embodiments, when the first error data sent in the same frame is ORed and then stored in the first storage unit M21, it is first determined whether the address of the first error data in the current frame is the same as the address of the already stored error data; if they are the same, the first error data in the current frame is ORed with the already stored error data and then stored in the first storage unit M21, and the address of the first error data sent in the current frame is discarded; if they are not the same, the first error data in the current frame is stored in the remaining free address of the first storage unit M21.

[0123] In this embodiment, after the previous error data (i.e., the already stored error data) is stored in the first storage unit M21, when more error data is read from the first storage unit M1, it is first determined whether the address of the first error data sent in the current cycle is the same as the address of the cached, already stored error data. If they are the same, the first error data sent in the current cycle and the already stored error data are ORed and then stored in the first storage unit M21, and the address of the first error data sent in the current cycle is discarded (not stored). If they are different, the first error data sent in the current cycle is directly stored in the remaining free address of the first storage unit M21, and the address of the corresponding first error data is stored in the second storage unit M22. This setting reduces the possibility of duplicate addresses of the error data ultimately written to the second storage unit M2, thereby further saving storage space.

[0124] In some embodiments, in step S103 above, the addresses of erroneous data are compared, and a time-lapse flag signal is generated based on the address comparison result and the number of signal lines N, including:

[0125] Compare whether the addresses corresponding to the leading edge error data and the trailing edge error data of the same signal line are the same;

[0126] Identify at least two signal lines whose addresses correspond to the leading edge error data and trailing edge error data of the same signal line.

[0127] Compare whether the addresses corresponding to the leading edge error data or trailing edge error data between at least two signal lines are the same.

[0128] This setup, using signal lines as units, first determines whether the addresses corresponding to the leading edge error data and trailing edge error data under each signal line are the same. It then selects at least two signal lines under the same signal line whose addresses correspond to the leading edge error data and trailing edge error data are the same. Finally, it compares the addresses of the error data between the selected signal lines, that is, it selects the addresses corresponding to the leading edge error data or trailing edge error data under the corresponding signal line for comparison. This further speeds up the comparison of the addresses of the error data corresponding to N signal lines and saves comparison time.

[0129] In some embodiments, in step S103 above, generating a time-sharing flag signal based on the address comparison result and the number of signal lines N can be achieved through the following method:

[0130] Based on the address comparison result and the number of signal lines N, a time-sharing flag signal is generated by looking up a table; the address comparison result includes one of the following:

[0131] The first comparison result is that the addresses of leading-edge error data and trailing-edge error data acquired under the same signal line are the same, while the addresses of leading-edge error data or trailing-edge error data acquired between different signal lines are different. When the first comparison result is obtained, the required number of beats to be distributed is determined to be N. Based on the number of beats and the number of signal lines N, a beat division flag signal is generated. For example, case 2 in 2-way mode and case 3 in 4-way mode.

[0132] The second comparison result is that the addresses of the leading edge error data and trailing edge error data acquired under the same signal line are the same, and the addresses of the leading edge error data or trailing edge error data acquired under some different signal lines are also the same. When the second comparison result is obtained, the required number of beats is determined to be an integer greater than 1 and less than N. Based on the number of beats and the number of signal lines N, a beat division flag signal is generated. For example, case 2 in 4WAY mode.

[0133] The third comparison result: The addresses of the leading edge error data and trailing edge error data acquired under the same signal line are the same, and the addresses of the leading edge error data or trailing edge error data acquired under all different signal lines are also the same. When the third comparison result is obtained, the required number of beats is determined to be 1. Based on the number of beats and the number of signal lines N, a beat division flag signal is generated. For example, Case 1 in 2-WAY mode and Case 1 in 4-WAY mode.

[0134] The fourth comparison result is a comparison result other than the first, second, and third comparison results. When the fourth comparison result is obtained, the required number of beats is determined to be 2N. Based on the number of beats and the number of signal lines N, a beat division flag signal is generated. For example, case 3 in 2-way mode and case 4 in 4-way mode.

[0135] In some embodiments, Figure 7 A schematic diagram of an error memory structure is provided. Based on the capture module 231, the error memory 23 further includes: a third storage unit M3 and a data selection module 232. The input terminal of the third storage unit M3 is connected to the output terminal of the second storage unit M2, and the input terminal of the data selection module 232 is connected to the output terminal of the third storage unit M3. The third storage unit M3 is used to cache the error data and the address of the error data in the second storage unit M2. The data selection module 232 is used to send a read enable signal to the third storage unit M3 when the third storage unit M3 is not empty, so that the third storage unit M3 outputs the error data to the fourth storage unit M4. Figure 8 Another schematic diagram of the structure of digital board 2 is provided. Figure 2 Based on this, the digital board 2 also includes a fourth storage unit M4, which is connected to the error memory 23 and is used to store error data output by the error memory 23. In this embodiment, the third storage unit M3 can be a FIFO (First In First Out) memory, and the fourth storage unit M4 can be a DDR (Double Data Rate) memory.

[0136] In this embodiment, after step S105 above, where the error data and its address are sent from the first storage unit M1 to the second storage unit M2 according to the time-sharing flag signal, the method further includes:

[0137] The erroneous data and its address in the second storage unit M2 are synchronously cached in the third storage unit M3. When the third storage unit M3 is not empty, a read enable signal is sent to the third storage unit M3, causing the third storage unit M3 to output the erroneous data. The erroneous data is then stored in the fourth storage unit M4 according to the address of the corresponding erroneous data.

[0138] In this embodiment, by setting the third storage unit M3 and the data selection module 232, the process of transferring erroneous data from the second storage unit M2 to the fourth storage unit M4 is made smoother.

[0139] In some embodiments, when storing error data into the fourth storage unit M4 according to the address of the corresponding error data, it is first determined whether the address of the currently read error data is the same as the address of the error data already stored in the fourth storage unit M4; if they are the same, the currently read error data is ORed with the already stored error data and then stored into the fourth storage unit M4; if they are not the same, the currently read error data is stored into the remaining free address of the fourth storage unit M4 according to the address of the corresponding error data.

[0140] In this embodiment, the erroneous data is stored in the fourth storage unit M4, but the address of the erroneous data is not stored in the fourth storage unit M4; instead, it serves as an index corresponding to the erroneous data stored in the fourth storage unit M4. It can be understood that the address of the erroneous data is the storage address of the erroneous data stored in the fourth storage unit M4. This embodiment improves the space utilization of the fourth storage unit M4 and also improves the index utilization of the erroneous data address by determining whether the address of the currently read erroneous data is the same as the address of the erroneous data already stored in the fourth storage unit M4.

[0141] In some embodiments, Figure 9 Another schematic diagram of the error memory structure is provided, such as Figure 9 As shown, the error memory 23 includes: a capture module 231, a third storage unit M3, a data selection module 232, a master control parsing module 233, and an access processing module 234. The capture module 231 is connected to the input terminal of the third storage unit M3, the third storage unit M3 is connected to the data selection module 232, the data selection module 232 is also connected to a fourth storage unit M4 outside the error memory 23, the master control parsing module 233 is connected to the access processing module 234, and the access processing module 234 is connected to the data selection module 232. Specifically, the capture module 231 executes the DUT test result processing method, outputs error data and its address, caches it in the third storage unit M3, and then stores the error data in the fourth storage unit M4; the master control parsing module 233 receives and parses the input master control configuration instructions; and the access processing module 234 receives the master control configuration instructions and accesses the fourth storage unit M4 through the data selection module 232 to read and write the error data within the fourth storage unit M4.

[0142] In one embodiment, Figure 10 A flowchart illustrating another method for processing DUT test results is provided. This method can be applied to the error memory in the aforementioned test machine and includes the following steps:

[0143] Step S201: Capture the comparison data corresponding to the N signal lines.

[0144] Step S202, Preprocessing mode selection. A preprocessing mode, such as MM mode, FT mode, FZ mode, or FO mode, is pre-configured in the capture module 231 to convert the format of the comparison data corresponding to the N signal lines, obtaining the converted comparison data that needs to be used, so as to ultimately determine which comparison data belongs to erroneous data.

[0145] Taking 2WAY as an example, if the preprocessing mode is selected as FT mode (direct storage of comparison data), the leading edge comparison data A''0 and trailing edge comparison data A''1 corresponding to signal line A, and the leading edge comparison data B''0 and trailing edge comparison data B''1 corresponding to signal line B, will still be the original comparison data after format conversion.

[0146] Step S203, Data Address Mapping. Based on the user-configured mapping relationship, the preprocessed comparison data and its addresses are mapped.

[0147] Error memory 23 acquires the mapping function and captured address data. In this embodiment, the mapping function is sent from the host computer to error memory 23 of digital board 2, and the captured address data is sent from vector generator 21 of digital board 2 to error memory 23.

[0148] According to the preset mapping function, the converted comparison data and captured address data corresponding to N signal lines are used as input to obtain the mapped comparison data and mapped address corresponding to N signal lines. The mapped comparison data and the mapped address are in one-to-one correspondence. The mapped comparison data for each signal line includes the mapped leading edge comparison data and the mapped trailing edge comparison data.

[0149] Taking 2-way preprocessing with FT mode as an example, the specific steps are as follows:

[0150] The converted comparison data for the two signal lines are as follows: for signal line A, the leading edge comparison data is A''0 and the trailing edge comparison data is A''1; for signal line B, the leading edge comparison data is B''0 and the trailing edge comparison data is B''1.

[0151] The converted comparison data corresponding to the two signal lines is used as input to participate in the mapping function operation to obtain the mapped comparison data corresponding to the two signal lines.

[0152] For example, the leading edge comparison data corresponding to signal line A is 4 bits of data with the value 1101 after conversion. After the mapping function is applied, the mapped leading edge comparison data is 4 bits of data with the value 1011. Similarly, the address data corresponding to the leading edge comparison data of signal line A can be 4 bits of data with the value 0110. After participating in the mapping function, the output address data is 4 bits of address 1001. The mapped address 1001 corresponds to the mapped leading edge comparison data, that is, the mapped address 1001 is the address of the mapped leading edge comparison data.

[0153] Similarly, the same mapping function is applied to other signal lines and their corresponding addresses, which will not be elaborated here.

[0154] Step S204, data filtering. Filter out non-zero data to obtain erroneous data.

[0155] Step S205, FIFO1 data buffer. The erroneous data, its address, and the time-lapse flag signal are concatenated, and the concatenated data is stored in FIFO1 (i.e., the first storage unit M1). If a data backpressure overflow occurs, proceed to step S209.

[0156] Step S206: Error data is sent to RAM in batches, and the address of the error data is sent to the register. RAM is the first storage unit M21, and the register is the second storage unit M22.

[0157] Step S207: FIFO2 data and address buffer. RAM sends the erroneous data to FIFO2 (i.e., the third storage unit) buffer, and the register synchronously sends the address of the erroneous data to FIFO2 buffer.

[0158] Step S208: Error data is uploaded to DDR. Error data output from FIFO2 will be stored in DDR (i.e., the fourth memory unit M4) according to its error data address.

[0159] Step S209: Data backpressure overflow report.

[0160] In steps S201 to S209 above, for erroneous data corresponding to multiple signal lines, the system determines whether their addresses are the same, enabling phased transmission and storage. This saves erroneous data transmission and storage time and improves the processing efficiency of DUT test results. Furthermore, erroneous data belonging to the same phase are ORed together and stored later, saving storage space. Moreover, setting FIFOs at both ends of the RAM makes reading and writing erroneous data in the RAM smoother.

[0161] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0162] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0163] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for processing DUT test results, characterized in that, include: The comparison data is captured based on samples from N signal lines, and the comparison data corresponding to each signal line includes leading edge comparison data and trailing edge comparison data; where N is a natural number greater than 0; The comparison data corresponding to the N signal lines are filtered to extract the erroneous data and the address of the erroneous data; The addresses of the erroneous data are compared, and a time-lapse flag signal is generated based on the address comparison result and the number of signal lines N. The error data, the address of the error data, and the time stamp signal are spliced ​​together, and the spliced ​​data is stored in the first storage unit. According to the time-sharing flag signal, the error data and the address of the error data in the first storage unit are sent to the second storage unit in time-sharing order; wherein, the error data sent in the same time-sharing order have the same address, and the error data sent in the same time-sharing order are ORed and then stored in the second storage unit.

2. The DUT test result processing method according to claim 1, characterized in that, The addresses of the erroneous data are compared, and based on the address comparison result and the number N of the signal lines, a time-sequence flag signal is generated, including: Compare whether the addresses corresponding to the leading edge error data and the trailing edge error data of the same signal line are the same; Compare whether the addresses corresponding to the leading edge error data or the trailing edge error data are the same between different signal lines; The time-sharing flag signal is generated based on the address comparison result and the number N of the signal lines.

3. The DUT test result processing method according to claim 2, characterized in that, Comparing whether the addresses corresponding to the leading edge error data or the trailing edge error data are the same between different signal lines includes: Identify at least two signal lines whose addresses correspond to the leading edge error data and the trailing edge error data under the same signal line; Compare whether the addresses corresponding to the leading edge error data or the trailing edge error data are the same between the at least two signal lines.

4. The DUT test result processing method according to claim 2, characterized in that, Based on the address comparison result and the number N of signal lines, the time-sharing flag signal is generated, including: Based on the address comparison result and the number of signal lines N, the time-sharing flag signal is generated by looking up a table; wherein the address comparison result includes one of the following: First comparison result: The addresses of the leading edge error data and the trailing edge error data obtained under the same signal line are the same, while the addresses of the leading edge error data or the trailing edge error data obtained between different signal lines are different; Second comparison result: The addresses of the leading edge error data and the trailing edge error data obtained under the same signal line are the same, and the addresses of the leading edge error data or the trailing edge error data obtained under some different signal lines are also the same; The third comparison result is that the addresses of the leading edge error data and the trailing edge error data obtained under the same signal line are the same, and the addresses of the leading edge error data or the trailing edge error data obtained under all different signal lines are also the same. Fourth comparison result: A comparison result other than the first comparison result, the second comparison result, and the third comparison result.

5. The DUT test result processing method according to claim 1, characterized in that, The second storage unit includes a first storage section and a second storage section. Based on the time-sharing flag signal, the erroneous data and its address in the first storage unit are sent to the second storage unit in time-sharing order. This includes: Based on the batch flag signal, the first erroneous data and the address of the first erroneous data belonging to the same batch are determined. The first erroneous data sent in the same batch are ORed together and stored in the first storage unit. The address of one of the first erroneous data sent in the same batch is stored in the second storage unit.

6. The DUT test result processing method according to claim 5, characterized in that, After performing a bitwise OR operation on the first erroneous data sent in the same photo, the data is stored in the first storage unit, including: Determine whether the address of the first erroneous data captured in the current scan is the same as the address of the already stored erroneous data; If they are determined to be the same, the first error data of the current photo is ORed with the stored error data and then stored in the first storage unit, and the address of the first error data sent in the current photo is discarded. If the data is determined to be different, the first erroneous data is stored in the remaining free address of the first storage unit.

7. The DUT test result processing method according to claim 1, characterized in that, The comparison data corresponding to the N signal lines is filtered to extract the corresponding error data and the address of the error data, including: Select the preprocessing mode to perform format conversion on the comparison data corresponding to the N signal lines, and obtain the converted comparison data corresponding to the N signal lines; According to the preset mapping function, the converted comparison data and captured address data corresponding to the N signal lines are used as input to obtain the mapped comparison data and mapped address corresponding to the N signal lines. The mapped comparison data and the mapped address are in one-to-one correspondence. The mapped comparison data corresponding to each signal line includes the mapped leading edge comparison data and the mapped trailing edge comparison data. The mapped comparison data corresponding to N signal lines is filtered and selected to obtain the erroneous data and the address of the erroneous data.

8. The DUT test result processing method according to claim 1, characterized in that, After sending the erroneous data and its address from the first storage unit to the second storage unit according to the time-sharing flag signal, the method further includes: The error data and its address in the second storage unit are synchronously cached in the third storage unit; When the third storage unit is not empty, a read enable signal is sent to the third storage unit, causing the third storage unit to output the erroneous data; The error data is stored in the fourth storage unit according to the address of the corresponding error data.

9. The DUT test result processing method according to claim 8, characterized in that, The error data is stored in the fourth storage unit according to the address of the corresponding error data, including: Determine whether the address of the currently read erroneous data is the same as the address of the erroneous data already stored in the fourth storage unit; If they are determined to be the same, the currently read error data is ORed with the already stored error data and then stored in the fourth storage unit; If the data is determined to be different, the currently read erroneous data is stored in the remaining free address of the fourth storage unit according to the address of the corresponding erroneous data.

10. An error memory, characterized in that, include: The capture module includes a processing unit, a first storage unit, and a second storage unit, which are connected sequentially. The processing unit executes the DUT test result processing method according to any one of claims 1 to 7, splices the error data, the address of the error data, and the time-sharing flag signal, stores the spliced ​​data in the first storage unit, and sends the error data and the address of the error data in the first storage unit to the second storage unit cache according to the time-sharing flag signal.

11. The error storage device according to claim 10, characterized in that, The processing unit includes a preprocessing mode selection module, a mapping module, and a filtering module connected in sequence. The preprocessing mode selection module is used to receive comparison data corresponding to N signal lines, and to perform format conversion on the comparison data corresponding to the N signal lines to obtain the converted comparison data corresponding to the N signal lines. The mapping module is used to take the converted comparison data and captured address data corresponding to the N signal lines as input to obtain the mapped comparison data and mapped address corresponding to the N signal lines. The mapped comparison data and the mapped address are in one-to-one correspondence. The mapped comparison data corresponding to each signal line includes mapped leading edge comparison data and mapped trailing edge comparison data. The filtering module is connected to the first storage unit and is used to filter and compare the mapped data corresponding to the N signal lines to obtain the error data and the address of the error data.

12. The error memory according to claim 10 or claim 11, characterized in that, The processing unit further includes a state machine, which is connected to the first storage unit and the second storage unit at both ends, respectively, and is used to send the error data and the address of the error data in the first storage unit to the second storage unit cache according to the time-sharing flag signal.

13. The error storage device according to claim 10, characterized in that, The second storage unit includes: a first storage section and a second storage section; wherein, The first storage unit is used to store the error data; The second storage unit is used to store the address of the error data.

14. The error storage device according to claim 10, characterized in that, The error memory further includes: a third storage unit and a data selection module, wherein the input terminal of the third storage unit is connected to the output terminal of the second storage unit, and the input terminal of the data selection module is connected to the output terminal of the third storage unit; The third storage unit is used to cache the error data and the address of the error data in the second storage unit; The data selection module is used to send a read enable signal to the third storage unit when the third storage unit is not empty, so that the third storage unit outputs the erroneous data to the fourth storage unit.

15. The error storage device according to claim 14, characterized in that, The error storage also includes a master control parsing module and an access processing module. The access processing module is connected to the data selection module. The master control parsing module is used to receive and parse the input master control configuration command. The access processing module is used to receive the master control configuration command and access the fourth storage unit through the data selection module.

16. A digital board, characterized in that, include: Vector generator, timing processor, and error memory; among which, The vector generator is used to output test sequence data and expected data of N signal lines to the timing processor, and to output address data to the error memory; The timing processor is used to shape the test sequence data of the N signal lines, output the excitation signals corresponding to the N signal lines to the device under test, acquire the sampling data of the N signal lines, and compare the sampling data under each signal line with the expected data to generate comparison data based on the sampling of the N signal lines. The error memory captures the comparison data sampled from the N signal lines, captures the address data, and executes the DUT test result processing method according to any one of claims 1 to 9 to store the error data in the fourth storage unit.

17. A testing machine, characterized in that, include: A host computer and the digital board according to claim 16, wherein the host computer and the digital board are connected; wherein... The host computer is used to send the test sequence to the digital board; The digital board is used to test the device under test according to the test sequence and generate test results.

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