Gate driving circuit and display panel

Abstract

This application discloses a gate driving circuit and a display panel. By controlling a fifth transistor to a first clock signal, a current path is periodically formed between a first node and a second node. The third and fifth transistors control the on / off state of the current path between the second low-potential line and the first node. The fourth and fifth transistors control the on / off state of the current path between the second high-potential line and the first node. The seventh and eighth transistors control the on / off state of the current path between the second high-potential line and the second low-potential line and the third node. A sixth transistor controls one of the signals transmitted by the first low-potential line and a first electrical signal to be transmitted to the first node. The voltage value of the first electrical signal is less than the voltage value of the signal transmitted by the first low-potential line, so as to stabilize the potential of the first node, thereby keeping the operating states of the first transistor and the second transistor stable.

Description

[0001] This divisional application is a divisional application of Chinese patent application No. 202310928332.5, filed on July 26, 2023, entitled "Gate Driving Circuit and Display Panel". Technical Field

[0002] This application relates to the field of display technology, specifically to a gate driving circuit and a display panel. Background Technology

[0003] In display panels, gate drive circuits are typically used to provide corresponding gate drive signals for different transistors, and the stability of these gate drive signals is particularly critical to the operational stability of the transistors.

[0004] However, the potential jump of the corresponding signal in the gate drive circuit can easily affect the potential stability of the internal node, and the potential stability of the internal node will further affect the stability of the gate drive signal. Summary of the Invention

[0005] This application provides a gate driving circuit and a display panel to improve the technical problem of low potential stability of the gate driving signal.

[0006] In a first aspect, this application provides a gate driving circuit comprising a plurality of cascaded shift registers, each shift register including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first transistor includes a gate electrically connected to a first node of the shift register, a first terminal electrically connected to a first high-potential line, and a second terminal electrically connected to a first output terminal of the shift register. The second transistor includes a gate electrically connected to a first node, a first terminal electrically connected to a first low-potential line, and a second terminal electrically connected to the first output terminal. The third transistor includes a gate configured to receive a start control signal or a first gate driving signal output from a previous stage shift register, a first terminal electrically connected to a second low-potential line, and a second terminal electrically connected to a second node of the shift register. The fourth transistor includes a gate electrically connected to the gate of the third transistor, a first terminal electrically connected to a second high-potential line, and a second terminal electrically connected to a second node. The fifth transistor includes a gate configured to receive a first clock signal, a first terminal electrically connected to the first node, and a second terminal electrically connected to the second node. The sixth transistor includes a gate electrically connected to the third node or the first output terminal of the shift register of this stage, a first terminal electrically connected to the first low-potential line or configured to receive a first electrical signal, and a second terminal electrically connected to the first node. The seventh transistor includes a gate electrically connected to the first node, a first terminal electrically connected to the second high-potential line, and a second terminal electrically connected to the third node. The eighth transistor includes a gate electrically connected to the first node, a first terminal electrically connected to the second low-potential line, and a second terminal electrically connected to the third node. Wherein, the first transistor is a P-channel transistor, the second transistor is an N-channel transistor; the voltage value of the signal transmitted through the second low-potential line is less than the voltage value of the signal transmitted through the first low-potential line, the voltage value of the first electrical signal is less than the voltage value of the signal transmitted through the first low-potential line; the first clock signal is a periodic signal.

[0007] Secondly, this application provides a gate driving circuit comprising a plurality of cascaded shift registers, each shift register including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The first transistor includes a gate electrically connected to a first node of the shift register, a first terminal electrically connected to a first high-potential line, and a second terminal electrically connected to a first output terminal of the shift register. The second transistor includes a gate electrically connected to the first node, a first terminal electrically connected to a first low-potential line, and a second terminal electrically connected to the first output terminal. The third transistor includes a gate configured to receive a start control signal or a first gate driving signal output from a previous-stage shift register, a first terminal electrically connected to a second low-potential line, and a second terminal electrically connected to a second node of the shift register. The fourth transistor includes a gate electrically connected to the gate of the third transistor, a first terminal electrically connected to a second high-potential line, and a second terminal electrically connected to a second node. The fifth transistor includes a gate configured to receive a first clock signal, a first terminal electrically connected to the first node, and a second terminal electrically connected to the second node. The sixth transistor includes a gate electrically connected to the second node of the shift register of the next stage, a first terminal electrically connected to the first low potential line, and a second terminal electrically connected to the first node.

[0008] Wherein, the first transistor is a P-channel transistor, and the second transistor is an N-channel transistor; the signal transmitted by the first high-potential line is the same as the signal transmitted by the second high-potential line, and the signal transmitted by the first low-potential line is the same as the signal transmitted by the second low-potential line; the first clock signal is a periodic signal.

[0009] This application provides a display panel comprising a plurality of pixel circuits arranged in an array and a gate driving circuit as described in at least one embodiment above. Each pixel circuit includes a light-emitting device, a driving transistor, and a compensation transistor configured to input a control data signal to the gate of the driving transistor. The driving transistor is configured to generate a driving current according to the data signal to drive the light-emitting device to emit light. The gates of the compensation transistors in the plurality of pixel circuits located in the same row are all electrically connected to the first output terminal of the same shift register.

[0010] The gate driving circuit and display panel provided in this application control the fifth transistor to a first clock signal to control the periodic formation of a current path between the first node and the second node. This allows the third and fifth transistors to control the on / off state of the current path between the second low-potential line and the first node, and the fourth and fifth transistors to control the on / off state of the current path between the second high-potential line and the first node. Furthermore, the seventh and eighth transistors control the on / off state of the current path between the second high-potential line and the second low-potential line and the third node. Subsequently, the sixth transistor controls one of the signals transmitted by the first low-potential line and the first electrical signal to be transmitted to the first node. The voltage value of the first electrical signal is less than the voltage value of the signal transmitted by the first low-potential line, thereby stabilizing the potential of the first node using either the signal transmitted by the first low-potential line or the first electrical signal. This stabilizes the operating state of the first and second transistors controlled by the signals of the first node, improving the stability of the first gate driving signal output by the gate driving circuit. Attached Figure Description

[0011] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0012] Figure 1 This is a schematic diagram of the pixel circuit structure in related technologies.

[0013] Figure 2 for Figure 1 Timing diagram of the pixel circuit.

[0014] Figure 3 This is a schematic diagram of the first structure of the gate drive circuit in the related technology.

[0015] Figure 4 for Figure 3 The timing diagram of the gate drive circuit is shown.

[0016] Figure 5 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the first stage of the process.

[0017] Figure 6 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the second stage of the process.

[0018] Figure 7 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the third stage of the process.

[0019] Figure 8 for Figure 3The gate drive circuit shown is in Figure 4 A schematic diagram of the fourth stage of the process.

[0020] Figure 9 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the fifth stage of the process.

[0021] Figure 10 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the sixth stage of the process.

[0022] Figure 11 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the seventh stage of the process.

[0023] Figure 12 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the eighth stage of the process.

[0024] Figure 13 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the ninth stage of the process.

[0025] Figure 14 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the tenth stage.

[0026] Figure 15 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the eleventh stage.

[0027] Figure 16 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the twelfth stage of the process.

[0028] Figure 17 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the state in the thirteenth stage.

[0029] Figure 18 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the state in the fourteenth stage.

[0030] Figure 19 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the state in the fifteenth stage.

[0031] Figure 20 This is a schematic diagram of a second structure of the gate drive circuit in the related technology.

[0032] Figure 21 for Figure 20 The timing diagram of the gate drive circuit is shown.

[0033] Figure 22 for Figure 20 The gate drive circuit shown is in Figure 21 A schematic diagram of the first stage of the process.

[0034] Figure 23 for Figure 20 The gate drive circuit shown is in Figure 21 A schematic diagram of the second stage of the process.

[0035] Figure 24 for Figure 20 The gate drive circuit shown is in Figure 21 A schematic diagram of the third stage of the process.

[0036] Figure 25 for Figure 20 The gate drive circuit shown is in Figure 21 A schematic diagram of the fourth stage of the process.

[0037] Figure 26 for Figure 20 The gate drive circuit shown is in Figure 21 A schematic diagram of the fifth stage of the process.

[0038] Figure 27 for Figure 20 The gate drive circuit shown is in Figure 21 A schematic diagram of the sixth stage of the process.

[0039] Figure 28 for Figure 20 The gate drive circuit shown is in Figure 21 A schematic diagram of the seventh stage of the process.

[0040] Figure 29 for Figure 20 The gate drive circuit shown is in Figure 21 A schematic diagram of the eighth stage of the process.

[0041] Figure 30 This is a timing diagram illustrating the generation of the Nth negative pulse gate drive signal provided in an embodiment of this application.

[0042] Figure 31 for Figure 3 or Figure 20 The diagram shows the timing sequence of some nodes in the gate drive circuit.

[0043] Figure 32 This is a schematic diagram of a first structure of the gate drive circuit provided in an embodiment of this application.

[0044] Figure 33 This is a schematic diagram of a second structure of the gate drive circuit provided in an embodiment of this application.

[0045] Figure 34 for Figure 32 , Figure 33 The timing diagram of the gate drive circuit is shown.

[0046] Figure 35 for Figure 32 The gate drive circuit shown is in Figure 34 A schematic diagram of the first stage of the process.

[0047] Figure 36 for Figure 32 The gate drive circuit shown is in Figure 34 A schematic diagram of the second stage of the process.

[0048] Figure 37 for Figure 32 The gate drive circuit shown is in Figure 34 A schematic diagram of the third stage of the process.

[0049] Figure 38 for Figure 32 The gate drive circuit shown is in Figure 34 A schematic diagram of the fourth stage of the process.

[0050] Figure 39 for Figure 32 The gate drive circuit shown is in Figure 34 A schematic diagram of the fifth stage of the process.

[0051] Figure 40 for Figure 32 The gate drive circuit shown is in Figure 34 A schematic diagram of the sixth stage of the process.

[0052] Figure 41 for Figure 32 The gate drive circuit shown is in Figure 34 A schematic diagram of the seventh stage of the process.

[0053] Figure 42 for Figure 32 The gate drive circuit shown is in Figure 34 A schematic diagram of the eighth stage of the process.

[0054] Figure 43 for Figure 32 The gate drive circuit shown is in Figure 34 A schematic diagram of the ninth stage of the process.

[0055] Figure 44 for Figure 32 The gate drive circuit shown is in Figure 34 A schematic diagram of the tenth stage.

[0056] Figure 45 for Figure 32 The gate drive circuit shown is in Figure 34 A schematic diagram of the eleventh stage.

[0057] Figure 46 for Figure 32 The gate drive circuit shown is in Figure 34 A schematic diagram of the twelfth stage of the process.

[0058] Figure 47 for Figure 32 The gate drive circuit shown is in Figure 34 A schematic diagram of the state in the thirteenth stage.

[0059] Figure 48 for Figure 32 The gate drive circuit shown is in Figure 34 A schematic diagram of the state in the fourteenth stage.

[0060] Figure 49 for Figure 32 The gate drive circuit shown is in Figure 34 A schematic diagram of the state in the fifteenth stage.

[0061] Figure 50 This is a schematic diagram of a third structure of the gate drive circuit provided in this embodiment.

[0062] Figure 51 for Figure 50 The timing diagram of the gate drive circuit is shown.

[0063] Figure 52 for Figure 50 The gate drive circuit shown is in Figure 51 A schematic diagram of the first stage of the process.

[0064] Figure 53 for Figure 50 The gate drive circuit shown is in Figure 51 A schematic diagram of the second stage of the process.

[0065] Figure 54 for Figure 50 The gate drive circuit shown is in Figure 51 A schematic diagram of the third stage of the process.

[0066] Figure 55 for Figure 50 The gate drive circuit shown is in Figure 51 A schematic diagram of the fourth stage of the process.

[0067] Figure 56 for Figure 50 The gate drive circuit shown is in Figure 51 A schematic diagram of the fifth stage of the process.

[0068] Figure 57 for Figure 50 The gate drive circuit shown is in Figure 51 A schematic diagram of the sixth stage of the process.

[0069] Figure 58 for Figure 50 The gate drive circuit shown is in Figure 51 A schematic diagram of the seventh stage of the process.

[0070] Figure 59 for Figure 50 The gate drive circuit shown is in Figure 51 A schematic diagram of the eighth stage of the process.

[0071] Figure 60 for Figure 3 or Figure 20 The diagram shows a cascaded structure between shift registers in the gate drive circuit.

[0072] Figure 61 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application.

[0073] Figure 62 This is a schematic diagram of the pixel circuit provided in an embodiment of this application.

[0074] Figure 63 for Figure 62 Timing diagram of the pixel circuit. Detailed Implementation

[0075] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0076] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Features thus defined as "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more unless otherwise explicitly specified.

[0077] In the gate driving circuit of application No. 202310191137.9, the Nth-level negative pulse gate driving signal Pout[N] has one negative pulse in one frame. The Nth-level positive pulse gate driving signal Nout[N] has two positive pulses in one frame, and the pulse widths of the two positive pulses must be equal and both be 2H. This restricts the width of the positive pulses of the Nth-level positive pulse gate driving signal Nout[N] to remain consistent and cannot be changed, so that if the width of the positive pulses of the Nth-level positive pulse gate driving signal Nout[N] is greater than 2H, the number of negative pulses of the Nth-level negative pulse gate driving signal Pout[N] in one frame will increase.

[0078] Therefore, this will limit Figure 1 The pixel circuit shown is in accordance with Figure 2 The timing sequence shown is followed by operation. Specifically, Figure 1 The pixel circuit shown may include at least one of the following: a write transistor T2P, a drive transistor T1P, a first light-emitting control transistor T5P, a second light-emitting control transistor T6P, a first initialization transistor T4P, a second initialization transistor T7P, a third initialization transistor T8P, a compensation transistor T3P, a light-emitting device D1, a storage capacitor Cst, and a bootstrap capacitor CbOst.

[0079] The first high-potential line is electrically connected to the first terminal of the first light-emitting control transistor T5P and one end of the storage capacitor Cst. The second terminal of the first light-emitting control transistor T5P is electrically connected to the first terminal of the driving transistor T1P and the first terminal of the writing transistor T2P. The second terminal of the driving transistor T1P is electrically connected to the first terminal of the compensation transistor T3P and the first terminal of the second light-emitting control transistor T6P. The second terminal of the second light-emitting control transistor T6P is electrically connected to the first terminal of the second initialization transistor T7P and the anode of the light-emitting device D1. The cathode of the light-emitting device D1 is electrically connected to the first low-potential line.

[0080] The light-emitting control line is electrically connected to the gate of the first light-emitting control transistor T5P and the gate of the second light-emitting control transistor T6P.

[0081] The second terminal of the write transistor T2P is electrically connected to the data line, and the gate of the write transistor T2P is electrically connected to one end of the bootstrap capacitor CbOst, and connected to the Nth negative pulse gate drive signal Pout[N]. The second terminal of the second initialization transistor T7P is electrically connected to the second initialization line, and the gate of the second initialization transistor T7P is connected to the gate drive signal Pscan2.

[0082] The second terminal of the compensation transistor T3P is electrically connected to the gate of the driving transistor T1P, and the gate of the compensation transistor T3P is connected to the Nth positive pulse gate drive signal Nout[N].

[0083] The gate of the driving transistor T1P is electrically connected to the other end of the storage capacitor Cst, the other end of the bootstrap capacitor CbOst, and the first terminal of the first initialization transistor T4P.

[0084] The second terminal of the first initialization transistor T4P is electrically connected to the first initialization line, and the gate of the first initialization transistor T4P is connected to the (N-1)th stage positive pulse gate drive signal Nout[N-1].

[0085] The first terminal of the third initialization transistor T8P is electrically connected to the first terminal of the driving transistor T1P, the second terminal of the third initialization transistor T8P is electrically connected to the third initialization line, and the gate of the third initialization transistor T8P shares the gate drive signal Pscan2 with the gate of the second initialization transistor T7P.

[0086] It should be noted that the second initialization line can also be replaced with the first initialization line, which can reduce the number of traces required for the pixel circuit and help increase the density of the pixel circuit in the display panel.

[0087] In this application, the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain. For example, when the first electrode is the source, the second electrode is the drain; or, when the first electrode is the drain, the second electrode is the source.

[0088] The system includes a first high-potential line for transmitting the positive power supply signal VDD, a first low-potential line for transmitting the negative power supply signal VSS, and a data line for transmitting the data signal Data. A light-emitting control line is used to transmit the light-emitting control signal EM. A first initialization line is used to transmit the first initialization signal Vi1. A second initialization line is used to transmit the second initialization signal. A third initialization line is used to transmit the third initialization signal Vi3. A first gate drive line is used to transmit the Nth-stage negative pulse gate drive signal Pout[N]. Second gate drive lines connected to shift registers of different stages are used to transmit the (N-1)th-stage positive pulse gate drive signal Nout[N-1] and the Nth-stage positive pulse gate drive signal Nout[N], respectively.

[0089] As described above, in the gate driving circuit shown in application number 202310191137.9, the principle behind the generation of a negative pulse in one frame for the Nth-level negative pulse gate driving signal Pout[N] is that the second pulse of the reset signal RST filters out the first pulse of the start control signal STV or the NYth-level positive pulse gate driving signal Nout[NY]. Therefore, the widths of the two positive pulses of the start control signal STV or the NYth-level positive pulse gate driving signal Nout[NY] must be equal.

[0090] exist Figure 1 In the pixel circuit shown, in order to achieve synchronous conduction of the compensation transistor T3P and the first initialization transistor T4P, the pulse of the (N-1)th stage positive pulse gate drive signal Nout[N-1] and the pulse of the Nth stage positive pulse gate drive signal Nout[N] need to partially overlap. This is also Figure 1 The reason why the first initialization transistor T4P in the pixel circuit shown must be connected to the N-1th stage positive pulse gate drive signal Nout[N-1].

[0091] Furthermore, in order to complete the transmission of the third initialization signal Vi3 sequentially through node A and node B to node Q, and to reset the potentials of nodes A, B, and Q, the third initialization transistor T8P and the compensation transistor T3P need to be turned on synchronously. This requires the pulse of the gate drive signal Pscan2 to overlap with the pulse of the Nth positive pulse gate drive signal Nout[N].

[0092] And in order to Figure 1 The pixel circuit shown can continue to use the gate drive signal Pscan2, whose pulse width is limited to 1H. This requires adjustment. Figure 2 The driving timing of the pixel circuit shown also requires, correspondingly, the following: Figure 1 The gate drive circuit shown has been improved.

[0093] Against this backdrop, in order to alleviate the technical problem that the pulse of the gate drive signal is difficult to adapt to the required time and width, this embodiment provides a gate drive circuit. Please refer to [link / reference]. Figures 3 to 30 ,like Figure 3 , Figure 20 As shown, the gate drive circuit includes multiple shift registers, and the shift registers include at least one of the following: a cascade signal selection module 10, a pull-up control module 20, a first filter module 30, a second filter module 80, and a first output module 46.

[0094] The stage transmission signal selection module 10 is electrically connected between the first node O / O[N] and the start control line and the NYth stage positive pulse gate drive line, where Y is an integer greater than or equal to 2.

[0095] The pull-up control module 20 controls the potential of the second node K based on the potential of the first node O / O[N] and the potential of the first clock signal.

[0096] The first filter module 30 is electrically connected between the intermediate node and one of the second node K or the third node Q. The control terminal of the first filter module 30 is electrically connected to the Nth positive pulse gate drive line, where X is an integer greater than or equal to 2.

[0097] The second filter module 80 is electrically connected between the intermediate node and another of the second node K or the third node Q, and the control terminal of the second filter module 80 is electrically connected to the N-2th stage positive pulse gate drive line.

[0098] The first output module 46 is electrically connected to the third node Q, the fourth node P, and the Nth stage negative pulse gate drive line.

[0099] It is understood that the gate driving circuit provided in this embodiment filters out the first part of the second pulse that appears later in a frame by the first filtering module 30, and filters out the second part of the first pulse that appears earlier and the second pulse that appears later in a frame by the second filtering module 80. This can retain the first part of the first pulse with a fixed width, and then control the first output module 46 to output a gate driving signal with a pulse of that fixed width at the corresponding time. After this improvement, it can be adapted to the driving requirements of the back end.

[0100] In one embodiment, the shift register further includes a first inverting module 50 and a second output module 70. The first inverting module 50 is electrically connected between the second node K and the fourth node P. The second output module 70 is electrically connected to the second node K and the Nth positive pulse gate drive line.

[0101] Understandably, after Figure 3 , Figure 20 After the improvement, since the first filtering module 30 can filter out the first part of the second pulse that appears later in a frame for the second node K, and the second filtering module 80 can filter out the last part of the first pulse that appears earlier and the last part of the second pulse that appears later in a frame for the second node K, the first part of the first pulse with a fixed width can be retained. Then, the first output module 46 is controlled to output a gate drive signal with a pulse of that fixed width at the corresponding time. The pulse width of the Nth positive pulse gate drive signal Nout[N] provided by the second output module 70 will not affect the pulse width of the Nth negative pulse gate drive signal Pout[N]. Therefore, the two pulse widths of the Nth positive pulse gate drive signal Nout[N] in a frame can not only be modulated to a width greater than 2H, but also the two pulse widths can be modulated separately without needing to be equal. This provides support for the improvement of the driving timing of the pixel circuit.

[0102] In one embodiment, such as Figure 3 , Figure 20As shown, the first filtering module 30 includes a first filtering transistor T11 and a first capacitor C2. One of the source or drain of the first filtering transistor T11 is electrically connected to the second node K, and the other of the source or drain of the first filtering transistor T11 is electrically connected to the intermediate node. The gate of the first filtering transistor T11 is electrically connected to the NXth positive pulse gate drive line. One end of the first capacitor C2 is electrically connected to the gate of the first filtering transistor T11, and the other end of the first capacitor C2 is electrically connected to the other of the source or drain of the first filtering transistor T11.

[0103] It should be noted that, such as Figure 30 As shown, the first filtering module 30 is used to filter out the first part of the second pulse that appears later in a frame at the second node K.

[0104] In one embodiment, such as Figure 3 , Figure 20 As shown, the second filtering module 80 includes a second filtering transistor T8. One of the sources or drains of the second filtering transistor T8 is electrically connected to the intermediate node, and the other of the sources or drains of the second filtering transistor T8 is electrically connected to the third node Q. The gate of the first filtering transistor T11 is electrically connected to the (N-2)th stage positive pulse gate drive line.

[0105] It should be noted that, such as Figure 30 As shown, the second filtering module 80 is used to filter out the latter part of the first pulse that appears first in a frame and the latter part of the second pulse that appears later in a frame for the second node K.

[0106] Therefore, the first filtering module 30 and the second filtering module 80 are used to filter out the second pulse and retain the first part of the first pulse with a fixed width.

[0107] In one embodiment, such as Figure 20 As shown, the shift register also includes an isolation module 75, which is connected in series between the second node K and the input terminal of the second output module 70. The control terminal of the isolation module 75 is connected to the first clock signal.

[0108] It should be noted that the isolation module 75 is used to reduce the coupling between the pulse amplitude of the Nth negative pulse gate drive signal Pout[N] and the pulse amplitude of the Nth positive pulse gate drive signal Nout[N], thereby stabilizing the high potential of the Nth positive pulse gate drive signal Nout[N].

[0109] In one embodiment, such as Figure 20As shown, the isolation module 75 includes a sixth transistor T14. One of the sources or drains of the sixth transistor T14 is electrically connected to the second node K, and the other of the sources or drains of the sixth transistor T14 is electrically connected to the input terminal of the second output module 70. The gate of the sixth transistor T14 is connected to the first clock signal. The sixth transistor T14 is a P-channel thin-film transistor.

[0110] It should be noted that the sixth transistor T14 can reduce the coupling between the pulse amplitude of the Nth stage negative pulse gate drive signal Pout[N] and the pulse amplitude of the Nth stage positive pulse gate drive signal Nout[N], thereby stabilizing the high potential of the Nth stage positive pulse gate drive signal Nout[N].

[0111] In other embodiments, the isolation module 75 may also include a series connection between the gate of the sixth transistor T14 and node N.

[0112] The input terminal of the stage transmission signal selection module 10 is electrically connected to the start control line or the NYth stage positive pulse gate drive line, where N is an integer greater than or equal to 1 and Y is an integer greater than or equal to 1.

[0113] The input terminal of the pull-up control module 20 is electrically connected to the output terminal of the cascade signal selection module 10, and the control terminal of the pull-up control module 20 is electrically connected to the first clock line.

[0114] The input terminal of the first filtering module 30 is electrically connected to the output terminal of the pull-up control module 20, and the control terminal of the first filtering module 30 is electrically connected to the reset line.

[0115] The control terminal of the pull-up module 40 is electrically connected to the output terminal of the first filter module 30, the input terminal of the pull-up module 40 is electrically connected to the second clock line, and the output terminal of the pull-up module 40 is electrically connected to the Nth negative pulse gate drive line. The input terminal of the first inverting module 50 is electrically connected to the output terminal of the pull-up control module 20.

[0116] The control terminal of the pull-down module 60 is electrically connected to the output terminal of the first inverting module 50, the input terminal of the pull-down module 60 is electrically connected to the high-potential line, and the output terminal of the pull-down module 60 is electrically connected to the Nth negative pulse gate drive line.

[0117] In one embodiment, the first output module 46 includes a pull-up module 40 and a pull-down module 60.

[0118] It should be noted that the first wiring can be either a start control line or an NY-level positive pulse gate drive line; where NY is less than or equal to 0, the first wiring is a start control line. The N-level positive pulse gate drive line, which is also the second gate control line, is used to transmit the N-level positive pulse gate drive signal Nout[N], i.e., the second gate drive signal. The N-level negative pulse gate drive line, which is also the first gate control line, is used to transmit the N-level negative pulse gate drive signal Pout[N], i.e., the first gate drive signal.

[0119] In one embodiment, the first filtering module 30 includes a first filtering transistor T11 and a first capacitor C2. One of the sources or drains of the first filtering transistor T11 is electrically connected to the second node K, and the other of the sources or drains of the first filtering transistor T11 is electrically connected to the third node Q. The gate of the first filtering transistor T11 is connected to a reset signal RST. One end of the first capacitor C2 is electrically connected to the gate of the first filtering transistor T11, and the other end of the first capacitor C2 is electrically connected to the other of the sources or drains of the first filtering transistor T11.

[0120] The ratio of the channel width to the channel length of the first filter transistor T11 is greater than or equal to 0.5 and less than or equal to 1.5.

[0121] It should be noted that this embodiment helps to ensure the output stability of the Nth negative pulse gate drive signal Pout[N], and avoids the coupling pull-down phenomenon before the negative pulse arrives.

[0122] In one embodiment, the pull-up module 40 includes a pull-up transistor T6 and a second capacitor C1. The gate of the pull-up transistor T6 is electrically connected to one of the sources or drains of the first filter transistor T11. One of the sources or drains of the pull-up transistor T6 is electrically connected to a second clock line, and the other of the sources or drains of the pull-up transistor T6 is electrically connected to the Nth negative pulse gate drive line. One end of the second capacitor C1 is electrically connected to the gate of the pull-up transistor T6, and the other end of the second capacitor C1 is electrically connected to the other of the sources or drains of the pull-up transistor T6. The ratio of the capacitance of the first capacitor C2 to that of the second capacitor C1 is greater than or equal to 0.5.

[0123] It should be noted that the ratio of the capacitance of the first capacitor C2 to the capacitance of the second capacitor C1 in this embodiment is designed to further ensure the output stability of the Nth negative pulse gate drive signal Pout[N] and avoid the coupling pull-down phenomenon before the arrival of the negative pulse.

[0124] Specifically, the capacitance of the first capacitor C2 can be greater than or equal to 50fF. The capacitance of the second capacitor C1 can be greater than or equal to 100fF.

[0125] The ratio of the channel width to the channel length of the pull-up transistor T6 is greater than 30:1, which helps to further ensure the output stability of the Nth negative pulse gate drive signal Pout[N]. The pull-up transistor T6 can be a P-channel thin-film transistor.

[0126] In one embodiment, the cascade signal selection module 10 includes transistors T13 and T12. One of the sources or drains of transistor T13 is electrically connected to a low-potential line, and the other of the sources or drains of transistor T13 is electrically connected to the input terminal of the pull-up control module 20. The first gate of transistor T13 is electrically connected to the start control line or the NY-level positive pulse gate drive line, and the first gate of transistor T13 is electrically connected to the second gate of transistor T13. Transistor T13 is an N-channel thin-film transistor. One of the sources or drains of transistor T12 is electrically connected to a high-potential line, and the other of the sources or drains of transistor T12 is electrically connected to the other of the sources or drains of transistor T13. The gate of transistor T12 is electrically connected to the first gate of transistor T13. Transistor T12 is a P-channel thin-film transistor.

[0127] It should be noted that in this embodiment, the stage transmission signal selection module 10 not only has an inverse function, that is, the input signal and the output signal have opposite potentials at the same time, but also serves to make the Nth stage positive pulse gate drive signal Nout[N] serve as the stage transmission signal between shift registers. Otherwise, stage transmission cannot be achieved between shift registers, which will cause the gate drive circuit to fail to provide the corresponding gate drive signal normally.

[0128] The ratio of the channel width to the channel length of transistor T13 is greater than 2:1. The ratio of the channel width to the channel length of transistor T12 ranges from 0.5:1 to 3:1.

[0129] The high-potential line is used to transmit the high-potential signal VGH, which can control the N-channel thin-film transistor to turn on or the P-channel thin-film transistor to turn off. The low-potential line is used to transmit the low-potential signal VGL, which can control the P-channel thin-film transistor to turn on or the N-channel thin-film transistor to turn off.

[0130] In one embodiment, the pull-up control module 20 includes a pull-up control transistor T2, one of the source or drain of the pull-up control transistor T2 is electrically connected to the output terminal of the transmission signal selection module 10, the other of the source or drain of the pull-up control transistor T2 is electrically connected to the input terminal of the first filter module 30, and the gate of the pull-up control transistor T2 is electrically connected to the first clock line.

[0131] It should be noted that the pull-up control transistor T2 can be a P-channel thin-film transistor. The ratio of the channel width to the channel length of the pull-up control transistor T2 ranges from 0.5:1 to 3:1.

[0132] In one embodiment, the first inverting module 50 includes a fourth transistor T3 and a fifth transistor T1. One of the sources or drains of the fourth transistor T3 is electrically connected to a high-potential line, the other of the sources or drains of the fourth transistor T3 is electrically connected to one of the sources or drains of the fifth transistor T1 and the control terminal of the pull-down module 60, the other of the sources or drains of the fifth transistor T1 is electrically connected to a low-potential line, and the output terminal of the pull-up control module 20 is electrically connected to the gate of the fourth transistor T3, the first gate of the fifth transistor T1, and the second gate of the fifth transistor T1.

[0133] It should be noted that the fourth transistor T3 is a P-channel thin-film transistor, and the fifth transistor T1 is a dual-gate N-channel thin-film transistor. This improves the dynamic performance of the fourth transistor T3 and the fifth transistor T1, thereby improving the dynamic performance of the first inverting module 50.

[0134] The ratio of the channel width to the channel length of the fourth transistor T3 ranges from 0.5:1 to 3:1. The ratio of the channel width to the channel length of the fifth transistor T1 is greater than or equal to 2:1.

[0135] In one embodiment, the pull-down module 60 includes a pull-down transistor T7, one of the source or drain of the pull-down transistor T7 is electrically connected to a high-potential line, the other of the source or drain of the pull-down transistor T7 is electrically connected to the Nth negative pulse gate drive line, and the gate of the pull-down transistor T7 is electrically connected to the output terminal of the first inverting module 50, i.e., the fourth node P.

[0136] It should be noted that the pull-down transistor T7 can be a P-channel thin-film transistor. With the combined action of the pull-down module 60 and the pull-up module 40, the required Nth-level negative pulse gate drive signal Pout[N] can be modulated.

[0137] The ratio of the channel width to the channel length of the pull-down transistor T7 is greater than or equal to 30:1.

[0138] The second output module 70 includes transistors T9 and T10. One of the sources or drains of transistor T9 is electrically connected to a high-potential line, and the other of the sources or drains of transistor T9 is electrically connected to one of the sources or drains of transistor T10 and the Nth positive pulse scan line. The other of the sources or drains of transistor T10 is electrically connected to a low-potential line. The output terminal of the pull-up control module 20 is electrically connected to the gate of transistor T9, the first gate of transistor T10, and the second gate of transistor T10.

[0139] It should be noted that transistor T9 is a P-channel thin-film transistor, and transistor T10 is a dual-gate N-channel thin-film transistor. This improves the dynamic performance of transistors T9 and T10, thereby enhancing the dynamic performance of the second output module 70.

[0140] The ratio of the channel width to the channel length of the first transistor T9 is greater than or equal to 30:1. The ratio of the channel width to the channel length of the second transistor T10 is greater than or equal to 30:1.

[0141] In one embodiment, the second filtering module 80 includes a second filtering transistor T8, one of the source or drain of the second filtering transistor T8 is electrically connected to the output terminal of the first filtering module 30, the other of the source or drain of the second filtering transistor T8 is electrically connected to the control terminal of the pull-up module 40, and the gate of the second filtering transistor T8 is connected to the filtering control signal RST2.

[0142] It should be noted that the second filter transistor T8 can be a P-channel thin-film transistor or an N-channel thin-film transistor.

[0143] The ratio of the channel width to the channel length of the second filter transistor T8 can be in the range of 0.5:1 to 3:1.

[0144] In one embodiment, the Nth-stage shift register further includes a feedback module 90, which includes transistors T4 and T5. One of the sources or drains of transistor T4 is electrically connected to the output of pull-up control module 20, the gate of transistor T4 is electrically connected to the second clock line, the other of the sources or drains of transistor T4 is electrically connected to one of the sources or drains of transistor T5, the other of the sources or drains of transistor T5 is electrically connected to the high-potential line, and the gate of transistor T5 is electrically connected to the output of the first inverting module 50.

[0145] The ratio of the channel width to the channel length of transistor T4 ranges from 0.5:1 to 3:1. The ratio of the channel width to the channel length of transistor T5 also ranges from 0.5:1 to 3:1.

[0146] It should be noted that the feedback module 90 can maintain the second node K at a high potential based on the potential of the fourth node P and the potential of the second clock line. That is, when the fourth node P is at a low potential and the second clock signal CK is at a low potential, the high potential line can control the potential of the second node K to the potential of the high potential signal VGH.

[0147] It should be noted that the Nth positive pulse gate drive line is used to transmit the Nth positive pulse gate drive signal Nout[N]. The Nth negative pulse gate drive line is used to transmit the Nth negative pulse gate drive signal Pout[N]. The first clock line is used to transmit the first clock signal XCK. The second clock line is used to transmit the second clock signal CK. The start control line is used to transmit the start control signal STV. The NYth positive pulse gate drive line is used to transmit the NYth positive pulse gate drive signal Nout[NY]. The NXth positive pulse gate drive line is used to transmit the NXth positive pulse gate drive signal Nout[NX]. The reset line is used to transmit the reset signal RST.

[0148] Figure 3 The operation of the shift register shown in the diagram within a frame may include, for example: Figure 4 The following stages are shown:

[0149] Phase 1 S1: As Figure 4 , Figure 5 As shown, the start control signal STV, reset signal RST, second clock signal CK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are all at low potential, the first clock signal XCK is at high potential, the first node O / O[N], the second node K, the intermediate node W, and the third node Q are all at high potential, the fourth node P is at low potential, the Nth stage positive pulse gate drive signal Nout[N] is at low potential, and the Nth stage negative pulse gate drive signal Pout[N] is at high potential.

[0150] Phase 2 S2: As Figure 4 , Figure 6As shown, the start control signal STV, reset signal RST, first clock signal XCK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are all at low potential, the second clock signal CK is at high potential, the first node O / O[N], the second node K, the intermediate node W, and the third node Q are all at high potential, the fourth node P is at low potential, the Nth stage positive pulse gate drive signal Nout[N] is at low potential, and the Nth stage negative pulse gate drive signal Pout[N] is at high potential.

[0151] Phase 3 S3: As Figure 4 , Figure 7 As shown, the start control signal STV, the second clock signal CK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are all at low potentials, the reset signal RST and the first clock signal XCK are at high potentials, the first node O / O[N], the second node K, the intermediate node W, and the third node Q are all at high potentials, the fourth node P is at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at low potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0152] Phase 4 S4: such as Figure 4 , Figure 8 As shown, the start control signal STV, the first clock signal XCK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are all at low potentials, the reset signal RST and the second clock signal CK are at high potentials, the first node O / O[N], the second node K, the intermediate node W, and the third node Q are all at high potentials, the fourth node P is at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at low potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0153] Phase 5 S5: As Figure 4 , Figure 9 As shown, the second clock signal CK is at a low potential, the start control signal STV, the reset signal RST, the first clock signal XCK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at a high potential, the second node K, the intermediate node W, and the third node Q are at a high potential, the first node O / O[N] and the fourth node P are at a low potential, the Nth stage positive pulse gate drive signal Nout[N] is at a low potential, and the Nth stage negative pulse gate drive signal Pout[N] is at a high potential.

[0154] Phase 6 (S6): (e.g.) Figure 4 , Figure 10As shown, the first clock signal XCK is at a low potential, the start control signal STV, the reset signal RST, the second clock signal CK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at a high potential, the intermediate node W, the fourth node P, and the third node Q are all at a high potential, the second node K and the first node O / O[N] are at a low potential, the Nth stage positive pulse gate drive signal Nout[N] is at a high potential, and the Nth stage negative pulse gate drive signal Pout[N] is at a high potential.

[0155] Stage 7 (S7): Figure 4 , Figure 11 As shown, the reset signal RST and the second clock signal CK are at low potentials, the start control signal STV, the first clock signal XCK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at high potentials, the fourth node P and the third node Q are both at high potentials, the intermediate node W, the second node K, and the first node O / O[N] are at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at high potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0156] Stage 8 S8: As Figure 4 , Figure 12 As shown, the reset signal RST and the first clock signal XCK are at low potentials, the start control signal STV, the second clock signal CK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at high potentials, the fourth node P and the third node Q are both at high potentials, the intermediate node W, the second node K, and the first node O / O[N] are at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at high potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0157] Stage 9 S9: As Figure 4 , Figure 13 As shown, the second clock signal CK and the N-2th positive pulse gate drive signal Nout[N-2] are at low potential, the reset signal RST, the start control signal STV, and the first clock signal XCK are at high potential, the intermediate node W, the first node O / O[N], the fourth node P, and the third node Q are all at high potential, the second node K is at low potential, the Nth positive pulse gate drive signal Nout[N] is at high potential, and the Nth negative pulse gate drive signal Pout[N] is at high potential.

[0158] Stage 10 S10: As Figure 4 , Figure 14As shown, the start control signal STV, the first clock signal XCK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at low potentials, the reset signal RST and the second clock signal CK are at high potentials, the second node K, the intermediate node W, the first node O / O[N] and the third node Q are all at high potentials, the fourth node P is at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at low potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0159] Phase 11 S11: As Figure 4 , Figure 15 As shown, the reset signal RST and the N-2th stage positive pulse gate drive signal Nout[N-2] are at low potential, the start control signal STV, the first clock signal XCK, and the second clock signal CK are at high potential, the fourth node P and the third node Q are both at high potential, the second node K, the intermediate node W, and the first node O / O[N] are at low potential, the Nth stage positive pulse gate drive signal Nout[N] is at high potential, and the Nth stage negative pulse gate drive signal Pout[N] is at high potential.

[0160] Stage Twelve S12: As Figure 4 , Figure 16 As shown, the second clock signal CK, the start control signal STV, the reset signal RST, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at low potentials, the first clock signal XCK is at high potentials, the fourth node P and the first node O / O[N] are both at high potentials, the third node Q, the second node K, and the intermediate node W are at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at high potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at low potentials.

[0161] Phase Thirteen S13: As Figure 4 , Figure 17 As shown, the first clock signal XCK, the start control signal STV, the reset signal RST, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at low potentials, the second clock signal CK is at high potentials, the second node K, the intermediate node W, the third node Q, and the first node O / O[N] are all at high potentials, the fourth node P is at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at low potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0162] Phase Fourteen S14: As Figure 4 , Figure 18As shown, the second clock signal CK, the start control signal STV, the reset signal RST, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at low potentials, the first clock signal XCK is at high potentials, the second node K, the intermediate node W, the third node Q, and the first node O / O[N] are all at high potentials, the fourth node P is at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at low potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0163] Phase 15 S15: As Figure 4 , Figure 19 As shown, the first clock signal XCK, the start control signal STV, the reset signal RST, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at low potentials, the second clock signal CK is at high potentials, the second node K, the intermediate node W, the third node Q, and the first node O / O[N] are all at high potentials, the fourth node P is at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at low potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0164] It should be noted that, Figures 5 to 19 The "cross" in the diagram indicates that the transistor it covers is in the off state, while the transistors not covered by the "cross" are in the on state. Figures 5 to 19 The dashed arrow in the diagram indicates the direction of the current.

[0165] Figure 20 The operation of the shift register shown in the diagram within a frame may include, for example: Figure 21 The following stages are shown:

[0166] Phase 1 S1: As Figure 21 , Figure 22 As shown, the start control signal STV and the second clock signal CK are both at a low level, the first clock signal XCK is at a high level, node N is at a high level, the fourth node P is at a low level, and the Nth stage positive pulse gate drive signal Nout[N] is at a low level.

[0167] Phase 2 S2: As Figure 21 , Figure 23 As shown, the start control signal STV and the first clock signal XCK are at a low level, the second clock signal CK is at a high level, node N is at a high level, the fourth node P is at a low level, and the Nth positive pulse gate drive signal Nout[N] is at a low level.

[0168] Phase 3 S3: As Figure 21 , Figure 24As shown, the second clock signal CK is at a low potential, the start control signal STV and the first clock signal XCK are at a high potential, node N is at a high potential, the fourth node P is at a low potential, and the Nth positive pulse gate drive signal Nout[N] is at a low potential.

[0169] Phase 4 S4: such as Figure 21 , Figure 25 As shown, the first clock signal XCK is at a low potential, the start control signal STV and the second clock signal CK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth positive pulse gate drive signal Nout[N] is at a high potential.

[0170] Phase 5 S5: As Figure 21 , Figure 26 As shown, the second clock signal CK is at a low potential, the start control signal STV and the first clock signal XCK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth positive pulse gate drive signal Nout[N] is at a high potential.

[0171] Phase 6 (S6): (e.g.) Figure 21 , Figure 27 As shown, the first clock signal XCK is at a low potential, the start control signal STV and the second clock signal CK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth positive pulse gate drive signal Nout[N] is at a high potential.

[0172] Stage 7 (S7): Figure 21 , Figure 28 As shown, the start control signal STV and the second clock signal CK are at a low level, the first clock signal XCK is at a high level, the fourth node P is at a high level, the node N is at a low level, and the Nth stage positive pulse gate drive signal Nout[N] is at a high level.

[0173] Stage 8 S8: As Figure 21 , Figure 29 As shown, the start control signal STV and the first clock signal XCK are at a low level, the second clock signal CK is at a high level, node N is at a high level, the fourth node P is at a low level, and the Nth positive pulse gate drive signal Nout[N] switches from a high level to a low level.

[0174] It should be noted that, Figures 22 to 29 The "cross" in the diagram indicates that the transistor it covers is in the off state, while the transistors not covered by the "cross" are in the on state. Figures 22 to 29 The dashed arrow in the diagram indicates the direction of the current.

[0175] Based on the above, Figure 30The process of generating the negative pulse of the Nth-level negative pulse gate drive signal Pout[N] is illustrated. For clarity, the two pulses from right to left in the same signal are referred to as the first pulse and the second pulse, respectively. The second node K transmits the first pulse and the second pulse sequentially within one frame. The high potential of the first part of the two pulses of the (N-2)th-level positive pulse gate drive signal Nout[N-2] controls the second filter module 80 to filter out the latter part of the first pulse and the latter part of the second pulse output by the second node K. The high potential of the latter part of the first pulse of the reset signal RST controls the first filter module 30 to filter out the first part of the second pulse output by the second node K. At this point, the width of the second pulse of the intermediate node W also narrows; the second pulse output by the second node K is completely filtered out, leaving only the first part of the first pulse output by the second node K to form a negative pulse at the third node Q. The negative pulse of the third node Q activates the pull-up module 40, forming the negative pulse of the Nth-level negative pulse gate drive signal Pout[N] with a fixed width.

[0176] Please see Figure 31 , Figure 31 The second node K of the gate drive circuit shown is affected by the voltage jumps of the first clock signal XCK and / or the second clock signal CK. Since the potentials of the second node K and the fifth node N are linked, both the potentials of the second node K and the fifth node N will exhibit significant fluctuations during the high and low level phases (e.g., ...). Figure 31 (The burrs or spikes shown).

[0177] like Figure 31 As shown, especially the potential of the fifth node N is significantly affected by the bootstrap coupling of the first gate drive signal during the low-level phase, resulting in a significant dip in the second gate drive signal, i.e., the Nth-level positive pulse gate drive signal Nout[N], during the high-level phase (e.g. Figure 31 (As shown in the dashed box in the middle), this not only reduces the potential stability of the second gate drive signal, but also leads to a decrease in the consistency between the various second gate drive signals transmitted in the display panel, thereby affecting the uniformity of the display.

[0178] Based on this, this embodiment provides a gate driving circuit, please refer to [link / reference]. Figures 32 to 59 ,like Figure 32 , Figure 33 ,as well as Figure 50 As shown, the gate drive circuit includes multiple shift registers, and the shift registers include at least one of the following: a stage signal selection module 10, a pull-up control module 20, a first filter module 30, a second filter module 80, a first inverting module 50, a first output module 46, a second output module 70, and a voltage regulation module 71.

[0179] The cascade signal selection module 10 is electrically connected between the first wiring and the first node O / O[N].

[0180] The pull-up control module 20 controls the potential of the second node K based on the potential of the first node O / O[N] and the potential of the first clock signal XCK.

[0181] The first filter module 30 is electrically connected between the second node K and the third node Q, and the control terminal of the first filter module 30 is connected to the reset signal RST.

[0182] The second filter module 80 is electrically connected between the first filter module 30 and the third node Q, and the control terminal of the second filter module 80 is connected to the filter control signal RST2.

[0183] The first inverting module 50 is connected between the second node K and the fourth node P.

[0184] The first output module 46 outputs the first gate drive signal based on the potential of the third node Q and the potential of the fourth node P.

[0185] The second output module 70 includes a P-channel first transistor T9 and an N-channel second transistor T10. The first terminal of the first transistor T9 is electrically connected to a first high-potential line, and the second terminal of the first transistor T9 is electrically connected to the first terminal of the second transistor T10 to output a second gate drive signal. The second terminal of the second transistor T10 is connected to a first low-potential signal. The second node K is electrically connected to the gate of the first transistor T9 and the gate of the second transistor T10.

[0186] One end of the voltage regulation module 71 is connected to a low voltage signal, and the other end of the voltage regulation module 71 is connected to the gate of the second transistor T10. The control terminal of the voltage regulation module 71 is electrically connected to the fourth node P, the output terminal of the second output module 70, or the first node of the next-stage shift register, i.e., O[n+1].

[0187] It is understood that the gate drive circuit provided in this embodiment, under the control of one of the fourth node P, the output terminal of the second output module 70, or the first node of the next-stage shift register, namely O[n+1], can stabilize or reduce the gate potential of the second transistor T10 through a low voltage signal, so that the second transistor T10 is stabilized or better in the off state to reduce leakage current, thereby maintaining the potential of the second gate drive signal at a high potential or pulse amplitude, thereby improving the potential stability of the gate drive signal.

[0188] It should be noted that the filter control signal RST2 can be the N-2th stage positive pulse gate drive signal Nout[N-2], and other stages of positive pulse gate drive signals can also be selected according to the filtering needs.

[0189] It should be noted that, in one embodiment, the voltage regulation module 71 is used to stabilize or reduce the low potential of the second node K. Alternatively, in another embodiment, the voltage regulation module 71 is also used to stabilize or reduce the gate potential of the second transistor T10 during the duration of the positive pulse of the second gate drive signal.

[0190] In one embodiment, the voltage regulation module 71 includes a third transistor T15, the first terminal of the third transistor T15 is connected to a low voltage signal, the second terminal of the third transistor T15 is electrically connected to the gate of the second transistor T10, and the gate of the third transistor T15 is electrically connected to one of the fourth node P, the output terminal of the second output module 70, or the first node of the next-level shift register, i.e., O[n+1].

[0191] It should be noted that the third transistor T15 can stabilize or reduce the gate potential of the second transistor T10 during the duration of the positive pulse of the second gate drive signal, so that the second transistor T10 is stable or better in the off state to reduce leakage current, thereby maintaining the potential of the second gate drive signal at a high potential or pulse amplitude, thereby improving the potential stability of the gate drive signal.

[0192] In one embodiment, such as Figure 32 As shown, the gate of the third transistor T15 is electrically connected to one of the fourth node P and the output terminal of the second output module 70. The low voltage signal is the first low potential signal, and the channel type of the third transistor T15 is the same as that of the second transistor T10.

[0193] In this embodiment, both the low voltage signal and the first low potential signal are signal NVGL.

[0194] It should be noted that, since the low voltage signal is the first low potential signal, in this embodiment, the second transistor T10 and the third transistor T15 can share the same low potential line, which can save the number of traces required for the gate drive circuit. The channel type of the third transistor T15 is the same as that of the second transistor T10, and the third transistor T15 can be turned on when the second transistor T10 is in the off state, so as to further reduce the gate potential of the second transistor T10.

[0195] In one embodiment, such as Figure 33 As shown, the gate of the third transistor T15 is electrically connected to one of the fourth node P and the output terminal of the second output module 70. The channel type of the third transistor T15 is the same as that of the second transistor T10, and the potential of the low voltage signal is lower than that of the first low potential signal.

[0196] In this embodiment, the first low-potential signal is signal NVGL, and the low-voltage signal is signal NVGL2.

[0197] It should be noted that the channel type of the third transistor T15 is the same as that of the second transistor T10. This allows the third transistor T15 to transmit the signal NVGL2 to the gate of the second transistor T10 even when the second transistor T10 is in the off state. Compared to the signal NVGL, this further reduces the gate potential of the second transistor T10, thereby reducing its leakage current. This improves the stability of the low potential at the second node K and the low potential at the intermediate node W.

[0198] In one embodiment, the potential difference between signal NVGL and signal NVGL2 is greater than or equal to 2V.

[0199] It should be noted that this embodiment can not only reduce the leakage current of the second transistor T10, but also adjust the threshold voltage of the second transistor T10 to shift in the positive direction, thereby increasing the range of the threshold voltage of the second transistor T10.

[0200] In one embodiment, such as Figure 35 As shown, the first inverting module 50 includes a P-channel fourth transistor T3 and an N-channel fifth transistor T1. The first terminal of the fourth transistor T3 is electrically connected to the second high-potential line, the second terminal of the fourth transistor T3 is electrically connected to the fourth node P, and the gate of the fourth transistor T3 is electrically connected to the second node K. The first terminal of the fifth transistor T1 is electrically connected to the fourth node P, the second terminal of the fifth transistor T1 is connected to the second low-potential signal, and the gate of the fifth transistor T1 is electrically connected to the second node K. The potential of the second low-potential signal is lower than the potential of the low-voltage signal.

[0201] In this embodiment, the second low-potential signal is signal PVGL, and the low-voltage signal is signal NVGL.

[0202] It should be noted that when the fifth transistor T1 is turned on, the gate-source voltage difference of the third transistor T15 can be made less than zero, which can effectively ensure the stability of the third transistor T15 under dual 85.

[0203] In one embodiment, the second transistor T10 is a dual-gate transistor, and the first gate of the second transistor T10 is electrically connected to the second node K and the second gate of the second transistor T10; the third transistor T15 is a dual-gate transistor, and the first gate of the third transistor T15 is electrically connected to the fourth node P and the second gate of the third transistor T15.

[0204] It should be noted that the second transistor T10 and the third transistor T15 are dual-gate transistors, which can not only reduce the drift of the threshold voltage, but also improve the accuracy of control.

[0205] In one embodiment, such as Figure 50 As shown, the gate of the third transistor T15 is electrically connected to the first node O[n+1] of the next stage shift register. The low voltage signal is the first low potential signal, and the channel type of the third transistor T15 is different from that of the second transistor T10. The shift register also includes a sixth transistor T14. The first terminal of the sixth transistor T14 is electrically connected to the second node K, and the second terminal of the sixth transistor T14 is electrically connected to the gate of the first transistor T9. The gate of the sixth transistor is connected to the first clock signal XCK, and the channel type of the sixth transistor is the same as that of the first transistor T9.

[0206] In this embodiment, both the low voltage signal and the first low potential signal are signal VGL.

[0207] It should be noted that the first node of the next-stage shift register, O[n+1], is used as the signal source for the gate of the third transistor T15. The potential of O[n+1] is out of phase with the potential of the fourth node P, while the waveform of O[n+1] is basically the same as the waveform of the fifth node N. Therefore, by using O[n+1] to control the P-channel third transistor T15, the potential of the fifth node N can be continuously and sufficiently pulled down, so that the voltage of the fifth node N reaches the target potential VGL-Vth. This also reduces the leakage current of the second transistor T10 and improves the stability of the high potential provided by the second output module 70.

[0208] Where VGL is the potential of the low-level signal, and Vth is the threshold voltage of the second transistor T10.

[0209] Figure 32 , Figure 33 ,as well as Figure 50 For details on the other structural components and working principle of the gate drive circuit shown, please refer to the aforementioned description of the gate drive circuit.

[0210] Figure 34 for Figure 32 , Figure 33 The timing diagram of the gate drive circuit is shown.

[0211] Figure 32 , Figure 33 The operation of the shift register shown in the diagram within a frame may include, for example: Figure 34 The following stages are shown:

[0212] Phase 1 S1: As Figure 34 , Figure 35As shown, the start control signal STV, reset signal RST, second clock signal CK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are all at low potential, the first clock signal XCK is at high potential, the first node O / O[N], the second node K, the intermediate node W, and the third node Q are all at high potential, the fourth node P is at low potential, the Nth stage positive pulse gate drive signal Nout[N] is at low potential, and the Nth stage negative pulse gate drive signal Pout[N] is at high potential.

[0213] Phase 2 S2: As Figure 34 , Figure 36 As shown, the start control signal STV, reset signal RST, first clock signal XCK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are all at low potential, the second clock signal CK is at high potential, the first node O / O[N], the second node K, the intermediate node W, and the third node Q are all at high potential, the fourth node P is at low potential, the Nth stage positive pulse gate drive signal Nout[N] is at low potential, and the Nth stage negative pulse gate drive signal Pout[N] is at high potential.

[0214] Phase 3 S3: As Figure 34 , Figure 37 As shown, the start control signal STV, the second clock signal CK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are all at low potentials, the reset signal RST and the first clock signal XCK are at high potentials, the first node O / O[N], the second node K, the intermediate node W, and the third node Q are all at high potentials, the fourth node P is at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at low potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0215] Phase 4 S4: such as Figure 34 , Figure 38 As shown, the start control signal STV, the first clock signal XCK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are all at low potentials, the reset signal RST and the second clock signal CK are at high potentials, the first node O / O[N], the second node K, the intermediate node W, and the third node Q are all at high potentials, the fourth node P is at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at low potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0216] Phase 5 S5: As Figure 34 , Figure 39As shown, the second clock signal CK is at a low potential, the start control signal STV, the reset signal RST, the first clock signal XCK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at a high potential, the second node K, the intermediate node W, and the third node Q are at a high potential, the first node O / O[N] and the fourth node P are at a low potential, the Nth stage positive pulse gate drive signal Nout[N] is at a low potential, and the Nth stage negative pulse gate drive signal Pout[N] is at a high potential.

[0217] Phase 6 (S6): (e.g.) Figure 34 , Figure 40 As shown, the first clock signal XCK is at a low potential, the start control signal STV, the reset signal RST, the second clock signal CK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at a high potential, the intermediate node W, the fourth node P, and the third node Q are all at a high potential, the second node K and the first node O / O[N] are at a low potential, the Nth stage positive pulse gate drive signal Nout[N] is at a high potential, and the Nth stage negative pulse gate drive signal Pout[N] is at a high potential.

[0218] Stage 7 (S7): Figure 34 , Figure 41 As shown, the reset signal RST and the second clock signal CK are at low potentials, the start control signal STV, the first clock signal XCK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at high potentials, the fourth node P and the third node Q are both at high potentials, the intermediate node W, the second node K, and the first node O / O[N] are at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at high potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0219] Stage 8 S8: As Figure 34 , Figure 42 As shown, the reset signal RST and the first clock signal XCK are at low potentials, the start control signal STV, the second clock signal CK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at high potentials, the fourth node P and the third node Q are both at high potentials, the intermediate node W, the second node K, and the first node O / O[N] are at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at high potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0220] Stage 9 S9: As Figure 34 , Figure 43As shown, the second clock signal CK and the N-2th positive pulse gate drive signal Nout[N-2] are at low potential, the reset signal RST, the start control signal STV, and the first clock signal XCK are at high potential, the intermediate node W, the first node O / O[N], the fourth node P, and the third node Q are all at high potential, the second node K is at low potential, the Nth positive pulse gate drive signal Nout[N] is at high potential, and the Nth negative pulse gate drive signal Pout[N] is at high potential.

[0221] Stage 10 S10: As Figure 34 , Figure 44 As shown, the start control signal STV, the first clock signal XCK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at low potentials, the reset signal RST and the second clock signal CK are at high potentials, the second node K, the intermediate node W, the first node O / O[N] and the third node Q are all at high potentials, the fourth node P is at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at low potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0222] Phase 11 S11: As Figure 34 , Figure 45 As shown, the reset signal RST and the N-2th stage positive pulse gate drive signal Nout[N-2] are at low potential, the start control signal STV, the first clock signal XCK, and the second clock signal CK are at high potential, the fourth node P and the third node Q are both at high potential, the second node K, the intermediate node W, and the first node O / O[N] are at low potential, the Nth stage positive pulse gate drive signal Nout[N] is at high potential, and the Nth stage negative pulse gate drive signal Pout[N] is at high potential.

[0223] Stage Twelve S12: As Figure 34 , Figure 46 As shown, the second clock signal CK, the start control signal STV, the reset signal RST, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at low potentials, the first clock signal XCK is at high potentials, the fourth node P and the first node O / O[N] are both at high potentials, the third node Q, the second node K, and the intermediate node W are at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at high potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at low potentials.

[0224] Phase Thirteen S13: As Figure 34 , Figure 47As shown, the first clock signal XCK, the start control signal STV, the reset signal RST, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at low potentials, the second clock signal CK is at high potentials, the second node K, the intermediate node W, the third node Q, and the first node O / O[N] are all at high potentials, the fourth node P is at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at low potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0225] Phase Fourteen S14: As Figure 34 , Figure 48 As shown, the second clock signal CK, the start control signal STV, the reset signal RST, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at low potentials, the first clock signal XCK is at high potentials, the second node K, the intermediate node W, the third node Q, and the first node O / O[N] are all at high potentials, the fourth node P is at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at low potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0226] Phase 15 S15: As Figure 34 , Figure 49 As shown, the first clock signal XCK, the start control signal STV, the reset signal RST, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at low potentials, the second clock signal CK is at high potentials, the second node K, the intermediate node W, the third node Q, and the first node O / O[N] are all at high potentials, the fourth node P is at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at low potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0227] It should be noted that, Figures 35 to 49 The "cross" in the diagram indicates that the transistor it covers is in the off state, while the transistors not covered by the "cross" are in the on state. Figures 35 to 49 The dashed arrow in the diagram indicates the direction of the current.

[0228] In one frame, the gate driving circuit includes stages S100 and S200. The first stages S1 to the fifteenth stage S15 belong to stage S100, in which the pulses of each first gate driving signal and each second gate driving signal are output. In stage S200, the pulses of each first gate driving signal and each second gate driving signal are not required. Therefore, by keeping at least one of the first clock signal XCK and the second clock signal CK at a low potential, the potential switching frequency of at least one of the first clock signal XCK and the second clock signal CK can be reduced, thereby reducing power consumption.

[0229] Figure 50 The operation of the shift register shown in the diagram within a frame may include, for example: Figure 51 The following stages are shown:

[0230] Phase 1 S1: As Figure 51 , Figure 52 As shown, the start control signal STV and the second clock signal CK are both at a low level, the first clock signal XCK is at a high level, node N is at a high level, the fourth node P is at a low level, and the Nth stage positive pulse gate drive signal Nout[N] is at a low level.

[0231] Phase 2 S2: As Figure 51 , Figure 53 As shown, the start control signal STV and the first clock signal XCK are at a low level, the second clock signal CK is at a high level, node N is at a high level, the fourth node P is at a low level, and the Nth positive pulse gate drive signal Nout[N] is at a low level.

[0232] Phase 3 S3: As Figure 51 , Figure 54 As shown, the second clock signal CK is at a low potential, the start control signal STV and the first clock signal XCK are at a high potential, node N is at a high potential, the fourth node P is at a low potential, and the Nth positive pulse gate drive signal Nout[N] is at a low potential.

[0233] Phase 4 S4: such as Figure 51 , Figure 55 As shown, the first clock signal XCK is at a low potential, the start control signal STV and the second clock signal CK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth positive pulse gate drive signal Nout[N] is at a high potential.

[0234] Phase 5 S5: As Figure 51 , Figure 56As shown, the second clock signal CK is at a low potential, the start control signal STV and the first clock signal XCK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth positive pulse gate drive signal Nout[N] is at a high potential.

[0235] Phase 6 (S6): (e.g.) Figure 51 , Figure 57 As shown, the first clock signal XCK is at a low potential, the start control signal STV and the second clock signal CK are at a high potential, the fourth node P is at a high potential, the node N is at a low potential, and the Nth positive pulse gate drive signal Nout[N] is at a high potential.

[0236] Stage 7 (S7): Figure 51 , Figure 58 As shown, the start control signal STV and the second clock signal CK are at a low level, the first clock signal XCK is at a high level, the fourth node P is at a high level, the node N is at a low level, and the Nth stage positive pulse gate drive signal Nout[N] is at a high level.

[0237] Stage 8 S8: As Figure 51 , Figure 59 As shown, the start control signal STV and the first clock signal XCK are at a low level, the second clock signal CK is at a high level, node N is at a high level, the fourth node P is at a low level, and the Nth positive pulse gate drive signal Nout[N] switches from a high level to a low level.

[0238] It should be noted that, Figures 52 to 9 The "cross" in the diagram indicates that the transistor it covers is in the off state, while the transistors not covered by the "cross" are in the on state. Figures 52 to 9 The dashed arrow in the diagram indicates the direction of the current.

[0239] Figure 60 for Figure 3 , Figure 20 , Figure 32 , Figure 33 or Figure 50 The diagram shows a cascaded structure of different shift registers in a gate drive circuit. From top to bottom, the shift registers are arranged as follows: Stage 1, Stage 2, Stage 3... Stage N, and Stage N+1... etc. Each shift register operates according to the input first clock signal XCK and second clock signal CK.

[0240] In this system, the control terminals of the first filter module 30 and the second filter module 80 in the first-stage shift register are both connected to a low-level signal VGL, and the input terminal (IN) of the first-stage shift register connected to the start control line is connected to the start control signal STV. The first-stage shift register outputs the corresponding first-stage negative pulse gate drive signal Pout[1] and first-stage positive pulse gate drive signal Nout[1]. The first-stage negative pulse gate drive signal Pout[1] and first-stage positive pulse gate drive signal Nout[1] are used to drive virtual pixels (Dummy) or leave them floating.

[0241] The control terminals of the first filter module 30 and the second filter module 80 in the second-stage shift register are both connected to a low-level signal VGL. The start control line connected to the second-stage shift register is connected to the cascaded signal, namely the first-stage positive pulse gate drive signal Nout[1]. The second-stage shift register outputs the corresponding second-stage negative pulse gate drive signal Pout[2] and second-stage positive pulse gate drive signal Nout[2]. The second-stage negative pulse gate drive signal Pout[2] and second-stage positive pulse gate drive signal Nout[2] are used to drive virtual pixels (Dummy) or leave them floating.

[0242] The control terminals of the first filter module 30 and the second filter module 80 in the third-stage shift register are both connected to a low-potential signal VGL. The start control line connected to the third-stage shift register is connected to the cascaded signal, namely the second-stage positive pulse gate drive signal Nout[2]. The third-stage shift register outputs the corresponding third-stage negative pulse gate drive signal Pout[3] and third-stage positive pulse gate drive signal Nout[3]. The third-stage negative pulse gate drive signal Pout[3] and third-stage positive pulse gate drive signal Nout[3] are used to drive virtual pixels (Dummy) or leave them floating.

[0243] The same logic applies to the others, until the control terminals of the first filter module 30 and the second filter module 80 in the Nth-stage shift register are respectively connected to the Nth-stage positive pulse gate drive signal Nout[NX] and the (N-2)th-stage positive pulse gate drive signal Nout[N-2]. The starting control line connected to the Nth-stage shift register is connected to the cascaded signal, namely the (N-1)th-stage positive pulse gate drive signal Nout[N-1]. The Nth-stage shift register outputs the corresponding Nth-stage negative pulse gate drive signal Pout[N] and Nth-stage positive pulse gate drive signal Nout[N]. The Nth-stage negative pulse gate drive signal Pout[N] and the Nth-stage positive pulse gate drive signal Nout[N] are used to drive the first row of pixel circuits (Pixel).

[0244] The control terminals of the first filter module 30 and the second filter module 80 in the (N+1)th stage shift register are sequentially connected to the (N-X+1)th stage positive pulse gate drive signal Nout[N-X+1] and the (N-1)th stage positive pulse gate drive signal Nout[N-1], respectively. The start control line connected to the (N+1)th stage shift register is connected to the cascaded signal, namely the Nth stage positive pulse gate drive signal Nout[N]. The (N+1)th stage shift register outputs the corresponding (N+1)th stage negative pulse gate drive signal Pout[N+1] and the (N+1)th stage positive pulse gate drive signal Nout[N+1]. The (N+1)th stage negative pulse gate drive signal Pout[N+1] and the (N+1)th stage positive pulse gate drive signal Nout[N+1] are used to drive the second row pixel circuit (Pixel).

[0245] The same logic applies to subsequent shift registers. It's important to note that because some shift register outputs are connected to virtual pixels or are left floating, the outputs of the Nth-level shift register are not connected to the Nth row of pixel circuits. Instead, the row number of pixel circuits connected depends on the number of shift registers connected to virtual pixels or left floating. For example, if shift registers 1 through 3 are connected to virtual pixels, then the outputs of the Nth-level shift register are connected to the (N-3)th row of pixel circuits.

[0246] The same logic applies to other shift registers in the future.

[0247] Figure 61 The display panel shown includes pixel circuits arranged in an array in the display area. Figure 32 The display panel shown includes pixel circuits arranged in an array in the display area, a first gate driving circuit 151 that provides a light emission control signal EM, a fourth gate driving circuit 154 that provides a gate driving signal Pscan2, a second gate driving circuit 152 that provides an Nth-level negative pulse gate driving signal Pout[N] and a gate driving signal Nscan, and a third gate driving circuit 153 that provides an Nth-level negative pulse gate driving signal Pout[N] and a gate driving signal Nscan.

[0248] The first gate driving circuit 151 can be located on the left side of the display area. The output of each shift register in the first gate driving circuit 151 provides a light emission control signal EM to the two adjacent rows of pixel circuits through the corresponding light emission control line, which is a single-sided driving circuit.

[0249] The fourth gate drive circuit 154 can be located on the right side of the display area. The output of each shift register in the fourth gate drive circuit 154 provides a gate drive signal Pscan2 to the pixel circuit of a row through the corresponding gate drive line, which is a single-sided drive.

[0250] The second gate driving circuit 152 is located between the first gate driving circuit 151 and the display area. The third gate driving circuit 153 is located between the fourth gate driving circuit 154 and the display area. A scan line transmitting the Nth negative pulse gate driving signal Pout[N] is electrically connected to the output of a shift register in the second gate driving circuit 152, the output of a shift register in the third gate driving circuit 153, and the pixel circuit of one row. A gate driving line transmitting the gate driving signal Nscan is electrically connected to the output of a shift register in the second gate driving circuit 152, the output of a shift register in the third gate driving circuit 153, and the pixel circuit of one row. This is a dual-side driving configuration.

[0251] Both the second gate drive circuit 152 and the third gate drive circuit 153 can be adopted. Figure 3 , Figure 20 The gate drive circuit is shown. The gate drive signal Nscan may include the Nth positive pulse gate drive signal Nout[N] and the (N-3)th positive pulse gate drive signal Nout[N-3].

[0252] because Figure 1 The pixel circuit shown has a necessary reason for connecting the gate of the first initialization transistor T4P to the (N-1)th stage positive pulse gate drive signal Nout[N-1]. Figure 33 In the pixel circuit shown, after the gate of the write transistor T2P is connected to the Nth level negative pulse gate drive signal Pout[N] and the gate of the compensation transistor T3P is connected to the Nth level positive pulse gate drive signal Nout[N], not only can the gate of the third initialization transistor T8P continue to use the existing gate drive signal Pscan2 (without needing to improve the fourth gate drive circuit 154), but the gate of the first initialization transistor T4P can also be replaced with the N-3 level positive pulse gate drive signal Nout[N-3].

[0253] After that, Figure 62 The pixel circuit shown can operate in one frame not only Figure 63 In addition to the existing stage P12, an additional stage P11 can be added. In this stage P11, the potentials of the three terminals (Q, A, B) of the driving transistor T1P can be reset by synchronously turning on the first initialization transistor T4P and the compensation transistor T3P, so as to reduce the drift of the threshold voltage of the driving transistor T1P and improve the flicker at different refresh frequencies.

[0254] In one embodiment, this embodiment provides a display panel that includes the gate driving circuit and pixel circuit described in at least one of the above embodiments.

[0255] It is understood that, since the display panel provided in this embodiment includes the gate driving circuit in at least one of the above embodiments, it can also be controlled by one of the fourth node P, the output terminal of the second output module 70 or the first node of the next level shift register, i.e., O[n+1]. The voltage adjustment module 71 can stabilize or reduce the gate potential of the second transistor T10 through a low voltage signal, so that the second transistor T10 is stable or better in the off state to reduce leakage current, thereby maintaining the potential of the second gate driving signal at a high potential or pulse amplitude, thereby improving the potential stability of the gate driving signal.

[0256] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0257] The gate driving circuit and display panel provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A gate driving circuit, characterized in that, This includes multiple cascaded shift registers, wherein the shift registers include: The first transistor (T9) includes a gate electrically connected to the first node (K) of the shift register of this stage, a first electrode electrically connected to the first high potential line (NVGH), and a second electrode electrically connected to the first output terminal of the shift register of this stage. The second transistor (T10) includes a gate electrically connected to the first node (K), a first electrode electrically connected to the first low potential line (NVGL), and a second electrode electrically connected to the first output terminal. The third transistor (T13) includes a gate configured to receive a start control signal (STV) or a first gate drive signal (Nout[NY]) output from the shift register of the preceding stage, a first terminal electrically connected to a second low potential line (PVGL), and a second terminal electrically connected to a second node (O) of the shift register of this stage. The fourth transistor (T12) includes a gate electrically connected to the gate of the third transistor (T13), a first electrode electrically connected to the second high potential line (PVGH), and a second electrode electrically connected to the second node (O). The fifth transistor (T2) includes a gate configured to receive a first clock signal (XCK), a first electrode electrically connected to the first node (K), and a second electrode electrically connected to the second node (O); The sixth transistor (T15) includes a gate electrically connected to the third node (P) or the first output terminal of the shift register described in this stage, a first terminal electrically connected to the first low potential line (NVGL) or configured to receive a first electrical signal, and a second terminal electrically connected to the first node (K). The seventh transistor (T3) includes a gate electrically connected to the first node (K), a first electrode electrically connected to the second high potential line (PVGH), and a second electrode electrically connected to the third node (P). The eighth transistor (T1) includes a gate electrically connected to the first node (K), a first electrode electrically connected to the second low potential line (PVGL), and a second electrode electrically connected to the third node (P). Wherein, the first transistor (T9) is a P-channel transistor, and the second transistor (T10) is an N-channel transistor; the voltage value of the signal transmitted by the second low potential line (PVGL) is less than the voltage value of the signal transmitted by the first low potential line (NVGL), the voltage value of the first electrical signal is less than the voltage value of the signal transmitted by the first low potential line (NVGL), and the first clock signal is a periodic signal.

2. A gate driving circuit, characterized in that, This includes multiple cascaded shift registers, wherein the shift registers include: The first transistor (T9) includes a gate electrically connected to the first node (K) of the shift register of this stage, a first electrode electrically connected to the first high potential line (VGH), and a second electrode electrically connected to the first output terminal of the shift register of this stage. The second transistor (T10) includes a gate electrically connected to the first node (K), a first electrode electrically connected to the first low potential line (VGL), and a second electrode electrically connected to the first output terminal. The third transistor (T13) includes a gate configured to receive a start control signal (STV) or a first gate drive signal (Nout[NY]) output by the shift register of the preceding stage, a first terminal electrically connected to a second low potential line, and a second terminal electrically connected to a second node (O) of the shift register of this stage; The fourth transistor (T12) includes a gate electrically connected to the gate of the third transistor (T13), a first electrode electrically connected to the second high potential line, and a second electrode electrically connected to the second node (O). The fifth transistor (T2) includes a gate configured to receive a first clock signal (XCK), a first terminal electrically connected to the first node (K), and a second terminal electrically connected to the second node (O); and The sixth transistor (T15) includes a gate electrically connected to the second node (O) of the shift register of the next stage, a first terminal electrically connected to the first low potential line (VGL), and a second terminal electrically connected to the first node (K). Wherein, the first transistor (T9) is a P-channel transistor, and the second transistor (T10) is an N-channel transistor; the signal transmitted by the first high potential line (VGH) is the same as the signal transmitted by the second high potential line, and the signal transmitted by the first low potential line (VGL) is the same as the signal transmitted by the second low potential line; the first clock signal is a periodic signal.

3. The gate driving circuit according to claim 2, characterized in that, The shift register also includes: The ninth transistor (T14) includes a gate configured to receive the first clock signal (XCK), a first terminal electrically connected to the first node (K), and a second terminal electrically connected to the gate of the first transistor (T9) and the gate of the second transistor (T10). The ninth transistor (T14) has the same channel type as the fifth transistor (T2).

4. The gate driving circuit according to claim 2, characterized in that, The shift register also includes: The seventh transistor (T3) includes a gate electrically connected to the first node (K), a first terminal electrically connected to the second high potential line (VGH), and a second terminal electrically connected to the third node (P) of the shift register of this stage; The eighth transistor (T1) includes a gate electrically connected to the first node (K), a first electrode electrically connected to the second low potential line (VGL), and a second electrode electrically connected to the third node (P). The first terminal of the sixth transistor (T15) is electrically connected to the first terminal of the eighth transistor (T1).

5. The gate driving circuit according to claim 1 or 4, characterized in that, The shift register also includes: The tenth transistor (T4) includes a gate configured to receive a second clock signal (CK), a first electrode electrically connected to the first node (K), and a second electrode; and The eleventh transistor (T5) includes a gate electrically connected to the third node (P), a first electrode electrically connected to the second high potential line, and a second electrode electrically connected to the second electrode of the tenth transistor (T4). Wherein, the second clock signal is a periodic signal, and the frequency of the first clock signal is the same as the frequency of the second clock signal, and the phase of the first clock signal is different from the phase of the second clock signal.

6. The gate driving circuit according to claim 1 or 4, characterized in that, The shift register also includes: The twelfth transistor (T6) includes a gate electrically connected to the first node (K), a first terminal configured to receive a second clock signal (CK), and a second terminal electrically connected to the second output terminal of the gate drive circuit. The thirteenth transistor (T7) includes a gate electrically connected to the third node (P), a first electrode electrically connected to the second high-potential line (PVGH), and a second electrode electrically connected to the second output terminal; and The first capacitor (C1) is electrically connected between the twelfth transistor (T6) and the second output terminal.

7. The gate driving circuit according to claim 6, characterized in that, The shift register also includes: The fourteenth transistor (T8) includes a gate configured to receive a reset signal (RST), a first terminal electrically connected to the first node (K), and a second terminal electrically connected to the gate of the twelfth transistor (T6).

8. The gate driving circuit according to claim 7, characterized in that, The shift register also includes: The fifteenth transistor (T11) includes a gate configured to receive a filter control signal (RST2), a first terminal electrically connected to the first node (K), and a second terminal electrically connected to the first terminal of the fourteenth transistor (T8); and The second capacitor (C2) is electrically connected between the gate of the fifteenth transistor (T11) and the second terminal of the fifteenth transistor (T11).

9. A display panel, characterized in that, include: The gate driving circuit as described in any one of claims 1 to 8; as well as Multiple pixel circuits arranged in an array, each pixel circuit including a light-emitting device, a driving transistor, and a compensation transistor configured to input a control data signal to the gate of the driving transistor, the driving transistor being configured to generate a driving current according to the data signal to drive the light-emitting device to emit light; In this configuration, the gates of the compensation transistors in the multiple pixel circuits located in the same row are all electrically connected to the first output terminal of the shift register of the same level.

10. The display panel according to claim 9, characterized in that, The pixel circuit also includes: A first initialization transistor is configured to control the on / off state of a current path between a first initialization line and the gate of the driving transistor. In the same pixel circuit, the gate of the compensation transistor and the gate of the first initialization transistor are electrically connected to shift registers of different levels, and the shift register to which the gate of the compensation transistor is electrically connected is cascaded after the shift register to which the gate of the first initialization transistor is electrically connected.

Images