A method and system for establishing a Ka-band digital phased array beam based on FPGA

Abstract

The application relates to the technical field of digital phased array, and discloses a Ka-band digital phased array beam establishment method and system based on FPGA. Real-time data of a dynamic target is acquired by a collection module, phase difference analysis and frequency synchronization processing are performed, and a synchronous data set corresponding to an azimuth angle and a frequency is output; based on the data set, an initial phase amplitude weight set is generated through parallel calculation, if the complexity exceeds a preset threshold, the synchronous data set is segmented to obtain a weight data subset. An amplitude and phase control code sequence is generated based on the weight data subset, if the mapping precision is not up to standard, the parameters are adjusted to regenerate, after the mapping precision is up to standard, control instructions are extracted, real-time code streams are generated through synchronous timing processing, if the detection and issuance delay exceeds a threshold, the transmission protocol is optimized, and a low-delay path is determined. The instructions are issued along the path, beam pointing is calibrated and verified, and a final confirmation signal of beam establishment is acquired. The method improves the beam establishment precision and efficiency and adapts to the dynamic target tracking demand.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of digital phased array technology, and in particular to a Ka-band digital phased array beam establishment method and system based on FPGA. BACKGROUND

[0002] Phased array antenna technology is a core supporting technology in the fields of radar, communication, satellite navigation, etc., which realizes rapid beam pointing and flexible adjustment through electronic control, and becomes a key component of modern high-precision wireless systems. In particular, in high-frequency scenarios such as Ka band, the beam response speed and pointing accuracy directly determine the upper limit of system performance, and are crucial to applications such as high-precision detection and high-speed data transmission. Therefore, optimizing Ka-band phased array beam establishment technology has become an important task to improve the adaptability and reliability of wireless systems.

[0003] Current Ka-band phased array beam establishment methods have obvious limitations. Traditional schemes mostly rely on pre-stored weight data or external complex calculation units, which are difficult to adapt to dynamic scene requirements. In the face of frequent changes in target azimuth and frequency (such as high-speed moving target tracking), the system response lags behind, and the beam parameters cannot be quickly adjusted. The core bottleneck is in the weight data processing link. As the key to controlling the phase and amplitude of the array elements, the weight needs to be calculated based on real-time azimuth and frequency information. When the size of the array elements increases, the amount of data processing increases exponentially, making it difficult to balance calculation efficiency and real-time performance. At the same time, after the weight is generated, it needs to be mapped to amplitude and phase control codes and sent to the array element chip. This process is easily restricted by transmission protocols and hardware synchronization capabilities, resulting in code stream delay or distortion, further affecting the efficiency of beam establishment.

[0004] In high-dynamic application scenarios, the above problems are more prominent. High-speed moving target tracking needs to complete the whole process of "data acquisition-weight calculation-beam adjustment" in milliseconds. Due to high computational load and large transmission delay, the existing methods are prone to beam pointing lag, resulting in loss of target signal. Moreover, the coordination between weight calculation and amplitude and phase control code delivery is insufficient, either because of weak parallel processing capability, which prolongs the calculation time, or because of low synchronization accuracy, which leaves residual errors, making it difficult to balance real-time performance and accuracy. These problems restrict the application value of Ka-band phased array systems and cannot provide reliable technical support for high-dynamic scenarios, so more efficient beam establishment techniques are needed. SUMMARY

[0005] The present application provides a Ka-band digital phased array beam establishment method and system based on FPGA to improve the accuracy and efficiency of beam establishment and adapt to dynamic target tracking requirements.

[0006] In a first aspect, to solve the above technical problems, the present application provides a Ka-band digital phased array beam establishment method based on FPGA, comprising:

[0007] acquire real-time input data from a dynamic target tracking environment through an azimuth and frequency information acquisition module, and perform synchronous processing using phase difference analysis and frequency synchronization technology, to output a synchronous data set corresponding to azimuth and frequency;

[0008] Based on the synchronous data set, a parallel computing algorithm is used to perform array element phase estimation and amplitude parameter calibration, and a multi-core processor is used to divide parallel tasks and balance computing load to generate an initial phase amplitude weight set;

[0009] The computational complexity of the initial phase amplitude weight set is evaluated, and if the evaluation result exceeds a preset complexity threshold, the synchronous data set is segmented through a data block parallelization mechanism to obtain a weight data subset;

[0010] Based on the weight data subset, the amplitude and phase code sequence generation and data compression encoding are sequentially performed through a synchronous transmission algorithm, and then mapped into an amplitude and phase control code sequence;

[0011] Determine whether the mapping accuracy of the amplitude and phase control code sequence meets the beam pointing calibration requirement;

[0012] If not, adjust the amplitude and phase code sequence generation parameters based on the weight data subset to regenerate the amplitude and phase control code sequence;

[0013] If yes, extract control instructions from the amplitude and phase control code sequence that meets the beam pointing calibration requirement through an array element chip interface, and process the control instructions using synchronous timing control technology to generate a real-time code stream that is issued to the antenna array;

[0014] Detect the issuance delay of the real-time code stream, and if the issuance delay is higher than a preset delay threshold, adjust the transmission protocol optimization parameters according to real-time feedback information to determine a low-delay code stream distribution path;

[0015] Issue the control instructions to the array element chip along the low-delay code stream distribution path, and calibrate and verify the beam pointing, and after verification, obtain a final confirmation signal of beam establishment.

[0016] In an alternative embodiment, the real-time input data is acquired from a dynamic target tracking environment through an azimuth and frequency information acquisition module, and synchronous processing is performed using phase difference analysis and frequency synchronization technology, to output a synchronous data set corresponding to azimuth and frequency, which includes:

[0017] The real-time azimuth and frequency signals of the dynamic target are synchronously captured through the azimuth and frequency information acquisition module to generate original azimuth and frequency signals;

[0018] Based on the original azimuth signal and the original frequency signal, noise interference is removed and effective signals are extracted to obtain processed azimuth effective signals and frequency effective signals;

[0019] Based on the azimuth effective signals and the frequency effective signals, a phase difference analysis technique is used to calibrate the time reference of the azimuth signal, and a frequency synchronization technique is used to adjust the sampling time of the frequency signal to form a preliminary synchronization data set;

[0020] Based on the preliminary synchronization data set, time deviation verification is performed. If the deviation meets the preset deviation accuracy, a synchronization data set is output. If not, the time alignment of the azimuth and frequency signals is recalibrated based on the deviation until the preset deviation accuracy is met.

[0021] Among them, the effective signal refers to the signal part reflecting the azimuth characteristics and frequency characteristics of the dynamic target.

[0022] In an optional implementation, based on the synchronization data set, a parallel computing algorithm is used to estimate the array element phase and calibrate the amplitude parameter, and a multi-core processor is used to divide the parallel tasks and balance the computing load to generate an initial phase amplitude weight set, including:

[0023] Based on the azimuth and frequency information of the synchronization data set and the distribution characteristics of the array element array, the multi-core processor decomposes the array element phase estimation and amplitude calibration tasks into subtasks, calculates the array element parameters in a specific region corresponding to each subtask, and obtains a subtask list.

[0024] Based on the subtask list, each subtask is calculated in parallel, the phase difference value of the array element is derived based on the azimuth information to determine the phase parameter, and the amplitude parameter is determined by combining the frequency characteristics to correct the amplitude attenuation of the array element signal, to obtain the local phase amplitude parameter corresponding to each subtask.

[0025] According to the calculation progress of each subtask, the multi-core processor dynamically adjusts the load, splits the lagging subtasks to idle cores for acceleration, and combines the leading subtasks to obtain the load-balanced local phase amplitude parameter.

[0026] The load-balanced local phase amplitude parameters are summarized, and after array collaboration verification, an initial phase amplitude weight set covering all array elements is generated.

[0027] In an optional implementation, the calculation complexity of the initial phase amplitude weight set is evaluated. If the evaluation result exceeds the preset complexity threshold, the synchronization data set is divided by a data block parallelization mechanism to obtain a weight data subset, including:

[0028] Based on the number of array elements, parameter dimension and operation amount characteristics of the initial phase amplitude weight set, a calculation complexity evaluation model is constructed to quantitatively evaluate from the dimensions of operation time consumption, resource occupation rate and parallel processing feasibility, and a complexity evaluation result is obtained;

[0029] The complexity evaluation result is compared with a preset complexity threshold value, and if it does not exceed, the initial weight set is used, and if it exceeds, a data block parallelization segmentation process is started; wherein the preset complexity threshold value is set according to the system real-time requirement and the maximum parallel processing capability of the multi-core processor;

[0030] Based on the azimuth angle and frequency data correlation characteristics of the synchronization data set, a data block parallelization mechanism is used for segmentation, and each independent data block is divided into groups of array elements, each independent data block contains complete azimuth angle and frequency information of the corresponding group of array elements, and the calculation complexity is lower than the preset complexity threshold value;

[0031] Each data block is mapped to the corresponding array element parameter in the initial weight set to generate a matching weight data segment, and an optimized weight data subset is obtained by summarizing.

[0032] In an optional implementation, based on the weight data subset, the amplitude and phase code sequence generation and data compression coding are sequentially performed by a synchronization transmission algorithm, and then mapped into an amplitude and phase control code sequence, including:

[0033] Based on the array element phase and amplitude parameters in the optimized weight data subset, the phase code and amplitude code are converted according to the array element chip amplitude and phase control protocol, and the amplitude and phase code sequence is formed by combining the array element number;

[0034] The data redundancy characteristics of the amplitude and phase code sequence are analyzed, a compression coding strategy based on code type redundancy is used to remove repeated code segments and retain key indexes, and a compressed amplitude and phase code sequence is obtained to reduce the transmission amount;

[0035] According to the timing constraints of the synchronization transmission algorithm, the compressed amplitude and phase code sequence is parsed into phase and amplitude control codes for array element recognition, the time reference of each array element control code is ensured to be consistent through synchronization markers, and an amplitude and phase control code sequence is formed by mapping.

[0036] In an optional implementation, based on the weight data subset, the amplitude and phase code sequence generation parameters are adjusted, and a new amplitude and phase control code sequence is generated, including:

[0037] The error source of the previous amplitude and phase control code sequence mapping accuracy is analyzed, the array element phase and amplitude parameter deviation in the weight data subset is combined, and the amplitude and phase code generation key parameters that need to be adjusted are determined; wherein the amplitude and phase code generation key parameters include the phase conversion coefficient, the amplitude calibration factor and the synchronization marker time interval;

[0038] According to the error analysis result, the phase conversion coefficient is linearly corrected according to the deviation between the phase code theoretical value and the actual value, a dynamic compensation amount is introduced to the amplitude calibration factor in combination with the amplitude code error compensation requirement, and the synchronization mark time interval in the amplitude-phase code generation key parameter is fine-tuned according to the time sequence consistency requirement of each array element control code;

[0039] Based on the adjusted amplitude-phase code generation key parameter, the array element phase and amplitude parameters are re-extracted from the weight data subset, the amplitude-phase code sequence combination, data compression encoding and instruction format mapping are sequentially performed, and a new amplitude-phase control code sequence is generated.

[0040] In an optional implementation, the control instructions are extracted from the amplitude-phase control code sequence meeting the beam pointing calibration requirement through the array element chip interface, the control instructions are processed by using the synchronous time sequence control technology, and a real-time code stream is generated and sent to the antenna array surface, including:

[0041] According to the instruction analysis protocol of the array element chip interface, the phase control instructions and the amplitude control instructions corresponding to each array element are extracted from the amplitude-phase control code sequence, the correspondence between the instructions and the array elements is established according to the array element number, and an initial control instruction set is formed;

[0042] Based on the reference clock of the synchronous time sequence control technology, the time sequence of each instruction in the initial control instruction set is calibrated, the execution time mark of the instruction is unified, and a time sequence aligned control instruction set is obtained;

[0043] The time sequence aligned control instruction set is packaged according to the transmission format of the antenna array surface, frame header check information and transmission identification are added, and a real-time code stream is generated and sent to the antenna array surface.

[0044] In an optional implementation, the transmission delay of the real-time code stream is detected, and if the transmission delay is higher than a preset delay threshold, the transmission protocol optimization parameters are adjusted according to the real-time feedback information, and a low-delay code stream distribution path is determined, including:

[0045] According to the real-time code stream transmission time sequence mark and the array element chip receiving timestamp, the real-time code stream transmission-reception time difference is calculated and summarized, and a delay detection result is obtained;

[0046] The delay detection result is compared with the preset delay threshold, and if the delay detection result does not exceed the preset delay threshold, the current path is used, and if the delay detection result exceeds the preset delay threshold, a transmission protocol optimization process is triggered; wherein the preset delay threshold is set according to the beam pointing response speed requirement of the antenna array surface;

[0047] Based on the delay node distribution and the transmission bottleneck in the real-time feedback information, the transmission protocol optimization parameters are adjusted, the data frame length is adjusted, the retransmission mechanism is optimized, and the bandwidth is dynamically allocated to balance the path load;

[0048] According to the adjusted transmission protocol optimization parameter, a candidate code stream distribution path is simulated and evaluated in terms of delay, paths with the lowest delay and meeting stability requirements are screened, and the code stream distribution path is determined.

[0049] In an optional implementation, the control instruction is issued along the low-delay code stream distribution path to the array element chip, calibration verification of beam pointing is performed, and after the verification is passed, a final confirmation signal of beam establishment is acquired, including:

[0050] Along the low-delay code stream distribution path, the control instruction is issued in batches according to the array element reception timing, and through a synchronous transmission mechanism, each array element receives and executes at the same time, driving the antenna array surface to form an initial beam;

[0051] Based on the target tracking environment feedback signal, actual pointing information of the initial beam is acquired, deviation from a preset target azimuth angle is compared and analyzed, and preliminary calibration verification is completed;

[0052] If the deviation is within a preset allowable range, the verification is passed, and a final confirmation signal of beam establishment is generated; if the deviation is out of range, the control instruction is adjusted according to the deviation, and the verification is reissued along the low-delay path until the final confirmation signal is acquired after meeting the requirements.

[0053] In a second aspect, the application also provides a Ka-band digital phased array beam establishment system based on FPGA, including:

[0054] The data synchronization acquisition module acquires real-time input data from a dynamic target tracking environment through the azimuth angle and frequency information acquisition module, and performs synchronous processing by using phase difference analysis and frequency synchronization technology, and outputs a synchronous data set corresponding to the azimuth angle and the frequency;

[0055] The initial weight generation module generates an initial phase amplitude weight set by using a parallel computing algorithm to estimate the phase of the array element and calibrate the amplitude parameter based on the synchronous data set, and divides parallel tasks and balances the computing load by using a multi-core processor.

[0056] The complexity evaluation module evaluates the calculation complexity of the initial phase amplitude weight set, and if the evaluation result exceeds a preset complexity threshold, the synchronous data set is divided into a weight data subset by using a data block parallelization mechanism.

[0057] The control code generation module generates an amplitude-phase code sequence and data compression encoding by using a synchronous transmission algorithm based on the weight data subset, and then maps the amplitude-phase control code sequence.

[0058] The precision conformity judgment module judges whether the mapping precision of the amplitude and phase control code sequence meets the beam pointing calibration requirement, and if not, adjusts the amplitude and phase code sequence generation parameter based on the weight data subset to regenerate the amplitude and phase control code sequence, and if yes, transmits the amplitude and phase control code sequence meeting the beam pointing calibration requirement to the real-time code stream generation module.

[0059] The real-time code stream generation module extracts the control instruction from the amplitude and phase control code sequence meeting the beam pointing calibration requirement through the array element chip interface, processes the control instruction by using the synchronous timing control technology, and generates the real-time code stream to be issued to the antenna array surface.

[0060] The low-delay path determination module detects the issuing delay of the real-time code stream, and if the issuing delay is higher than the preset delay threshold, adjusts the transmission protocol optimization parameter according to the real-time feedback information to determine the low-delay code stream distribution path.

[0061] The beam verification confirmation module issues the control instruction to the array element chip along the low-delay code stream distribution path, calibrates and verifies the beam pointing, and after the verification passes, obtains the final confirmation signal of the beam establishment.

[0062] Compared with the prior art, the present application has the following beneficial effects:

[0063] (1) The azimuth angle and frequency information acquisition module is used to acquire real-time data of a dynamic target, and a phase difference analysis and frequency synchronization technology is used for processing, so as to output an azimuth angle-frequency synchronization data set. Meanwhile, a multi-core processor is used to perform parallel segmentation of tasks and balance the load, so as to generate an initial phase amplitude weight set. This method solves the problems of low data synchronization precision and concentrated calculation load in the traditional method, completely retains the key signal characteristics of the dynamic target, improves the weight calculation efficiency, provides accurate and efficient data basis for subsequent beam establishment, and adapts to the real-time processing requirements of high dynamic scenes.

[0064] (2) The calculation complexity of the initial phase amplitude weight set is evaluated, and when the calculation complexity exceeds a preset threshold, a data block parallelization mechanism is used to segment the synchronization data set to obtain a weight data subset. This adaptive processing strategy breaks through the limitation of the traditional fixed calculation mode, dynamically adjusts the data processing scale according to the weight calculation complexity, effectively balances the calculation complexity and real-time performance, especially in the scene with a large number of array elements, and avoids the system response lag caused by excessive data volume.

[0065] (3) The amplitude and phase control code sequence is generated based on the weight data subset, and the mapping precision is judged, and when the mapping precision does not meet the requirement, the parameter is adjusted to regenerate the amplitude and phase control code sequence. This process solves the calibration deviation problem of the traditional control code generation by using the closed-loop mechanism of "generation-verification-optimization", significantly improves the matching degree of the amplitude and phase control code and the beam pointing requirement, and lays a foundation for subsequent accurate antenna array control.

[0066] (4) The control instruction meeting the accuracy requirement is processed by the synchronous timing control technology to generate the real-time code stream issued to the antenna array. This technical means solves the problem of inconsistent timing in traditional instruction processing, ensures the time reference of the control instruction of each array element uniform, avoids the distortion of the code stream caused by the timing deviation of the instruction, improves the reliability and executability of the real-time code stream, and guarantees the stability of the subsequent transmission and execution link.

[0067] (5) The real-time code stream issuing delay is detected, and the transmission protocol optimization parameter is adjusted and the low-delay code stream distribution path is determined when the threshold is exceeded. This optimization strategy specifically solves the pain point of high transmission delay in the traditional transmission, controls the code stream issuing delay in a reasonable range by dynamically adjusting the transmission parameter and path screening, especially adapts to the scene such as high-speed moving target tracking which requires high response speed, and avoids the beam pointing lag caused by transmission delay.

[0068] (6) The control instruction is issued along the low-delay path, and the beam pointing is calibrated and verified, and if it fails, it is re-adjusted and issued. This verification closed-loop mechanism solves the pointing deviation problem that may occur in the traditional beam establishment "one-time execution", ensures that the beam pointing meets the requirements through multiple rounds of calibration, finally outputs a reliable beam establishment confirmation signal, significantly improves the beam establishment accuracy and stability of the Ka-band phased array system, and provides reliable technical support for high-precision applications in the fields of radar, communication and the like. BRIEF DESCRIPTION OF DRAWINGS

[0069] Figure 1 is a flowchart of a Ka-band digital phased array beam establishment method based on FPGA provided by an embodiment of the present application;

[0070] Figure 2 is a structural schematic diagram of a Ka-band digital phased array beam establishment system based on FPGA provided by an embodiment of the present application. DETAILED DESCRIPTION

[0071] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0072] With reference to Figure 1 , the present application provides a Ka-band digital phased array beam establishment method based on FPGA, comprising the following steps:

[0073] S11, acquiring real-time input data from a dynamic target tracking environment by an azimuth angle and frequency information acquisition module, and performing synchronous processing by using phase difference analysis and frequency synchronization technology, to output a synchronous data set corresponding to the azimuth angle and the frequency;

[0074] S12, performing array element phase estimation and amplitude parameter calibration by using a parallel computing algorithm based on the synchronous data set, dividing parallel tasks and balancing computing load by using a multi-core processor, and generating an initial phase amplitude weight set;

[0075] S13, evaluating the calculation complexity of the initial phase amplitude weight set, and if the evaluation result exceeds a preset complexity threshold, dividing the synchronous data set by using a data block parallelization mechanism to obtain a weight data subset;

[0076] S14, sequentially performing amplitude and phase code sequence generation and data compression encoding by using a synchronous transmission algorithm based on the weight data subset, and then mapping into an amplitude and phase control code sequence;

[0077] S15, judging whether the mapping precision of the amplitude and phase control code sequence meets the beam pointing calibration requirement; if not, adjusting the amplitude and phase code sequence generation parameter based on the weight data subset, and regenerating the amplitude and phase control code sequence; if yes, extracting a control instruction from the amplitude and phase control code sequence meeting the beam pointing calibration requirement by using an array element chip interface, and processing the control instruction by using a synchronous timing control technology to generate a real-time code stream to be issued to an antenna array;

[0078] S16, detecting the issuance delay of the real-time code stream, and if the issuance delay is higher than a preset delay threshold, adjusting a transmission protocol optimization parameter according to real-time feedback information to determine a low-delay code stream distribution path;

[0079] S17, issuing the control instruction to the array element chip along the low-delay code stream distribution path, and calibrating and verifying the beam pointing, and after the verification is passed, obtaining a final confirmation signal of beam establishment.

[0080] In step S11, real-time input data is acquired from a dynamic target tracking environment by an azimuth angle and frequency information acquisition module, and synchronous processing is performed by using phase difference analysis and frequency synchronization technology, to output a synchronous data set corresponding to the azimuth angle and the frequency.

[0081] In an embodiment, the present embodiment takes a Ka band (28 GHz) phased array radar tracking an airborne dynamic target (such as a drone) as a scene, and a azimuth angle-frequency acquisition system (integrating a 16-channel phased array antenna and a high-speed ADC module) controlled by an FPGA is used to realize the synchronous data set generation process in detail.

[0082] Firstly, the original signals are captured synchronously: through the azimuth information acquisition module (including phase interferometer, measurement range 0-360°, accuracy ±0.1°) and the frequency information acquisition module (Ka band receiver, center frequency 28 GHz, bandwidth 1 GHz) of the phased array antenna, the real-time azimuth signal and the frequency signal of the dynamic target are synchronously captured under the trigger of the 100 MHz synchronous clock output by the FPGA. The original azimuth signal is output in 16-bit binary format, and each frame contains an azimuth value (such as 30.5°) and a 1 ns precision timestamp; the original frequency signal is quantized to 12-bit data by ADC (sampling rate 2GSps), and each frame contains 4096 sampling points, reflecting the Doppler frequency offset characteristics (range ±500 MHz) of the target. During the acquisition process, through the synchronous pulse control of the FPGA, the timestamp deviation of the two types of original signals is strictly controlled to be ≤500 ps, and the generated original data is temporarily stored in the on-chip RAM (capacity 8 MB) of the FPGA.

[0083] Then, the noise removal processing and effective signal extraction are performed: for the original azimuth signal, a 64-order FIR low-pass filter (cutoff frequency 10 kHz) implemented by FPGA is used to filter out the high-frequency noise introduced by antenna mechanical jitter, and then 32-point sliding window variance detection is used to remove abnormal values (such as jumps caused by target flickering) with variance > (0.01°) ² ; for the original frequency signal, an adaptive LMS filter (convergence factor 0.01) of the FPGA is used to suppress clutter interference, and through FFT analysis, the signal segment with a center frequency in the range of 27.5-28.5 GHz and a signal-to-noise ratio ≥25 dB is extracted - here, the "effective signal" is the signal part reflecting the true azimuth (deviation ≤0.2°) and Doppler frequency offset (deviation ≤1 MHz) of the target, and finally the processed azimuth effective signal (accuracy ±0.08°) and frequency effective signal (frequency offset stability ±0.5 MHz) are obtained.

[0084] Subsequently, the time reference calibration and preliminary synchronous data set construction are performed: based on the azimuth effective signal, the phase difference analysis technique is used to calibrate the time reference - the azimuth phase difference of adjacent sampling points (interval 10 μs) is compared with the theoretical phase difference of the target motion (derived from the radar ranging data), and the timestamp is corrected in steps of 10 ps to make the azimuth signal time reference accuracy ≤100 ps; at the same time, the frequency synchronization is realized through the phase-locked loop (PLL, bandwidth 1 MHz) built-in the FPGA, the sampling time of the frequency signal is dynamically adjusted to ensure alignment (deviation ≤200 ps) with the azimuth signal time reference. The calibrated two types of effective signals are integrated according to the timestamp to form a preliminary synchronous data set (each frame contains azimuth, frequency, 1 ns timestamp, frame rate 100 kHz).

[0085] Finally, time offset verification and synchronized dataset output: preset time offset accuracy threshold is "azimuth angle and frequency signal timestamp difference value ≤ 500 ps" (adapt to Ka band phased array beam fast pointing requirement). Traverse the preliminary synchronization dataset, calculate the timestamp difference value Δt of each frame, if Δt ≤ 500 ps, directly output the synchronization dataset in the format of "frame number + timestamp + azimuth angle + frequency" (stored in the external DDR4 of FPGA, capacity 1 GB); if a frame Δt = 600 ps (threshold value), adjust the PLL phase offset to recalibrate the sampling time, reconstruct the preliminary dataset and verify again, until all frames Δt ≤ 500 ps, finally output the azimuth angle-frequency synchronization dataset that meets the time synchronization requirements, providing the basis for subsequent phase amplitude weight calculation.

[0086] In step S12, based on the synchronization dataset, the array element phase estimation and amplitude parameter calibration are performed using a parallel computing algorithm, the multi-core processor is used to divide the parallel tasks and balance the computing load, and the initial phase amplitude weight set is generated.

[0087] In one embodiment, the present embodiment connects the previous "synchronization dataset generation" link, continues the Ka band (28 GHz) phased array radar tracking airborne target (drone) scene, based on the synchronization dataset (containing target azimuth angle, Doppler frequency and 1 ns accuracy timestamp, frame rate 100 kHz) output by the previous link, combined with 16 channel phased array antenna (array element spacing 5.35 mm, corresponding to Ka band half wavelength, distributed in 4x4 matrix) and four-core ARM Cortex-A53 processor integrated in FPGA (clock frequency 1.5 GHz, supporting task parallel scheduling), the initial phase amplitude weight set generation process is completely realized.

[0088] First, task decomposition: based on the azimuth angle (such as 30.5°, accuracy ± 0.08°), frequency (such as 28.2 GHz, frequency deviation ± 0.5 MHz) in the synchronization dataset and the spatial distribution of 16 array elements (divided into 4 regional sub-arrays according to columns, 4 array elements in each sub-array, and the signal correlation of array elements in the same region is ≥ 95%), the four-core processor divides the "16 array element phase estimation + amplitude calibration" total task into 4 independent sub-tasks. Each sub-task corresponds to a regional sub-array, and the corresponding frame segment (2000 frames of data are allocated to each sub-task) of the input synchronization dataset and the calculation deadline (≤ 10 μs, adapt to the real-time requirement of 100 kHz frame rate) are determined, forming a sub-task list sorted by region, which is distributed to 4 cores for parallel execution by the processor task scheduler, ensuring that there is no data dependency between sub-tasks.

[0089] Then perform parallel computing: in terms of phase parameter calculation, based on the azimuth angle θ in the synchronization dataset, the array element phase difference formula is used: , (where d = 5.35 mm is the distance between adjacent elements in the same area, λ = 10.7 mm is the wavelength in the Ka band, and c = 3 x 10 8 m / s and the center frequency 28 GHz), the phase difference value of the elements is derived. For example, for a certain subarray corresponding to an azimuth angle of 30.5°, sinθ = 0.5075, and by substituting, we get (about 58.3°), and the phase difference is corrected to 58.3 ± 0.15° in combination with the azimuth angle fluctuation ± 0.08°, taking the first element in the area as the phase reference 0°, and the absolute phase parameters of each element are obtained by accumulating the phase difference (accuracy ± 0.1°); in terms of amplitude parameter calculation, the attenuation correction formula is combined with the frequency characteristics: , (where A0= 20 dB is the reference amplitude, f0= 28 GHz is the center frequency, and f is the actual frequency of the target) to correct the attenuation, such as when the target frequency is 28.2 GHz, lg(28.2 / 28) = 0.0029, and by substituting the formula, we get A = 19.8 dB, and in combination with the frequency deviation ± 0.5 MHz, the amplitude is corrected to 19.8 ± 0.05 dB (accuracy ± 0.03 dB), and the local phase and amplitude parameters are output by each subtask and temporarily stored in the shared memory of the processor.

[0090] Subsequently, the load is dynamically adjusted: the processor tracks the progress through real-time monitoring modules (sampling interval 1 μs) and sets the progress ≥ 80% within the cutoff time as advanced and ≤ 60% as lagging. If the subtask processed by core 1 has slightly high data noise, and the progress is only 55% (lagging) at 8 μs, it is split into two "2-element" small tasks, one of which is dispatched to core 4 (core 4 is in an advanced state with a progress of 90% at this time); at the same time, the preprocessing tasks of the subsequent 100 frames of data of core 4 are combined to avoid core idling. After adjustment, all subtasks are completed within 9-10 μs, and the core CPU usage rate is stabilized at 70%-75%, obtaining the local parameters after load balancing (the parameter deviation between subtasks is ≤ 0.05° / 0.02 dB).

[0091] Finally, the local parameters of the four sub-tasks are integrated to form a global parameter list according to the rule of "region from left to right, same region from top to bottom", and the array consistency check is performed through the mean square error (MSE). The phase deviation Δφ and the amplitude deviation ΔA of adjacent sub-arrays are calculated. The square sum of all phase deviations and the square sum of amplitude deviations are calculated, then the sum is divided by the number of elements (N=4) of the adjacent sub-array, and the square root is taken to get the MSE value. The parameter consistency is evaluated, and the preset MSE≤0.08 is passed (adapted to the Ka band beam pointing accuracy requirement). If the MSE of a certain adjacent sub-array is 0.1 (exceeding the threshold), the calculation precision of sinθ in the phase model of the sub-task is modified to 6 decimal places, and the MSE is reduced to 0.07 after re-calculation. Finally, an initial phase amplitude weight set covering 16 elements (format: "element number + phase value + amplitude value + time stamp") is generated and stored in the FPGA external DDR4, providing a data basis for subsequent complexity evaluation.

[0092] In step S13, the calculation complexity of the initial phase amplitude weight set is evaluated, and if the evaluation result exceeds the preset complexity threshold, the synchronization data set is divided by the data block parallelization mechanism to obtain a weight data subset.

[0093] In one embodiment, the present embodiment connects the previous "initial phase amplitude weight set generation" link and continues the Ka band (28 GHz) phased array radar tracking airborne target (drone) scene. Based on the initial phase amplitude weight set (containing 16 element phase values, amplitude values and time stamps, stored in the FPGA external DDR4) generated in the previous link and the four-core ARM Cortex-A53 processor (1.5 GHz), the same synchronization data set (containing target azimuth, frequency and 1 ns timestamp, frame rate 100 kHz) is used to realize calculation complexity evaluation and weight data subset generation.

[0094] First, a calculation complexity evaluation model is constructed: taking the number of elements (16), the parameter dimension (2D, phase + amplitude), and the operation amount (15 floating point operations per element to support subsequent amplitude and phase code generation, total operation amount 240) as input, the three-dimensional quantitative evaluation is performed. The operation time is measured by the processor timer, and the whole processing of the initial weight set (including parameter calling, amplitude and phase conversion pre-calculation) takes about 12μs. The resource occupation rate is obtained by the processor monitoring module, and the average CPU usage rate is 85% and the memory occupation rate is 60% during whole processing. The parallel processing feasibility analysis of the sub-task dependency finds that there is a 20% dependency relationship in the calculation of cross-region elements, and the parallel efficiency is only 80%, forming an evaluation result of "time consumption 12μs, CPU usage rate 85%, parallel efficiency 80%".

[0095] Then compare with the preset complex threshold: the threshold is set according to the real-time requirement of the system (adapt to 100 kHz frame rate, single processing time ≤10 μs) and the parallel processing capacity of the processor (CPU maximum stable use rate 80%, parallel efficiency ≥85%). Because the evaluation result is 12 μs>10 μs, CPU use rate 85%>80%, parallel efficiency 80%<85%, which exceeds the threshold, the data block parallel segmentation is started; if it does not exceed the threshold, the initial weight set is directly used.

[0096] Then perform data block segmentation: based on the azimuth angle and frequency correlation characteristics of the synchronization data set (azimuth angle deviation of the same column element ≤0.1°, frequency correlation ≥98%), it is divided into 4 independent data blocks (each block contains 4 same column elements) according to "column element group". Each data block contains the complete azimuth angle (such as 30.5°±0.08°), frequency (28.2 GHz±0.5 MHz) and timestamp information of the corresponding element, and the pre-computed verification shows that the single block processing time is about 2.5 μs (≤10 μs / 4), the single core CPU use rate is 70% (≤80%), and the parallel efficiency is 95% (no cross-block dependence), which are all below the threshold.

[0097] Finally, the weight data subset is generated: the 4 data blocks are respectively mapped to the parameters of the corresponding column elements in the initial weight set, such as the phase (58.3°±0.15°, etc.) and amplitude (19.8 dB±0.05 dB, etc.) of the 1st, 5th, 9th and 13th elements in the 1st column data block, to generate the "azimuth angle-frequency-weight" matched weight data segment; four segments are summarized to ensure that the timestamp is consistent with the synchronization data set, and the optimized weight data subset (containing 4 column element group segments) is obtained, which is stored in the on-chip RAM of the FPGA, providing a low complexity data basis for subsequent amplitude and phase code sequence generation.

[0098] In step S14, based on the weight data subset, the amplitude and phase code sequence generation and data compression encoding are sequentially performed by a synchronous transmission algorithm, and then mapped into an amplitude and phase control code sequence.

[0099] In an embodiment, the present embodiment connects the "weight data subset generation" link in the foregoing, continues the Ka band (28 GHz) phased array radar tracking air target (drone) scene, and based on the weight data subset (containing 4 column element group segments, each segment corresponding to the phase value, amplitude value and matched azimuth angle-frequency information of 4 same column elements, stored in the on-chip RAM of the FPGA) generated in the foregoing, combines the element control chip (selecting HMC624LP4E, supporting SPI amplitude and phase control protocol, adapting to the Ka band high-speed response requirement) and the synchronous transmission algorithm (based on 100 MHz clock design, transmission period 10 μs), and realizes the amplitude and phase control code sequence generation process.

[0100] Firstly, the amplitude-phase code sequence combination is carried out: the code type conversion is carried out based on the array element parameters in the weight data subset. Taking the first column array element group (1, 5, 9, 13 array elements) as an example, the phase values are calculated as 58.3°, 58.4°, 58.3°, 58.3° by the phase difference formula, and converted into 8-bit phase codes in turn as 00100011, 00100100, 00100011, 00100011; the amplitude values are all calculated as 19.8 dB (after correction) by the amplitude attenuation formula, and converted into 4-bit amplitude codes as 1001 (corresponding to 18 dB, error ≤0.2 dB, due to the limitation of chip coding resolution, the deviation from the theoretical value calculated by the formula is within the allowable range). The “phase code-amplitude code” pairs are combined according to the array element number (1-16, column priority), such as 1 array element “00100011-1001” and 5 array element “00100100-1001”, and finally an amplitude-phase code sequence with a total length of 16x(8+4)=192 bits is formed, and the code type repetition rate of the same column array elements in the sequence reaches 75% (such as the phase code repetition of the 3 array elements in the 1st column, which is caused by the minimal deviation of the phase values of the same column array elements calculated by the phase difference formula).

[0101] Then, the data compression coding is carried out: through the analysis of the redundancy detection module (sliding window length 12 bits) of the FPGA, it is found that the “phase code-amplitude code” combination repetition degree of the same column array elements is high (such as 3 groups of completely consistent in the 3 array elements in the 3rd column, because the amplitude values of the array elements in the column are all 19.8 dB calculated by the amplitude attenuation formula, and the phase value deviation is ≤0.1°), and the code type similarity of the adjacent array elements across columns reaches 60%. The compression strategy based on the code type repetition degree is adopted: the “code segment content-repetition number” index is recorded for the continuously repeated code segment, such as the “00100011-1001” in the 1st column appearing 3 times in succession, which is recorded as “[00100011-1001]-3” after compression; only the reference code segment and the deviation value are stored for the high similarity cross-column code segment (such as the deviation of 1 bit between a code segment in the 2nd column and the reference code segment in the 1st column, which is recorded as “reference [00100011-1001]+deviation 00000001”). After the compression processing, the length of the amplitude-phase code sequence is reduced from 192 bits to 102 bits, the transmission amount is reduced by about 47%, the FPGA internal bus bandwidth occupation is reduced, the code type characteristics corresponding to the formula calculation parameters are retained, and the parameter accuracy after subsequent decoding is ensured without loss.

[0102] Finally, the mapping is the amplitude and phase control code sequence: according to the timing constraints of the synchronous transmission algorithm (10 μs transmission period per frame, adapting to 100 kHz frame rate), the compressed code segment is restored (such as “[00100011-1001]-3” is restored to 3 complete code segments, and the phase and amplitude values corresponding to the restored code type are still consistent with the formula calculation results in step S12) by the FPGA decoding module, and the deviation code segment is corrected, to obtain the control code corresponding to the 16 elements. An 8-bit synchronization marker “10101010” is added at the starting position of each frame of control code, which is calibrated by the FPGA 100 MHz global synchronization clock, ensuring that the time reference deviation of each element receiving the control code is ≤100 ps (meeting the timing accuracy requirements of Ka-band beam rapid pointing). The final amplitude and phase control code sequence contains 8-bit synchronization markers + 192-bit control codes per frame, with a total length of 200 bits, stored in the FPGA output FIFO (depth 1024), providing a basis for subsequent mapping accuracy judgment.

[0103] In step S15, it is judged whether the mapping accuracy of the amplitude and phase control code sequence meets the beam pointing calibration requirements; if not, the amplitude and phase code sequence generation parameters are adjusted based on the weight data subset, and the amplitude and phase control code sequence is regenerated; if yes, the control instructions are extracted from the amplitude and phase control code sequence that meets the beam pointing calibration requirements through the element chip interface, and the control instructions are processed using synchronous timing control technology to generate real-time code streams that are issued to the antenna array.

[0104] In one embodiment, the present embodiment connects the previous “amplitude and phase control code sequence generation” link and continues the Ka-band (28 GHz) phased array radar scenario. Based on the generated amplitude and phase control code sequence, weight data subset and HMC624LP4E element chip, it is first judged whether the mapping accuracy meets the beam pointing calibration requirements (preset deviation ≤0.3°), and then parameter adjustment is performed for the non-compliant scenario.

[0105] If the mapping accuracy meets the requirements (such as the actual measured pointing deviation of each element is ≤0.3°), the amplitude and phase control code sequence is directly used for the subsequent control instruction extraction process.

[0106] If it does not meet (such as the actual measurement of 16 elements, 6-8, 12-16 element pointing deviation of 0.4-0.5°, exceed the preset threshold), adjust as follows: first analyze the error source: combined with the theoretical parameters in the weight data subset (such as the 6th element theoretical phase 62.1°, amplitude 20.2dB) and actual code value, it is found that there is a 1.8% nonlinear deviation in phase code conversion (theoretical 62.1° corresponds to code value 00100110, actual output 63.2°), the amplitude code is 0.9dB lower than the theoretical value due to link loss, and the synchronization marker time interval is 10μs, which makes the deep element receive delay 120ps, so it is determined that the phase conversion coefficient, amplitude calibration factor and synchronization marker time interval need to be adjusted.

[0107] Subsequently, the parameters are adjusted: the phase conversion coefficient is modified from 1.0 to 0.982 (to offset 1.8% positive deviation), ensuring that the phase code corresponds to a phase deviation of ≤0.05°; the amplitude calibration factor introduces a 0.045 compensation (original 1.0→1.045), compensating for 0.9dB loss; the synchronization marker time interval is fine-tuned to 9.9μs, making the element receive delay ≤50ps.

[0108] Finally, the sequence is regenerated: based on the adjusted parameters, the element parameters are extracted from the weight data subset (such as the 6th element phase 62.1° converted by the modified coefficient, corresponding to the phase code 00100101), the code sequence combination, compression (keeping 102 bits long) and synchronization marker addition are re-executed, and a new amplitude and phase control code sequence is generated. Again, the verification shows that all element pointing deviations are reduced to 0.2-0.28°, meeting the calibration requirements.

[0109] It is worth noting that the control instructions are extracted from the amplitude and phase control code sequence that meets the beam pointing calibration requirements through the element chip interface, and the control instructions are processed using the synchronous timing control technology to generate real-time code streams that are sent to the antenna array.

[0110] In one embodiment, the present embodiment connects the previous "amplitude and phase control code sequence adjustment" link and continues the Ka band (28GHz) phased array radar tracking of air target scenarios, based on the amplitude and phase control code sequence that meets the beam pointing calibration requirements (each element pointing deviation 0.2-0.28°, stored in the FPGA output FIFO), the SPI interface protocol of the HMC624LP4E element chip and the FPGA synchronous timing control module (100MHz reference clock, phase jitter ≤10ps), to realize control instruction extraction, timing processing and real-time code stream generation.

[0111] Firstly, the control instructions are extracted: according to the SPI instruction analysis protocol of HMC624LP4E (the amplitude-phase control code sequence frame structure is "8-bit synchronization marker + 16 groups (8-bit phase control code + 4-bit amplitude control code)"), the FPGA identifies the synchronization marker "10101010" through the SPI decoding module, and then extracts the phase control instructions (8 bits, such as the 6th array element "00100101") and the amplitude control instructions (4 bits, such as the 6th array element "1010") of the 16 array elements in turn according to the rule that "each 12 bits after the synchronization marker correspond to an array element". The "instruction-array element" correspondence is established according to the array element number (1-16, column priority order), for example, "00100101-1010" is bound to the 6th array element to form an initial control instruction set, and each group of instructions is attached with an array element number and an original timestamp, and temporarily stored in the FPGA instruction cache (capacity 512KB).

[0112] Then, the timing calibration is performed: based on the 100MHz reference clock (providing 10ns precision time mark), the execution time of the instructions in the initial control instruction set is uniformly performed, that is, the execution time of all array element instructions is set to "500ns after the reference clock trigger", and the transmission path difference is corrected through the delay compensation algorithm: the transmission delay of the instructions of the 12th-16th array elements is 80ps more than that of the 1st-4th array elements, so 80ps compensation is added to the execution time mark of the instructions to ensure that the actual execution time deviation of all instructions is ≤30ps (meeting the timing consistency requirement of Ka-band beam fast switching), and the timing-aligned control instruction set is obtained.

[0113] Finally, the real-time code stream is packaged: the timing-aligned instruction set is packaged according to the transmission format of the antenna array (self-defined frame structure), including "32-bit CRC32 frame header check (calculated based on instruction data, used for integrity check) + 16-bit frame number (cycled by 1-10000, adapted to 100kHz frame rate) + 8-bit transmission identification (fixed as "KA-BEAM-CTRL", used for array identification) + instruction data area (16 groups of timing-aligned control instructions) + 8-bit frame tail". The total length of each frame of the packaged real-time code stream is 32+16+8+(16x12)+8=264 bits, which is transmitted to the 16-channel phased array antenna array through the high-speed serial interface (transmission rate 1Gbps, bit error rate ) of the FPGA, providing a basis for subsequent code stream delay detection.

[0114] In step S16, the transmission delay of the real-time code stream is detected, and if the transmission delay is higher than a preset delay threshold, the transmission protocol optimization parameters are adjusted according to the real-time feedback information to determine a low-delay code stream distribution path.

[0115] In one implementation, the present embodiment connects the previous "real-time code stream generation" link, continues the Ka-band (28GHz) phased array radar tracking of airborne target scenarios, and based on the real-time code stream (264 bits per frame, including 32-bit CRC32 check, 16-bit frame number, 8-bit "KA-BEAM-CTRL" identifier, and 16 sets of control instructions, transmitted through a 1Gbps high-speed serial interface) generated in the previous link and HMC624LP4E array element chip, combined with the FPGA delay detection module (integrating a 100MHz reference clock and a 1ps precision timestamp unit), to realize delay detection, protocol optimization and path determination.

[0116] First, delay detection is performed: when the FPGA transmits the real-time code stream, a transmission time sequence marker (t send , precision 1ps) based on the 100MHz clock is added for each frame, such as t send =1000ns for the first frame and t send =1010ns for the second frame (adapted to the 10ns interval of 100kHz frame rate); after the 16 array element chips receive the code stream, they record the reception timestamp (t recv ) through the built-in timestamp unit and feed it back to the FPGA. The delay detection module calculates the transmission-reception time difference for each frame, and the results are obtained by summarizing multiple frames: the average At for array elements 1-4 is 350ns, for array elements 5-8 is 420ns, for array elements 9-12 is 550ns, for array elements 13-16 is 620ns, the overall average is 485ns, and the maximum is 620ns.

[0117] Then, the preset threshold is compared: the threshold is set according to the response speed requirement of the antenna array beam pointing (the radar needs to complete beam switching within 600ns, so the preset "maximum delay ≤600ns" is set). Since the maximum delay of array elements 13-16 is 620ns>600ns, the transmission protocol optimization is triggered; if the delay of all array elements is ≤600ns, the current "FPGA→single serial bus→array element" path is used.

[0118] Subsequently, the transmission protocol parameters are adjusted: the bottleneck is identified through feedback data - the delay of array elements 9-16 is high, which is caused by the long transmission path (the wiring distance is 5cm longer than that of array elements 1-8), resulting in signal attenuation, and the original protocol frame length of 264 bits has a frame header accounting for 12% (32 / 264), the stop-and-wait ARQ retransmission mechanism has a single delay of 100ns, and the bandwidth is allocated equally among the 16 array elements (62.5Mbps per array element). Targeted adjustments: the frame length is increased to 528 bits (the frame header is still 32 bits, accounting for 6%); the retransmission mechanism is changed to selective ARQ (only retransmit error frames, with a delay of 30ns); and the bandwidth is dynamically allocated (50Mbps for each of array elements 1-8, 75Mbps for each of array elements 9-16, and the total bandwidth is still 1Gbps).

[0119] Finally determine the low delay path: simulation evaluation of 3 candidate paths - candidate 1 (dual bus: 1-8 No. 1 path, 9-16 No. 1 path) average delay 320ns, maximum 380ns, packet loss rate ; candidate 2 (star bus) average 290ns but need additional 8 interfaces, stability fluctuation (packet loss rate occasionally up to ); candidate 3 (original single path) optimized maximum 580ns. Comprehensive screening candidate 1 as distribution path, ensure all array element delay ≤400ns, meet the demand of beam fast response.

[0120] In step S17, the control instruction is issued to the array element chip along the low delay code stream distribution path, the beam pointing is calibrated and verified, and after the verification is passed, the final confirmation signal of beam establishment is obtained.

[0121] In an embodiment, the present embodiment connects the previous "low delay code stream distribution path determination" link, continues the Ka band (28GHz) phased array radar tracking airborne target scene, uses the determined low delay path (dual bus: 1-8 array elements as shallow bus, 9-16 array elements as deep bus), combines HMC624LP4E array element chip, FPGA synchronous transmission module (100MHz reference clock, phase jitter ≤10ps) and beam pointing verification unit, realizes control instruction issuing, calibration verification and final confirmation signal acquisition.

[0122] When issuing control instructions along the low delay path, FPGA processes batches according to array element receiving time sequence from time sequence aligned control instruction set: shallow bus carries 8 groups of instructions of 1-8 array elements, deep bus carries 8 groups of instructions of 9-16 array elements, each batch of instructions is separated by 50ns (adapted to 1Gbps transmission rate, avoiding bus conflict). Through synchronous transmission mechanism to ensure simultaneous execution - take 100MHz reference clock rising edge as trigger signal, two-way bus sends instructions synchronously, array element chip receives and modifies path difference through built-in delay compensation unit (shallow compensation 20ps, deep compensation 30ps), finally all array element instruction execution time deviation ≤15ps, drive 16 channel antenna array to form initial beam (theoretical pointing is set to 30.5° based on synchronous data set, covering target tracking area).

[0123] Based on the target tracking environment feedback signal (radar echo phase difference information after receiving and processing by array element), the actual pointing of the initial beam is collected by the phase interferometer: 1-8 array elements point to 30.55°-30.65°, 9-16 array elements point to 30.6°-30.7°, compared with the preset target azimuth angle 30.5°, the maximum deviation is 0.2° (≤ preset allowable range 0.3°), the preliminary calibration verification is passed. If the actual pointing of the 13th array element is 30.9° (deviation 0.4° exceeds the range) in a certain verification, the phase control instruction is adjusted according to the deviation (from "00101100" to "00101011", corresponding to a decrease of 1.40625°), which is reissued along the double bus, and the pointing deviation is reduced to 0.25° again, which meets the requirements.

[0124] After verification, the FPGA confirmation signal generation module integrates key information: path identification "double bus-shallow layer + deep layer", actual pointing deviation of each array element (1-8, 0.05°-0.15°, 9-16, 0.1°-0.2°), instruction issuance timestamp (100MHz clock synchronization, accuracy 1ps) and frame number (5000th frame, adaptive to 100kHz frame rate), generates a 32-byte final confirmation signal (format "path identification + deviation list + timestamp + frame number + CRC16 check"). The signal is stored in the FPGA non-volatile memory and uploaded to the radar main control system, indicating that the Ka band digital phased array beam is established and can enter the stable tracking stage.

[0125] In summary, the application collects azimuth angle and frequency data from a dynamic target tracking environment, generates a synchronized data set through synchronous processing; based on the data set, an initial phase amplitude weight set is generated by parallel computing of a multi-core processor, and a weight data subset is obtained by segmentation as needed; the amplitude and phase control code sequence is generated and the mapping precision is optimized accordingly; the control instruction is extracted to generate a real-time code stream, and the low delay path is determined for issuance; finally, the beam pointing is calibrated and the confirmation signal is obtained, realizing the establishment of the Ka band digital phased array beam. Through the application, the problems of low data synchronization accuracy, concentrated computing load, inaccurate control code calibration and high transmission delay in traditional methods can be solved, the real-time performance and pointing accuracy of beam establishment are significantly improved, which is suitable for high dynamic scenes such as high-speed moving target tracking, and provides reliable support for Ka band high-precision systems in radar, communication and other fields, and ensures the stable performance in high frequency scenes.

[0126] Reference Figure 2 The second embodiment of the application provides a Ka band digital phased array beam establishment system based on FPGA, comprising:

[0127] The data synchronization acquisition module: through the azimuth angle and frequency information acquisition module, real-time input data is acquired from the dynamic target tracking environment, and a phase difference analysis and frequency synchronization technology is used for synchronization processing, and an azimuth angle and frequency corresponding synchronization data set is output;

[0128] The initial weight generation module: based on the synchronization data set, a parallel computing algorithm is used for array element phase estimation and amplitude parameter calibration, a multi-core processor is used for dividing parallel tasks and balancing the computing load, and an initial phase amplitude weight set is generated;

[0129] The complexity evaluation module: the calculation complexity of the initial phase amplitude weight set is evaluated, if the evaluation result exceeds the preset complexity threshold, the synchronization data set is divided through the data block parallelization mechanism, and a weight data subset is obtained;

[0130] The control code generation module: based on the weight data subset, through a synchronization transmission algorithm, amplitude and phase code sequence generation and data compression encoding are sequentially executed, and then mapped into an amplitude and phase control code sequence;

[0131] The precision conformity judgment module: whether the mapping precision of the amplitude and phase control code sequence meets the beam pointing calibration requirement is judged; if not, the amplitude and phase code sequence generation parameters are adjusted based on the weight data subset, and the amplitude and phase control code sequence is regenerated; if yes, the amplitude and phase control code sequence meeting the beam pointing calibration requirement is transmitted to the real-time code stream generation module;

[0132] The real-time code stream generation module: control instructions are extracted from the amplitude and phase control code sequence meeting the beam pointing calibration requirement through an array element chip interface, and the control instructions are processed by using a synchronous timing control technology, and a real-time code stream is generated and sent to an antenna array;

[0133] The low-delay path determination module: the delivery delay of the real-time code stream is detected, if the delivery delay is higher than a preset delay threshold, the transmission protocol optimization parameters are adjusted according to real-time feedback information, and a low-delay code stream distribution path is determined;

[0134] The beam verification confirmation module: the control instructions are sent to the array element chip along the low-delay code stream distribution path, the beam pointing is calibrated and verified, and after the verification is passed, a final confirmation signal of beam establishment is acquired.

[0135] It should be noted that the FPGA-based Ka-band digital phased array beam establishment system provided by the embodiment of the application is used to execute all flow steps of the FPGA-based Ka-band digital phased array beam establishment method of the above-mentioned embodiment, and the working principles and beneficial effects of the two are one-to-one corresponding, thus it is not repeated.

[0136] The above-described specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above-described specific embodiments are merely examples of the present application and are not intended to limit the protection scope of the present application. It is particularly pointed out that any modification, equivalent replacement, improvement, etc. made by those skilled in the art within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for establishing a Ka-band digital phased array beam based on FPGA, characterized in that, The method comprises the following steps: Real-time input data is acquired from a dynamic target tracking environment by an azimuth and frequency information acquisition module, and a phase difference analysis and frequency synchronization technology is used for synchronous processing, and a synchronous data set corresponding to the azimuth and frequency is output; Based on the synchronous data set, a parallel computing algorithm is used for array element phase estimation and amplitude parameter calibration, a multi-core processor is used to divide parallel tasks and balance the computing load, and an initial phase amplitude weight set is generated; The computing complexity of the initial phase amplitude weight set is evaluated, and if the evaluation result exceeds a preset complexity threshold, the synchronous data set is divided by a data block parallelization mechanism to obtain a weight data subset, which specifically includes: based on the number of array elements, parameter dimensions and operation amount characteristics of the initial phase amplitude weight set, a computing complexity evaluation model is constructed, and the complexity evaluation result is obtained by quantitatively evaluating the operation time consumption, resource occupation rate and parallel processing feasibility; The complexity evaluation result is compared with the preset complexity threshold, and if it is not exceeded, the initial weight set is used, and if it is exceeded, the data block parallelization segmentation process is started; wherein, the preset complexity threshold is set according to the system real-time requirement and the maximum parallel processing capability of the multi-core processor; Based on the azimuth and frequency data correlation characteristics of the synchronous data set, the data block parallelization mechanism is used for segmentation, and each independent data block is divided into groups according to the array elements, each independent data block contains complete azimuth and frequency information of the corresponding group of array elements, and the computing complexity is lower than the preset complexity threshold; Each data block is mapped to the corresponding array element parameter in the initial weight set to generate a matched weight data segment, and an optimized weight data subset is obtained by summarizing; Based on the weight data subset, the amplitude and phase code sequence generation and data compression encoding are sequentially executed by a synchronous transmission algorithm, and then mapped into an amplitude and phase control code sequence; It is judged whether the mapping accuracy of the amplitude and phase control code sequence meets the beam pointing calibration requirement or not; If not, the amplitude and phase code sequence generation parameters are adjusted based on the weight data subset, and the amplitude and phase control code sequence is regenerated; If yes, control instructions are extracted from the amplitude and phase control code sequence that meets the beam pointing calibration requirement through an array element chip interface, and the control instructions are processed by a synchronous timing control technology to generate real-time code streams that are sent to the antenna array. Detect the delivery delay of the real-time code stream, and if the delivery delay is higher than a preset delay threshold, adjust the transmission protocol optimization parameters according to real-time feedback information, and determine a low-delay code stream distribution path, specifically including: calculating the real-time code stream transmission time difference based on the real-time code stream transmission time sequence mark and the array element chip receiving timestamp, and collecting the delay detection results; comparing the delay detection results with the preset delay threshold, if not exceeding, the current path is used, if exceeding, the transmission protocol optimization process is triggered; wherein the preset delay threshold is set according to the antenna array surface beam pointing response speed requirement; based on the delay node distribution and transmission bottleneck in the real-time feedback information, the transmission protocol optimization parameters are adjusted, the data frame length is adjusted, the retransmission mechanism is optimized, and the bandwidth is dynamically allocated to balance the path load; according to the adjusted transmission protocol optimization parameters, the delay of the candidate code stream distribution path is simulated and evaluated, the path with the lowest delay and the stability up to the standard is screened, and the code stream distribution path is determined; The control instruction is delivered to the array element chip along the low-delay code stream distribution path to calibrate and verify the beam pointing, and after the verification is passed, the final confirmation signal of the beam establishment is obtained.

2. The FPGA-based Ka-band digital phased array beam establishing method according to claim 1, characterized in that, The real-time input data is obtained from the dynamic target tracking environment by the azimuth and frequency information acquisition module, and the synchronous processing is performed by using the phase difference analysis and frequency synchronization technology, and the synchronous data set corresponding to the azimuth and frequency is output, including: The real-time azimuth signal and frequency signal of the dynamic target are synchronously captured by the azimuth and frequency information acquisition module to generate the original azimuth signal and the original frequency signal; Based on the original azimuth signal and the original frequency signal, the noise interference is removed and the effective signal is extracted to obtain the processed azimuth effective signal and the frequency effective signal; Based on the azimuth effective signal and the frequency effective signal, the time reference of the azimuth signal is calibrated by using the phase difference analysis technology, and the sampling time of the frequency signal is adjusted by using the frequency synchronization technology to form a preliminary synchronous data set; Based on the preliminary synchronous data set, the time deviation is checked, if the deviation meets the preset deviation accuracy, the synchronous data set is output, if not, the time alignment of the azimuth and frequency signals is recalibrated based on the deviation until the preset deviation accuracy is met; The effective signal refers to the signal part reflecting the azimuth characteristics and frequency characteristics of the dynamic target.

3. The FPGA-based Ka-band digital phased array beam establishing method according to claim 1, characterized in that, Based on the synchronous data set, the array element phase estimation and amplitude parameter calibration are performed by using the parallel computing algorithm, the multi-core processor is used to divide the parallel tasks and balance the computing load to generate an initial phase amplitude weight set, including: Based on the azimuth and frequency information of the synchronous data set and the array distribution characteristics, the array element phase estimation and amplitude calibration tasks are decomposed into subtasks by the multi-core processor, and the array element parameter calculation of each subtask corresponding to a specific region is performed to obtain a subtask list; Based on the subtask list, each subtask is calculated in parallel, the phase difference value of the array element is derived based on the azimuth information to determine the phase parameter, and the amplitude parameter is determined by combining the frequency characteristics to correct the amplitude attenuation of the array element signal to obtain the local phase amplitude parameter corresponding to each subtask. According to the progress of each subtask, the multi-core processor dynamically adjusts the load, splits the lagging subtasks to the idle cores for acceleration, and combines the advanced subtasks to obtain the local phase and amplitude parameters after load balancing; The local phase and amplitude parameters after load balancing are summarized, and after array synergy verification, an initial phase and amplitude weight set covering all array elements is generated.

4. The FPGA-based Ka-band digital phased array beam establishing method according to claim 1, characterized in that, Based on the weight data subset, the amplitude and phase code sequence generation and data compression coding are sequentially executed by a synchronous transmission algorithm, and then mapped into an amplitude and phase control code sequence, including: Based on the array element phase and amplitude parameters in the optimized weight data subset, the phase code and amplitude code are converted according to the array element chip amplitude and phase control protocol, and the amplitude and phase code sequence is formed by combining the array element numbers; The data redundancy characteristics of the amplitude and phase code sequence are analyzed, a compression coding strategy based on code type redundancy is adopted to remove repeated code segments and retain key indexes, and the compressed amplitude and phase code sequence is obtained to reduce the transmission amount; According to the timing constraints of the synchronous transmission algorithm, the compressed amplitude and phase code sequence is parsed into phase and amplitude control codes for array element recognition, the time reference of each array element control code is ensured to be consistent through synchronous markers, and the amplitude and phase control code sequence is mapped.

5. The FPGA-based Ka-band digital phased array beam establishing method according to claim 1, characterized in that, The amplitude and phase code sequence generation parameters are adjusted based on the weight data subset, and a new amplitude and phase control code sequence is generated, including: The error sources of the previous amplitude and phase control code sequence mapping accuracy not meeting the standard are analyzed, the array element phase and amplitude parameter deviations in the weight data subset are combined to determine the amplitude and phase code generation key parameters that need to be adjusted; wherein the amplitude and phase code generation key parameters include the phase conversion coefficient, the amplitude calibration factor and the synchronous marker time interval; According to the error analysis result, the phase conversion coefficient is linearly corrected according to the deviation amount between the theoretical value and the actual value of the phase code, a dynamic compensation amount is introduced to the amplitude calibration factor according to the amplitude code error compensation requirement, and the synchronous marker time interval in the amplitude and phase code generation key parameters is fine-tuned according to the timing consistency requirement of each array element control code; Based on the adjusted amplitude and phase code generation key parameters, the array element phase and amplitude parameters are extracted from the weight data subset again, the amplitude and phase code sequence combination, data compression coding and instruction format mapping are sequentially executed, and a new amplitude and phase control code sequence is generated.

6. The FPGA-based Ka-band digital phased array beam establishing method according to claim 1, characterized in that, The control instructions are extracted from the amplitude and phase control code sequence that meets the beam pointing calibration requirements through the array element chip interface, and the control instructions are processed by using the synchronous timing control technology to generate a real-time code stream that is sent to the antenna array, including: According to the instruction analysis protocol of the array element chip interface, the phase control instructions and the amplitude control instructions corresponding to each array element are extracted from the amplitude and phase control code sequence, the correspondence between the instructions and the array elements is established according to the array element number, and an initial control instruction set is formed; Based on the reference clock of the synchronous timing control technology, the timing of each instruction in the initial control instruction set is calibrated, the execution time markers of the instructions are unified, and a timing-aligned control instruction set is obtained; The timing-aligned control instruction set is packaged according to the transmission format of the antenna array, frame header verification information and transmission identifiers are added, and a real-time code stream that is sent to the antenna array is generated.

7. The FPGA-based Ka-band digital phased array beam establishing method according to claim 1, characterized in that, The control instruction is issued to the array element chip along the low-delay code stream distribution path, the beam pointing is calibrated and verified, and after the verification is passed, a final confirmation signal of beam establishment is obtained, including: Along the low-delay code stream distribution path, the control instruction is issued in batches according to the array element receiving time sequence, and through a synchronous transmission mechanism, each array element receives and executes at the same time to drive the antenna array to form an initial beam; Based on the target tracking environment feedback signal, the actual pointing information of the initial beam is collected, the deviation is compared and analyzed with the preset target azimuth angle, and the preliminary calibration verification is completed; If the deviation is within the preset allowable range, the verification is passed, and a final confirmation signal of beam establishment is generated; if the deviation is out of range, the control instruction is adjusted according to the deviation, and the verification is reissued along the low-delay path until the final confirmation signal is obtained after meeting the requirements.

8. A FPGA-based Ka-band digital phased array beam building system, characterized in that, Including: Data synchronous acquisition module: real-time input data is obtained from the dynamic target tracking environment through the azimuth angle and frequency information acquisition module, and synchronous processing is performed using phase difference analysis and frequency synchronization technology, and synchronous data set corresponding to the azimuth angle and frequency is output; Initial weight generation module: based on the synchronous data set, array phase estimation and amplitude parameter calibration are performed using a parallel computing algorithm, the multi-core processor is used to divide parallel tasks and balance the computing load, and an initial phase amplitude weight set is generated; Complexity evaluation module: the calculation complexity of the initial phase amplitude weight set is evaluated, if the evaluation result exceeds the preset complexity threshold, the synchronous data set is divided into weight data subsets through data block parallelization mechanism, including: based on the array element number, parameter dimension and operation amount characteristics of the initial phase amplitude weight set, a calculation complexity evaluation model is constructed, the operation time consumption, resource occupation rate and parallel processing feasibility are quantitatively evaluated, and the complexity evaluation result is obtained; the complexity evaluation result is compared with the preset complexity threshold, if it is not exceeded, the initial weight set is used, if it is exceeded, the data block parallelization segmentation process is started; wherein, the preset complexity threshold is set according to the system real-time requirement and the maximum parallel processing capacity of the multi-core processor; based on the azimuth angle and frequency data correlation characteristics of the synchronous data set, the data block parallelization mechanism is used for segmentation, and each independent data block is divided into groups according to the array element, each independent data block contains complete azimuth angle and frequency information of the corresponding group of array elements, and the calculation complexity is lower than the preset complexity threshold; the data blocks are mapped to the corresponding array element parameters in the initial weight set to generate matched weight data segments, and the optimized weight data subsets are obtained by summarizing; Control code generation module: based on the weight data subset, the amplitude and phase code sequence generation and data compression coding are sequentially executed through the synchronous transmission algorithm, and then mapped into the amplitude and phase control code sequence; Accuracy compliance judgment module: judge whether the mapping accuracy of the amplitude and phase control code sequence meets the beam pointing calibration requirement; if not, adjust the amplitude and phase code sequence generation parameters based on the weight data subset, and regenerate the amplitude and phase control code sequence; if yes, the amplitude and phase control code sequence meeting the beam pointing calibration requirement is transmitted to the real-time code stream generation module; The real-time code stream generation module extracts control instructions from the amplitude and phase control code sequence meeting the beam pointing calibration requirements through the array element chip interface, and processes the control instructions using a synchronous timing control technology to generate real-time code streams that are sent to the antenna array surface; The low-delay path determination module detects the sending delay of the real-time code stream, and if the sending delay is higher than a preset delay threshold, adjusts the transmission protocol optimization parameters according to real-time feedback information, and determines a low-delay code stream distribution path, specifically including: calculating the real-time code stream transmission time difference according to the real-time code stream transmission time sequence mark and the array element chip receiving timestamp, and collecting the delay detection results; comparing the delay detection results with the preset delay threshold, and if the delay detection results do not exceed the preset delay threshold, the current path is used, and if the delay detection results exceed the preset delay threshold, the transmission protocol optimization process is triggered; wherein the preset delay threshold is set according to the beam pointing response speed requirement of the antenna array surface; based on the delay node distribution and transmission bottleneck in the real-time feedback information, the transmission protocol optimization parameters are adjusted, the data frame length is adjusted, the retransmission mechanism is optimized, and the bandwidth is dynamically allocated to balance the path load; according to the adjusted transmission protocol optimization parameters, the delay of the candidate code stream distribution path is simulated and evaluated, the path with the lowest delay and the best stability is selected, and the code stream distribution path is determined; The beam verification confirmation module sends the control instructions to the array element chip along the low-delay code stream distribution path, calibrates and verifies the beam pointing, and after the verification is passed, the final confirmation signal of the beam establishment is obtained.

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