Detection feedback module, image signal processing chip, board card and electronic equipment

Abstract

The invention provides a detection feedback module, an image signal processing chip, a board card and electronic equipment. The image signal processing chip comprises an image signal processing module, a processor main control module and a detection feedback module; the image signal processing module carries out image signal processing on image data signals in the input image signals; and the processor main control module determines an image signal processing result to be output according to the time sequence detection result output by the comprehensive judgment feedback sub-module. The detection feedback module comprises a time sequence detection feedback sub-module and a comprehensive judgment feedback sub-module; a time sequence detection feedback sub-module detects a time sequence synchronization signal carried in the image signal to obtain a time sequence detection mark; the comprehensive judgment feedback sub-module determines a time sequence detection result according to the time sequence detection mark; the error detection of the function of the image signal processing module can be carried out in a time sequence detection mode, and the design of the universal detection feedback module can accelerate the tape-out debugging process.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and more particularly to a detection feedback module, an image signal processing chip, a circuit board, and electronic equipment. Background Technology

[0002] For Image Signal Processing (ISP) chip development, when designing the Image Signal Processing Pipeline (ISP Pipeline) module, it is necessary not only to implement the basic functional design but also to consider advanced development aspects, including error detection and early warning for module functions. This helps to accelerate the subsequent verification and simulation process and the tape-out and debugging process, thereby shortening the overall chip development cycle and reducing chip development costs.

[0003] For error detection in module functionality, the common approach is to select key control signals, data signals, or error-prone areas in the design to generate module interrupt signals, which are then fed back to the ISP system so that the system can obtain the module's operating status. This technique is a unique error detection method. Its uniqueness lies in the fact that different designs are required to implement error detection for modules with different functions, and each module needs to be developed independently. This leads to problems such as long development cycles and low error detection efficiency.

[0004] Specifically, for error detection of module functions, existing technologies typically employ the following methods: based on the module's specific function, select empty / full signals from a FIFO (First In First Out) system, state machine status signals, counter signals, etc., to form a module interrupt signal, which is then fed back to the ISP system. This allows the system to obtain the module's operating status and determine whether the module's function has malfunctioned. This unique error detection method requires different design and development for modules with different functions, resulting in a significant time consumption.

[0005] This section is intended to provide background or context for the embodiments of the invention set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention

[0006] To address the problems in the prior art, this application provides a detection feedback module, an image signal processing chip, a circuit board, and an electronic device, which can detect errors in the function of the image signal processing module through timing detection. This general-purpose detection feedback module design can accelerate the tape-out and debugging process.

[0007] To solve the above-mentioned technical problems, this application provides the following technical solution:

[0008] In a first aspect, this application provides a detection feedback module applied to an image signal processing chip, comprising:

[0009] Timing detection feedback submodule and comprehensive judgment feedback submodule;

[0010] The timing detection feedback submodule detects the timing synchronization signal carried in the image signal to obtain the timing detection flag.

[0011] The comprehensive judgment feedback submodule determines the timing detection result based on the timing detection flag; wherein, the timing detection result is used to indicate whether the image signal processing result of the corresponding image signal is correct.

[0012] Furthermore, the detection feedback module includes multiple timing detection feedback sub-modules; each timing detection feedback sub-module corresponds to an image signal processing sub-module in the image signal processing chip; and the image signal processing sub-modules are connected in a pipeline manner.

[0013] Each of the aforementioned timing detection feedback submodules detects the timing synchronization signal carried in the image signal processed by the corresponding image signal processing submodule;

[0014] The comprehensive judgment feedback submodule determines the timing detection result corresponding to each frame based on the timing detection flags of the same frame.

[0015] Furthermore, the timing detection feedback submodule performs vertical synchronization width detection, vertical trailing edge detection, effective polarity detection, and vertical leading edge detection on the timing synchronization signal carried in the image signal.

[0016] Furthermore, during the vertical synchronization width detection stage, the timing detection feedback submodule detects the vertical synchronization signal, horizontal synchronization signal, and effective polarity signal in the timing synchronization signal;

[0017] If a falling edge of the vertical synchronization signal is detected, the system enters the vertical synchronization width detection state and determines that a fault has occurred before the vertical synchronization signal is detected.

[0018] If a rising edge of the valid polarity signal is detected, the system enters an idle state and determines that a fault has occurred before the valid polarity signal is detected.

[0019] If the rising edge of the vertical synchronization signal is detected and the duration of the horizontal synchronization signal does not meet the preset duration requirement, the system enters the idle state and determines that a fault has occurred due to insufficient duration of the vertical synchronization signal.

[0020] If a falling edge of the horizontal synchronization signal is detected, and the duration between adjacent horizontal synchronization signals does not meet the preset duration requirement, the system enters the idle state and determines that a fault of insufficient interval time of the horizontal synchronization signal has occurred.

[0021] Furthermore, in the vertical trailing edge detection stage, the timing detection feedback submodule detects the vertical synchronization signal, horizontal synchronization signal, and effective polarity signal in the timing synchronization signal;

[0022] If a falling edge of the vertical synchronization signal is detected, the system enters the vertical synchronization width detection state and determines that a fault has occurred before the vertical synchronization signal is detected.

[0023] If the rising edge of the valid polarity signal is detected and the duration of the horizontal synchronization signal does not meet the preset duration requirement, then the system enters an idle state and determines that a fault has occurred before the valid polarity signal is detected.

[0024] If a falling edge of the horizontal synchronization signal is detected, and the duration period between adjacent horizontal synchronization signals does not meet the preset duration requirement, and the duration of the horizontal synchronization signal does not meet the preset duration requirement, then the system enters the idle state, and it is determined that a fault of insufficient interval time of the horizontal synchronization signal has occurred.

[0025] Furthermore, in the effective polarity detection stage, the timing detection feedback submodule detects the vertical synchronization signal, horizontal synchronization signal, and effective polarity signal in the timing synchronization signal;

[0026] If a falling edge of the vertical synchronization signal is detected, the system enters the vertical synchronization width detection state and determines that a fault has occurred before the vertical synchronization signal is detected.

[0027] If a rising edge of the valid polarity signal is detected, and the duration of the valid polarity signal is not equal to the duration corresponding to the image width, then the system enters an idle state and determines that a discontinuity fault of the valid polarity signal has occurred.

[0028] If the rising edge of the valid polarity signal is detected, and the rising edge of the horizontal synchronization signal is detected, the system enters the idle state and determines that a fault of insufficient horizontal trailing edge duration has occurred.

[0029] If a falling edge of the horizontal synchronization signal is detected, and a falling edge of the valid polarity signal is detected, the system enters the idle state and determines that a fault of insufficient duration of the horizontal leading edge has occurred.

[0030] If a falling edge of the horizontal synchronization signal is detected, and the duration between adjacent horizontal synchronization signals does not meet the preset duration requirement, and the number of horizontal synchronization signals is not equal to the image width, then the system enters the idle state and determines that either the horizontal synchronization signal interval time is insufficient or the effective polarity signal duration is insufficient.

[0031] Furthermore, in the vertical leading edge detection stage, the timing detection feedback submodule detects the vertical synchronization signal, horizontal synchronization signal, and effective polarity signal in the timing synchronization signal;

[0032] If the rising edge of the vertical synchronization signal is detected, the system enters the vertical synchronization width detection state and determines that a fault has occurred before the vertical synchronization signal is detected.

[0033] If the rising edge of the valid polarity signal or the duration between adjacent horizontal synchronization signals is not equal to the duration corresponding to the image width, the system enters an idle state and determines that a fault has occurred due to insufficient duration of the vertical leading edge.

[0034] Secondly, this application provides an image signal processing chip, including: an image signal processing module, a processor main control module, and the detection feedback module;

[0035] The image signal processing module performs image signal processing on the image data signal in the input image signal;

[0036] The processor main control module determines the image signal processing result to be output based on the timing detection result output by the comprehensive judgment feedback submodule.

[0037] Furthermore, the image signal processing chip further includes: a frame buffer module, used to buffer the correct image signal processing result output by the last stage image signal processing submodule in the pipeline; if the processor main control module determines that the image signal processing result of the image signal is incorrect based on the timing detection result, it outputs the image signal processing result at a preset time from the frame buffer module.

[0038] Furthermore, if the processor main control module determines that the image signal processing result of the image signal is incorrect based on the timing detection result, it determines to output the image signal processing result of the specified image signal processing submodule for that frame of image signal.

[0039] Thirdly, this application provides a board card including the aforementioned chip.

[0040] Fourthly, this application provides an electronic device including the aforementioned board.

[0041] To address the problems in existing technologies, the detection feedback module provided in this application is applicable to all image signal processor systems that use timing synchronization signals. Compared to traditional uniqueness detection methods, the detection feedback module, image signal processing chip, board, and electronic equipment provided in this application can use the same structural design when detecting different image signal processor systems, resulting in shorter chip development time. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a diagram showing the internal structure of the image signal processing chip and its connection to external devices in an embodiment of this application.

[0044] Figure 2 This is a schematic diagram illustrating the conditions that the timing synchronization signal must meet in the embodiments of this application;

[0045] Figure 3 This is a schematic diagram of the workflow of the detection feedback module in an embodiment of this application;

[0046] Figure 4 This is a schematic diagram of the detection status of the detection feedback module in an embodiment of this application;

[0047] Figure 5 This is a schematic diagram of the workflow of the output signal selection module in the embodiments of this application. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and descriptions of the present invention are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. The acquisition, storage, use, and processing of data in the technical solutions of this application all comply with the relevant provisions of laws and regulations. The user information in the embodiments of this application is obtained through legal and compliant means, and the acquisition, storage, use, and processing of user information have been authorized and agreed upon by the customer.

[0049] To facilitate understanding of the technical solution provided in this application, the relevant content of the technical solution in this application will be explained below.

[0050] For ISP chip development, when designing the ISP Pipeline module, it is necessary to consider the ISP chip's operation during debugging and after delivery, and to perform error detection on the image signal processing module within the ISP chip. Therefore, a functional error detection component needs to be designed when designing the ISP Pipeline module. Existing functional error detection modules are generally developed separately for image signal processing modules with different functions, resulting in long development cycles and low error detection efficiency.

[0051] To address the aforementioned issues, this application proposes an error detection method applicable to image signal processing modules with various functions. This error detection method performs functional testing on the image signal processing module based on timing synchronization signals. Since timing synchronization signals are critical control signals for data signals, they are independent of the module's actual functions (e.g., sharpening filtering, edge detection) and all conform to a unified official standard protocol, making them universal signals across various modules within the chip. Therefore, this error detection method can be used for image signal processing modules with various functions, resulting in a short development cycle and good detection performance.

[0052] In one embodiment, see Figure 1 In order to enable error detection of the image signal processing module function through timing detection and accelerate the tape-out debugging process, this application provides an image signal processing chip, including: an image signal processing module, a processor main control module, a detection feedback module and a frame buffer module;

[0053] The image signal processing module acquires the original image signal and performs image signal processing on the image data signal in the original image signal to obtain multi-frame processed images;

[0054] The detection feedback module detects the timing synchronization signal in the raw image signal received from the image signal processing module according to the detection start command of the processor main control module, and obtains the timing detection result;

[0055] The processor main control module queries the multi-frame processing images for the frame processing image with the correct timing based on the timing detection results, and outputs the query frame processing image; if no frame processing image with the correct timing is found, the control frame buffer module outputs the frame processing image at the preset time.

[0056] The detection feedback module includes a timing detection feedback submodule and a comprehensive judgment feedback submodule. Each timing detection feedback submodule sequentially performs vertical synchronization width detection, vertical trailing edge detection, effective polarity detection, and vertical leading edge detection on the received timing synchronization signal to obtain the timing detection flag corresponding to each timing detection feedback submodule. The comprehensive judgment feedback submodule performs logical judgment on each timing detection flag to obtain the timing detection result.

[0057] The frame buffer module is used to buffer the frame processing image at a preset time, and output the frame processing image at the preset time when it receives the image output signal from the processor main control module.

[0058] In one embodiment, the image signal processing module includes multiple image signal processing sub-modules. Figure 1 These are denoted as module 1 through module N, respectively. The detection feedback module includes multiple timing detection feedback sub-modules; each timing detection feedback sub-module detects the timing synchronization signal received from the corresponding image signal processing sub-module to obtain the corresponding timing detection flag.

[0059] It is understood that this application provides a detection feedback module and an image signal processing chip including the detection feedback module, applicable to all image signal processing systems that use timing synchronization signals. It solves the problem of quickly troubleshooting errors in image signal processing systems. The embodiments of this application fully consider the flexibility, independence, and resource consumption of chip design.

[0060] In the actual design and development of chips, timing synchronization signals, such as vsync and hsync, are used in each module of the image signal processing pipeline. These timing synchronization signals are key control signals for data signals; they are independent of the module's own function and all conform to a unified official standard protocol, making them universal signals across all modules within the chip. However, the timing synchronization signals of the image signal processing system's transmission interface are highly susceptible to environmental interference and errors. Once an error occurs, the output data connected to the image signal processing system will also be incorrect, inevitably leading to display problems on the terminal device. Based on these two characteristics, a universal detection method can be adopted: by judging the correctness of these universal signals, such as timing synchronization signals, the cause of data errors in the image signal processing system can be investigated, and the correctness of image output can be ensured through timely responses within the chip.

[0061] In practical implementation, firstly, the chip internally employs a state machine mechanism, specifically a finite state machine (FSM, referred to as "state machine" in the embodiments of this application). This allows for flexible detection of any timing error and provides feedback on the error type (including error type 1 to error type 10 below), facilitating subsequent upgrades and functional expansion. The "feedback of error type" can be implemented by the detection feedback module within the image signal processing chip. If necessary, the detection feedback module can feed back the error type to the processor's main control module, which then directly feeds it back to the external display device. When the detection feedback module detects a timing synchronization signal error in a certain image signal processing submodule within the image signal processing module, it generates a corresponding flag. The flag can include the specific sequence number of the image signal processing submodule and the corresponding error type.

[0062] It should be noted that, in one embodiment, the timing detection flag may include multiple flag bits, each carrying an indicator of whether the image processing result is correct or incorrect, and the sequence number of the image signal processing submodule corresponding to that correct / incorrect indicator. In another embodiment, the timing detection flag only includes an indicator of whether the image processing result is correct or incorrect. A queue (which may be in hardware form, a register) is provided between each timing detection feedback submodule and the comprehensive feedback submodule. The depth of the queue is at least N (the number of modules) - 1. The comprehensive feedback submodule determines which image signal processing submodule the timing detection flag corresponds to based on its position in the queue; furthermore, image frame identification can be achieved using queue pointers.

[0063] For the latter embodiment, a specific example is as follows: Each timing detection feedback submodule corresponds to an N-bit register, and the timing detection flags output by the timing detection feedback submodule are stored in the register sequentially. For example, the timing detection flag of frame 0 is stored in the 0th bit of the register, and so on. Then, the flag bits at the same position in each register can be selected to form an N-bit one-dimensional array, which is then input to the comprehensive judgment feedback submodule. The comprehensive feedback submodule can then output the timing detection results according to a fixed clock cycle (for example, if the processing latency of the pipeline is 100 frames, then the comprehensive feedback submodule outputs the timing detection results every 100 frames), ensuring that the timing of the output timing detection results is consistent with the timing of the output by the image processing module.

[0064] Based on this, if error localization is required, each timing detection feedback module also has a corresponding register to store the error type. After the comprehensive judgment feedback submodule locates the image processing submodule with the error based on the input one-dimensional array, it reads the error type from the corresponding register. The error type in this register is deleted each time it is read, or overwritten the next time it is written.

[0065] Secondly, based on the relationship of timing synchronization signals, the detection process is divided into stages to cover all error scenarios. Furthermore, parameterized configuration allows for flexible adjustment of the detection feedback module to suit different timing requirements. Finally, the frame buffer of the image signal processing system is reused; when a timing synchronization signal error is detected, the image in the frame buffer is selected for display, reducing the probability of display errors on the terminal device. The chip and corresponding timing detection method provided in this application are independent of the specific functions of the image signal processing module. That is, for image signal processing modules with different specific functions, this chip and its corresponding detection method are flexible, independent, and universal. Further expansion is easily possible if additional upgrades are needed later. Moreover, using the same development methods for multiple modules in the image signal processing system results in a short development cycle, fast error localization, and low area resource consumption, effectively shortening chip development time and having significant practical value for enhancing the overall performance of the image signal processing system.

[0066] See Figure 1 As shown, the architecture of the image signal processing chip provided in this application includes: a detection feedback module, an image signal processing module, a processor main control module (Central Processing Unit, or CPU), an input / output interface module (including input / output interfaces), an image signal processing module (providing image signal processing functions), and a frame buffer module. Specifically, the raw image signal (including data signals and timing synchronization signals) enters the image signal processing module (which can be understood as the image signal processing functional module) through the input interface in the input / output interface module. Then, the image signal processing module performs functional processing (e.g., sharpening filtering, edge detection) on the data signals in the raw image signal, that is, using... Figure 1 Modules 1 through N perform various algorithmic processing. Modules 1 through N are all image signal processing sub-modules.

[0067] Meanwhile, each module in the image signal processing module can be connected to a timing detection feedback submodule. In one embodiment, each timing detection feedback submodule in the detection feedback module outputs a timing error flag error_dvp_flag (e.g., but not limited to, 0 representing correct timing or 1 representing timing error); where error_dvp_flag 1 ~ error_dvp_flag N correspond one-to-one with module 1 ~ module N. When any error_dvp_flag is 1, it can be uniquely determined which module has a timing error, so that the comprehensive judgment feedback submodule can perform a comprehensive judgment on the timing error flags error_dvp_flag1 ~ error_dvp_flag N, and feed back the comprehensive judgment result (i.e., the timing detection result) to the processor main control module through the bus.

[0068] Specifically, as mentioned above, error_dvp_flag 1 ~ error_dvp_flag N are the timing error flags for modules 1 to N, respectively. Each timing error flag is generated by its corresponding timing detection feedback submodule. That is, each timing error flag is the timing detection output result of the corresponding image signal processing submodule for each timing detection feedback submodule. The comprehensive judgment feedback submodule can obtain the "timing detection output (i.e., error_dvp_flag)" corresponding to each timing detection feedback submodule, and then perform comprehensive judgment to obtain the comprehensive judgment result (timing detection result). The comprehensive judgment result (timing detection result) can be: the sequence number of the image signal processing submodule where the timing synchronization signal error occurred, i.e., module X (X∈[1,N]).

[0069] The comprehensive judgment process is shown in Table 1.

[0070] Table 1. Explanation of Output Signal Selection (for the same frame)

[0071]

[0072] In case 1, `error_dvp_flag 1` is 1, indicating that the timing of module 1 is incorrect. In this situation, there is no need to check the timing of subsequent modules. This is because, in terms of timing, each module receives the image signal (including data signals and timing synchronization signals) processed by the previous module. If the timing of the previous module is incorrect, the timing of the subsequent module will inevitably be incorrect. Therefore, the overall judgment result (timing detection result) can be: module 1 has a timing error. Subsequently, the processor main control module will receive this overall judgment result (timing detection result) and generate an instruction. The instruction content is: output the frame processing image at a preset time in the "frame buffer module". Here, the preset time can refer to a frame processing image within a historical time period; this frame processing image should be generated under completely correct timing conditions.

[0073] In scenario 3, error_dvp_flag 1 is 0, error_dvp_flag 2 is 0, and error_dvp_flag 3 is 1. At this point, the overall judgment result (timing detection result) is: module 3 has a timing error. Subsequently, the processor main control module will receive this overall judgment result (timing detection result) and generate an instruction. The instruction content is: output the frame processing image at a preset time in the "frame buffer module," or output the frame processing image processed by module 2 with correct timing. The preset time can refer to a frame processing image within a historical time period, which should be generated under completely correct timing conditions.

[0074] It should be noted that if there are N modules in total, and the timing of module N is incorrect while the timing of modules 1 to N-1 is correct, then the processor main control module can select any one of modules 1 to N-1 and issue an instruction to output the frame processing image of that module.

[0075] It should also be noted that, see Figure 5 The final output signal of the image signal processing chip provided in this application includes at least two cases:

[0076] First, the image signal processing chip is in a normal operating phase after debugging. This phase must ensure that the display can display normally. When a timing error occurs in the image signal processing submodule, the final output signal can be the previous correct frame image signal extracted from the frame buffer module, or it can be the image signal processing result output by the previous image signal processing submodule (e.g., module 2) of the image signal processing submodule (e.g., module 3) in the pipeline that has a timing error.

[0077] Second, the image signal processing chip is in the debugging stage. When a timing error occurs in the image signal processing submodule, the image signal processing result corresponding to the image signal processing submodule with the timing error in the image signal processing submodule pipeline can be output; or the image signal processing result of the target image signal processing submodule (generally the correct image signal processing result) can be output as needed; the error type and error location can also be output together.

[0078] It should also be noted that the output signal selection shown in Table 1 is for the same frame. As a pipeline, module 1 processes the 0th frame signal and then immediately processes the 1st frame signal, and so on. Therefore, while module 5 is processing the 0th frame signal, module 1 is already processing the 4th frame signal. Consequently, the timing detection flag of the 4th frame signal fed back by the timing detection feedback submodule corresponding to module 1 will precede the timing detection flag of the 1st frame signal fed back by the timing detection feedback submodule corresponding to module 5. At this point, a timing management mechanism is needed to ensure that the output is not out of order. This mechanism can be: each timing detection flag carries a frame identifier (which can be a frame number or a timestamp when the original image signal enters the timing detection module), and each module has a corresponding buffer to cache at least N-1 frames of signal processing results.

[0079] In summary, the processor main control module, based on the comprehensive judgment result of the detection feedback module, makes corresponding control actions to enable the chip to select a frame of image from module 1 to module N for output or to select the previous frame of image from the frame buffer module for output. Finally, the selected image (data) is output to the display device for display through the output interface in the input / output interface module. Thus, the chip and system provided in this application have completed the entire signal processing process of error detection, flag feedback, and terminal display. The chip and system provided in this application will be described in detail below.

[0080] As described above, the detection feedback module and image signal processing chip containing the detection feedback module provided in this application are applicable to all image signal processor systems that use timing synchronization signals. Compared with traditional uniqueness detection methods, the detection feedback module, image signal processing chip, board, and electronic equipment provided in this application can use the same structural design when detecting different image signal processor systems, resulting in shorter chip development time, faster fault location, and more timely response.

[0081] In one embodiment, see Figure 1The image signal processing chip also includes an output signal selection module, which is used to obtain a frame processing image at a preset time from the frame buffer module or to obtain a frame processing image with correct timing from the image signal processing module according to the image selection signal sent by the processor main control module.

[0082] Specifically, the output signal selection module is a module used for hard-wired selection among multiple output signal sources. Its core function is to achieve signal routing through physical circuit switching, ensuring that the correct frame processing image can be obtained from the corresponding module (frame buffer module or image signal processing submodule) according to the instructions (image selection signal) of the processor main control module, and then output to the display device for display.

[0083] In one embodiment, see Figure 1 The detection feedback module includes a comprehensive judgment feedback submodule, which generates timing detection results based on each timing detection flag and feeds the timing detection results back to the processor main control module.

[0084] Understandably, see Figure 2 According to the timing standards for display video interfaces, the correct timing of display video interfaces must meet the following conditions:

[0085] (1) The durations of vsw, vbp, and vfp simultaneously meet the requirements.

[0086] (2) The durations of hsw, hbp, and hfp simultaneously meet the requirements.

[0087] (3) The consecutive valid time = image width, and the number of valid rows = image height.

[0088] (4) The relationship between vsync, hsync, and valid meets the requirements (see the following explanation).

[0089] (5) The polarity of vsync, hsync, and valid all meet the requirements (see the following explanation).

[0090] exist Figure 2 In this context, vtotal represents the number of lines in a single frame; htotal represents the number of clock cycles in a single line; and the polarity of vsync and hsync can be either "active high" or "active low". The criterion for determining a timing synchronization signal error is: if any of the above five conditions is not met, the timing synchronization signal is considered faulty. See Table 2 for symbol explanations.

[0091] Table 2

[0092]

[0093] It should be noted that the timing described above is also known as DVP (Digital Video Port) timing, which is only one timing requirement and is merely an example. This application is also applicable to other timing requirements, which can be achieved simply by configuring the parameters.

[0094] In one embodiment, see Figure 3 and Figure 4 The timing detection feedback submodule performs vertical synchronization width detection, vertical trailing edge detection, effective polarity detection, and vertical leading edge detection on its respective timing synchronization signal in sequence.

[0095] It is understandable that the working process of the (timing) detection feedback module within the chip is described in [reference needed]. Figure 3 As shown.

[0096] Specifically, the vertical synchronization signal vsync, the horizontal synchronization signal hsync, the valid polarity signal valid, and an internal counter are used as the criteria for determining the state transitions of the state machine. See also Figure 4 As shown, the state machine has different transition cases for different timing situations, corresponding to different cases; based on the case, it is determined whether the state transition is normal or abnormal; if an abnormality occurs, the rising edge of error_dvp_flag will be detected.

[0097] Based on the relationship between vsync, hsync, and valid, the module in this embodiment adopts a state machine mechanism, dividing the detection process into four stages according to the sequential process of the vsync signal: vertical synchronization width detection vsw_check, vertical trailing edge detection vbp_check, valid polarity detection valid_check, and vertical leading edge detection vfp_check. (See [link to relevant documentation]). Figure 4 As shown.

[0098] The basis for this division is as follows: First, Vsync is a vertical synchronization signal. Generally, image signal processing requires frame reset, which means that the detection process and the processing process are based on frames and keep them synchronized. Second, Vsync is a signal in the DVP timing standard. Based on Vsync, it is applicable to all image processing systems and has universality and versatility.

[0099] See Figure 4Entering the idle state signifies the start of a new round of timing checks. Only a transition from the vfp_check state to the idle state indicates a possibility of a correct timing synchronization signal; transitions from any other state to the idle state indicate an error in the timing synchronization signal. The prerequisite for transitioning to the next state is that no timing error has occurred in that state. Otherwise, based on the actual logical judgment result, the current state transitions to the corresponding state (e.g., but not limited to, transitioning to the previous state). The "logical judgment" process is detailed below.

[0100] exist Figure 4 At each stage of the process, based on the judgment conditions, the specific error type can be determined. The main error types include the following:

[0101] Error type 1: vsync arrives early, not enough time (one frame);

[0102] Error type 2: Valid arrives prematurely, overlapping with vsync or hsync;

[0103] Error type 3: hsync interval time does not meet requirements;

[0104] Error type 4: The duration of the vsw does not meet the requirement;

[0105] Error type 5: VBP duration does not meet requirements;

[0106] Error type 6: VFP duration does not meet requirements;

[0107] Error type 7: hbp duration does not meet requirements;

[0108] Error type 8: HFP duration does not meet requirements;

[0109] Error type 9: Valid is discontinuous, with bubbles;

[0110] Error type 10: Valid continuous time requirement not met.

[0111] It should be noted that the specific duration of each signal can be flexibly configured according to timing requirements, which demonstrates that the embodiments of this application can configure the detection parameters in the timing detection stage. In specific implementation, this can be achieved by configuring the timeout of the corresponding timer: assuming the timing requirement is 100 clock cycles for vsw, then the timeout of the timer corresponding to vsw is 100 clock cycles.

[0112] The following details the specific error types that will occur under what conditions in the four stages mentioned above. Using vsync, hsync, and valid as examples, and levels 1-4 to represent the levels of the judgment conditions, the process proceeds as follows: first level 1 (first level); if level 1 is satisfied, level 2 (second level); if level 2 is satisfied, level 3 (third level); and if level 3 is satisfied, level 4 (fourth level). Levels 1-4 can be understood as a nested relationship in the program execution process.

[0113] In the embodiments of this application, see Figure 4 The state machine consists of five states: idle state, vertical synchronization width detection state (corresponding to the vsw_check stage), vertical trailing edge detection state (corresponding to the vbp_check stage), valid polarity detection state (corresponding to the valid_check stage), and vertical leading edge detection state (corresponding to the vfp_check stage). Each detection process starts from the idle state, and the subsequent state (i.e., which detection stage) is determined by the following judgment logic. When performing timing checks, it starts from the idle state, and then performs state transitions according to the instructions of the state machine.

[0114] In one embodiment, see Figure 3 and Figure 4 During the vertical synchronization width detection phase (vsw_check phase), the timing detection feedback submodule detects the vertical synchronization signal, horizontal synchronization signal, and effective polarity signal in the timing synchronization signal.

[0115] If a falling edge of the vertical synchronization signal is detected, the system enters the vertical synchronization width detection state and determines that a fault has occurred before the vertical synchronization signal is detected.

[0116] If a rising edge of a valid polarity signal is detected, the system enters an idle state and determines the valid polarity signal until a fault occurs.

[0117] If a rising edge of the vertical synchronization signal is detected, and the duration of the horizontal synchronization signal (in terms of the number of signals) does not meet the preset duration requirement, the system enters an idle state and determines that a fault of insufficient vertical synchronization signal duration has occurred.

[0118] If a falling edge of the horizontal synchronization signal is detected, and the duration of the period between adjacent horizontal synchronization signals (in terms of the number of cycles) does not meet the preset duration requirement, the system enters an idle state and determines that a fault of insufficient horizontal synchronization signal interval has occurred.

[0119] Understandably, the judgment logic in the vsw_check phase is as follows:

[0120] Level 1 - If a falling edge of the vsync signal is detected

[0121] Entering vsw_check state (error type 1)

[0122] Level 1 - If a valid signal rising edge is detected

[0123] Entering idle state (Error type 2)

[0124] Level 1 - If a rising edge of the vsync signal is detected

[0125] Level 2 - If the cnt_hs_vsw (the hsync count counter during the vsw phase) is detected to meet the vsw duration requirement.

[0126] Entering vbp_check state (normal timing, no errors)

[0127] Level 2 - Otherwise

[0128] Entering idle state (error type 4)

[0129] Level 1 - If a falling edge of the hsync signal is detected

[0130] Level 2 - If cnt_hotal (the number of duration cycles between adjacent hsyncs) meets the htotal duration requirement.

[0131] Maintain the vsw_check state (normal timing, no errors).

[0132] Level 2 - Otherwise

[0133] Entering idle state (error type 3)

[0134] In one embodiment, see Figure 3 and Figure 4 During the vertical trailing edge detection phase (vbp_check phase), the timing detection feedback submodule detects the vertical synchronization signal, horizontal synchronization signal, and effective polarity signal in the timing synchronization signal.

[0135] If a falling edge of the vertical synchronization signal is detected, the system enters the vertical synchronization width detection state and determines that a fault has occurred before the vertical synchronization signal is detected.

[0136] If a rising edge of a valid polarity signal is detected, and the duration of the horizontal synchronization signal (in terms of the number of signals) does not meet the preset duration requirement, the system enters an idle state and determines the period before a valid polarity signal occurs until a fault occurs.

[0137] If a falling edge of the horizontal synchronization signal is detected, and the duration period (in terms of the number of consecutive periods) between adjacent horizontal synchronization signals does not meet the preset duration requirement, and the duration of the horizontal synchronization signal (in terms of the number of signals) does not meet the preset duration requirement, then the system enters an idle state and determines that a fault of insufficient horizontal synchronization signal interval has occurred.

[0138] Understandably, the judgment logic in the vbp_check phase is as follows:

[0139] Level 1 - If a falling edge of the vsync signal is detected

[0140] Entering vsw_check state (error type 1)

[0141] Level 1 - If a valid rising edge is detected

[0142] Level 2 - If the cnt_hs_vbp (the hsync count counter for the vbp phase) is detected to meet the vbp duration requirement.

[0143] Entering the valid_check state (normal timing, no errors).

[0144] Level 2 - Otherwise

[0145] Entering idle state (Error type 2)

[0146] Level 1 - If a falling edge of the hsync signal is detected

[0147] Level 2 - If cnt_hotal (the number of duration cycles between adjacent hsyncs) meets the htotal duration requirement and cnt_hs_vbp >= 1

[0148] Maintain vbp_check status (normal timing, no errors).

[0149] Level 2 - Otherwise

[0150] Entering idle state (error type 3)

[0151] In one embodiment, see Figure 3 and Figure 4 During the valid polarity detection phase (valid_check phase), the timing detection feedback submodule detects the vertical synchronization signal, horizontal synchronization signal, and valid polarity signal in the timing synchronization signal;

[0152] If a falling edge of the vertical synchronization signal is detected, the system enters the vertical synchronization width detection state and determines that a fault has occurred before the vertical synchronization signal is detected.

[0153] If a rising edge of the valid polarity signal is detected, and the continuous duration of the valid polarity signal is not equal to the duration corresponding to the image width, then the system enters an idle state and determines that a fault of discontinuity of the valid polarity signal has occurred.

[0154] If a rising edge of a valid polarity signal is detected, and a rising edge of a horizontal synchronization signal is detected, the system enters an idle state and determines that a fault of insufficient horizontal trailing edge duration has occurred.

[0155] If a falling edge of the horizontal synchronization signal is detected, and a falling edge of the valid polarity signal is also detected, the system enters an idle state and determines that a fault has occurred due to insufficient duration of the horizontal leading edge.

[0156] If a falling edge of the horizontal sync signal is detected, and the duration period (in terms of the number of times) between adjacent horizontal sync signals does not meet the preset duration requirement, and the number of horizontal sync signals is not equal to the image width, then the system enters an idle state and determines that either the horizontal sync signal interval time is insufficient or the effective polarity signal duration is insufficient.

[0157] Understandably, the judgment logic in the valid_check phase is as follows:

[0158] Level 1 - If a falling edge of the vsync signal is detected

[0159] Entering vsw_check state (error type 1)

[0160] Level 1 - If a valid rising edge is detected

[0161] Level 2 - If cnt_clk_valid (number of consecutive valid periods) is not equal to the image width.

[0162] Entering idle state (Error type 9)

[0163] Level 2 - If a rising edge of the hsync signal is detected

[0164] Entering idle state (error type 7)

[0165] Level 1 - If a falling edge of the hsync signal is detected

[0166] Level 2 - If a valid falling edge is detected

[0167] Entering idle state (error type 8)

[0168] Level 2 - Otherwise

[0169] Level 3 - If cnt_hotal is detected to meet the htotal duration requirement and cnt_clk_valid is equal to the image width.

[0170] Level 4 - If cnt_hs_valid (the hsync count counter in the valid phase) = image height is detected

[0171] Entering the vfp_check state (normal timing, no errors).

[0172] Level 4 - Otherwise

[0173] Maintain valid_check status

[0174] Level 3 - Otherwise

[0175] Entering idle state (error type 3 or 10)

[0176] In one embodiment, see Figure 3 and Figure 4 During the vertical leading edge detection phase (vfp_check phase), the timing detection feedback submodule detects the vertical synchronization signal, horizontal synchronization signal, and effective polarity signal in the timing synchronization signal.

[0177] If the rising edge of the vertical synchronization signal is detected, the system enters the vertical synchronization width detection state and determines that a fault has occurred before the vertical synchronization signal is detected.

[0178] If the rising edge of a valid polarity signal or the duration (in terms of the number of cycles) between adjacent horizontal synchronization signals is not equal to the duration corresponding to the image width, the system enters an idle state and determines that a fault has occurred due to insufficient duration of the vertical leading edge.

[0179] Understandably, the judgment logic in the vfp_check phase is as follows:

[0180] Level 1 - If a rising edge of the vsync signal is detected

[0181] Entering vsw_check state (error type 1)

[0182] Level 1 - If a valid rising edge is detected or cnt_hotal is not equal to the image width.

[0183] Entering idle state (error type 6)

[0184] Level 1 - Otherwise

[0185] Maintain the vfp_check state (normal timing, no errors).

[0186] In one embodiment, this application provides an image signal processing chip system, including an image signal processing chip and a display device; the display device receives and displays the frame-processed image output by the image signal processing chip.

[0187] Understandably, see Figure 1 The display device is located outside the chip and is connected to the chip through the output interface in the input / output interface module.

[0188] As mentioned above, the comprehensive judgment result of the comprehensive judgment feedback submodule includes the module number where a timing error occurred. After the comprehensive judgment feedback submodule sends the "module number where a timing error occurred (e.g., module 3)" to the processor main control module, the processor main control module can determine the frame image to be output according to the logic shown in Table 2. See the foregoing for details.

[0189] It should also be noted that the detection feedback module and the image signal processing chip including the detection feedback module provided in this application can be applied, but are not limited to, to tape-out debugging scenarios. In tape-out debugging scenarios, if the timing of the frame image that module 3 should output is incorrect, the frame image output by module 1 or module 2 can be output for developers to use.

[0190] The specific implementation steps are as follows: First, the vsync and hsync signals are input into module 1 of the image signal processing system along with the data signal flow. Then, module 1 inputs the vsync and hsync signals into module 2, and so on. Module N-1 inputs the vsync and hsync signals into module N. Each sub-module performs timing detection separately and obtains error_dvp_flag. If the value is 1, it indicates that the timing synchronization signal in the corresponding module is faulty. Then, a comprehensive judgment is made based on the values ​​of error_dvp_flag 1~N, and the result is fed back to the processor main control module so that the processor main control module can select the image signal from a module that has not encountered an error or the previous frame image signal from the frame buffer module for output. For specific selection options, please refer to Table 1 (assuming N=3, x in the table represents 1 or 0). Taking case 1 as an example: if error_dvp_flag 1 is 1, it means that the timing synchronization signal of module 1 is faulty. Therefore, the image signal output by this module will definitely be faulty, the image signal input to subsequent modules will be faulty, and the output signal will also definitely be faulty. The value of error_dvp_flag 2 or error_dvp_flag 3 is irrelevant; the previous frame must be selected for output.

[0191] In one embodiment, this application provides a board card that includes a chip.

[0192] In one embodiment, an electronic device according to this application includes a circuit board.

[0193] In summary, for the entire image signal processing chip development cycle, the debugging process often takes longer than the design process. This application's embodiment incorporates a timing detection module into the ISP pipeline, effectively shortening chip development time while providing real-time timing status feedback. This allows for flexible selection of the image signal processing system's output, effectively reducing the probability of terminal display errors. In other words, it achieves such a significant technical effect with minimal area consumption, making it highly significant for image signal processing chip development.

[0194] Furthermore, the (timing) detection feedback module in this application is designed using a state machine mechanism in stages, offering both flexibility and versatility. Future upgrades can be easily implemented by adding additional detection functions, such as counter frame reset. It is convenient to use, eliminating concerns about module functionality and signal connection complexity.

[0195] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0196] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A detection feedback module, characterized in that, Applications in image signal processing chips include: Timing detection feedback submodule and comprehensive judgment feedback submodule; The timing detection feedback submodule detects the timing synchronization signal carried in the image signal to obtain the timing detection flag. The comprehensive judgment feedback submodule determines the timing detection result based on the timing detection flag; wherein, the timing detection result is used to indicate whether the image signal processing result of the corresponding image signal is correct.

2. The detection feedback module according to claim 1, characterized in that, The detection feedback module includes multiple timing detection feedback sub-modules; each timing detection feedback sub-module corresponds to an image signal processing sub-module in the image signal processing chip; the image signal processing sub-modules are connected in a pipeline manner. Each of the aforementioned timing detection feedback submodules detects the timing synchronization signal carried in the image signal processed by the corresponding image signal processing submodule; The comprehensive judgment feedback submodule determines the timing detection result corresponding to each frame based on the timing detection flags of the same frame.

3. The detection feedback module according to claim 1, characterized in that, The timing detection feedback submodule performs vertical synchronization width detection, vertical trailing edge detection, effective polarity detection, and vertical leading edge detection on the timing synchronization signal carried in the image signal.

4. The detection feedback module according to claim 3, characterized in that, During the vertical synchronization width detection stage, the timing detection feedback submodule detects the vertical synchronization signal, horizontal synchronization signal, and effective polarity signal in the timing synchronization signal. If a falling edge of the vertical synchronization signal is detected, the system enters the vertical synchronization width detection state and determines that a fault has occurred before the vertical synchronization signal is detected. If a rising edge of the valid polarity signal is detected, the system enters an idle state and determines that a fault has occurred before the valid polarity signal is detected. If the rising edge of the vertical synchronization signal is detected and the duration of the horizontal synchronization signal does not meet the preset duration requirement, the system enters the idle state and determines that a fault has occurred where the vertical synchronization signal duration is insufficient. If a falling edge of the horizontal synchronization signal is detected, and the duration between adjacent horizontal synchronization signals does not meet the preset duration requirement, the system enters the idle state and determines that a fault of insufficient interval time of the horizontal synchronization signal has occurred.

5. The detection feedback module according to claim 3, characterized in that, During the vertical trailing edge detection phase, the timing detection feedback submodule detects the vertical synchronization signal, horizontal synchronization signal, and effective polarity signal in the timing synchronization signal. If a falling edge of the vertical synchronization signal is detected, the system enters the vertical synchronization width detection state and determines that a fault has occurred before the vertical synchronization signal is detected. If the rising edge of the valid polarity signal is detected and the duration of the horizontal synchronization signal does not meet the preset duration requirement, then the system enters an idle state and determines that a fault has occurred before the valid polarity signal is detected. If a falling edge of the horizontal synchronization signal is detected, and the duration period between adjacent horizontal synchronization signals does not meet the preset duration requirement, and the duration of the horizontal synchronization signal does not meet the preset duration requirement, then the system enters the idle state, and it is determined that a fault of insufficient interval time of the horizontal synchronization signal has occurred.

6. The detection feedback module according to claim 3, characterized in that, During the effective polarity detection phase, the timing detection feedback submodule detects the vertical synchronization signal, horizontal synchronization signal, and effective polarity signal in the timing synchronization signal. If a falling edge of the vertical synchronization signal is detected, the system enters the vertical synchronization width detection state and determines that a fault has occurred before the vertical synchronization signal is detected. If a rising edge of the valid polarity signal is detected, and the duration of the valid polarity signal is not equal to the duration corresponding to the image width, then the system enters an idle state and determines that a discontinuity fault of the valid polarity signal has occurred. If the rising edge of the valid polarity signal is detected, and the rising edge of the horizontal synchronization signal is detected, the system enters the idle state and determines that a fault of insufficient horizontal trailing edge duration has occurred. If a falling edge of the horizontal synchronization signal is detected, and a falling edge of the valid polarity signal is detected, the system enters the idle state and determines that a fault of insufficient duration of the horizontal leading edge has occurred. If a falling edge of the horizontal synchronization signal is detected, and the duration between adjacent horizontal synchronization signals does not meet the preset duration requirement, and the number of horizontal synchronization signals is not equal to the image width, then the system enters the idle state and determines that either the horizontal synchronization signal interval time is insufficient or the effective polarity signal duration is insufficient.

7. The detection feedback module according to claim 3, characterized in that, During the vertical leading edge detection stage, the timing detection feedback submodule detects the vertical synchronization signal, horizontal synchronization signal, and effective polarity signal in the timing synchronization signal; If the rising edge of the vertical synchronization signal is detected, the system enters the vertical synchronization width detection state and determines that a fault has occurred before the vertical synchronization signal is detected. If the rising edge of the valid polarity signal or the duration between adjacent horizontal synchronization signals is not equal to the duration corresponding to the image width, the system enters an idle state and determines that a fault has occurred due to insufficient duration of the vertical leading edge.

8. An image signal processing chip, characterized in that, include: The image signal processing module, the processor main control module, and the detection feedback module according to any one of claims 1 to 7; The image signal processing module performs image signal processing on the image data signal in the input image signal; The processor main control module determines the image signal processing result to be output based on the timing detection result output by the comprehensive judgment feedback submodule.

9. The image signal processing chip according to claim 8, characterized in that, Also includes: The frame buffer module is used to buffer the correct image signal processing results output by the last-stage image signal processing submodule in the pipeline; If the processor main control module determines that the image signal processing result of the image signal is incorrect based on the timing detection result, it outputs the image signal processing result at a preset time from the frame buffer module.

10. The image signal processing chip according to claim 8, characterized in that, If the processor main control module determines that the image signal processing result of the image signal is incorrect based on the timing detection result, it determines to output the image signal processing result of the specified image signal processing submodule for that frame of image signal.

11. A circuit board, characterized in that, Includes the chip described in claim 8.

12. An electronic device, characterized in that, Includes the board as described in claim 11.

Images