Display device without DA converter

Abstract

Display device (10) with a substrate (12) and a display area (30) arranged on the substrate (12), wherein the display area (30) comprises a plurality of pixels (32) arranged in a two-dimensional array, wherein the display device (10) comprises the following: a first control loop (40) arranged on the substrate (12), wherein the first control loop (40) comprises a plurality of first input signal lines (XSR control signal, 42, 44, 45), (Idata, 46), (Yck, 48), a plurality of first electronic components (XSR(1), XSR(2), ..., 52), (Latch(R1), Latch(G1), ..., 62), (S1, S2) and a plurality of data lines (DR1, DG1, ..., 64), wherein the data lines (DR1, DG1, ..., 64) are arranged to provide image data for the pixels (32), wherein the first electronic components (XSR(1), XSR(2), ..., 52), (Latch(R1), Latch(G1), ..., 62), (S1, S2) are configured to receive data signals from the first input signal lines specifying the image data; a second control loop arranged on the substrate (12), wherein the second control loop (70) comprises a plurality of second input signal lines (YSR control signal), a plurality of second electronic components (YSR(1), YSR(2), ..., 82) and a plurality of sampling lines (P1, P2, ...), wherein the sampling lines (P1, P2, ...) are arranged to provide timing control signals for the pixels (32), and wherein the second electronic components (YSR(1), YSR(2), ..., 82) are configured to receive timing pulses from the second input signal lines specifying the timing control signals; and a connecting cable (20) comprising a plurality of first connecting lines (24) and a plurality of second connecting lines (24), wherein the first input signal lines (42, 44, 45), (Idata, 46), (Yck, 48) are electrically connected to the first connecting lines (24) to receive the data signals, and the second input signal lines (YSR control signal) are electrically connected to the second connecting lines (24) to receive the time pulses, and wherein the data signals are digital signals, wherein the digital signals have an amplitude range, wherein the connecting cable (20) is further configured to provide reference signals for controlling the image data in the first control circuit (40) and for controlling the timing control signals in the second control circuit (70), wherein the reference signals have a signal voltage range, wherein the amplitude range of the digital signals is greater than the signal voltage range of the reference signals.

Description

BACKGROUND area

[0001] The present invention generally relates to a display device with a display area comprising a plurality of pixels arranged in a two-dimensional array. Description of the state of the art

[0002] US 2004 / 0008172 A1 discloses a display device comprising: display elements located near the intersections of vertically and horizontally oriented signal lines and scanning lines; image acquisition units, each corresponding to at least one of the display elements, which each convert incident radiation in a predetermined area into an electrical signal; electrical charge storage devices that store the electrical charge according to the electrical signal converted by the image acquisition units; and a signal processing unit that generates digital image data according to the image captured by the image acquisition unit based on the stored electrical charge of the electrical charge storage device for each of a plurality of image acquisition conditions.

[0003] US patent 20100123738 A1 discloses display devices and methods for controlling them, in particular an active matrix display device for providing a gradation display and a method for controlling it.

[0004] US Patent 20020047822 A1 discloses an active-matrix liquid crystal display device with a plurality of unit pixels arranged in a matrix configuration, each unit pixel being subdivided into a plurality of subpixels. Each subpixel has a subpixel electrode, a pixel transistor connected to the subpixel electrode, and a voltage control capacitor connected to the subpixel electrode. A voltage control capacitor line for supplying a compensation voltage signal is connected to the voltage control capacitor, such that after the write operation to the subpixel is complete, the potential of the compensation voltage signal is varied to modulate the potential of the subpixel electrode to a predetermined voltage using the voltage control capacitor.This combination of spatial dithering, achieved through pixel division technology, and a capacitively coupled control method eliminates the need for digital-to-analog converter circuits, achieves a grayscale display based on a digital image signal, and reduces power consumption.

[0005] In a display device where a display area has a plurality of pixels, thin-film transistors (TFTs) are commonly used as switching elements to control the charging and discharging of the pixels. At least one driver IC is used to drive the TFT switching elements. A prior art display device is described in Fig. Figure 1 shows a driver IC. One of its functions is to receive digital data and convert it into analog signals. Typically, the amplitude of the digital data is significantly smaller than that of the analog signals. In a liquid crystal display (LCD), the transmission of light through the liquid crystal layer is controlled by an electric field applied to the layer. The amplitude of the analog signals applied to the pixels, along with the polarizers located on opposite sides of the liquid crystal layer, controls at least part of the pixel brightness levels and the grayscale of the display. As the image quality of a display device has improved, the role of the driver IC has become more important. In particular, large display areas, such as television screens and computer monitors, require a greater number of driver ICs.

[0006] As in Fig. As shown in Figure 1, the display device 2 has a substrate 3 for receiving a display area 4, one or more control loops 5, and a driver IC 6. The driver IC 6 is configured to receive input signals from a connector, such as a flexible printed circuit (FPC) 7. One of the functions of the driver IC 6 is to provide analog signals specifying image data to the display area 4 under the control of the control loop 5. Since the driver IC occupies a small area of ​​the substrate outside the display area, the substrate must have a boundary area large enough to accommodate the driver ICs.

[0007] In smaller display devices, such as personal portable displays and information displays for use in household appliances and office equipment, image quality is less critical. Some of these displays tend to have a small substrate, and the boundary area outside the display area is relatively small. Eliminating the use of driver ICs would be desirable to minimize this boundary area. SUMMARY

[0008] This problem is solved by a display device according to claim 1. The display device comprises a substrate for arranging a display area with a pixel array, and control loops with shift registers and latch registers to provide image data and timing signals for the pixels. The control loops have input signal lines that are electrically connected by a connecting cable to receive data signals specifying the image data, as well as timing pulses specifying the timing signals. The connecting cable is also configured to provide reference signals for the shift registers and latch registers in the control loops. The data signals are digital signals with an amplitude range that is greater than the amplitude range of the reference signals.Each pixel has three subpixels, and each color subpixel has three color sub-areas configured to receive timing signals from a different sampling line. No driver IC is placed on the substrate to process analog signals.

[0009] The display area comprises a plurality of pixels arranged in a two-dimensional array, the display device comprising the following: a first control loop arranged on the substrate, wherein the first control loop comprises a plurality of first input signal lines, a plurality of first electronic components and a plurality of data lines, wherein the data lines are arranged to provide image data to the pixels, wherein the first electronic components are configured to receive data signals from the first input signal lines specifying the image data; a second control loop arranged on the substrate, wherein the second control loop comprises a plurality of second input signal lines, a plurality of second electronic components, and a plurality of scanning lines, the scanning lines being arranged to provide timing control signals to the pixels, and the second electronic components being configured to receive timing pulses from the second input signal lines specifying the timing control signals; and a connecting cable comprising a plurality of first connecting lines and a plurality of second connecting lines, wherein the first input signal lines are electrically connected to the first connecting lines to receive the data signals via them, and the second input signal lines are electrically connected to the second connecting lines to receive the time pulses via them, and wherein the data signals are digital signals.

[0010] According to one embodiment of the present invention, the first input signal lines comprise a data signal line for providing the data signals to the first electronic components.

[0011] According to one embodiment of the present invention, each of the pixels comprises a plurality of color subpixels arranged to receive the image data from one of the other data lines, and wherein each color subpixel comprises a plurality of color sub-areas, each color sub-area being arranged to receive the timing control signals from one of the other scanning lines.

[0012] According to one embodiment of the present invention, the data lines comprise a first data line, a second data line and a third data line, and the color subpixels comprise a red subpixel, a green subpixel and a blue subpixel, wherein the red subpixel comprises a plurality of red sub-areas arranged to receive image data from the first data line, the green subpixel comprises a plurality of green sub-areas arranged in the first direction to receive image data from the second data line, and the blue subpixel comprises a plurality of blue sub-areas arranged to receive image data from the third data line.

[0013] According to one embodiment of the present invention, the sub-areas in each red subpixel, green subpixel and blue subpixel comprise a first sub-area, a second sub-area and a third sub-area, wherein the third sub-area is twice as large as the second sub-area and the second sub-area is twice as large as the first sub-area.

[0014] According to one embodiment of the present invention, each pixel comprises a plurality of pixel sub-areas, each of the pixel sub-areas being arranged to receive the timing control signals from another scanning line, each pixel sub-area comprising a red sub-area, a green sub-area and a blue sub-area.

[0015] According to one embodiment of the present invention, the first electronic components comprise a plurality of first shift registers and a plurality of capture registers configured to control the image data, wherein the first input signal lines comprise a plurality of control signal lines arranged to provide shift clock signals and capture clock signals, wherein the first shift registers are configured to provide the data signals for the capture registers in response to the shift clock signals, and wherein the capture registers are configured to provide the image data for the color subpixels in response to the capture clock signals.

[0016] According to one embodiment of the present invention, the second electronic components comprise a plurality of second shift registers configured to control the timing control signals, wherein the second input signal lines are arranged to provide shift clock signals, and wherein the second shift registers are configured to spread the time pulses for the color sub-areas in response to the shift clock signals.

[0017] According to one embodiment of the present invention, the pixels are arranged in a plurality of pixel rows in the first direction and a plurality of pixel columns in the second direction, and wherein each pixel comprises a plurality of pixel sub-areas arranged in the second direction, each of the pixel sub-areas being arranged to receive the timing control signals from another scanning line, and wherein each pixel sub-area comprises a plurality of color sub-areas arranged in the first direction, each color sub-area being arranged to receive the image data from another data line.

[0018] According to one embodiment of the present invention, the plurality of color sub-regions comprise red sub-regions, green sub-regions, and blue sub-regions, and wherein each pixel comprises a plurality of color subpixels, including a red subpixel with the red sub-regions, a green subpixel with the green sub-regions, and a blue subpixel with the blue sub-regions, and wherein the first electronic components comprise a plurality of first shift registers and a plurality of capture registers configured to control the image data, and the first input signal lines comprise a plurality of control signal lines arranged to provide first shift clock signals and capture clock signals, wherein the first shift registers are configured to provide the data signals for the capture registers in response to the first shift clock signals, and wherein the capture registers are configuredto provide the image data for the color subpixels in response to the capture clock signals.

[0019] According to one embodiment of the present invention, the second electronic components comprise a plurality of second shift registers configured to control the timing control signals, wherein the second input signal lines are arranged to provide second shift clock signals, and wherein the second shift registers are configured to provide the time pulses for the color sub-areas in response to the second shift clock signals.

[0020] According to one embodiment of the present invention, each of the pixel rows comprises N color subpixels, wherein N is a positive integer greater than one, wherein the first electronic components comprise N first shift registers and N capture registers, wherein the plurality of control signal lines are arranged to provide N shift clock signals and N capture clock signals in one row period, and wherein each of the time pulses has a pulse width substantially equal to one row period.

[0021] According to one embodiment of the present invention, each of the pixel columns comprises M pixel sub-areas, wherein M is a positive integer greater than one, wherein the second electronic components comprise M second shift registers and the second input signal lines are arranged to provide M successive second shift clock pulses for the M second shift registers in one frame time.

[0022] According to one embodiment of the present invention, a frame time is equal to 1 / 60 of a second.

[0023] According to one embodiment of the present invention, the substrate comprises a glass substrate.

[0024] According to one embodiment of the present invention, the connecting cable comprises one or more flexible printed circuits arranged to receive the data signals and time pulses from a control system.

[0025] According to one embodiment of the present invention, the digital signals comprise a first voltage level and a second voltage level, wherein the first voltage level is essentially equal to 10 V and the second voltage level is essentially equal to -10 V.

[0026] According to one embodiment of the present invention, the first electronic components comprise a plurality of first switching elements for controlling the image data, and The second electronic components comprise a variety of second switching elements for controlling the timing control signals, with the first and second switching elements being made only of thin-film transistors.

[0027] According to one embodiment of the present invention, the connecting cable is further configured to provide reference signals in order to provide a voltage reference for some of the first and second switching elements, wherein the reference signals comprise a signal voltage range between -3 V and 6 V.

[0028] According to one embodiment of the present invention, each of the first shift registers and catch registers comprises a plurality of switching elements made of thin-film transistors.

[0029] The present invention is explained by reading the description in conjunction with the drawings from Fig. 2 to 10 obviously. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] To better understand the specific features of this disclosure mentioned above, a more detailed description of the implementations summarized above can be obtained by referring to some of the implementations illustrated in the attached diagrams. It should be noted, however, that the attached diagrams only illustrate common implementations of this disclosure and should not be understood as limiting its scope, since the disclosure may permit other equally effective implementations. Fig. Figure 1 illustrates a prior art display device. Fig. Figure 2 illustrates a display device according to an embodiment of the present invention. Fig. Figure 3 illustrates the control loops that control image data and make it available for the display area, according to an embodiment of the present invention. Fig. Figure 4 illustrates a pixel on the display area according to an embodiment of the present invention. Fig. Figure 5 illustrates a part of the electronic circuit that provides image data for the display area. Fig. Figure 6 illustrates a part of the electronic circuit that provides timing control signals for the display area. Fig. Figure 7 illustrates an electronic circuit configured to perform some of the image data reception and capture functions of the electronic circuits. Fig. Figure 8 is a timing diagram that shows data and time signals in the electronic circuit. Fig. 7 shows. Fig. Figure 9 is a graphical representation of digital signals and reference signals. Fig. Figure 10 illustrates the connection between the display device and a system that provides image data and timing control signals.

[0031] To facilitate understanding, identical reference symbols have been used where possible to identify identical elements common to the figures. It is considered that elements and features from one implementation may be advantageously incorporated into other implementations without further explanation. DETAILED DESCRIPTION

[0032] In a color display device, pixels are typically arranged in a two-dimensional array, and each pixel has a plurality of color subpixels in R, G, and B. In one embodiment of the present invention, each color subpixel consists of a number of sub-areas of the same color, and each sub-area is arranged to display either a "dark" level or a "light" level, independently of other sub-areas. The signal indicating the image data provided for each sub-area can be expressed by two states, such as "H" and "L". In other words, the data signals indicating the image data provided for each pixel are digital signals. In one embodiment of the present invention, the data signals are discrete signals implemented in alternating phases.The display device according to the present invention comprises control loops with shift registers and capture registers configured to control the image data. The control loops are arranged to receive the data signals directly from a timing system via a connecting cable. The display device according to the present invention does not have a driver IC.

[0033] Fig. Figure 2 illustrates a display device according to one embodiment of the present invention. As can be seen in Fig. As shown in Figure 2, the display device 10 has a substrate 12, a display area 30, and one or more control loops 40, 70 configured to receive signals from a variety of connecting lines 24, 25 in a connecting cable 20, which may be, for example, a flexible printed circuit (FPC). The first control loop 40 is referred to as a V-circuit, and the second control loop 70 is referred to as an H-circuit for their functions. The substrate 10 can be made of glass or any suitable material. As described below in conjunction with Fig. 7. Digital signals are received from the connecting lines 24 and reference signals are received from the connecting lines 25 in the connecting cable 20.

[0034] The display area 30 comprises a plurality of pixels 32 arranged in a two-dimensional array in a first direction and a second direction (see Fig. 4).

[0035] How to in Fig. As shown in Figure 3, the V-circuit 40 comprises a plurality of first control signal lines (XSR control signal lines), a data signal line (Idata), and a capture signal line (Yck); a plurality of first shift registers (XSR(1), XSR(2), ...) electrically connected to the first control signal lines; an image data reception circuit electrically connected to the first shift registers and the data signal line; a plurality of capture registers (Latch(R1), Latch(G1), ...) electrically connected to the image data reception circuit; and a plurality of data lines (DR1, DG1, ...) electrically connected to the capture registers for providing image data to the display area 30. The first shift registers, the image data reception circuit, and the capture registers include switching elements made from TFTs for controlling the image data.The first control signal lines, the data signal line, and the capture signal line are collectively referred to as the first input signal lines. The first shift registers and capture registers are collectively referred to as the first electronic components.

[0036] The H-circuit 70 comprises a plurality of second control signal lines (YSR control signal lines), a plurality of second shift registers (YSR(1), YSR(2), ...) electrically connected to the second control signal lines, and a plurality of sampling lines (P1, P2, ...) electrically connected to the second shift registers to provide control signals for the pixels. The second shift registers include switching elements made from TFTs for controlling the timing signals. The second control signal lines are also referred to as the second input signal lines, and the second shift registers are also referred to as the second electronic components.

[0037] According to one embodiment of the present invention, the first input signal lines and the second input signal lines are electrically connected and configured to receive digital signals from the connecting lines 24 of the connecting cable 20. The digital signals comprise data signals specifying the image data and time pulses specifying the timing signals. The timing of the data signals and the timing signals are specified in Fig. 8 shown.

[0038] How to in Fig. As shown in Figure 4, each of the pixels 32 has a plurality of color subpixels 33, such as a red subpixel 33R, a green subpixel 33G, and a blue subpixel 33B, arranged in the first direction. The pixel 32 can also be divided into a plurality of pixel sub-regions 34, 36, and 38, arranged in the second direction. In one embodiment of the present invention, the red subpixel 33R has three red sub-regions R(1), R(2), and R(4), the green subpixel 33G has three green sub-regions G(1), G(2), and G(4), and the blue subpixel 33B has three blue sub-regions B(1), B(2), and B(4).The three blue sub-areas are designated as first blue sub-area 34B, second blue sub-area 36B, and third blue sub-area 38B; the three red sub-areas are designated as first red sub-area 34R, and so on. Therefore, the sub-areas in each of the red subpixel 33R, the green subpixel 33G, and the blue subpixel 33B comprise a first sub-area, a second sub-area, and a third sub-area. In one embodiment of the present invention, a third sub-area is twice the size of a second sub-area, and a second sub-area is twice the size of a first sub-area. For example, sub-area R(4) is twice the size of sub-area R(2), which is twice the size of R(1).

[0039] How to in Fig. As shown in Figure 4, the red subpixel 33R, the green subpixel 33G, and the blue subpixel 33B are arranged to receive image data separately from data lines DRn, DGn, and DBn. ​​Since the introduction of image data into each of the pixel sub-areas 34, 36, and 38 is independent of other sub-areas, three sampling lines, Pm, Pm+1, and Pm+2, are used to provide gate signals for the switching elements in the sub-areas (not shown).

[0040] How to in Fig. As can be seen in Figure 5, the first control loop 40 comprises a plurality of control signal lines 42, 44, a sliding signal line 45, a data signal line 46 and a catch signal line 48. These signal lines are electrically connected to the connecting lines 24 of a connecting cable 20 (see Figure 5). Fig. 2) The first control loop 40 further comprises a shift register array 50, an image data receiver circuit 54, and a capture register array 60. The shift register array 50 is configured to receive shift clock signals from the control signal lines 42 and 44. The image data receiver circuit 54 is configured to receive data signals specifying image data from the data signal line 46. The capture register array 60 is configured to receive capture clock signals from the capture signal line 48. The capture register array 60 comprises a plurality of capture registers 62. Each capture register 62 is configured to provide image data for the pixels via a data line 64. The image data reception circuit 54 comprises a plurality of image data reception elements 56. Each image data reception element 56 is configured to provide the image data for a corresponding capture register 62 based on the data signals received from the data signal line 46.The shift register array 50 comprises a plurality of shift registers 52 electrically connected to the control signal lines 42, 44, wherein the control signal lines 42 are clock signal lines arranged to control the shifting of shift registers 52 with shifted pulses. The shifted pulses in the control signal lines 42 determine when the image signals from the data signal line 46 can be fed into the capture registers 62. The process of feeding the image data into the first control loop 40 is repeated until all data (D1 - Dn) are locked (see ). Fig. 8) The control signal line 44 is arranged to provide a reference voltage Vss (not shown) in each of the shift registers 52. Each of the shift registers 52 is electrically connected to an image data receiver 56, which is electrically connected to a capture register 62. Each of the shift registers 52 is configured to output a control signal SRn in response to the shifted pulses in the control signal lines 42 (see Figure 8). Fig. 7) to provide the corresponding image data receiver 56. The image data receiver 56 is configured to provide the image data to the corresponding capture register 62 in response to the control signal SRn. The capture register 62 is electrically connected to a data line 64 and is configured to provide the image data for a column of color subpixels in response to the capture clock signals (see Fig. 3 and Fig. 4) to provide, which are provided in the receiving signal line 48. According to the present invention, the data signals provided by the data signal line 46 are digital signals received by one of the connecting lines 24 in the connecting cable 20. In one embodiment of the present invention, the amplitude of the digital signals received by the connecting cable 20 is +10 V or -10 V (see Fig. 9) There is no need to use a driver IC to convert the digital signals into analog signals.

[0041] How to in Fig. As can be seen in Figure 6, the second electronic circuit 70 comprises a plurality of control signal lines 72, 74 and a shift register array 80. The shift register array 80 comprises a plurality of shift registers 82 electrically connected to the control signal lines 72 and 74, the control signal lines 72 being clock signal lines arranged to control the shifting of the shift registers 82 with shifted pulses. The control signal line 74 is arranged to provide a reference voltage Vss (not shown) in each of the shift registers 82. Each of the shift registers 82 is electrically connected to a sample line 84 and is configured to provide a gate pulse for a set of pixel sub-areas in response to the shifted pulses in the control signal lines 72 (see Figure 6). Fig. 3 and Fig. 4).

[0042] Fig. Figure 7 illustrates an electronic circuit 58 arranged to perform the receive and capture functions of an image data receiver element 56 and the corresponding 62, according to an embodiment of the present invention. In the electronic circuit 58, VH = 6 V, L0 = -3 V, L255 = 3 V. These reference voltages or signals are provided by the connecting cables 25 in the connecting cable 20 (see Figure 7). Fig. 2) L0 and L255 are used to control the light / darkness of sub-areas 34, 36, and 38. The reference voltage L0 or L255 is supplied to the sub-areas via corresponding data lines (DR1, DG1, DB1, ...). Data and XData terminals are connected to data signal line 46 to receive data signals. The SRn terminals are connected to the output of the corresponding shift register 52. Dn is connected to a data line DRn. The pre-Yck signal is the SRn+1 signal, and the reset signal is a shifted signal of Yck. As can be seen in Fig. As can be seen in Figure 7, the electronic circuit 58 consists largely of a multitude of switching elements such as S1 and S2. The switching elements in the capture registers 62, image data reception elements 56, and shift registers 52 and 82 can be manufactured as a thin-film transistor (TFT). Since each of the pixel sub-areas (34R, 36R, ...) is arranged to display image data in two planes according to the states of the digital signals, the display device of the present invention does not have a driver IC to "drive" the pixel sub-areas. Therefore, the substrate area can be used in an optimal manner. Fig. 7 are Data and XData data signals received by the data signal line 46, which is electrically connected to one of the connecting lines 24 of the connecting cable 20. The connecting lines 24 are also referred to as control signal conductors, and the connecting lines 25 are also referred to as reference signal conductors, which are used to provide reference signals or voltages for the shift registers and catch registers.

[0043] Fig. Figure 8 is a timing diagram that shows data and time signals in the electronic circuit. Fig. Figure 7 relates to the shifted pulses in the H-circuit 70. The interval between two adjacent shifted YSRm pulses (or gate-pulsed) represents a frame time (TF) of the display area, and the pulse width of each of the shifted YSRm pulses is the interval provided to perform the image data transfer in one line time (TR), or when all data (D1-Dn) is locked. For example, in a display area where pixels are arranged in a plurality of pixel rows and pixel columns, and each pixel row comprises N color subpixels, the first control loop (V-circuit 40) comprises N first shift registers and N catch registers, and the plurality of clock signal lines 42 are arranged to provide N shift clock signals, and the catch signal line 48 is arranged to provide N catch clock signals in one line time. Each of the time pulses (shifted pulse YSRm) has a pulse width that is essentially equal to one line time.

[0044] In a display area where each of the pixel columns comprises M pixel sub-areas, the second control loop (H-circuit 70) comprises M second shift registers, and the second signal lines 72 are arranged to provide M successive time pulses for the M second shift registers in a frame time. In one embodiment of the present invention, a frame time is 1 / 16 of a second, but can be less than or greater than 1 / 60 of a second.

[0045] In one embodiment of the present invention, the reference voltage Vgh of the digital signals is equal to 10 V and the reference voltage Vcf is equal to -10 V. As can be seen in Fig. As can be seen in Figure 9, the amplitude of the digital signals is significantly larger than the range of the reference signals. The voltage range of the reference signals is typically 0 to 6 V.

[0046] Fig. Figure 10 illustrates the electronic connection between the display device and a system that provides image data and performs timing control. As shown in Fig. As shown in Figure 10, the display device 10 receives data signals and timing signals from a control system 11 via one or more connecting cables 20. For example, the connecting cables 20 include a flexible printed circuit (FPC) 21 and a flexible printed circuit 22. FPC 21 may include control signal conductors 24 that are electrically connected to the XSR control signal lines 42 and 44, data signal line 46, capture signal line 48, and reference signal conductors 25 to provide reference signals for the shift registers and capture registers in the V-circuit 40 (see Figure 10). Fig. 3) FPC 22 can include control signal conductors 24, which are electrically connected to the YSR control signal lines 72 and 74, and other reference signal conductors 25 to provide reference signals for the shift registers in the H-circuit 70 (see Fig. 3) Since the switching elements in control loops 40 and 70 are made of TFTs for shifting and capture purposes, the control loops 40 and 70 only require display information provided in digital signals and one or more reference signals (Vss, VH, LO, L255, ground). According to the present invention, image-related information required for image display is carried only in digital signals, not in analog signals. There is no need to use driver ICs to process image-related information.

[0047] In summary, the display device of the present invention comprises a substrate and a display area arranged on the substrate. The display area comprises a plurality of pixels arranged in a two-dimensional array. The display device further comprises one or more control loops arranged on the substrate, the control loops having electronic components configured to provide image data for the pixels and to control the timing of image data acquisition. The control loops are arranged to receive digital signals specifying image data and time pulses directly from a connecting cable.

[0048] While the foregoing is directed to implementations of the present disclosure, other and further implementations of the disclosure may be developed without deviating from its basic scope, and the scope of which is determined by the following claims.

Claims

[1] Display device (10) with a substrate (12) and a display area (30) arranged on the substrate (12), wherein the display area (30) comprises a plurality of pixels (32) arranged in a two-dimensional array, wherein the display device (10) comprises: a first control loop (40) arranged on the substrate (12), wherein the first control loop (40) comprises a plurality of first input signal lines (XSR control signal, 42, 44, 45), (Idata, 46), (Yck, 48), a plurality of first electronic components (XSR(1), XSR(2), ..., 52), (Latch(R1), Latch(G1), ..., 62), (S1, S2) and a plurality of data lines (DR1, DG1, ..., 64), wherein the data lines (DR1, DG1, ..., 64) are arranged to provide image data for the pixels (32), wherein the first electronic components (XSR(1), XSR(2), ..., 52), (Latch(R1), Latch(G1), ..., 62), (S1, S2) are configured to receive data signals from the first input signal lines specifying the image data; a second control loop arranged on the substrate (12), wherein the second control loop (70) comprises a plurality of second input signal lines (YSR control signal), a plurality of second electronic components (YSR(1), YSR(2), ..., 82) and a plurality of sampling lines (P1, P2, ...), wherein the sampling lines (P1, P2, ...) are arranged to provide timing control signals for the pixels (32), and wherein the second electronic components (YSR(1), YSR(2), ..., 82) are configured to receive timing pulses from the second input signal lines specifying the timing control signals; and a connecting cable (20) comprising a plurality of first connecting lines (24) and a plurality of second connecting lines (24), wherein the first input signal lines (42, 44, 45), (Idata, 46), (Yck, 48) are electrically connected to the first connecting lines (24) to receive the data signals, and the second input signal lines (YSR control signal) are electrically connected to the second connecting lines (24) to receive the time pulses, and wherein the data signals are digital signals, wherein the digital signals have an amplitude range, wherein the connecting cable (20) is further configured to provide reference signals for controlling the image data in the first control circuit (40) and for controlling the timing control signals in the second control circuit (70), wherein the reference signals have a signal voltage range, wherein the amplitude range of the digital signals is greater than the signal voltage range of the reference signals. [2] Display device (10) according to claim 1, wherein the first input signal lines (XSR control signal, 42, 44, 45), (Idata, 46), (Yck, 48) comprise a data signal line (Idata, 46) for providing the data signals to the first electronic components (XSR(1), XSR(2), ..., 52), (Latch(R1), Latch(G1), ..., 62), (S1, S2). [3] Display device (10) according to claim 1, wherein each of the pixels (32) comprises a plurality of color subpixels (33, 33R, 33G, 33B), wherein each color subpixel (33, 33R, 33G, 33B) is arranged to receive the image data from one of the other data lines (DR1, DG1, ..., 64), and wherein each color subpixel (33, 33R, 33G, 33B) comprises a plurality of color sub-areas (R(1), R(2), R(4), G(1), G(2), G(4), B(1), B(2), B(4)), wherein each color sub-area (R(1), R(2), R(4), G(1), G(2), G(4), B(1), B(2), B(4)) is arranged to receive the timing control signals from one of the other scanning lines (P1, P2, ...). received. [4] Display device (10) according to claim 3, wherein the data lines (DR1, DG1, ..., 64) comprise a first data line (DRn, 64), a second data line (DGn, 64) and a third data line (DRn, 64), and the color subpixels (33, 33R, 33G, 33B) comprise a red subpixel (33R), a green subpixel (33G) and a blue subpixel (33B), wherein the red subpixel (33R) comprises a plurality of red sub-areas (R(1), R(2), R(4)) arranged to receive the image data from the first data line (DRn, 64), the green subpixel (33G) comprises a plurality of green sub-areas (G(1), G(2), G(4)) arranged in the first direction to receive image data from the second data line (DGn, 64), wherein the blue Subpixel (33B) comprises a multitude of blue sub-areas (B(1), B(2), B(4)) arranged to receive image data from the third data line (DRn, 64). [5] Display device (10) according to claim 4, wherein the sub-areas (R(1), R(2), R(4), G(1), G(2), G(4), B(1), B(2), B(4)) in each of the red subpixel (33R), the green subpixel (33G) and the blue subpixel (33B) comprise a first sub-area (R(1), G(1), B(1)), a second sub-area (R(2), G(2), B(2)) and a third sub-area (R(4), G(4), B(4)), wherein the third sub-area (R(4), G(4), B(4)) is twice as large as the second sub-area (R(2), G(2), B(2)) and the second sub-area (R(2), G(2), B(2)) is twice as large as the first sub-area (R(1), G(1), B(1)). [6] Display device (10) according to claim 1, wherein each pixel (32) comprises a plurality of pixel sub-areas (34, 36, 38), wherein each of the pixel sub-areas (34, 36, 38) is arranged to receive the timing control signals from another scanning line (Pm, Pm+1, Pm+2, Pm+3), wherein each pixel sub-area (34, 36, 38) comprises a red sub-area (34R, 36R, 38R), a green sub-area (34G, 38G) and a blue sub-area (34B, 36B, 38B). [7] Display device (10) according to claim 3, wherein the first electronic components (XSR(1), XSR(2), ..., 52), (Latch(R1), Latch(G1), ..., 62), (S1, S2) comprise a plurality of first shift registers (XSR(1), XSR(2), ..., 52) and a plurality of capture registers (Latch(R1), Latch(G1), ..., 62) configured to control the image data, and wherein the first input signal lines (XSR control signal, 42, 44, 45), (Idata, 46), (Yck, 48) comprise a plurality of control signal lines (42, 44), (Yck, 48) arranged to provide shift clock signals and capture clock signals, wherein the first shift registers (XSR(1), XSR(2), ..., 52) are configured to output the data signals for the to provide capture registers, wherein the capture registers (Latch(R1), Latch(G1), ...,62) are configured to provide image data for the color subpixels (33, 33R, 33G, 33B) in response to the capture clock signals. [8] Display device (10) according to claim 3, wherein the second electronic components (YSR(1), YSR(2), ...,82) comprise a plurality of second shift registers (YSR(1), YSR(2), ...,82) configured to control the timing control signals, wherein the second input signal lines (YSR control signal, 72, 74, 75) are arranged to provide shift clock signals, wherein the second shift registers (YSR(1), YSR(2), ...,82) are configured to provide the time pulses for the color sub-areas (R(1), R(2), R(4), G(1), G(2), G(4), B(1), B(2), B(4)) in response to the shift clock signals. [9] Display device (10) according to claim 1, wherein the pixels (32) are arranged in a plurality of pixel rows in the first direction and a plurality of pixel columns in the second direction, and wherein each pixel comprises a plurality of pixel sub-areas (34, 36, 38) arranged in the second direction, each of the pixel sub-areas (34, 36, 38) being arranged to receive the timing control signals from another scanning line (Pm, Pm+1, Pm+2, Pm+3), and wherein each pixel sub-area (34, 36, 38) comprises a plurality of color sub-areas (34R, 36R, 38R, 34G, 38G, 34B, 36B, 38B) being arranged in the first direction, each color sub-area (34R, 36R, 38R, 34G, 38G, 34B, 36B, 38B) is arranged to receive the image data from another data line (DR1, DG1, ..., 64). [10] Display device (10) according to claim 9, wherein the plurality of color sub-areas (34R, 36R, 38R, 34G, 38G, 34B, 36B, 38B) comprises red sub-areas (34R, 36R, 38R), green sub-areas (34G, 38G) and blue sub-areas (34B, 36B, 38B), and wherein each pixel comprises a plurality of color subpixels (33, 33R, 33G, 33B), including a red subpixel (33R) with the red sub-areas (R(1), R(2), R(4)), a green subpixel (33G) with the green sub-areas (G(1), G(2), G(4)) and a blue subpixel (33B) with the blue sub-areas (B(1), B(2), B(4)), and wherein the first electronic components (XSR(1), XSR(2), ...,52), (Latch(R1), Latch(G1), ...,62), (S1, S2) a plurality of first shift registers (XSR(1), XSR(2), ..., 52) and a plurality of catch registers (Latch(R1), Latch(G1), ..., 62) which are configured to control the image data, and the first input signal lines (XSR control signal, 42, 44, 45), (Idata, 46), (Yck, 48) comprise a plurality of control signal lines (42, 44), (Yck, 48) which are arranged to provide first shift clock signals and capture clock signals, wherein the first shift registers (XSR(1), XSR(2), ...,52) are configured to provide the data signals for the capture registers (Latch(R1), Latch(G1), ...,62) in response to the first shift clock signals, wherein the capture registers (Latch(R1), Latch(G1), ...,62) are configured to provide the image data for the color subpixels (33, 33R, 33G, 33B) in response to the capture clock signals. [11] Display device (10) according to claim 10, wherein the second electronic components (YSR(1), YSR(2), ...,82) comprise a plurality of second shift registers (YSR(1), YSR(2), ...,82) configured to control the timing control signals, wherein the second input signal lines (YSR control signal, 72, 74, 75) are arranged to provide second shift clock signals, wherein the second shift registers (YSR(1), YSR(2), ...,82) are configured to provide the time pulses (YSR1,...,YSRm) for the color sub-areas (34R, 36R, 38R, 34G, 38G, 34B, 36B, 38B) in response to the second shift clock signals. [12] Display device (10) according to claim 11, wherein each of the pixel rows comprises N color subpixels, wherein N is a positive integer greater than one, wherein the first electronic components (XSR(1), XSR(2), ...,52), (Latch(R1), Latch(G1), ...,62), (S1, S2) comprise N first shift registers (XSR(1), XSR(2), ...,52) and N catch registers (Latch(R1), Latch(G1), ...,62), wherein the plurality of control signal lines (42, 44), (Yck, 48) are arranged to provide N shift clock signals and N catch clock signals in one row period, and wherein each of the time pulses has a pulse width (YSRm) substantially equal to one row period. [13] Display device (10) according to claim 12, wherein each of the pixel columns comprises M pixel sub-areas, wherein M is a positive integer greater than one, wherein the second electronic components (YSR(1), YSR(2), ...,82) comprise M second shift registers (YSR(1), YSR(2), ...,82) and the second input signal lines (YSR control signal lines, 72, 74, 75) are arranged to provide M successive second shift clock pulses for the M second shift registers (YSR(1), YSR(2), ...,82) in one frame time (TF). [14] Display device (10) according to claim 13, wherein the frame time (TF) is equal to 1 / 60 of a second. [15] Display device (10) according to claim 1, wherein the substrate (12) comprises a glass substrate. [16] Display device (10) according to claim 1, wherein the connecting cable (20) comprises one or more flexible printed circuits (21, 22) arranged to receive the data signals and time pulses from a control system (11). [17] Display device (10) according to claim 1, wherein the digital signals comprise a first voltage level and a second voltage level, wherein the first voltage level is essentially equal to 10 V and the second voltage level is essentially equal to -10 V. [18] Display device (10) according to claim 1, wherein the first electronic components (XSR(1), XSR(2), ...,52), (Latch(R1), Latch(G1), ...,62), (S1, S2) comprise a variety of first switching elements (S1, S2) for controlling the image data and the second electronic components (YSR(1), YSR(2), ...,82) comprise a plurality of second switching elements for controlling the timing control signals, wherein the first (S1, S2) and second switching elements are made only of thin-film transistors. [19] Display device (10) according to claim 18, wherein reference signals are configured to provide a voltage reference for some of the first (S1, S2) and second switching elements. [20] Display device (10) according to claim 7, wherein each of first shift registers (XSR(1), XSR(2), ...,52), (Latch(R1) and catch register Latch(G1), ...,62) comprises a plurality of switching elements (S1, S2) made of thin-film transistors.

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