Mapping entry management method and storage device

Abstract

The present application provides a mapping item management method and a storage device. The method comprises: configuring a plurality of cache queues in a buffer memory; putting a mapping item into a first cache queue according to an operation instruction from a host system; in response to a trigger condition being met, performing one of a first reorganization operation and a second reorganization operation on the first cache queue according to an order in which the mapping items enter the first cache queue and a hit count corresponding to the mapping items; in the first reorganization operation, moving a first mapping item in the first cache queue to a second cache queue; and in the second reorganization operation, removing a second mapping item in the first cache queue and putting identification information corresponding to the second mapping item into a third cache queue. Thus, the management efficiency of the mapping items can be improved.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a mapping item management method and storage device. Background Technology

[0002] Flash memory devices or other types of non-volatile memory devices perform interactions (such as data access) between the host system and the memory device through a mapping between logical addresses and physical addresses. Generally, when an operation instruction is received from the host system, the memory controller first checks whether the mapping information related to the logical address indicated by the operation instruction already exists in a predetermined buffer memory. If this mapping information exists in the buffer memory, the memory controller can directly access the corresponding physical address based on the mapping information in the buffer memory, such as reading data from this physical address. However, if this mapping information does not exist in the buffer memory, the memory controller needs to spend a considerable amount of time reading the mapping information from the memory module, loading it into the buffer memory, and then accessing the corresponding physical address based on this mapping information.

[0003] However, due to device size limitations or deployment costs, the capacity of the buffer memory available to the memory controller in some types of storage devices is very small. Therefore, during storage device operation, the memory controller often can only cache a small portion of recently used or anticipatedly needed mapping information in the buffer memory in a round-robin fashion. If the currently needed mapping information is not present in the buffer memory, the data access performance of the storage device will degrade. Over the long term, this leads to unstable data access performance. Summary of the Invention

[0004] The present invention provides a mapping item management method and a storage device, which can improve the above-mentioned problems and thereby steadily improve the data access performance of the storage device.

[0005] Embodiments of the present invention provide a mapping item management method for a storage device, wherein the storage device includes a memory module, and the mapping item management method includes: configuring a plurality of cache queues in a buffer memory; placing at least one mapping item into a first cache queue among the plurality of cache queues according to at least one operation instruction from a host system, wherein the at least one mapping item carries mapping information corresponding to the at least one operation instruction; in response to a trigger condition being met, performing one of a first sorting operation and a second sorting operation on the first cache queue according to the order in which the at least one mapping item entered the first cache queue and the number of hits corresponding to the at least one mapping item; in the first sorting operation, moving a first mapping item in the first cache queue to a second cache queue among the plurality of cache queues; and in the second sorting operation, removing a second mapping item from the first cache queue and placing identification information corresponding to the second mapping item into a third cache queue among the plurality of cache queues.

[0006] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module, and a memory controller. The memory controller is connected to the connection interface and the memory module. The memory controller is used to execute the mapping item management method described above.

[0007] Based on the above, multiple cache queues can be configured in a buffer memory. According to operation instructions from the host system, corresponding mapping entries can be placed into a first cache queue among the multiple cache queues. Specifically, the mapping entries may carry mapping information corresponding to the operation instructions. After a triggering condition is met, one of a first reorganization operation and a second reorganization operation can be performed on the first cache queue according to the order in which the mapping entries entered the first cache queue and the number of hits corresponding to the mapping entries. In the first reorganization operation, a first mapping entry in the first cache queue can be moved to a second cache queue among the multiple cache queues. Furthermore, in the second reorganization operation, a second mapping entry in the first cache queue can be removed, and the identification information corresponding to the second mapping entry can be placed into a third cache queue among the multiple cache queues.

[0008] Therefore, compared to traditional methods that can only perform mapping item replacement in the buffer memory based on simple Least Recently Used (LRU) algorithms, the mapping item management method and storage device provided by this invention can effectively increase the probability of the mapping item currently cached in the buffer memory being hit, thereby steadily improving the data access performance of the storage device. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0010] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0011] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0012] Figure 4 This is a schematic diagram illustrating the configuration of multiple cache queues in a buffer memory according to an embodiment of the present invention;

[0013] Figure 5 This is a schematic diagram illustrating the second sorting operation performed on a first cache queue according to an embodiment of the present invention;

[0014] Figure 6 This is a schematic diagram illustrating the first compaction operation performed on a first cache queue according to an embodiment of the present invention;

[0015] Figure 7 This is a schematic diagram illustrating the third compaction operation performed on the third buffer queue according to an embodiment of the present invention;

[0016] Figure 8 This is a schematic diagram illustrating the fourth compaction operation performed on the second buffer queue according to an embodiment of the present invention;

[0017] Figure 9 This is a flowchart illustrating a mapping item management method according to an embodiment of the present invention. Detailed Implementation

[0018] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0019] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0020] The host system 11 may include a processor 111 and a buffer memory 112. The processor 111 is used to handle all or part of the operation of the host system 11. For example, the processor 111 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations thereof.

[0021] Buffer memory 112 is connected to processor 111 and used to cache data. For example, buffer memory 112 may include dynamic random access memory (DRAM) or other types of volatile memory. Buffer memory 112 can be used as the main memory of host system 11. In addition, host system 11 may also include various hardware circuit modules such as power management circuitry, mouse, keyboard, screen, and / or wired / wireless communication circuitry, which will not be described in detail here.

[0022] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0023] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0024] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a CPU, or other programmable general-purpose or special-purpose microprocessor, DSP, programmable controller, ASIC, PLD, or other similar device or a combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller.

[0025] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0026] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0027] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0028] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0029] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuitry), which is not limited by the present invention.

[0030] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1) to 301(B). Each physical unit includes multiple storage units for non-volatile storage of data.

[0031] In one embodiment, an entity unit may include at least one entity programming unit. Furthermore, an entity erasure unit may include multiple entity programming units.

[0032] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and the present invention is not limited thereto. In one embodiment, an entity programming unit is also referred to as an entity page.

[0033] In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0034] In one embodiment, multiple programmed units within a single physical erase unit can be erased simultaneously. For example, when an erase operation is performed on a single physical erase unit, an erase voltage can be applied to the multiple programmed units within that unit to change the threshold voltage of at least a portion of the memory cells in those units. By performing an erase operation on a single physical erase unit, the data stored in that unit can be erased. In one embodiment, a physical erase unit is also referred to as a physical block.

[0035] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0036] In one embodiment, if a certain entity unit does not store valid data, this entity unit can be associated with the free area 32. Furthermore, entity units in the free area 32 can be erased to clear the data in that entity unit. In one embodiment, entity units in the free area 32 are also referred to as idle entity units. In one embodiment, the free area 32 is also referred to as the free pool.

[0037] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0038] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(1)-302(C) to map physical units (i.e., physical units 301(1)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0039] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0040] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information (also known as mapping information) in this management table (i.e., the logic-to-physical mapping table).

[0041] In one embodiment, each mapping information may be contained in a mapping entry. Alternatively, in one embodiment, each mapping information may be recorded in a management table (i.e., a logical-to-entity mapping table) in the form of a mapping entry.

[0042] In one embodiment, the memory control circuit 23 may configure multiple cache queues in the buffer memory 24. In particular, these cache queues may be dedicated to caching mapping items with mapping information and / or identification information associated with a particular mapping item.

[0043] In one embodiment, if the storage device 12 supports Host Memory Buffering (HMB) technology or similar technology that can share memory with the host system 11, then the buffer memory 24 can also be replaced by or used in conjunction with the buffer memory 112 in the host system 11.

[0044] In one embodiment, the plurality of cache queues are of at least three types, and the total number of cache queues of each type is at least one. In the following embodiments, a first cache queue, a second cache queue, and a third cache queue will be used as examples of the above-mentioned different types of cache queues.

[0045] In one embodiment, the capacity of the first cache queue must be less than the capacity of the second cache queue. For example, assuming the first cache queue can be used to cache at most N mapping entries and the second cache queue can be used to cache at most M mapping entries, then M is greater than N, where M and N are both positive integers. Furthermore, the capacity of the second cache queue may be the same as or different from the capacity of the third cache queue.

[0046] In one embodiment, a first cache queue may be dedicated to caching the most recently loaded mapping entries into buffer memory 24. A second cache queue may be dedicated to caching mapping entries previously cached in the first cache queue and initially identified as having a relatively high probability (or potential) of subsequent hits. In particular, the second cache queue may be used to store more mapping entries than the first cache queue. Furthermore, a third cache queue may be dedicated to caching the identification information corresponding to mapping entries evicted from the first and / or second cache queues.

[0047] In one embodiment, the identification information corresponding to a mapping item may include an index, which can be used to associate or identify the mapping item. Specifically, the amount of data corresponding to the identification information (e.g., the index) of a mapping item may be less than the amount of data for the mapping item itself. In other words, while the first and second cache queues can be used to cache mapping items, the third cache queue can only be used to cache the identification information corresponding to the mapping item, and is not used to cache the mapping item itself.

[0048] In one embodiment, after receiving an operation instruction (also called a target operation instruction) from the host system 11, the memory control circuit 23 can parse the target operation instruction to obtain the logic unit (also called the target logic unit) indicated by the target operation instruction and the instruction code. For example, this instruction code may reflect that the target operation instruction is a write instruction, a read instruction, a delete instruction, or other types of operation instructions.

[0049] In one embodiment, the memory control circuit 23 can determine the mapping item (also called the target mapping item) to be queried at the moment, based on the logic unit (i.e., the target logic unit) indicated by the target operation instruction. For example, the target mapping item may carry mapping information corresponding to the target operation instruction. For example, this mapping information may reflect the mapping relationship between the target logic unit and a certain entity unit (also called the target entity unit) in the memory module 122.

[0050] In one embodiment, if the target mapping item (i.e., the target mapping item) to be queried already exists in the buffer memory 24, the memory control circuit 23 can determine that the target mapping item in the buffer memory 24 has been matched and read the target mapping item from the buffer memory 24. Then, the memory control circuit 23 can execute the operation indicated by the target operation instruction (also called the target operation) on the target entity unit in the memory module 122 according to the target mapping item. For example, the target operation can be a read operation, a write operation, or a delete operation, and the type of target operation is not limited to these.

[0051] In one embodiment, if the target mapping item (i.e., the desired mapping item) is not present in the buffer memory 24, the memory control circuit 23 determines that no mapping item has been matched in the buffer memory 24. In response to the absence of a matched mapping item in the buffer memory 24, the memory control circuit 23 reads the required mapping item (i.e., the target mapping item) from the management table (i.e., the logic-to-entity mapping table) in the memory module 122 and loads the target mapping item into the buffer memory 24. Then, the memory control circuit 23 can also perform the aforementioned target operation on the target entity unit in the memory module 122 according to the target mapping item.

[0052] It should be noted that, compared to the case where the target mapping item in the buffer memory 24 is hit, when no mapping item in the buffer memory 24 is hit, the memory control circuit 23 needs to spend more time reading the target mapping item from the memory module 122, resulting in an operation delay. However, the mapping item management method proposed in this invention can improve this problem and increase the probability of the mapping item in the buffer memory 24 being hit. Therefore, the data access performance of the storage device 12 can be stably improved.

[0053] In one embodiment, after configuring multiple cache queues, the memory control circuit 23 can obtain at least one operation instruction from the host system 11. Then, the memory control circuit 23 can place at least one mapping item into the first cache queue according to the operation instruction. For example, the newly placed mapping item into the first cache queue may carry mapping information corresponding to the operation instruction.

[0054] In one embodiment, after at least one mapping item is placed into the first cache queue, the memory control circuit 23 can simultaneously record the order in which each mapping item enters the first cache queue and the number of hits corresponding to the at least one mapping item (also known as hit count information). For example, the memory control circuit 23 can use multiple indicators to point to different mapping items in the first cache queue (or multiple locations in the first cache queue where different mapping items are stored) to reflect the order in which these mapping items enter the first cache queue. In addition, the hit count can reflect the number of times each mapping item in the first cache queue is hit after being placed into the first cache queue.

[0055] In one embodiment, after a mapping item is initially placed into the first cache queue (or buffer memory 24), the memory control circuit 23 can set the hit count corresponding to this mapping item to an initial value (e.g., "0"). Subsequently, regardless of which cache queue a mapping item in the buffer memory 24 is currently located in, whenever this mapping item is hit, the hit count corresponding to this mapping item will be updated (e.g., incremented by "1").

[0056] In one embodiment, after at least one mapping item is placed into the first cache queue, the memory control circuit 23 continuously monitors whether the triggering conditions are met. For example, the triggering conditions may include: (1) the first cache queue is full, (2) the first cache queue is full and a new mapping item is to be placed into the first cache queue, (3) the number of hits corresponding to the mapping item meets a preset condition, and (4) at least one of the following is described in detail.

[0057] (1) First cache queue is full: This means that the first cache queue has been filled with multiple mapping items and cannot accommodate more mapping items.

[0058] (2) The first cache queue is full and a new mapping item is to be added to the first cache queue: This means that when the first cache queue is full, it has been determined that at least one mapping item (i.e., a new mapping item) is waiting to be added to the first cache queue.

[0059] (3) Hit count meets preset conditions: This means that the hit count of at least one mapping item currently in the first cache queue meets preset conditions. For example, if the hit count meets preset conditions, it can reflect that there are at least K mapping items in the first cache queue, and these K mapping items have been hit P times. K and P can be set according to practical needs.

[0060] (4) Accumulated host operation count reaches a preset number: This means that the cumulative number of host operations executed over a period of time has reached a preset number. For example, each operation instruction from host system 11 can correspond to one host operation. In addition, the triggering conditions can be adjusted according to practical needs, and this invention does not impose any restrictions.

[0061] In one embodiment, in response to a trigger condition being met, the memory control circuit 23 may perform a sorting operation on the first cache queue according to the order in which at least one mapping item enters the first cache queue and the hit count corresponding to the at least one mapping item, so as to reduce the total number of mapping items in the first cache queue. For example, this sorting operation may include a first sorting operation and a second sorting operation.

[0062] In one embodiment, during the first reorganization operation, the memory control circuit 23 can move at least one mapping item (also referred to as the first mapping item) from the first cache queue to the second cache queue. Conversely, during the second reorganization operation, the memory control circuit 23 can remove at least one mapping item (also referred to as the second mapping item) from the first cache queue. Simultaneously, the memory control circuit 23 can place the identification information corresponding to the second mapping item into the third cache queue. The identification information of the second mapping item can be used to identify the second mapping item, and the amount of data in the identification information of the second mapping item is less than the amount of data in the second mapping item itself.

[0063] In one embodiment, through a first sorting operation, mapping items (i.e., first mapping items) that have been queried in the past (i.e., previously placed in the first cache queue) and have a relatively high probability (or potential) of subsequent hits can be moved to a larger second cache queue for complete storage. Therefore, when this mapping item (i.e., the first mapping item) needs to be queried again later, its complete information can be directly read from the second cache queue. This significantly improves the data access performance of the storage device 12.

[0064] On the other hand, through the second sorting operation, mapping items that have been queried in the past (i.e., previously placed in the first cache queue) but have a relatively low probability of being queried again (i.e., second mapping items) can be stored only in the form of identification information in the third cache queue, thus saving space usage in the third cache queue. Furthermore, when this mapping item (i.e., the second mapping item) needs to be queried again, although the complete information of this mapping item cannot be directly read from the buffer memory 24, it can still be quickly identified as a mapping item with a relatively high probability (or potential) of being hit in the future based on the identification information corresponding to this mapping item in the third cache queue, and returned to the second cache queue. This also helps to improve the data access performance of the storage device 12.

[0065] In one embodiment, the memory control circuit 23 may encode (or compress) a portion of the information content of the second mapping item (e.g., the number or identification code of the logical unit corresponding to the second mapping item) to obtain identification information corresponding to the second mapping item. For example, the memory control circuit 23 may perform hash encoding on a portion of the information content of the second mapping item (e.g., the number or identification code of the logical unit corresponding to the second mapping item) to obtain a hash code. Then, the memory control circuit 23 may determine this hash code as the identification information corresponding to the second mapping item.

[0066] In one embodiment, the memory control circuit 23 may also directly determine a portion of the information content of the second mapping item (e.g., the number or identification code of the logic unit corresponding to the second mapping item) as the identification information corresponding to the second mapping item. Furthermore, the memory control circuit 23 may also obtain the identification information corresponding to the second mapping item through other means, and this invention is not limited thereto.

[0067] In one embodiment, in response to the triggering condition being met, the memory control circuit 23 can dynamically determine whether to perform the first sorting operation and / or the second overall operation on the first cache queue based on the order in which at least one mapping item enters the first cache queue and the number of hits corresponding to the at least one mapping item.

[0068] In one embodiment, in response to the fulfillment of a trigger condition, the memory control circuit 23 can determine whether at least one mapping entry of a specific type (also referred to as a first candidate mapping entry) exists in the first cache queue. In particular, the number of hits corresponding to each first candidate mapping entry is greater than a threshold value (also referred to as a first threshold value). For example, the first threshold value can be "0" or other positive integers.

[0069] In one embodiment, in response to the presence of a first candidate mapping item in the first cache queue, the memory control circuit 23 may trigger a first defragmentation operation and determine the first mapping item from the first candidate mapping items. For example, if there is only one first candidate mapping item, the memory control circuit 23 may determine this first candidate mapping item as the first mapping item. However, if there are multiple first candidate mapping items, the memory control circuit 23 may determine the mapping item corresponding to the largest or relatively large number of hits among the first candidate mapping items as the first mapping item. Furthermore, if there is no first candidate mapping item in the first cache queue, the memory control circuit 23 may not trigger the first defragmentation operation.

[0070] In one embodiment, if there are multiple first candidate mapping entries in the first cache queue and at least two of the first candidate mapping entries correspond to the same number of hits, the memory control circuit 23 can further determine one of these mapping entries as the first mapping entry based on the order in which these mapping entries entered the first cache queue. For example, assuming there are two mapping entries (i.e., first candidate mapping entries) in the first cache queue with a hit count of "1" at the same time, the memory control circuit 23 can prioritize determining the mapping entry that entered the first cache queue later as the first mapping entry based on the order in which these two mapping entries with a hit count of "1" entered the first cache queue. The reason is that, compared to the mapping entries that entered the first cache queue earlier, the mapping entries that entered the first cache queue later may have a higher probability of being queried again in the near future.

[0071] In one embodiment, in response to the triggering condition being met, the memory control circuit 23 can determine whether there is at least one mapping entry of another type (also referred to as a second candidate mapping entry) in the first cache queue. In particular, the number of hits corresponding to each second candidate mapping entry is less than a threshold value (also referred to as a second threshold value). For example, the second threshold value can be "1" or other positive integers.

[0072] In one embodiment, in response to the presence of a second candidate mapping item in the first cache queue, the memory control circuit 23 may trigger a second sorting operation and determine the second mapping item from the second candidate mapping items. For example, if there is only one second candidate mapping item, the memory control circuit 23 may determine this second candidate mapping item as the second mapping item. However, if there are multiple second candidate mapping items, the memory control circuit 23 may determine the mapping item corresponding to the minimum or relatively small number of hits among the second candidate mapping items as the second mapping item. Furthermore, if there is no second candidate mapping item in the second cache queue, the memory control circuit 23 may not trigger the second sorting operation.

[0073] In one embodiment, if there are multiple second candidate mapping entries in the second cache queue, and at least two of the second candidate mapping entries correspond to the same number of hits, the memory control circuit 23 can further determine one of these mapping entries as the second mapping entry based on the order in which these mapping entries entered the first cache queue. For example, assuming that there are two mapping entries (i.e., second candidate mapping entries) in the first cache queue with a hit count of "0" at the same time, the memory control circuit 23 can prioritize determining the mapping entry that entered the first cache queue earlier as the second mapping entry based on the order in which these two mapping entries with a hit count of "0" entered the first cache queue. The reason is that, compared to mapping entries that entered the first cache queue later, mapping entries that entered the first cache queue earlier may have a higher probability of not being queried again in the near future.

[0074] In one embodiment, after the triggering condition is met, if the hit count corresponding to all mapping entries in the first cache queue is not less than the second threshold, the memory control circuit 23 can further subtract a preset value (also called the first preset value) from the hit count corresponding to each mapping entry in the first cache queue to obtain an adjusted hit count. For example, the first preset value can be "1" or other positive integers. This attempts to reduce the hit count corresponding to each mapping entry in the first cache queue. Then, the memory control circuit 23 can trigger a second sorting operation based on the adjusted hit count. The relevant operational details have been described above and will not be repeated here.

[0075] In one embodiment, after adding the identification information corresponding to the second mapping item to the third cache queue, in response to the second mapping item being hit, the memory control circuit 23 can also perform a sorting operation (also known as a third sorting operation) on the third cache queue. In the third sorting operation, the memory control circuit 23 can reread the second mapping item from the memory module 122 and put the re-acquired second mapping item into the second cache queue.

[0076] In one embodiment, in response to a full second cache queue, the memory control circuit 23 may subtract a preset value (also referred to as a second preset value) from the hit count corresponding to each mapping item in the second cache queue to obtain an adjusted hit count. For example, the second preset value may be "1" or other positive integers. This attempts to reduce the hit count corresponding to each mapping item in the second cache queue. Then, the memory control circuit 23 may trigger a reorganization operation (also referred to as a fourth reorganization operation) on the second cache queue based on the adjusted hit count.

[0077] In the fourth sorting operation, the memory control circuit 23 may remove at least one mapping entry (also referred to as the third mapping entry) from the second cache queue and place the identification information corresponding to the third mapping entry into the third cache queue. For example, after adjusting (e.g., reducing) the hit counts corresponding to each mapping entry in the second cache queue, the memory control circuit 23 may determine the mapping entry in the second cache queue that should have the minimum or relatively small hit count as the third mapping entry based on the adjusted hit counts.

[0078] In one embodiment, after adjusting (e.g., reducing) the hit counts corresponding to each mapping entry in the second cache queue, if there are multiple mapping entries in the second cache queue corresponding to the minimum or relatively small hit counts, the memory control circuit 23 can prioritize determining the mapping entry that entered the second cache queue earlier as the third mapping entry based on the order in which these mapping entries entered the first cache queue. The reason is that, compared to mapping entries that entered the second cache queue later, mapping entries that entered the second cache queue earlier may have a higher probability of not being queried again in the near future.

[0079] In one embodiment, the memory control circuit 23 may also monitor the update frequency of the queue contents for multiple cache queues. For example, the memory control circuit 23 may obtain this update frequency based on the total number of times the queue contents of the multiple cache queues are updated (e.g., mapping items are moved and / or removed) within a preset time range. In response to this update frequency being greater than a frequency threshold, the memory control circuit 23 may activate a cooling-off period. During this cooling-off period, the memory control circuit 23 may suspend updates to the queue contents for the multiple cache queues. For example, during this cooling-off period, the memory control circuit 23 may temporarily refrain from triggering the various sorting operations described above for the multiple cache queues. This avoids excessive system load due to updates in a short period of time and prevents a decline in the hit rate of mapping items due to excessive updates in some cases. However, if this update frequency is not greater than the frequency threshold, the memory control circuit 23 may not activate this cooling-off period.

[0080] In one embodiment, after a preset time interval, the memory control circuit 23 may reset the hit count corresponding to each mapping item in the first cache queue and / or the second cache queue. For example, after one hour (i.e., a preset time interval), the memory control circuit 23 may subtract a preset value (also called a third preset value) from the hit count corresponding to each mapping item in the first cache queue and / or the second cache queue to reset the hit count corresponding to each mapping item in the first cache queue and / or the second cache queue. For example, the third preset value may be "1" or other positive integers. Furthermore, the preset time interval may be any length of time, and the present invention is not limited thereto. Alternatively, in one embodiment, the memory control circuit 23 may also restore the hit count corresponding to each mapping item in the first cache queue and / or the second cache queue to its initial value (e.g., "0") to reset the hit count corresponding to these mapping items.

[0081] In one embodiment, the memory control circuit 23 can also clear the third cache queue after a preset period of time. This prevents the third cache queue from being occupied by too much identification information corresponding to mapping items that have not been hit for a long time.

[0082] Figure 4 This is a schematic diagram illustrating the configuration of multiple cache queues in a buffer memory according to an embodiment of the present invention. Please refer to... Figure 4 The memory control circuit 23 can configure the cache queues 41-43 in the buffer memory 40. For example, the buffer memory 40 may include... Figure 2 Buffer memory 24 Figure 1The buffer memory 112 or buffer memory 24 is a combination of buffer memory 112 and buffer memory 24. Cache queues 41-43 may represent a first cache queue, a second cache queue, and a third cache queue, respectively. Furthermore, in the following embodiments, it is assumed that cache queue 41 can store at most two mapping items, but the invention is not limited thereto.

[0083] Figure 5 This is a schematic diagram illustrating the second compaction operation performed on a first buffer queue according to an embodiment of the present invention. Please refer to... Figure 5 Assume that the memory control circuit 23 obtains operation instructions 501(1) and 501(2) from the host system 11 in sequence. The numbers “1” and “2” marked above the operation instructions 501(1) and 501(2) reflect the order in which the operation instructions 501(1) and 501(2) are obtained (i.e., operation instruction 501(1) with number “1” is obtained first, and operation instruction 501(2) with number “2” is obtained next).

[0084] According to operation instructions 501(1) and 501(2), the memory control circuit 23 can sequentially place mapping items 502(1) and 502(2) into the cache queue 41. For example, mapping items 502(1) and 502(2) can be read from the memory module 122 and loaded into the buffer memory 40 according to operation instructions 501(1) and 501(2), respectively. Mapping item 502(1) corresponds to operation instruction 501(1), and mapping item 502(2) corresponds to operation instruction 501(2). It should be noted that in Figure 5 In the embodiment, the number of hits C(1) and C(2) corresponding to mapping terms 502(1) and 502(2) respectively are both recorded as "0".

[0085] After placing mapping items 502(1) and 502(2) into cache queue 41, assume that memory control circuit 23 obtains operation instruction 501(3) from host system 11. The number "3" marked above operation instruction 501(3) reflects that the order in which operation instruction 501(3) was obtained is after operation instruction 501(2) (number "2").

[0086] exist Figure 5 In this embodiment, it is assumed that neither of the mapping entries 502(1) nor 502(2) currently stored in the cache queue 41 has been hit by the operation instruction 501(3). Therefore, the memory control circuit 23 can read the mapping entry 502(3) corresponding to the operation instruction 501(3) from the memory module 122 and attempt to put the mapping entry 502(3) into the cache queue 41.

[0087] In response to the cache queue 41 being full (and a new mapping item being added to the cache queue 41), the memory control circuit 23 can determine that the trigger condition has been met. In response to the trigger condition being met, the memory control circuit 23 can decide to trigger a first cleanup operation and / or a second cleanup operation.

[0088] exist Figure 5 In this embodiment, in response to the fact that the hit counts C(1) and C(2) corresponding to mapping items 502(1) and 502(2) are both "0" (i.e., the hit counts C(1) and C(2) are both less than the second threshold), the memory control circuit 23 can determine both mapping items 502(1) and 502(2) as second candidate mapping items. Then, the memory control circuit 23 can prioritize determining mapping item 502(1) as the second mapping item according to the order in which mapping items 502(1) and 502(2) are placed into the cache queue 41. That is, the memory control circuit 23 can determine mapping item 502(1) as the mapping item that will be eliminated from the cache queue 41 (i.e., the second mapping item).

[0089] In response to mapping item 502(1) being identified as the second mapping item, in the second sorting operation, the memory control circuit 23 may remove mapping item 502(1) from the cache queue 41 and place the identification information 503(1) (i.e., index) corresponding to mapping item 502(1) into the cache queue 43. After removing mapping item 502(1) from the cache queue 41, the memory control circuit 23 may place mapping item 502(3) into the cache queue 41 to replace the removed mapping item 502(1). In addition, the memory control circuit 23 may record the hit count C(3) corresponding to mapping item 502(3) as "0".

[0090] Figure 6 This is a schematic diagram illustrating the performance of a first compaction operation on a first buffer queue according to an embodiment of the present invention. Please refer to... Figure 6 , continuing Figure 5 In this embodiment, it is assumed that the memory control circuit 23 obtains operation instruction 601 from the host system 11. The number "4" marked above operation instruction 601 indicates that operation instruction 601 was obtained after operation instruction 501(3) (number "3").

[0091] exist Figure 6 In this embodiment, it is assumed that the mapping item 502(2) currently stored in the cache queue 41 is hit by the operation instruction 601. Therefore, the memory control circuit 23 can directly read the mapping item 502(2) from the cache queue 41 and process the operation instruction 601 according to the mapping information carried by the mapping item 502(2).

[0092] On the other hand, in response to the mapping item 502(2) being hit by the operation instruction 601, the memory control circuit 23 can update the hit count C(2) corresponding to the mapping item 502(2). For example, the memory control circuit 23 can update the hit count C(2) from "0" to "1".

[0093] Furthermore, in response to the cache queue 41 being full, the memory control circuit 23 can determine that the trigger condition has been met. In response to the trigger condition being met and the number of hits C(2) being greater than a first threshold (e.g., "0"), the memory control circuit 23 can decide to trigger a first sorting operation and determine the mapping item 502(2) as the first mapping item.

[0094] In response to mapping item 502(2) being determined as the first mapping item, during the first sorting operation, memory control circuit 23 may move mapping item 502(2) from cache queue 41 to cache queue 42. At the same time, memory control circuit 23 may remove mapping item 502(2) from cache queue 41.

[0095] Figure 7 This is a schematic diagram illustrating the third compaction operation performed on the third buffer queue according to an embodiment of the present invention. Please refer to... Figure 7 , continuing Figure 6 In this embodiment, it is assumed that the memory control circuit 23 obtains operation instruction 701 from the host system 11. The number "5" marked above operation instruction 701 indicates that operation instruction 701 was obtained after operation instruction 601 (number "4").

[0096] exist Figure 7 In this embodiment, it is assumed that all mapping entries currently stored in cache queues 41 and 42 have not been hit by operation instruction 701. However, the mapping entry 502(1) corresponding to the identification information 503(1) currently stored in cache queue 43 (which has been removed) has been hit by operation instruction 701. In response to the mapping entry 502(1) being hit by operation instruction 701, the memory control circuit 23 can reread the mapping entry 502(1) corresponding to the identification information 503(1) from the memory module 122. Among them, the mapping entry 502(1) was previously stored in the cache queue 43. Figure 5 In some embodiments, it was removed from cache queue 41.

[0097] On the other hand, in response to the operation instruction 701 hitting the mapping item 502(1) and the identification information 503(1) corresponding to the mapping item 502(1) currently being stored in the cache queue 43, the memory control circuit 23 may trigger a third sorting operation. For example, in response to the operation instruction 701 hitting the mapping item 502(1), the memory control circuit 23 may check whether the identification information 503(1) corresponding to the mapping item 502(1) exists in the cache queue 43.

[0098] exist Figure 6 In this embodiment, in response to the presence of identification information 503(1) corresponding to mapping item 502(1) in the cache queue 43, the memory control circuit 23 may trigger a third sorting operation. In the third sorting operation, the memory control circuit 23 may place mapping item 502(1) into the cache queue 42.

[0099] Furthermore, in response to the operation instruction 701 hitting the mapping item 502(1) corresponding to the identification information 503(1), the memory control circuit 23 can also update the hit count C(1) corresponding to the mapping item 502(1). For example, the memory control circuit 23 can update the hit count C(1) from "0" to "1".

[0100] Figure 8 This is a schematic diagram illustrating the fourth compaction operation performed on the second buffer queue according to an embodiment of the present invention. Please refer to... Figure 8 , continuing Figure 7 In one embodiment, at a certain point in time, in response to the cache queue 42 being full, the memory control circuit 23 can subtract a preset value (e.g., "1") from the hit count corresponding to each mapping item in the cache queue 42 to obtain the adjusted hit count.

[0101] exist Figure 8 In this embodiment, it is assumed that after subtracting a preset value (e.g., "1") from the hit count C(1) corresponding to the mapping item 502(1) in the cache queue 42, the hit count C(1) corresponding to the mapping item 502(1) is updated to "0". Therefore, the memory control circuit 23 can determine the mapping item 502(1) as the mapping item to be evicted from the cache queue 42 (i.e., the third mapping item).

[0102] In response to mapping item 502(1) being identified as the third mapping item, in the fourth sorting operation, the memory control circuit 23 may remove mapping item 502(1) from the cache queue 42 and put the identification information 503(1) (i.e., the index) corresponding to mapping item 502(1) back into the cache queue 43. Furthermore, similar operational behaviors mentioned in the above embodiments can be repeated or slightly modified under the same or similar conditions to meet practical needs, and will not be repeated here.

[0103] Figure 9 This is a flowchart illustrating a mapping item management method according to an embodiment of the present invention. Please refer to... Figure 9In step S901, multiple cache queues are configured in the buffer memory. In step S902, at least one mapping item is placed into the first cache queue according to at least one operation instruction from the host system, wherein the at least one mapping item carries mapping information corresponding to the at least one operation instruction. In step S903, it is determined whether the triggering condition is met.

[0104] In response to the triggering condition being met, in step S904, one of a first reorganization operation and a second reorganization operation is performed on the first cache queue according to the order in which at least one mapping item enters the first cache queue and the hit count corresponding to the at least one mapping item. However, if the triggering condition is not met, the process can return to step S902 or perform other operations.

[0105] In step S905, during the first sorting operation, the first mapping item in the first cache queue is moved to the second cache queue. Furthermore, in step S906, during the second sorting operation, the second mapping item is removed from the first cache queue, and the identification information corresponding to the second mapping item is placed into the third cache queue.

[0106] However, Figure 9 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 9 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 9 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0107] In summary, the mapping item management method and storage device provided by this invention can store and manage mapping items and their identification information of different hit patterns by pre-setting multiple cache queues with different functions in the buffer memory. Furthermore, by storing mapping items with relatively low hit rates as identification information with smaller data volumes in the buffer memory, mapping items that have been removed from the buffer memory can be quickly restored to frequently queried mapping items when appropriate. This effectively increases the probability of currently cached mapping items in the buffer memory being hit, thereby steadily improving the data access performance of the storage device.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A mapping item management method, characterized in that, For a storage device, wherein the storage device includes a memory module, and the mapping item management method includes: Configure multiple cache queues in the buffer memory; According to at least one operation instruction from the host system, at least one mapping item is placed into the first cache queue of the plurality of cache queues, wherein the at least one mapping item carries mapping information corresponding to the at least one operation instruction; In response to the fulfillment of the triggering condition, one of a first reorganization operation and a second reorganization operation is performed on the first cache queue according to the order in which the at least one mapping item enters the first cache queue and the number of hits corresponding to the at least one mapping item; In the first sorting operation, the first mapping item in the first cache queue is moved to the second cache queue among the plurality of cache queues; and In the second sorting operation, the second mapping item in the first cache queue is removed, and the identification information corresponding to the second mapping item is placed into the third cache queue among the plurality of cache queues.

2. The mapping item management method according to claim 1 further includes: In response to at least one of the following: the first cache queue is full, the first cache queue is full and a new mapping item is to be added to the first cache queue, the number of hits meets a preset condition, and the cumulative number of host operations reaches a preset number, it is determined that the triggering condition has been met.

3. The mapping item management method according to claim 1, wherein the hit count reflects the number of times each of the at least one mapping item is hit after being placed in the first cache queue.

4. The mapping item management method according to claim 1, wherein the amount of data of the identification information corresponding to the second mapping item is less than the amount of data of the second mapping item itself.

5. The mapping item management method according to claim 1, wherein the step of performing one of the first reorganization operation and the second reorganization operation on the first cache queue according to the order in which the at least one mapping item enters the first cache queue and the hit count corresponding to the at least one mapping item includes: In response to the presence of a first candidate mapping item in the first cache queue, the first sorting operation is triggered, and the first mapping item is determined from the first candidate mapping item. The number of hits corresponding to the first candidate mapping item is greater than the first threshold value.

6. The mapping item management method according to claim 5, wherein the step of determining the first mapping item from the at least one first candidate mapping item includes: If there are at least two mapping items in the first candidate mapping items that correspond to the same number of hits, one of the at least two mapping items is determined as the first mapping item according to the order in which the at least two mapping items enter the first cache queue.

7. The mapping item management method according to claim 1, wherein the step of performing one of the first reorganization operation and the second reorganization operation on the first cache queue according to the order in which the at least one mapping item enters the first cache queue and the hit count corresponding to the at least one mapping item includes: In response to the presence of a second candidate mapping item in the first cache queue, the second sorting operation is triggered, and the second mapping item is determined from the second candidate mapping item. The number of hits corresponding to the second candidate mapping item is less than the second threshold value.

8. The mapping item management method according to claim 7, wherein the step of determining the second mapping item from the at least one second candidate mapping item includes: If there are at least two mapping items in the second candidate mapping items that correspond to the same number of hits, one of the at least two mapping items is determined as the second mapping item according to the order in which the at least two mapping items enter the first cache queue.

9. The mapping item management method according to claim 7, wherein the step of performing one of the first reorganization operation and the second reorganization operation on the first cache queue according to the order in which the at least one mapping item enters the first cache queue and the hit count corresponding to the at least one mapping item further includes: If the number of hits corresponding to all mapping entries in the first cache queue is not less than the second threshold, the number of hits corresponding to each mapping entry in the first cache queue is subtracted by a preset value to obtain the adjusted number of hits. as well as The second sorting operation is triggered based on the adjusted hit count.

10. The mapping item management method according to claim 1, further comprising: After adding the identification information corresponding to the second mapping item to the third cache queue, in response to the second mapping item being hit, a third sorting operation is performed on the third cache queue; as well as In the third sorting operation, the second mapping item is reread from the memory module and placed into the second cache queue.

11. The mapping item management method according to claim 1, further comprising: In response to the second cache queue being full, the hit count corresponding to each mapping item in the second cache queue is subtracted by a preset value to obtain the adjusted hit count; as well as Based on the adjusted hit count, in the fourth sorting operation, the third mapping item in the second cache queue is removed, and the identification information corresponding to the third mapping item is placed into the third cache queue.

12. The mapping item management method according to claim 1, further comprising: Monitor the update frequency of the queue contents for the multiple cache queues; In response to the update frequency exceeding a frequency threshold, a cooling-off period is activated; as well as During the cooling-off period, updates to the queue contents of the plurality of cache queues are paused.

13. The mapping item management method according to claim 1, further comprising: Every preset time interval, the hit count corresponding to each mapping item located in at least one of the first cache queue and the second cache queue is reset.

14. The mapping item management method according to claim 13, wherein the step of resetting the hit count corresponding to each mapping item located in at least one of the first cache queue and the second cache queue includes: Subtract a preset value from the number of hits corresponding to each mapping item located in at least one of the first cache queue and the second cache queue.

15. A storage device, characterized in that, include: Connection interface, used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory controller is used to execute the mapping item management method according to any one of claims 1 to 14.

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