Error upper bound device, determination method, medium, terminal and program product suitable for dynamic precision floating point multiply accumulate operation
By assigning error thresholds to floating-point multiplication and accumulation operations through feature acquisition and local threshold allocation modules, and combining the feedback mechanism of bit-based calculation and judgment modules, the problem of lacking a deterministic upper bound for error at the hardware level is solved. This enables the hierarchical decomposition and dynamic allocation of global precision targets, thereby improving the reliability and accuracy of the calculation results.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI GUANGYU XINCHEN TECHNOLOGY CO LTD
- Filing Date
- 2025-10-28
- Publication Date
- 2026-07-07
AI Technical Summary
In existing technologies, floating-point multiplication and accumulation operations lack deterministic upper bound determination of errors, making it difficult to guarantee the reliability and accuracy management of calculation results. In particular, at the hardware level, there is a lack of a hierarchical decomposition and dynamic allocation mechanism for global accuracy targets.
The design feature acquisition module collects the truncation compensation factor and accumulator tolerance factor of the operands. The local threshold allocation module allocates local error thresholds for the operation. The bit budget calculation module calculates the actual accuracy supply and demand of the error path, and the judgment and feedback module makes judgments and provides feedback to ensure that the error is within the global accuracy target range.
It implements deterministic error upper bound determination for each multiplication-accumulation operation, ensuring that the overall calculation result meets the global accuracy target, reducing error accumulation, and improving the reliability and accuracy management of the calculation result.
Smart Images
Figure CN121523639B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of floating-point arithmetic technology, and in particular to an error upper bound device, determination method, medium, terminal and program product suitable for dynamic precision floating-point multiplication and accumulation operations. Background Technology
[0002] In fields such as artificial intelligence accelerators, high-performance computing, and scientific simulations, floating-point multiplication and accumulation operations have become a bottleneck for system energy efficiency due to their enormous computational demands.
[0003] In pursuit of higher energy efficiency, some research has turned to approximate multipliers or dynamic bit-width truncation techniques. However, these methods mostly rely on probabilistic models or experience-based heuristics for truncation decisions, failing to provide deterministic, provable ULP (Unit in the Last Place) errors for each independent multiply-accumulate operation, which seriously affects the reliability of the computational results.
[0004] At the system level, existing solutions rely heavily on coarse-grained global control at the software or algorithm level for accuracy management. At the hardware level, there is a lack of a closed-loop control mechanism capable of progressively decomposing the global accuracy target and dynamically allocating it to each computational unit. This can easily lead to the accumulation and loss of control of local errors, making it difficult to ensure the overall numerical safety of the final output.
[0005] Therefore, it is necessary to provide an error upper bound device, determination method, medium, terminal and program product suitable for dynamic precision floating-point multiplication and accumulation operations to solve the above-mentioned problems existing in the prior art. Summary of the Invention
[0006] In view of the shortcomings of the prior art described above, the purpose of this application is to provide an error upper bound device, determination method, medium, terminal and program product suitable for dynamic precision floating-point multiplication and accumulation operations, so as to solve the technical problem that the prior art lacks a hardware mechanism that can provide a provable error upper bound at the level of item-by-item operation and can coordinate with the global precision target.
[0007] To achieve the above and other related objectives, the first aspect of this application provides an error upper bound device suitable for dynamic precision floating-point multiplication and accumulation operations, comprising:
[0008] The feature acquisition module is used to acquire the truncation compensation factor and accumulator tolerance factor of each operand based on the high-order segment of the mantissa of each input operand and the preset number of mantissa bits to retain.
[0009] The local threshold allocation module is used to allocate a local error threshold for the current multiply-accumulate operation based on the preset global error tolerance, number of remaining terms, remaining budget, energy consumption mode, and accumulator tolerance factor.
[0010] The bit-based budget calculation module is used to calculate the actual accuracy supply of each error path based on the number of mantissa bits to be retained, the truncation compensation factor, the accumulator tolerance factor, and the exponent difference. It also calculates the accuracy requirement of each error path based on the input number of effective mantissa bits, the local error threshold, and the safety margin.
[0011] The judgment and feedback module is used to make a judgment based on the actual accuracy supply and accuracy requirement calculated for each path; if all paths are passed, an accuracy pass signal is fed back; otherwise, an accuracy upgrade mechanism is triggered.
[0012] In some embodiments of the first aspect of this application, the feature acquisition module includes: a sticky bit and leading zero count acquisition unit, configured to obtain narrow window parameters and wide window parameters of each operand based on the high-order bits of the mantissa of each operand, perform a logical OR operation on the narrow window parameters to obtain sticky bits; and perform a leading zero count on the wide window parameters to obtain a leading zero count; a truncation compensation factor calculation unit, configured to calculate a truncation compensation factor for each operand based on the sticky bit, leading zero count, and mantissa retention bits of each operand; and an accumulator tolerance factor calculation unit, configured to calculate the final accumulator tolerance factor based on the input accumulator state sampling parameters and the set activation factor.
[0013] In some embodiments of the first aspect of this application, the local threshold allocation module includes: a data acquisition unit, configured to acquire a preset global error tolerance, number of remaining terms, remaining budget, energy consumption mode, and final accumulator tolerance factor; a global benchmark and dynamic adjustment calculation unit, configured to query a lookup table based on the acquired global error tolerance as the index address to obtain a global error threshold; and calculate a dynamic adjustment amount based on the acquired number of remaining terms and remaining budget; a mode bias acquisition unit, configured to select a corresponding bias value based on the input energy consumption mode; and a local error threshold calculation unit, configured to calculate the local error threshold of the current multiply-accumulate operation based on the global error threshold, dynamic adjustment amount, final accumulator tolerance factor, and bias value.
[0014] In some embodiments of the first aspect of this application, the bit-based budget calculation module includes: an error path analysis unit, used for asymmetric truncation based on the number of mantissa bits retained in the two operands, wherein the introduced error source paths include a first error path, a second error path, and a third error path; an error upper bound modeling unit, used for converting the errors introduced by the first error path, the second error path, and the third error path into exponential form to establish error upper bound models for the first error path, the second error path, and the third error path, respectively; a total error upper bound and judgment condition establishment unit, used for establishing a total error upper bound and judgment condition based on the error upper bound models of the first error path, the second error path, and the third error path; and a three-way bit-based budget calculation unit, used for calculating the bit-based budgets for the first error path, the second error path, and the third error path, respectively, based on the established total error upper bound and judgment condition.
[0015] In some embodiments of the first aspect of this application, a statistics and calibration module is also included, which is used to statistically analyze the distribution information obtained through calculation, the total number of upgrade events, and the distribution histogram of safety margin, and to perform calibration based on the statistically obtained distribution information, the total number of upgrade events, and the distribution histogram of safety margin.
[0016] In some embodiments of the first aspect of this application, a counter is used to count the total number of distribution information and upgrade events obtained through calculation.
[0017] To achieve the above and other related objectives, a second aspect of this application provides a method for determining the upper bound of errors in dynamic precision floating-point multiplication and accumulation operations, comprising:
[0018] Based on the high-order bits of the mantissa of each input operand and the preset number of mantissa bits to retain, the truncation compensation factor and accumulator tolerance factor of each operand are collected.
[0019] Based on the preset global error tolerance, number of remaining terms, remaining budget, energy consumption mode, and accumulator tolerance factor, a local error threshold is assigned to the current multiply-accumulate operation;
[0020] The actual accuracy supply of each error path is calculated based on the number of mantissa bits retained, the truncation compensation factor, the accumulator tolerance factor, and the exponent difference. The accuracy requirement of each error path is calculated based on the input number of effective mantissa bits, the local error threshold, and the safety margin.
[0021] The accuracy supply and accuracy requirement are determined based on the actual accuracy supply and accuracy requirement calculated for each path; if all paths are successful, an accuracy pass signal is fed back; otherwise, an accuracy upgrade mechanism is triggered.
[0022] To achieve the above and other related objectives, a third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method.
[0023] To achieve the above and other related objectives, a fourth aspect of this application provides a computer program product comprising computer program code that, when executed on a computer, causes the computer to implement the method.
[0024] To achieve the above and other related objectives, a fifth aspect of this application provides an electronic terminal, including a memory, a processor, and a computer program stored in the memory; the processor executes the computer program to implement the method.
[0025] As described above, the error upper bound device, determination method, medium, terminal, and program product applicable to dynamic precision floating-point multiplication and accumulation operations of this application have the following beneficial effects:
[0026] This application employs a feature acquisition module to collect truncation compensation factors and accumulator tolerance factors for each operand. Based on the accumulator tolerance factors collected by the feature acquisition module, a local threshold allocation module assigns a local error threshold to the current multiply-accumulate operation. Furthermore, a bit-based budget calculation module calculates the actual precision supply and precision requirements for each error path. A judgment and feedback module then performs judgment and feedback based on the actual precision supply and precision requirements of each error path, determining whether the preset asymmetric truncation operation for each operand meets the error requirements. Without relying on full-precision comparison, this application can provide a deterministic upper bound for the truncation error of each multiply-accumulate operation, establishing a budget allocation and closed-loop control between the local error threshold and the global error level, ensuring that the overall calculation result meets the global precision target. Attached Figure Description
[0027] Figure 1 The diagram shown is a block diagram of an error upper bound device applicable to dynamic precision floating-point multiplication and accumulation operations in one embodiment of this application.
[0028] Figure 2 The diagram shows the workflow of an error upper bound device applicable to dynamic precision floating-point multiplication and accumulation operations in one embodiment of this application.
[0029] Figure 3 The diagram shown is a flowchart illustrating an error upper bound determination method applicable to dynamic precision floating-point multiplication and accumulation operations in one embodiment of this application.
[0030] Figure 4 The diagram shown is a structural schematic of an electronic terminal according to an embodiment of this application. Detailed Implementation
[0031] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.
[0032] In the embodiments of this application, terms such as "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, "first XX" and "second XX" are merely used to distinguish different XXs and do not limit their order. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order, and that "first" and "second" do not necessarily imply that they are different.
[0033] It should be noted that, in the embodiments of this application, the words "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.
[0034] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.
[0035] Before providing a further detailed description of the present invention, the nouns and terms used in the embodiments of the present invention are explained, and the nouns and terms used in the embodiments of the present invention are subject to the following interpretations:
[0036] <1> ULP (Unit in the Last Place): Represents the distance between a floating-point number and its nearest significant floating-point number, which is the value represented by the last significant bit (the least significant bit of the mantissa) of the floating-point number. In computer science, it is used to evaluate the precision and error of floating-point operations.
[0037] <2> LZC (Leading Zero Count): refers to the number of consecutive "0"s in a binary number, starting from the most significant bit, until the first "1" is encountered.
[0038] <3> The POPC (Population Count) operation calculates how many bits are 1 in the binary representation of an integer.
[0039] <4> A look-up table (LUT) is a data structure that stores the mapping between data items and their associated output values.
[0040] <5> The IEEE-754 standard defines the representation and operation rules of floating-point numbers.
[0041] <6> Unpacking: The process of extracting the components of a floating-point number from its stored binary format, namely the sign bit, exponent part, and mantissa part.
[0042] To facilitate understanding of the embodiments of this application, in conjunction with Figure 1 and Figure 2 Detailed explanation. Figure 1 A block diagram illustrating an error upper bound device for dynamic precision floating-point multiplication and accumulation operations is shown in an embodiment of this application. Figure 2 This document illustrates the workflow of an error upper bound device for dynamic precision floating-point multiplication and accumulation operations in an embodiment of this application. The error upper bound device 100 for dynamic precision floating-point multiplication and accumulation operations in this embodiment includes: a feature acquisition module 101, a local threshold allocation module 102, a bit-based calculation module 103, and a judgment and feedback module 104.
[0043] The feature acquisition module 101 is used to acquire the truncation compensation factor and accumulator tolerance factor of each operand based on the high-order segment of the mantissa of each input operand and the preset number of mantissa bits to retain.
[0044] In some embodiments of this application, the feature acquisition module 101 includes: a sticky bit and leading zero count acquisition unit, used to obtain the narrow window parameter and wide window parameter of each operand based on the high-order segment of the mantissa of each operand, perform a logical OR operation on the narrow window parameter to obtain the sticky bit; and perform a leading zero count on the wide window parameter to obtain the leading zero count; a truncation compensation factor calculation unit, used to calculate the truncation compensation factor of each operand based on the sticky bit, leading zero count, and mantissa retention bit of each operand; and an accumulator tolerance factor calculation unit, used to calculate the final accumulator tolerance factor based on the input accumulator state sampling parameters and the set activation factor.
[0045] The specific process by which the sticky bit and leading zero count acquisition unit acquires the sticky bit and leading zero count is as follows:
[0046] For the two input operands ( , ) and accumulator ( The unpacking operation is performed, which involves breaking the data down into sign, exponent, and mantissa bits conforming to the IEEE-754 standard, and calculating the exponent difference. The formula is as follows:
[0047] ;Formula (1)
[0048] ;Formula (2)
[0049] in, Operands The index; Operands The index; Represents product The original index; This represents the exponent of the accumulator.
[0050] The specific process for extracting the high-order bits of the mantissa of two operands is as follows: Pre-set the operations for each operand (… , Asymmetric truncation is performed, and the number of operands is preset. The number of decimal places to retain is denoted as , operand The number of decimal places to retain is denoted as Extract the operands based on their complete mantissa digits and the preset number of mantissa digits to retain. , The high-order segment of the last digit.
[0051] Based on the extracted high-order bits of the mantissas of the two operands (a and b), the sticky bits s and leading zero count z (LZC) of operands a and b are calculated respectively. The specific process is as follows:
[0052] The narrow window parameters for each operand are obtained based on the extracted high-order bits of the mantissa of each operand. ) and wide window parameters ( The narrow window parameter represents the highest k bits in the truncated portion of the mantissa high-order segment, used for fast detection of sticky bits; the wide window parameter represents the highest few bits of the retained portion and the entire truncated portion, used for leading zero counting. The narrow window width is typically 2 to 3 bits, and the wide window width is typically 4 to 8 bits. The truncated window width k can be dynamically configured through the Control and Status Registers (CSR).
[0053] A logical OR operation is performed on all bits of the narrow window parameter to quickly determine whether the truncated high-order bits are all zeros. If sticky=1, it means that there is at least one 1 in the region, and truncation may introduce a large error; if sticky=0, it means that the window is discarded with all zeros. The specific formula is as follows:
[0054] ;Formula (3)
[0055] Count leading zeros for all bits of the wide window parameter. The specific formula is as follows:
[0056] ;Formula (4)
[0057] The stickiness bits and leading zero counts of operands a and b are calculated according to formulas (3) and (4) respectively, and are used as the truncation compensation factor for subsequent operand a. , Cutoff compensation factor for operand b The calculation.
[0058] The truncation compensation factor calculation unit calculates the truncation compensation factor for operand a. , Cutoff compensation factor for operand b The specific process is as follows:
[0059] Cutoff compensation factor for operand a , Cutoff compensation factor for operand b Based on the actual data characteristics of the truncated portion, the upper bound of the error is dynamically tightened, reflecting the "cleanliness" of the discarded window. The cleaner the window, the smaller the actual error.
[0060] It should be noted that the following text will use the truncation compensation factor of operand a. The specific derivation process is illustrated with an example, showing the truncation compensation factor for operand b. The specific derivation can be obtained similarly. Specifically, the number of bits discarded from operand a. The formula for obtaining it is as follows:
[0061] ;Formula (5)
[0062] in, This indicates the number of significant mantissa bits in the output, i.e., the number of significant mantissa bits (including hidden bits) required by the output result format. For example, FP32 single precision is 24 bits, FP64 double precision is 53 bits, and FP16 half precision is 11 bits. This indicates the number of mantissas to retain for operand a, i.e., the actual number of mantissas retained for operand a after truncation at the current precision level. This represents the gap between the required precision of the target and the precision actually provided by 'a'. The smaller the difference between the two, the closer the number of mantissa bits retained for operand 'a' is to the result requirement, i.e., the low error risk. The larger the difference between the two, the more low bits are discarded for operand 'a', i.e., the high potential upper bound risk of error.
[0063] Leading zero count z (LZC) represents the number of consecutive 0s counted starting from the most significant bit within the discard window; z ranges from 0 to 1. between.
[0064] The specific derivation process is as follows: If the entire discard window is 0 (s=0), it means that all discarded bits are 0, and the actual truncation error is 0. In this case, To obtain the maximum compensation value; if there is a 1 in the discard window (s=1), it means that the discarded bits contain at least one 1, which means that truncation does introduce error, in this case To compensate for truncation, the error risk of each truncation is dynamically assessed by analyzing the sticky bit s and the leading zero count z in real time. Thus, the truncation compensation factor for operand a is obtained. , Cutoff compensation factor for operand b .
[0065] To determine how many bits the product error can be reduced by aligning the accumulator and finally rounding it, an accumulator tolerance factor is introduced. The specific process by which the accumulator tolerance factor calculation unit obtains the accumulator tolerance factor is as follows:
[0066] Input the accumulator state sampling parameters into the accumulator tolerance factor calculation unit ( [w]), which represents bits 0 to w-1 of the accumulator mantissa. The sampling window width w indicates that the sampling area is located in the least significant bit portion of the accumulator mantissa, typically 6 to 8 bits.
[0067] Count leading zeros on the input accumulator state sampling parameters. This refers to the number of consecutive zeros counted from the least significant bit of these w bits towards the higher bits. The specific formula is as follows:
[0068] ;Formula (6)
[0069] Furthermore, a POPC (Population Count) operation is performed on the input accumulator state sampling parameters to obtain... This refers to counting how many bits are 1 in the lowest w bits of the accumulator mantissa, reflecting the noise density in the low-order region of the accumulator. The specific formula is as follows:
[0070] ;Formula (7)
[0071] by and As the union address, a configurable lookup table (LUT) is queried to find the initial accumulator tolerance factor. This value is an integer within the range [-2, +3]. If it is positive, the truncation can be relaxed; if it is negative, the truncation is tightened. The formula is as follows:
[0072] ;Formula (8)
[0073] Set activation conditions and determine activation factors. Its value is either 0 or 1, and the specific formula is as follows:
[0074] ;Formula (9)
[0075] in, Indicating targeting The minimum threshold for a continuous clean region; Indicating targeting The maximum permissible noise density threshold.
[0076] Based on the activation factor, obtain the final accumulator tolerance factor. The formula is as follows:
[0077] ;Formula (10)
[0078] Calculated based on formulas (8) and (10) and This information is passed to subsequent steps to dynamically adjust the local error threshold. .in, , The contents of the lookup table are configured by CSR.
[0079] By dynamically tightening the truncation window using viscous bits and leading zero counts, and by introducing a tolerance factor to correct the tolerance, the estimation of the upper bound of the error is made more accurate, avoiding underestimation of risk or excessive conservatism, and ensuring the stability and reliability of the calculation results.
[0080] The local threshold allocation module 102 is used to allocate a local error threshold for the current multiply-accumulate operation based on the preset global error tolerance, number of remaining terms, remaining budget, energy consumption mode and accumulator tolerance factor.
[0081] In some embodiments of this application, the local threshold allocation module includes: a data acquisition unit, used to acquire a preset global error tolerance, number of remaining terms, remaining budget, energy consumption mode, and final accumulator tolerance factor; a global benchmark and dynamic adjustment calculation unit, used to query a lookup table based on the acquired global error tolerance as the index address to obtain a global error threshold; and to calculate a dynamic adjustment amount based on the acquired number of remaining terms and remaining budget; a mode bias acquisition unit, used to select a corresponding bias value based on the input energy consumption mode; and a local error threshold calculation unit, used to calculate the local error threshold of the current multiply-accumulate operation based on the global error threshold, dynamic adjustment amount, final accumulator tolerance factor, and bias value.
[0082] The data acquisition unit acquires the preset global error tolerance, number of remaining terms, remaining budget, energy consumption mode, and final accumulator tolerance factor. Specifically, the global error tolerance required for the entire computation task is predefined. [1:0]), which is a 2-bit index value, measured using ULP. The remaining number of items is obtained through real-time status ( [N1:0]), which is the number of remaining dot product terms to be processed; and the remaining budget ( [N2:0]), which represents the remaining error budget. The remaining error budget is expressed in Q fixed-point format. The energy consumption mode configured by CSR is also obtained. [1:0]), which is a 2-bit mode selection signal. The final accumulator tolerance factor calculated by formula (10) also needs to be obtained synchronously. .
[0083] The specific process by which the global baseline and dynamic adjustment calculation unit calculates the global error threshold and dynamic adjustment is as follows:
[0084] by For the address, query a lookup table to obtain the global error threshold. ,as follows:
[0085] ;Formula (11)
[0086] in, Indicates the upper limit of the global error; This represents the binary logarithm and rounding down operation, which is essentially bit-based global error upper limit.
[0087] The dynamic adjustment is calculated using a dedicated lookup table and a piecewise linear approximator. This reflects the budget averaged over each remaining item, and the value is limited to the range of [-6, +6], as shown in the following formula:
[0088] ;Formula (12)
[0089] The result calculated by formula (12) If the value is greater than 0, it indicates that the budget is sufficient and the local threshold can be relaxed; if A value less than 0 indicates a tight budget, requiring a tightening of the threshold.
[0090] The local error threshold calculation unit is the local error threshold assigned to the current multiply-accumulate operation. The calculation formula is as follows:
[0091] ;Formula (13)
[0092] Where, bias(e_mode) represents the bias value under different energy consumption modes; This indicates that the summation result within the parentheses will be saturated.
[0093] Based on formula (13), the local error threshold of each term (dot1) of the current multiplication-accumulation operation is finally obtained. This information is used in subsequent calculation steps as a standard for judging the accuracy of this multiplication-accumulation operation. By introducing a dynamic threshold allocation mechanism for the number of remaining terms and the remaining budget, it is ensured that even in large-scale matrix operations, the overall calculation result still meets the global accuracy level set by the device.
[0094] The bit-based budget calculation module 103 is used to calculate the actual accuracy supply of each error path based on the number of mantissa bits retained, the truncation compensation factor, the accumulator tolerance factor, and the exponent difference, and to calculate the accuracy requirement of each error path based on the input number of effective mantissa bits, the local error threshold, and the safety margin.
[0095] The judgment and feedback module 104 is used to make a judgment based on the actual accuracy supply and accuracy requirement calculated for each path; if all paths are passed, an accuracy pass signal is fed back; otherwise, an accuracy upgrade mechanism is triggered.
[0096] In some embodiments of this application, the bit-based budget calculation module includes: an error path analysis unit, used for asymmetric truncation based on the number of mantissa bits retained in the two operands, where the introduced error sources include a first error path, a second error path, and a third error path; an error upper bound modeling unit, used for converting the errors introduced by the first, second, and third error paths into exponential form to establish error upper bound models for the first, second, and third error paths respectively; a total error upper bound and decision condition establishment unit, used for establishing a total error upper bound and decision condition based on the error upper bound models of the first, second, and third error paths; and a three-way bit-based budget calculation unit, used for calculating the bit-based budgets for the first, second, and third error paths respectively based on the established total error upper bound and decision condition.
[0097] The specific analysis process of the error path analysis unit is as follows: based on the preset operands Number of digits retained in the mantissa , operand Number of digits retained in the mantissa For operands respectively and operands The truncation process introduces three error paths: the first, the second, and the third. The first error path, A, involves only truncating the operands. The introduced error; the second error path B is to only truncate the operands. The introduced error; the third error path AB is for simultaneously truncating operands. , The cross-error term is generated by multiplying the results. The error components of the first error path A, the second error path B, and the third error path AB are converted to the ULP scale.
[0098] The specific formulas for converting the errors introduced by the first error path A, the second error path B, and the third error path AB into exponential form in the error upper bound modeling unit are as follows:
[0099] ;Formula (14)
[0100] ;Formula (15)
[0101] ;Formula (16)
[0102] in, Indicates the operands The upper bound of the final error introduced by truncation (measured in bits); Indicates the operands The upper bound of the final error introduced by truncation (measured in bits); Indicates simultaneous truncation of operands , The final upper bound of the introduced cross error term (measured in bits). , , Represents constant residual. , , This is used to correct rounding RNE, amplitude boundaries, or to offset amplification effects. For example, if truncation is used, the constant margin is at least 1; if the most recent rounding is used, the constant margin can be 0 or 1 as a safety factor; in the accumulator, carry can cause error propagation, therefore... The default value is 1 to 2.
[0103] The upper bound of the total error adopts a conservative approach of adding 1 bit to the dominant term. The formulas for establishing the upper bound of the total error and the decision criteria are as follows:
[0104] ;Formula (17)
[0105] in, This represents the local error threshold for the current item-by-item (dot1); This indicates the error magnitude converted to bits; "+1" indicates that in the ULP scale, a 1-bit safety margin is usually added to the conservative upper bound to ensure a safety threshold. This means that if any error path exceeds the limit, the whole operation is not safe. The left side of equation (17) represents the maximum possible error (measured in bits), and the right side represents the allowable error threshold. If equation (17) is true, it means that the current truncation operation is safe and meets the accuracy requirements of the current multiplication-accumulation operation; otherwise, it is necessary to recalculate or improve the accuracy.
[0106] The error and threshold judgment in formula (17) are completely rewritten as addition and comparison, so that the judgment can be completed in the hardware with a very small number of gates and a single cycle. Finally, the most stringent one of the three error paths is selected. The specific calculation process of the three-way bit budget calculation unit is as follows:
[0107] If formula (17) holds, then each error path satisfies Substitute and rearrange the terms, taking the first error path A as an example:
[0108] ;Formula (18)
[0109] ;Formula (19)
[0110] Similarly, the formulas for the second error path B and the third error path AB are as follows:
[0111] ;Formula (20)
[0112] ;Formula (21)
[0113] Then, integerization (bit estimation) and conservative conversion are performed to convert the constant margin C_X into a safety margin of integer M_X. ), using CSR configuration, which is 1 to 3 bits, and defined The final three-bit budget formulas are as follows:
[0114] ;Formula (22)
[0115] ;Formula (23)
[0116] ;Formula (24)
[0117] in, ( This indicates the actual accuracy supply for the three error paths; ( This indicates the accuracy requirements for the three error paths; ( ) represents the safety margin added for the three error paths, where C_ ( The remainder is converted to integer bits for rounding, offsetting risk amplification, etc. In formulas (22), (23), and (24), the left side represents the number of bits available, and the right side represents the number of bits needed. Only when the left-hand equation is greater than or equal to the right-hand equation is it safe; otherwise, the precision needs to be upgraded. Specifically, if This means that the first error path A passes through ( The error of the first error path A is within a controllable range; if This means that the second error path B passes through ( The error of the second error path B is within a controllable range; if This indicates that the third error path AB passes through ( The error of the third error path AB is within a controllable range, and only when all three paths pass through... Only if the current truncation asymmetric scheme passes will the output be output. That is, the preset asymmetric truncation operation is performed on the input end to ensure that the calculation error meets the requirements. In other words, the current precision level is acceptable and subsequent multiplication and accumulation operations can be performed at the current precision level; otherwise, the precision upgrade mechanism is triggered.
[0118] Error determination is performed by adding and comparing bit-based budget formulas (22), (23) and (24). The logic is simple, the latency is low, it can be parallelized with the multiplication pipeline, and it does not affect the timing of the main path. It is suitable as a dedicated IP core to be integrated into the accelerator.
[0119] The results were calculated based on formulas (22), (23) and (24). ( )and ( Define the safety margins for the three error paths. , , This indicates how much safety margin the current truncation scheme has relative to the failure boundary, as shown in the following formula:
[0120] ;Formula (25)
[0121] ;Formula (26)
[0122] ;Formula (27)
[0123] The decision strategy is to take the minimum safety margin, which yields... This value represents the safety margin (in bits) between the current scheme and failure, and is used for statistics and online calibration.
[0124] Simultaneously output This value represents the most stringent path. The most stringent error path among the three error paths must also satisfy formula (22) or formula (23) or formula (24), then the feedback accuracy is passed through the signal; otherwise, the recalculation mechanism is triggered. This judgment method only includes addition, subtraction and comparison, and removes multiplication, division and dynamic shift.
[0125] In some embodiments of this application, the error upper bound device applicable to dynamic precision floating-point multiplication and accumulation operations further includes a statistics and calibration module, which is used to statistically analyze the distribution information obtained through the operation, the total number of upgrade events, and the distribution histogram of the safety margin, and to perform calibration based on the statistically obtained distribution information, the total number of upgrade events, and the distribution histogram of the safety margin.
[0126] In some embodiments of this application, a counter is used to count the total number of distribution information and upgrade events obtained through calculation.
[0127] Specifically, to obtain the aforementioned , , Optional acquisition , , , A counter group (CNT_HITS[]) is designed to accumulate the passed operations according to the precision level or error source to obtain the distribution information of the passed operations; a counter (CNT_ESCALATE) is added to each event that triggers a precision upgrade to obtain the total number of upgrade events; the results of each operation are then calculated. Values are categorized into the corresponding intervals (bin) to obtain a distribution histogram of the safety margin (HIST_MARGIN[bin]).
[0128] Based on the aforementioned distribution information obtained through calculation, the total number of upgrade events, and the distribution histogram of safety margin, a conditional judgment is made if... If the rate of decline is too fast, it means that the average budget consumed per operation is too high and the local threshold is too loose. If the recalculation frequency exceeds the threshold, it means that the upgrade frequency exceeds the preset threshold, indicating that the current configuration is too aggressive. In this case, it is necessary to increase the safety margin or tighten the local error threshold.
[0129] The values of the internal counters CNT_HITS, CNT_ESCALATE, and histogram HIST_MARGIN are mapped to read-only registers for a stats bus. Optionally, when the calibration strategy determines that parameters need to be adjusted, a pulse signal is issued to write the calculated new parameters into the corresponding CSR, thereby completing an online calibration.
[0130] In some embodiments of this application, the error upper bound device applicable to dynamic precision floating-point multiplication and accumulation operations also includes some peripheral interfaces, such as interfaces for accessing clock or test clock signals, data signals (in parallel with multiplication / accumulation), window observation inputs, global budget inputs, control / status signals, statistical signals, and configuration and status register interfaces.
[0131] The error upper bound device for dynamic precision floating-point multiply-accumulate operations in this application embodiment provides a provable upper bound for the error of each multiply-accumulate operation term (dot1) at the current truncation level without performing a full precision comparison, and determines whether the local threshold and global ULP level target are met. If necessary, it triggers upgrade playback and supports asymmetric truncation to flexibly handle different truncation bits for the multiplicand and multiplier. Combined with local and global budget allocation, it can achieve a trade-off between accuracy and energy efficiency as needed to adapt to application scenarios with different data distributions. Furthermore, it precisely controls the error range in local determination, ensuring that most dot terms pass on the first attempt, reducing unnecessary upgrade recalculations; and it provides online statistics and adaptive parameter tuning mechanisms to further reduce playback overhead.
[0132] Figure 3 This is a flowchart illustrating the error upper bound determination method for dynamic precision floating-point multiplication and accumulation operations provided in this application embodiment. Figure 3 As shown, the error upper bound determination method applicable to dynamic precision floating-point multiplication and accumulation operations includes the following steps:
[0133] Step S31: Based on the high-order segments of the mantissa of each input operand and the preset number of mantissa bits to retain, collect the truncation compensation factor and accumulator tolerance factor of each operand.
[0134] Step S32: Based on the preset global error tolerance, number of remaining terms, remaining budget, energy consumption mode, and accumulator tolerance factor, assign a local error threshold to the current multiply-accumulate operation;
[0135] Step S33: Calculate the actual accuracy supply of each error path based on the number of mantissas retained, the truncation compensation factor, the accumulator tolerance factor, and the exponent difference. Calculate the accuracy requirement of each error path based on the input number of effective mantissas, the local error threshold, and the safety margin.
[0136] Step S34: Determine the actual accuracy supply and accuracy requirement calculated for each path; if all paths pass, a precision pass signal is fed back; otherwise, the precision upgrade mechanism is triggered.
[0137] It should be understood that the error upper bound determination method for dynamic precision floating-point multiplication and accumulation operations in this embodiment can realize the function of the error upper bound device for dynamic precision floating-point multiplication and accumulation operations described above. For the sake of brevity, it will not be described again here.
[0138] It should also be understood that the module division in the embodiments of this application is illustrative and only represents a logical functional division; in actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.
[0139] Figure 4 This is a schematic block diagram of the electronic terminal provided in an embodiment of this application. Figure 4 As shown, the electronic terminal 400 includes at least one processor 401, a memory 402, at least one network interface 403, and a user interface 405. The various components in the electronic terminal 400 are coupled together via a bus system 404. It is understood that the bus system 404 is used to implement communication between these components. In addition to a data bus, the bus system 404 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in… Figure 4 The general will label all buses as bus systems.
[0140] The user interface 405 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.
[0141] It is understood that memory 402 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.
[0142] In this embodiment of the invention, the memory 402 is used to store various types of data to support the operation of the electronic terminal 400. Examples of this data include: any executable program for operation on the electronic terminal 400, such as the operating system 4021 and application programs 4022; the operating system 4021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 4022 may contain various applications, such as a media player, browser, etc., for implementing various application services. The methods provided in this embodiment of the invention can be included in the application program 4022.
[0143] The methods disclosed in the above embodiments of the present invention can be applied to processor 401, or implemented by processor 401. Processor 401 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 401 or by instructions in the form of software. The processor 401 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 401 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. General-purpose processor 401 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in a memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.
[0144] In an exemplary embodiment, the electronic terminal 400 may be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs) to execute the aforementioned method.
[0145] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes: computer program code, which, when run on a computer, causes the computer to execute... Figure 3 The method in the illustrated embodiment.
[0146] According to the method provided in the embodiments of this application, this application also provides a computer-readable storage medium storing program code, which, when executed on a computer, causes the computer to perform... Figure 3 The method in the illustrated embodiment.
[0147] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).
[0148] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.
[0149] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0150] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0151] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0152] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0153] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs, DVDs), or semiconductor media (e.g., solid-state disks, SSDs, etc.).
[0154] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0155] In summary, addressing the technical problem of the lack of a hardware mechanism in existing technologies that can provide a provable upper bound for error at the item-by-item operation level and coordinate with the global precision target, this application provides an error upper bound device, determination method, medium, terminal, and program product suitable for dynamic precision floating-point multiply-accumulate operations. It designs a feature acquisition module to collect the truncation compensation factor and accumulator tolerance factor of each operand; based on the accumulator tolerance factor collected by the feature acquisition module, a local threshold allocation module assigns a local error threshold to the current multiply-accumulate operation; and a bit-based calculation module calculates the actual precision supply and precision requirement for each error path. Finally, a determination and feedback module performs determination and feedback based on the actual precision supply and precision requirement of each error path. This application, without relying on full-precision comparison, can provide a deterministic upper bound for the truncation error of each multiply-accumulate operation. A budget allocation and closed-loop control between local error thresholds and global error levels are established to ensure that the overall calculation results meet the global accuracy target. Furthermore, it supports asymmetric truncation of the multiplicand and multiplier, guaranteeing a more flexible trade-off between accuracy and energy efficiency. Simultaneously, an accumulator tolerance factor is introduced as a decision factor, making error assessment more consistent with actual numerical sensitivity and avoiding over-conservatism or underestimation of risk. While ensuring numerical reliability, dynamic gating of partial products and compressed trees is implemented, significantly reducing hardware power consumption. Furthermore, through statistical and online calibration mechanisms, the decision parameters are adaptively adjusted according to the runtime error distribution, further reducing the playback rate and increasing throughput. In short, this application not only improves computational efficiency and energy efficiency but also enhances numerical stability, significantly reducing costs while maintaining computational quality. It is suitable for AI accelerators, scientific computing chips, and other scenarios requiring efficient and reliable floating-point operations. Furthermore, the number of clock cycles required from the input data entering the error upper bound device for dynamic precision floating-point multiplication and accumulation operations in this application to the output determination and feedback result is short. Each step only involves addition, comparison, and lookup table lookup, resulting in a very shallow logic depth. Moreover, it operates completely in parallel with Booth encoding and partial product compression trees, without slowing down the multiplier's clock frequency. Therefore, this application effectively overcomes the various shortcomings of the prior art and possesses high industrial applicability.
[0156] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.
Claims
1. An error upper bound device suitable for dynamic precision floating-point multiplication and accumulation operations, characterized in that, include: The feature acquisition module is used to acquire the truncation compensation factor and accumulator tolerance factor of each operand based on the high-order segment of the mantissa of each input operand and the preset number of mantissa bits to retain. The local threshold allocation module is used to allocate a local error threshold for the current multiply-accumulate operation based on the preset global error tolerance, number of remaining terms, remaining budget, energy consumption mode, and accumulator tolerance factor. The bit-based budget calculation module is used to calculate the actual accuracy supply of each error path based on the number of mantissa bits to be retained, the truncation compensation factor, the accumulator tolerance factor, and the exponent difference. It also calculates the accuracy requirement of each error path based on the input number of effective mantissa bits, the local error threshold, and the safety margin. The bit-based budget calculation module includes: an error path analysis unit, used for asymmetric truncation based on the number of mantissas retained in the two operands, introducing error sources including a first error path, a second error path, and a third error path; an error upper bound modeling unit, used for converting the errors introduced by the first, second, and third error paths into exponential form to establish error upper bound models for the first, second, and third error paths respectively; a total error upper bound and decision condition establishment unit, used for establishing a total error upper bound and decision condition based on the error upper bound models of the first, second, and third error paths; and a three-way bit-based budget calculation unit, used for calculating the bit-based budgets for the first, second, and third error paths respectively based on the established total error upper bound and decision condition. The judgment and feedback module is used to make a judgment based on the actual accuracy supply and accuracy requirement calculated for each path; if all paths are passed, an accuracy pass signal is fed back; otherwise, an accuracy upgrade mechanism is triggered.
2. The error upper bound device for dynamic precision floating-point multiplication and accumulation operations according to claim 1, characterized in that, The feature acquisition module includes: The sticky bit and leading zero count acquisition unit is used to obtain the narrow window parameter and wide window parameter of each operand based on the high-order segment of the mantissa of each operand, perform a logical OR operation on the narrow window parameter to obtain the sticky bit, and perform a leading zero count on the wide window parameter to obtain the leading zero count. The truncation compensation factor calculation unit is used to calculate the truncation compensation factor of each operand based on the sticky bits, leading zero count, and mantissa retention bits of each operand. The accumulator tolerance factor calculation unit is used to calculate the final accumulator tolerance factor based on the input accumulator state sampling parameters and the set activation factor.
3. The error upper bound device for dynamic precision floating-point multiplication and accumulation operations according to claim 2, characterized in that, The local threshold allocation module includes: The data acquisition unit is used to acquire the preset global error tolerance, number of remaining items, remaining budget, energy consumption mode, and final accumulator tolerance factor. The global baseline and dynamic adjustment calculation unit is used to look up the lookup table based on the obtained global error tolerance as the index address to obtain the global error threshold; and to calculate the dynamic adjustment based on the obtained number of remaining items and remaining budget. The mode bias acquisition unit is used to select the corresponding bias value based on the input energy consumption mode. The local error threshold calculation unit is used to calculate the local error threshold of the current multiply-accumulate operation based on the global error threshold, dynamic adjustment amount, final accumulator tolerance factor, and bias value.
4. The error upper bound device for dynamic precision floating-point multiplication and accumulation operations according to claim 1, characterized in that, It also includes a statistics and calibration module, which is used to statistically analyze the distribution information obtained through calculation, the total number of upgrade events, and the distribution histogram of safety margin, and to perform calibration based on the statistically obtained distribution information, the total number of upgrade events, and the distribution histogram of safety margin.
5. The error upper bound device for dynamic precision floating-point multiplication and accumulation operations according to claim 4, characterized in that, A counter is used to count the distribution information and the total number of upgrade events obtained through the calculation.
6. A method for determining the upper bound of error in dynamic precision floating-point multiplication and accumulation operations, characterized in that, include: Based on the high-order bits of the mantissa of each input operand and the preset number of mantissa bits to retain, the truncation compensation factor and accumulator tolerance factor of each operand are collected. Based on the preset global error tolerance, number of remaining terms, remaining budget, energy consumption mode, and accumulator tolerance factor, a local error threshold is assigned to the current multiply-accumulate operation; The actual accuracy supply for each error path is calculated based on the number of mantissa bits retained, truncation compensation factor, accumulator tolerance factor, and exponent difference. The accuracy requirement for each error path is then calculated based on the input effective mantissa bits, local error threshold, and safety margin. The process includes: asymmetric truncation based on the number of mantissa bits retained for the two operands, introducing error sources from the first, second, and third error paths; converting the errors introduced by the first, second, and third error paths to exponential form to establish upper bound models for the first, second, and third error paths respectively; establishing a total error upper bound and judgment conditions based on the upper bound models of the first, second, and third error paths; and calculating the bit-based calculation formulas for the first, second, and third error paths based on the established total error upper bound and judgment conditions. The accuracy supply and accuracy requirement are determined based on the actual accuracy supply and accuracy requirement calculated for each path; if all paths are successful, an accuracy pass signal is fed back; otherwise, an accuracy upgrade mechanism is triggered.
7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in claim 6.
8. A computer program product, characterized in that, The computer program product includes computer program code that, when run on a computer, causes the computer to implement the method as described in claim 6.
9. An electronic terminal, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the method as described in claim 6.