Test vector generation apparatus and burn-in test system
By introducing a test vector generation device into the aging test system, and using multiple sequence generators and multiplexers to generate and select test sequences, the problem of insufficient configurability of the aging test bench is solved, enabling flexible testing of multi-register scan chains and improving the user experience.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN JIANGYUAN TECHNOLOGY CO LTD
- Filing Date
- 2026-01-19
- Publication Date
- 2026-05-29
Smart Images
Figure CN121541032B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit technology, and in particular to a test vector generation device and an aging test system. Background Technology
[0002] Aging tests involve subjecting chips to long-term testing under high temperature and high pressure to simulate rapid chip aging.
[0003] Currently, aging tests are mainly conducted by using the scan test technique in Design for Testability (DFT) to connect all registers into a scan chain. The chip containing the scan chain is then connected to an aging test bench. The aging test bench continuously injects test vectors (data and clock) into the chip, thereby achieving the purpose of repeatedly reversing the scan chain registers and thus enabling long-term chip testing.
[0004] However, when using this aging test method, if the test scan chain is very long and many registers need to be tested simultaneously, the aging test bench needs to generate a large number of test vectors. Since the aging test bench has low configurability for test vectors, it cannot generate and store a large number of test vectors, which will make it impossible to perform aging tests on chips with scan chains containing many registers, thus affecting the user experience. Summary of the Invention
[0005] In view of this, this application provides a test vector generation device and an aging test system. The main purpose is to improve the existing technology in the case of a long test scan chain, that is, when many registers need to be tested at the same time, the aging test bench needs to generate a large number of test vectors. Since the aging test bench has low configurability for test vectors, it cannot generate and store a large number of test vectors, which leads to the inability to perform aging tests on chips containing scan chains with many registers, thus affecting the user experience.
[0006] In a first aspect, this application provides a test vector generation apparatus, comprising: multiple sequence generators, a multiplexer, and a control circuit;
[0007] The control circuit is used to send test sequence generation signals to the multiple sequence generators respectively when the chip under test where the test vector generation device is located is connected to the aging test bench.
[0008] The sequence generator is used to generate candidate test sequences respectively upon receiving the test sequence generation signal, wherein each sequence generator generates one candidate test sequence, and the candidate test sequences generated by each sequence generator are different;
[0009] The multiplexer is used to select a target test sequence from the plurality of candidate test sequences, and the target test sequence is used to perform aging tests on the chip under test.
[0010] Optionally, the control circuit is further configured to receive test instructions sent by the aging test bench when the chip under test is connected to the aging test bench, and send test sequence generation signals to the plurality of sequence generators respectively according to the test instructions.
[0011] Optionally, the control circuit is further configured to receive sequence information corresponding to the target test sequence sent by the aging test bench when the chip under test is connected to the aging test bench, and send the sequence information to the multiplexer.
[0012] Optionally, the multiplexer is further configured to receive the sequence information and select a target test sequence from the plurality of candidate test sequences based on the sequence information, and input the target test sequence into the scan chain in the chip under test for aging test.
[0013] Optionally, the first terminals of the plurality of sequence generators are respectively connected to the first terminal of the control circuit, and the second terminals of the plurality of sequence generators are respectively connected to the first terminal of the multiplexer;
[0014] The second terminal of the control circuit is connected to the second terminal of the multiplexer, the third terminal of the control circuit is externally connected to the aging test bench, and the third terminal of the multiplexer is connected to the first terminal of the scan chain in the chip under test.
[0015] Secondly, this application provides an aging test system, including the test vector generation device described in the first aspect, an aging test bench, and a scan chain in the chip under test where the test vector generation device is located;
[0016] The aging test bench is used to send a test control signal to the chip under test when a connection is established with the chip under test. The test control signal is used to control the scan chain to enter the test mode.
[0017] Optionally, the aging test bench is further configured to send a clock signal to the chip under test when the scan chain switches to the test mode, the clock signal being used to control the scan chain to perform aging tests based on the target test sequence.
[0018] Optionally, the scan chain is used to receive the target test sequence sent by the multiplexer when switching to the test mode, and to perform aging tests based on the clock signal and the target test sequence.
[0019] Optionally, the scan chain is also used to output aging test results based on the clock signal.
[0020] Optionally, the second and third ends of the scan chain are respectively connected to the aging test bench. The second end of the scan chain is used to receive the test control signal, the third end of the scan chain is used to receive the clock signal, and the fourth end of the scan chain is used to output the aging test result. The scan chain includes multiple scan registers, which are connected in series.
[0021] By means of the above technical solution, this application provides a test vector generation device and an aging test system. The test vector generation device includes: multiple sequence generators, a multiplexer, and a control circuit. The control circuit, when the chip under test (WAT) connected to the test vector generation device is established with the aging test bench, sends test sequence generation signals to the multiple sequence generators respectively. Upon receiving the test sequence generation signals, each sequence generator generates a candidate test sequence, wherein each sequence generator generates one candidate test sequence, and the candidate test sequences generated by each sequence generator are different. The multiplexer selects a target test sequence from the multiple candidate test sequences, and the target test sequence is used to perform aging tests on the WAT chip. Compared with existing technologies, this application adds a test vector generation device to the chip under test, and then uses multiple sequence generators in the test vector generation device to generate multiple candidate test vectors. A multiplexer is used to select the target test vector from the multiple candidate test vectors for testing. During the testing process, the test bench no longer needs to provide test vectors to the chip under test, which reduces the requirements of the test bench. It can realize aging tests on chips containing scan chains with many registers, increases the flexibility of aging tests, and improves the user experience.
[0022] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description
[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This paper shows a schematic diagram of the structure of a test vector generation device provided in an embodiment of this application;
[0026] Figure 2 This illustration shows a schematic diagram of an interface connection structure for multiple scan registers provided in an embodiment of this application;
[0027] Figure 3 This paper shows a schematic diagram of the structure of an aging test system provided in an embodiment of this application;
[0028] Figure 4 This illustration shows a schematic diagram of a scan chain structure provided in an embodiment of this application;
[0029] Figure 5 This illustration shows a schematic diagram of the structure of a scan register provided in an embodiment of this application;
[0030] exist Figure 1 middle:
[0031] 11 - Multiple sequence generators; 12 - Multiplexer; 13 - Control circuit.
[0032] exist Figure 3 middle:
[0033] 1-Test vector generation device, 2-Aging test bench, 3-Scanning chain. Detailed Implementation
[0034] In the description of this disclosure, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.
[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.
[0036] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.
[0037] The present disclosure will be described in detail below with reference to the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present disclosure can be combined with each other.
[0038] The following is combined Figure 1 This disclosure describes a test vector generation apparatus according to some embodiments thereof.
[0039] This disclosure provides a test vector generation device 1, such as... Figure 1 As shown, it includes: multiple sequence generators 11, multiplexer 12 and control circuit 13;
[0040] The control circuit 13 is used to send test sequence generation signals to multiple sequence generators 11 when the chip under test located in the test vector generation device 1 is connected to the aging test bench; the sequence generator is used to generate candidate test sequences when it receives the test sequence generation signal; the multiplexer 12 is used to select the target test sequence from the multiple candidate test sequences; the target test sequence is used to perform aging test on the chip under test.
[0041] Each sequence generator produces a candidate test sequence, and the candidate test sequences generated by each sequence generator are different.
[0042] In the embodiments of this application, such as Figure 2As shown, the chip under test can be a chip containing multiple scan registers. Specifically, this is to achieve a more efficient Design for Testability (DFT) strategy, especially in large-scale integrated circuit (IC) design. These chips utilize scan chain technology to connect multiple registers through specific control logic, forming one or more chains that can continuously shift data. This design makes it easier to control and observe the state of internal registers during the testing phase, improving test coverage and accelerating fault detection.
[0043] Correspondingly, such as Figure 2 As shown, each scan register of the chip under test can include a data input terminal (i.e., Figure 2 The D interface in the middle), data output end (i.e. Figure 2 The Q interface and clock interface (i.e.) Figure 2 Based on the CK interface in the chip, each scan register is also equipped with an additional control input, specifically Scan Enable (SE), and two additional data input / output ports: Scan In (SI) and Scan Out (SO). In normal operating mode, these registers function like regular registers, but in test mode, they form one or more serial shift register chains via the SI and SO ports. During testing, a pre-calculated test vector (i.e., the desired input sequence) is shifted into the registers one by one through the SI port of the scan chain to stimulate the internal logic of the chip. Then, one or more clock cycles are executed to elicit a response from the internal logic. Finally, these responses are shifted out through the SO port and compared with the expected test results to verify the correctness of the circuit. Using a chip with multiple scan registers can significantly improve test coverage for complex integrated circuits, especially for logic blocks whose internal states are difficult to access directly. This helps detect manufacturing defects such as bridging, open circuits, and delay issues, thereby improving product quality and reliability.
[0044] In some examples, a burn-in test bench is a device specifically designed to simulate the performance degradation of a product under prolonged use or storage conditions to verify its reliability and stability. This type of testing, often referred to as "burn-in testing" or "stability testing," is widely used in electronic components, lighting equipment, power adapters, circuit boards, home appliances, automotive electronics, and other fields. The core purpose of a burn-in test bench is to identify potential quality issues before a product is released to the market, reducing customer complaints and return rates, and extending product lifespan.
[0045] It should be noted that the chip to be tested needs to be connected to the aging test bench before aging testing.
[0046] In this embodiment, a sequence generator is an electronic device or component capable of generating a predetermined sequence of signals. These signals are typically periodic and consist of binary digits, used in digital circuit design, communication systems, test equipment, and other applications requiring specific timing control.
[0047] For example, the core functions of the sequence generator in this application embodiment may include, but are not limited to: Signal generation: generating a series of binary digital signals according to a preset pattern. These signals can be simple repeating sequences or complex non-repeating sequences, depending on the application requirements. Synchronization control: typically controlled by an external synchronization pulse source to ensure that the generated sequence signals remain synchronized with other parts of the system. State machine implementation: internally, state machine logic is often used for design, with each state corresponding to one or more bits in the sequence, and the transitions between states determining the mode of the output sequence. Programmability: some sequence generators allow users to customize the sequence mode, increasing flexibility and applicability.
[0048] In some examples, a multiplexer (MUX) is an electronic circuit that selects one signal from multiple input signals and outputs it through a single output. This selection process is determined by one or more control signals (selection or address signals). Multiplexers are fundamental building blocks in digital logic design and are widely used in communication systems, computer systems, embedded systems, and other applications requiring flexible data routing. Specifically, a multiplexer has multiple data input lines and a common output line, as well as at least one selection control line. Multiplexers are combinational logic circuits, meaning their output depends only on the current input signal and is independent of previous inputs. Multiplexers can be cascaded to increase the number of input channels and meet different scale requirements.
[0049] Accordingly, the multiplexer 12 can control signals to determine which input signal is transmitted to the output. For example, a 2-to-1 multiplexer 12 can have a selection control signal; when the signal is 0, the first input is selected; when it is 1, the second input is selected. Similarly, a 4-to-1 multiplexer 12 requires two address signals (A1A0), with each address combination corresponding to a specific input channel.
[0050] For example, in practical applications, the design and use of multiplexer 12 need to consider factors such as signal delay, power consumption, and integration density. With the development of integrated circuit technology, the design of multiplexer 12 tends towards higher integration density, lower power consumption, and faster switching speeds. In modern system design, multiplexer 12 is often integrated into programmable logic devices for flexible configuration and reprogramming to meet the needs of different application scenarios.
[0051] Furthermore, multiplexer 12 can be implemented as a simple multiplexer using basic logic gates (such as AND gates, OR gates, NOT gates, etc.). In complex systems, more efficient circuit structures may be employed, such as using transmission gates (such as transistors) to achieve fast signal switching. The design and optimization of multiplexers is an important aspect of digital circuit design, playing a crucial role in improving system performance and flexibility.
[0052] For example, in the embodiments of this application, when the chip under test is connected to the aging test bench, multiple sequence generators 11 can generate multiple candidate test sequences, and multiplexer 12 can select a target test sequence from the multiple candidate test sequences for subsequent aging tests.
[0053] Optionally, the control circuit 13 is also used to receive test instructions sent by the aging test bench when the chip under test is connected to the aging test bench, and send test sequence generation signals to multiple sequence generators 11 according to the test instructions.
[0054] In this embodiment, the test command sent by the aging test bench can be a command generated based on the chip under test for testing the chip under test. The test command can include a test start signal, sequence information corresponding to the target test sequence selected for testing, etc. The specific content of the test command is not specifically limited in this embodiment.
[0055] Furthermore, the multiplexer 12 is also used to receive sequence information and select a target test sequence from multiple candidate test sequences based on the sequence information, and input the target test sequence into the scan chain in the chip under test for aging test.
[0056] It should be noted that when the multiplexer 12 selects from multiple candidate test sequences, it needs to select the target test sequence based on the sequence information sent by the aging test bench.
[0057] Correspondingly, the first ends of multiple sequence generators 11 are respectively connected to the first end of control circuit 13, and the second ends of multiple sequence generators 11 are respectively connected to the first end of multiplexer 12; the second end of control circuit 13 is connected to the second end of multiplexer 12, the third end of control circuit 13 is externally connected to aging test bench, and the third end of multiplexer 12 is connected to the first end of scan chain in chip under test.
[0058] In some examples, the test vector generation device 1 is a circuit that can generate multiple stimulus patterns through simple configuration, and the configuration can be changed during testing to meet the requirements of changing the test stimulus. It requires no stimulus from the test bench; the stimulus is entirely achieved through the circuit itself. This circuit structure consists of multiple sequence generators 11, a control circuit 13, and a multiplexer 12. Each sequence generation circuit generates a unique test sequence to meet the testing requirements of aging tests. Based on the control selection of the control circuit 13, the multiplexer 12 selects one of the multiple sequence generators for output and sends it to the subsequent scan input. The control circuit 13 is the core of this module; in addition to controlling the multiplexer 12, it also sends start and stop signals to each sequence generator to control its start and stop. The test vector generation function specifically replaces the test vectors (data and clock) provided by the test bench, meaning that the input stimulus no longer needs to be provided by the test bench; it is entirely completed by configuring the vector generation circuit. This allows for testing during aging tests while reducing the requirements of the test bench and increasing testing flexibility.
[0059] In some examples, embodiments of this disclosure also provide an aging test system, such as Figure 3 As shown, it includes a test vector generation device 1, an aging test bench 2, and a scan chain 3 in the chip under test where the test vector generation device 1 is located; the aging test bench 2 is used to send a test control signal to the chip under test when a connection is established with the chip under test, and the test control signal is used to control the scan chain 3 to enter the test mode.
[0060] For example, the chip under test may include a test vector generation device 1 and a scan chain 3, wherein, as Figure 4 The diagram shown illustrates the structure of a scanned chain. Specifically... Figure 4 Multiple scan registers in the scan chain can each include a data input terminal (i.e., ... Figure 4 The D interface in the middle), data output end (i.e. Figure 4 The Q interface in the middle), the inverting data output terminal (i.e. Figure 4 In Based on interfaces such as the clock interface, each scan register is also equipped with an additional control input, specifically Scan Enable (SE), and two additional data input / output ports: Scan In (SI) and Scan Out (SO). In normal operating mode, these registers function like regular registers, but in test mode, they form one or more serial shift register chains via the SI and SO ports. During testing, a pre-calculated test vector (i.e., the desired input sequence) is shifted into the registers one by one through the SI port of the scan chain to stimulate the internal logic of the chip. Subsequently, one or more clock cycles are executed to elicit a response from the internal logic. Finally, these responses are shifted out through the SO port and compared with the expected test results to verify the correctness of the circuit. Using a chip with multiple scan registers can significantly improve test coverage for complex integrated circuits, especially for logic blocks whose internal states are difficult to access directly. This helps detect manufacturing defects such as bridging, open circuits, and delay issues, thereby improving product quality and reliability.
[0061] In this embodiment, Scan Chain 3 is a key technology in the field of digital integrated circuit testing, falling under the category of Design for Testability (DFT). Its main purpose is to improve the testability of integrated circuits (ICs), enabling more effective detection and diagnosis of circuit faults during production testing and field maintenance. Scan Chain technology transforms registers in the design (such as D flip-flops) into scan registers, thereby linking these registers to form one or more shift register chains, facilitating automated testing in test mode.
[0062] Specifically, in normal operating mode, the registers receive signals from the normal data path. However, in test mode, by adding a control signal, specifically scan enable (SE), the register inputs are switched to receive the output from the previous register (scan output SO), while the output is connected to the input of the next register (scan input SI), forming a continuous chain of shift registers. During testing, a long test vector (i.e., a specific sequence of binary data) is first shifted and loaded into the registers throughout the chain via the input (SI) of scan chain 3. This process is typically accompanied by clock pulses, causing the data to shift bit by bit. After the test vector is loaded, the circuit runs for one or more clock cycles, stimulating the internal logic of the circuit to generate a response. Then, the response data is shifted and output via the output (SO) of scan chain 3 and compared with the expected result to detect whether the circuit is functioning correctly. By comparing the test response with the expected result, potential faults in the circuit can be identified. Complex test modes and algorithms (such as Automated Test Pattern Generation (ATPG)) can be used to improve fault coverage and ensure circuit reliability.
[0063] It should be noted that scan chain 3 contains multiple scan registers, such as Figure 5 The diagram shown illustrates the structure of a scan register, where each scan register can be configured with a data input terminal (i.e., ...). Figure 5 The D interface in the middle), data output end (i.e. Figure 5 The Q interface), inverting data output terminal, and clock interface (i.e.) Figure 5 CK interface in the middle), scan input (i.e. Figure 5 SI interface), scan output, scan enable interface (i.e. Figure 5 (such as the SE interface in the middle) etc.
[0064] For example, after the chip is returned to the wafer, an aging test is required, which involves testing the chip for a long time under high temperature and high pressure to simulate the rapid aging of the chip. The current aging test uses DFT scan test technology to connect all registers into a scan chain 3. The test station continuously feeds test vectors (data and clock) into the scan input to achieve the purpose of repeatedly reversing the scan and connecting registers, thereby realizing long-term chip testing.
[0065] Optionally, the aging test station 2 is also used to send a clock signal to the chip under test when the scan chain 3 switches to the test mode. The clock signal is used to control the scan chain 3 to perform aging tests based on the target test sequence.
[0066] In some examples, the scanning input in the prior art is to send scanning information to the chip under test via the test bench. In the embodiments of this application, the aging test bench 2 does not need to send scanning signals to the chip under test, but only needs to send clock signals and sequence information to the chip under test. The clock signal is used to control the scan chain 3 to start and end the aging test.
[0067] Furthermore, when switching to test mode, scan chain 3 is used to receive the target test sequence sent by multiplexer 12 and perform aging test based on clock signal and the target test sequence; scan chain 3 is also used to output aging test results according to clock signal.
[0068] Correspondingly, after receiving the clock signal, scan chain 3 begins to perform aging tests based on the target test sequence and outputs the test results.
[0069] Optionally, the second and third ends of the scan chain 3 are connected to the aging test bench 2 respectively. The second end of the scan chain 3 is used to receive the test control signal, the third end of the scan chain 3 is used to receive the clock signal, and the fourth end of the scan chain 3 is used to output the aging test result. The scan chain 3 contains multiple scan registers, which are connected in series.
[0070] It should be noted that the second and third ends of scan chain 3 can be the SE interface of multiple scan registers, the third end of scan chain 3 can be the clock (CK) interface of multiple scan registers, and the fourth end of scan chain 3 can be the SO interface of multiple scan registers.
[0071] Compared with existing technologies, this embodiment adds a test vector generation device to the chip under test, and then uses multiple sequence generators in the test vector generation device to generate multiple candidate test vectors. The multiplexer 12 selects the target test vector from the multiple candidate test vectors for testing. During the testing process, the test bench no longer needs to provide test vectors to the chip under test, which reduces the requirements of the test bench. It can realize aging tests on chips containing scan chains with many registers, increases the flexibility of aging tests, and improves the user experience.
[0072] Through the above description of the disclosed embodiments, those skilled in the art can clearly understand that this disclosure can be implemented by means of software plus necessary general-purpose hardware platforms, or it can be implemented by hardware.
[0073] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0074] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.
[0075] It should be noted that the technical solutions in this disclosure are not limited to use in aging test systems, but can also be extended to similar related applications that require control. All of these should fall within the protection scope of this disclosure, and no specific limitations are made here regarding the related applications that require control.
[0076] All articles and references disclosed above, including patent applications and publications, are incorporated herein by reference for various purposes. The term “substantially constitutes…” used to describe a combination should include the identified elements, components, parts, or steps, as well as other elements, components, parts, or steps that do not substantially affect the essential novelty of the combination. The use of the terms “comprising” or “including” to describe combinations of elements, components, parts, or steps herein also contemplates embodiments substantially constituted by such elements, components, parts, or steps. The use of the term “may” herein is intended to indicate that any described attribute included by “may” is optional.
[0077] Multiple elements, components, parts, or steps can be provided by a single integrated element, component, part, or step. Alternatively, a single integrated element, component, part, or step can be divided into multiple separate elements, components, parts, or steps. The use of "a" or "an" to describe an element, component, part, or step does not imply the exclusion of other elements, components, parts, or steps.
[0078] It should be understood that the above description is for illustrative purposes and not for limitation. Many embodiments and applications beyond the provided examples will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of this teaching should not be determined by reference to the above description, but rather by reference to the foregoing claims and the full scope of their equivalents. For purposes of completeness, all articles and references, including patent applications and published disclosures, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended as a waiver of that subject matter, nor should it be considered as a failure of the applicant to consider that subject matter as part of the disclosed subject matter. It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its spirit and scope. Thus, this disclosure is also intended to include such modifications and variations if they fall within the scope of the claims of this disclosure and their equivalents.
Claims
1. A test vector generation device, characterized in that, include: Multiple sequence generators, multiplexers, and control circuitry; The first terminals of the plurality of sequence generators are respectively connected to the first terminal of the control circuit, and the second terminals of the plurality of sequence generators are respectively connected to the first terminal of the multiplexer. The second terminal of the control circuit is connected to the second terminal of the multiplexer, the third terminal of the control circuit is externally connected to an aging test bench, and the third terminal of the multiplexer is connected to the first terminal of the scan chain in the chip under test. The control circuit is used to receive test instructions sent by the aging test bench when the chip under test where the test vector generation device is located is connected to the aging test bench, and to send test sequence generation signals to the plurality of sequence generators according to the test instructions. The sequence generator is used to generate candidate test sequences respectively upon receiving the test sequence generation signal, wherein each sequence generator generates one candidate test sequence, and the candidate test sequences generated by each sequence generator are different; The multiplexer is used to select a target test sequence from multiple candidate test sequences, and input the target test sequence into the scan chain in the chip under test for aging test. The target test sequence is used to perform aging test on the chip under test.
2. The test vector generation device according to claim 1, characterized in that, The control circuit is also used to receive sequence information corresponding to the target test sequence sent by the aging test bench when the chip under test is connected to the aging test bench, and to send the sequence information to the multiplexer.
3. The test vector generation device according to claim 2, characterized in that, The multiplexer is also used to receive the sequence information and select a target test sequence from the plurality of candidate test sequences based on the sequence information, and input the target test sequence into the scan chain in the chip under test for aging test.
4. An aging test system, characterized in that, Includes the test vector generation device, aging test bench, and scan chain in the chip under test where the test vector generation device is located, as described in any one of claims 1 to 3; The aging test bench is used to send a test control signal to the chip under test when a connection is established with the chip under test. The test control signal is used to control the scan chain to enter the test mode.
5. The aging test system according to claim 4, characterized in that, The aging test bench is also used to send a clock signal to the chip under test when the scan chain switches to the test mode. The clock signal is used to control the scan chain to perform aging tests based on the target test sequence.
6. The aging test system according to claim 5, characterized in that, The scan chain is used to receive the target test sequence sent by the multiplexer when switching to the test mode, and to perform aging tests based on the clock signal and the target test sequence.
7. The aging test system according to claim 6, characterized in that, The scanning chain is also used to output aging test results based on the clock signal.
8. The aging test system according to claim 7, characterized in that, The second and third ends of the scanning chain are respectively connected to the aging test bench. The second end of the scanning chain is used to receive the test control signal, the third end of the scanning chain is used to receive the clock signal, and the fourth end of the scanning chain is used to output the aging test result. The scanning chain includes multiple scanning registers, which are connected in series.