Bandgap reference circuit, method of operation thereof, and electronic device

Abstract

The application discloses a band gap reference circuit and a working method thereof and electronic equipment, and relates to the technical field of band gap reference circuits.The circuit comprises a pre-stabilization module, a starting module electrically connected with the pre-stabilization module, a band gap core module electrically connected with the starting module, and an operational amplifier module electrically connected with the band gap core module and the pre-stabilization module; wherein, the band gap core module is used for outputting a reference voltage source; the pre-stabilization module is used for buffering a power supply voltage, obtaining a working voltage, and providing the working voltage for the starting module and the operational amplifier module, and the pre-stabilization module is also used for feeding back the influence of the fluctuation of the power supply voltage on the reference voltage source to the pre-stabilization module for readjustment; the starting module is used for starting the band gap core module; and the operational amplifier module is used for performing negative feedback adjustment on the reference voltage source.The circuit can provide a reference voltage source with high PSRR and low temperature drift.

Description

Bandgap reference circuits and their operating methods, electronic equipment Technical Field

[0001] This invention relates to the field of bandgap reference circuit technology, and in particular to a bandgap reference circuit and its operating method, as well as an electronic device. Background Technology

[0002] Bandgap reference circuits are widely used in analog and mixed-signal circuits, such as power management chips and digital-to-analog converters, because they provide a stable and accurate reference voltage source. Therefore, high-precision voltage references are very important.

[0003] Figure 1 shows a traditional bandgap reference circuit. Its basic principle is to utilize the base-emitter voltage of bipolar transistors Q1 and Q2. The negative temperature coefficient they possess, and the thermal voltage difference they generate when operating at different current densities. The positive temperature coefficients cancel each other out. Specifically, this is achieved through resistors R1 and R2. Enlarge it proportionally, and then combine it with one The voltages are added together, and a stable reference voltage that is approximately equal to the silicon bandgap voltage is generated at the output. This voltage is independent of temperature under the first-order approximation.

[0004] The core drawback of this circuit is that it only achieves first-order temperature compensation, failing to eliminate the high-order nonlinear temperature drift of the BJT (Bipolar Junction Transistor) and resistors. Therefore, the accuracy and temperature drift performance of the reference voltage are limited. Furthermore, its accuracy heavily depends on the matching precision of the transistors and resistors; typically, strict matching is required to achieve good performance.

[0005] While high PSRR (Power Supply Rejection Ratio) and low temperature drift can be achieved to some extent through cascode structures and precise design, such circuit solutions still face a fundamental challenge: their positive and negative temperature coefficient voltages cannot be directly connected to the output, causing voltage deviations during transmission. Therefore, temperature coefficient and power supply rejection ratio are inherent bottlenecks over a wide temperature range (e.g., -40°C to 125°C). Furthermore, the cascode structure used to achieve high PSRR severely compresses signal swing at advanced low supply voltages.

[0006] Traditional bandgap references also suffer from significant shortcomings in dynamic performance and robustness. Their power supply rejection ratio (PSRR) typically deteriorates sharply at high frequencies, making it difficult to effectively suppress the ubiquitous power switching noise in modern SoCs (System on Chip). The circuit's reliance on dedicated startup circuitry introduces potential failure risks; poorly designed startup mechanisms can lead to system hangs or performance degradation. Summary of the Invention

[0007] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a bandgap reference circuit and its operating method, as well as an electronic device, capable of providing a reference voltage source with high PSRR and low temperature drift.

[0008] In a first aspect, a bandgap reference circuit according to an embodiment of the present invention includes:

[0009] Pre-regulated voltage module;

[0010] The startup module is electrically connected to the pre-stabilized voltage module.

[0011] The bandgap core module is electrically connected to the startup module;

[0012] The operational amplifier module is electrically connected to the bandgap core module and the pre-regulator module, respectively;

[0013] The bandgap core module is used to output a reference voltage source; the pre-regulation module is used to buffer the power supply voltage to obtain the operating voltage and provide the operating voltage to the startup module and the operational amplifier module. The pre-regulation module is also used to feed back the impact of the power supply voltage fluctuation on the reference voltage source to the pre-regulation module for readjustment; the startup module is used to start the bandgap core module; and the operational amplifier module is used to perform negative feedback regulation on the reference voltage source.

[0014] According to some embodiments of the present invention, the pre-regulator module includes:

[0015] The first inverter has an enable signal connected to its input terminal.

[0016] The second inverter is electrically connected to the output of the first inverter.

[0017] The first MOSFET has its gate electrically connected to the output terminal of the second inverter, and its source connected to the power supply voltage.

[0018] The first resistor, one end of which is electrically connected to the drain of the first MOSFET;

[0019] The second resistor has one end electrically connected to the other end of the first resistor, and the other end of the second resistor is grounded.

[0020] The second MOSFET has its gate electrically connected to one end of the second resistor, its drain electrically connected to the drain of the first MOSFET, and its source outputting the operating voltage.

[0021] According to some embodiments of the present invention, the first inverter includes:

[0022] The third MOS transistor, the gate of which is connected to the enable signal, and the source of which is connected to the power supply voltage;

[0023] The fourth MOS transistor has its gate connected to the gate of the third MOS transistor, its drain connected to the drain of the third MOS transistor, its source grounded, and its drain also electrically connected to the input terminal of the second inverter.

[0024] According to some embodiments of the present invention, the second inverter includes:

[0025] The fifth MOS transistor has its gate electrically connected to the drain of the fourth MOS transistor, and its source connected to the power supply voltage.

[0026] The sixth MOS transistor has its gate connected to the gate of the fifth MOS transistor, its drain connected to the drain of the fifth MOS transistor, and its source grounded.

[0027] According to some embodiments of the present invention, the startup module includes:

[0028] The seventh MOS transistor, the source of which is connected to the operating voltage;

[0029] The eighth MOS transistor has its gate electrically connected to the drain of the seventh MOS transistor, and its drain is grounded.

[0030] The third resistor has one end electrically connected to the drain of the seventh MOS transistor, and the other end grounded.

[0031] The ninth MOS transistor has its source connected to the operating voltage and its gate electrically connected to the gate of the seventh MOS transistor.

[0032] The tenth MOS transistor has its gate electrically connected to the gate of the ninth MOS transistor, and its source is connected to the operating voltage.

[0033] The eleventh MOS transistor has its drain electrically connected to the source of the eighth MOS transistor and the drain of the ninth MOS transistor, and its source is grounded.

[0034] The first transistor has its collector electrically connected to the drain of the tenth MOS transistor and the gate of the eleventh MOS transistor, and its emitter is grounded.

[0035] The twelfth MOS transistor has its gate electrically connected to the gate of the tenth MOS transistor, its source connected to the operating voltage, and its drain electrically connected to the base of the first transistor.

[0036] The fourth resistor has one end electrically connected to the base of the first transistor and the drain of the twelfth MOS transistor, and the other end is grounded.

[0037] The thirteenth MOS transistor has its gate electrically connected to the drain of the twelfth MOS transistor, its drain connected to the operating voltage, and its source connected to the output of the bandgap reference circuit.

[0038] According to some embodiments of the present invention, the bandgap core module includes:

[0039] The fourteenth MOS transistor, the drain of which is electrically connected to the operational amplifier module;

[0040] The collector of the second transistor is electrically connected to the source of the fourteenth MOS transistor, the emitter of the second transistor is grounded, and the base of the second transistor is electrically connected to the gate of the fourteenth MOS transistor.

[0041] The fifteenth MOS transistor, the drain of which is electrically connected to the operational amplifier module;

[0042] The collector of the third transistor is electrically connected to the source of the fifteenth MOS transistor, and the emitter of the third transistor is grounded.

[0043] The fourth transistor has its base electrically connected to the base of the second transistor and the gate of the fourteenth MOS transistor, its emitter grounded, and its collector electrically connected to the base of the third transistor.

[0044] The fifth resistor has one end electrically connected to the collector of the fourth transistor and the other end electrically connected to the base of the fourth transistor.

[0045] The sixth resistor has one end electrically connected to the other end of the fifth resistor and is connected to the output terminal of the bandgap reference circuit. The sixth resistor is a positive temperature coefficient resistor and the fifth resistor is a negative temperature coefficient resistor.

[0046] According to some embodiments of the present invention, the operational amplifier module includes:

[0047] The sixteenth MOS transistor, the source of which is connected to the operating voltage, and the drain of which is electrically connected to the drain of the fourteenth MOS transistor;

[0048] The seventeenth MOS transistor has its source connected to the operating voltage, its gate electrically connected to its drain and the gate of the sixteenth MOS transistor, and its drain electrically connected to the drain of the fifteenth MOS transistor.

[0049] The eighteenth MOS transistor, the gate of which is electrically connected to the gate of the seventeenth MOS transistor, and the source of which is connected to the operating voltage;

[0050] The nineteenth MOS transistor, the gate of which is electrically connected to the gate of the eighteenth MOS transistor, and the source of which is electrically connected to the drain of the eighteenth MOS transistor;

[0051] The twentieth MOS transistor has its drain electrically connected to the drain of the nineteenth MOS transistor and the gate of the twentieth MOS transistor, and its source is grounded.

[0052] The gate of the 21st MOSFET is electrically connected to the gate of the 20th MOSFET, and the source of the 21st MOSFET is grounded.

[0053] The drain of the 22nd MOSFET is electrically connected to the drain of the 21st MOSFET.

[0054] The 23rd MOSFET has its source connected to the operating voltage, its drain electrically connected to the source of the 22nd MOSFET, and its gate electrically connected to the gate of the 22nd MOSFET and the drain of the 16th MOSFET.

[0055] The 24th MOSFET has its source connected to the operating voltage and its gate connected to the bias voltage.

[0056] The drain of the 25th MOSFET is electrically connected to the drain of the 24th MOSFET, the source of the 25th MOSFET is grounded, and the gate of the 25th MOSFET is electrically connected to the drain of the 21st MOSFET.

[0057] The fifth transistor has its base electrically connected to the drain of the twenty-fourth MOS transistor, its collector connected to the operating voltage, and its emitter connected to the output terminal of the bandgap reference circuit.

[0058] According to some embodiments of the present invention, the operational amplifier module further includes:

[0059] The seventh resistor, one end of which is electrically connected to the drain of the twenty-fifth MOS transistor;

[0060] The first capacitor has one end electrically connected to the other end of the seventh resistor, and the other end of the first capacitor is electrically connected to the gate of the fourteenth MOS transistor.

[0061] Secondly, according to an embodiment of the present invention, a method for operating a bandgap reference circuit, based on the bandgap reference circuit described in the first aspect embodiment, includes:

[0062] The power supply voltage is buffered by the pre-regulator module to obtain the operating voltage, and the operating voltage is provided to the startup module and the operational amplifier module.

[0063] Based on the operating voltage, the bandgap core module is started by the starting module;

[0064] Based on the operating voltage, a reference voltage source is output through the bandgap core module, and the startup module is shut down;

[0065] The reference voltage source is adjusted by negative feedback through the operational amplifier module;

[0066] The pre-regulation module feeds back the impact of power supply voltage fluctuations on the reference voltage source to the pre-regulation module for readjustment.

[0067] Thirdly, an electronic device according to an embodiment of the present invention includes the bandgap reference circuit described in the first aspect embodiment.

[0068] The bandgap reference circuit and its operating method and electronic device according to embodiments of the present invention have at least the following beneficial effects: the power supply voltage is buffered by the pre-regulation module, and the influence of power supply voltage fluctuations on the reference voltage source is fed back to the pre-regulation module for readjustment, thereby improving PSRR and effectively suppressing power supply fluctuations; the reference voltage source output by the bandgap core module is negatively regulated by the operational amplifier module, making the output voltage more stable.

[0069] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0070] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0071] Figure 1 is a circuit diagram of a bandgap reference circuit in the prior art;

[0072] Figure 2 is a block diagram of the bandgap reference circuit according to an embodiment of the present invention;

[0073] Figure 3 is a circuit diagram of the bandgap reference circuit according to an embodiment of the present invention;

[0074] Figure 4 is a simplified schematic diagram of the bandgap core module and operational amplifier module according to an embodiment of the present invention;

[0075] Figure 5 is a circuit diagram of the pre-stabilized voltage module according to an embodiment of the present invention;

[0076] Figure 6 shows the temperature characteristic curve of the bandgap reference circuit according to an embodiment of the present invention;

[0077] Figure 7 shows the power supply rejection ratio frequency response curve of the bandgap reference circuit according to an embodiment of the present invention;

[0078] Figure 8 is a flowchart of the operation method of the bandgap reference circuit according to an embodiment of the present invention. Detailed Implementation

[0079] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0080] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0081] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0082] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0083] This invention provides a bandgap reference circuit, comprising: a pre-regulator module; a startup module electrically connected to the pre-regulator module; a bandgap core module electrically connected to the startup module; and an operational amplifier module electrically connected to both the bandgap core module and the pre-regulator module. The bandgap core module outputs a reference voltage source. The pre-regulator module buffers the power supply voltage to obtain an operating voltage and provides this operating voltage to the startup module and the operational amplifier module. The pre-regulator module also feeds back the impact of power supply voltage fluctuations on the reference voltage source for readjustment. The startup module starts the bandgap core module. The operational amplifier module performs negative feedback regulation on the reference voltage source. By buffering the power supply voltage through the pre-regulator module and feeding back the impact of power supply voltage fluctuations on the reference voltage source for readjustment, the PSRR (Power Supply Reduction Ratio) can be improved, resulting in better suppression of power supply fluctuations. The negative feedback regulation of the reference voltage source output by the bandgap core module through the operational amplifier module makes the output voltage more stable.

[0084] The bandgap reference circuit, its working method, and electronic equipment according to embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0085] On one hand, this invention proposes a bandgap reference circuit, as shown in Figure 2. This circuit includes a pre-regulator module 100, a startup module 200, a bandgap core module 400, and an operational amplifier module 300. The pre-regulator module 100 is electrically connected to both the startup module 200 and the operational amplifier module 300. The pre-regulator module 100 buffers the power supply voltage (VDD) to obtain an operating voltage (AVDD) and provides the operating voltage to both the startup module 200 and the operational amplifier module 300. The pre-regulator module 100 also filters fluctuations in the power supply voltage to influence the reference voltage source. The feedback mechanism is used to readjust the pre-regulator module 100, thereby improving the PSRR and effectively suppressing power supply fluctuations. The startup module 200 is electrically connected to the bandgap core module 400. The startup module 200 helps the bandgap core module 400 to start up effectively, and can be disconnected after the bandgap core module 400 is working normally. The operational amplifier module 300 is electrically connected to the bandgap core module 400. The operational amplifier module 300 is used to perform negative feedback regulation on the reference voltage source output by the bandgap core module 400, making the output voltage more stable.

[0086] According to the bandgap reference circuit of this application embodiment, the power supply voltage is buffered by the pre-regulator module 100, and the influence of power supply voltage fluctuations on the reference voltage source is fed back to the pre-regulator module 100 for readjustment, thereby improving PSRR and better suppressing power supply fluctuations; the reference voltage source output by the bandgap core module 400 is negatively regulated by the operational amplifier module 300, making the output voltage more stable.

[0087] Further, as shown in Figure 5, in some embodiments of this application, the pre-regulator module 100 includes a first inverter, a second inverter, a first MOSFET M5, a first resistor R7, a second resistor R8, and a second MOSFET M6. The input terminal of the first inverter is connected to an enable signal (EN). The input terminal of the second inverter is electrically connected to the output terminal of the first inverter. The output terminal of the second inverter is connected to the gate of the first MOSFET M5. The source of the first MOSFET M5 is connected to the power supply voltage (VDD). The drain of the first MOSFET M5 is electrically connected to one end of the first resistor R7. The other end of the first resistor R7 is electrically connected to one end of the second resistor R8, and the other end of the second resistor R8 is grounded. The gate of the second MOSFET M6 is electrically connected to one end of the second resistor R8. The drain of the second MOSFET M6 is electrically connected to the drain of the first MOSFET M5. The source of the second MOSFET M6 outputs an operating voltage (AVDD).

[0088] It should be noted that since power supply fluctuations can affect the output of the bandgap reference circuit, the power supply for the bandgap reference circuit in this application is not directly provided by the power supply voltage. Instead, the pre-regulator module 100 buffers the power supply voltage before supplying power to the circuit, forming a feedback loop that feeds back the influence of the power supply voltage on the output voltage to the pre-regulator module for readjustment, thereby improving PSRR. As shown in Figure 5, EN is the enable terminal, controlled by an external controller sending an enable signal. When a low-level signal is input to the enable terminal, the low-level signal passes through the first inverter and the second inverter, and the output remains low. The first inverter and the second inverter act as buffers, which enhance the signal and reduce noise. Because the output of the second inverter is connected to the gate of the first MOSFET M5, the gate of the first MOSFET M5 is at a low level and conducts after the system is powered on. The current of the first MOSFET M5 flows through the first resistor R7 and the second resistor R8, generating a voltage that drives the second MOSFET M6 to conduct. After the second MOSFET M6 conducts, a voltage drop appears across its drain and source. The operating voltage of the bandgap reference circuit is output from the source of the second MOSFET M6. When the power supply voltage fluctuates and rises, the output voltage of the bandgap reference circuit rises accordingly, causing the output branch current to rise. This increases the current drawn from the pre-regulator module 100, which in turn strengthens the conduction of the second MOSFET M6, increasing the current in its branch. This increases the voltage drop across the drain and source of the second MOSFET M6, thereby reducing its source voltage and regulating the voltage. This has a significant effect on improving PSRR. Compared with traditional pre-regulator circuits, this pre-regulator module 100 has a simple design, no operational amplifier, and better suppression of power supply fluctuations.

[0089] Furthermore, in some embodiments of this application, as shown in FIG3, the first inverter includes a third MOS transistor M1 and a fourth MOS transistor M2. The gate of the third MOS transistor M1 is connected to an enable signal, the source of the third MOS transistor M1 is connected to a power supply voltage, the drain of the third MOS transistor M1 is connected to the drain of the fourth MOS transistor M2, the gate of the fourth MOS transistor M2 is connected to the gate of the third MOS transistor M1, the source of the fourth MOS transistor M2 is grounded, and the drain of the fourth MOS transistor M2 is also electrically connected to the input terminal of the second inverter. The first inverter pulls up a PMOS transistor (M1) and pulls down an NMOS transistor (M2). When the input is high, the NMOS transistor is turned on and the PMOS transistor is turned off, resulting in a low output; when the input is low, the NMOS transistor is turned off and the PMOS transistor is turned on, resulting in a high output. Therefore, the third MOS transistor M1 and the fourth MOS transistor M2 constitute the first inverter. Similarly, the second inverter includes a fifth MOSFET M3 and a sixth MOSFET M4. The gate of the fifth MOSFET M3 is electrically connected to the drain of the fourth MOSFET M2, the source of the fifth MOSFET M3 is connected to the power supply voltage, the drain of the fifth MOSFET M3 is electrically connected to the drain of the sixth MOSFET M4, the gate of the sixth MOSFET M4 is connected to the gate of the fifth MOSFET M3, and the source of the sixth MOSFET M4 is grounded. The principle of the second inverter is similar to that of the first inverter and will not be elaborated here.

[0090] Further, as shown in Figure 3, in some embodiments of this application, the startup module 200 includes a seventh MOSFET M7, an eighth MOSFET M8, a third resistor R9, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, a first transistor Q6, a twelfth MOSFET M12, a fourth resistor R4, and a thirteenth MOSFET (NMOS); wherein, the source of the seventh MOSFET M7 is connected to the operating voltage, the drain of the seventh MOSFET M7 is electrically connected to the gate of the eighth MOSFET M8, and the drain of the eighth MOSFET M8 is grounded; one end of the third resistor R9 is electrically connected to the drain of the seventh MOSFET M7, and the other end of the third resistor R9 is grounded; the source of the ninth MOSFET M9 is connected to the operating voltage, the gate of the ninth MOSFET M9 is electrically connected to the gate of the seventh MOSFET M7 and the tenth MOSFET M10, and the source of the tenth MOSFET M10 is connected to the operating voltage; the eleventh MOSFET M11... The drain of transistor Q11 is electrically connected to the source of transistor M8 (eighth) and the drain of transistor M9 (ninth). The source of transistor M11 (eleventh) is grounded. The collector of transistor Q6 is electrically connected to the drain of transistor M10 (tenth) and the gate of transistor M11 (eleventh). The emitter of transistor Q6 is grounded. The gate of transistor M12 is electrically connected to the gate of transistor M10 (tenth). The source of transistor M12 is connected to the operating voltage. The drain of transistor M12 is electrically connected to the base of transistor Q6. One end of resistor R4 is electrically connected to the base of transistor Q6 and the drain of transistor M12. The other end of resistor R4 is grounded. The gate of transistor NMOS (thirteenth) is electrically connected to the drain of transistor M12 (twelfth). The drain of transistor NMOS is connected to the operating voltage. The source of transistor NMOS is connected to the output (Vout) of the bandgap reference circuit.

[0091] It should be noted that the operating voltage of the startup module 200 is provided by the pre-regulator module 100. The gate of the thirteenth MOSFET (NMOS) is connected to the bias voltage, the drain is connected to the operating voltage, and the source is connected to the output terminal of the bandgap reference circuit. When the startup module 200 is powered on, the gate of the eighth MOSFET M8 is connected to ground via the third resistor R9 and is turned on. After it is turned on, the drain voltage of the ninth MOSFET M9 decreases, so M7, M9, M10, and M12 are all turned on. The drain of M12 is pulled high, causing the NMOS transistor to turn on. Because the NMOS uses a low threshold voltage transistor, the circuit turns on when the difference between its gate voltage and source voltage exceeds a threshold voltage. At this time, current flows into the output branch to the bandgap core module 400, causing the bandgap core module 400 to start normal operation. After the bandgap core module 400 is working normally, the output voltage rises, causing the gate-source voltage of the NMOS transistor to be less than the threshold voltage, the NMOS transistor is turned off, and the startup module 200 is turned off.

[0092] Further, as shown in Figure 3, in some embodiments of this application, the bandgap core module 400 includes a fourteenth MOSFET M13, a second transistor Q7, a fifteenth MOSFET M18, a third transistor Q3, a fourth transistor Q4, a fifth resistor R6, and a sixth resistor R5; wherein, the drain of the fourteenth MOSFET M13 is electrically connected to the operational amplifier module 300, the source of the fourteenth MOSFET M13 is electrically connected to the collector of the second transistor Q7, the emitter of the second transistor Q7 is grounded, and the base of the second transistor Q7 is electrically connected to the gate of the fourteenth MOSFET M13; the drain of the fifteenth MOSFET M18 is electrically connected to the operational amplifier module 300, and the source of the fifteenth MOSFET M18 is electrically connected to the third transistor Q3. The collector of transistor Q3 is electrically connected, and the emitter of transistor Q3 is grounded. The base of transistor Q4 is electrically connected to the base of transistor Q7 and the gate of MOSFET M13. The emitter of transistor Q4 is grounded, and the collector of transistor Q4 is electrically connected to the base of transistor Q3. One end of resistor R6 is electrically connected to the collector of transistor Q4, and the other end of resistor R6 is electrically connected to the base of transistor Q4. One end of resistor R5 is electrically connected to the other end of resistor R6. Resistor R5 is connected to the output terminal (Vout) of the bandgap reference circuit. Resistor R5 is a positive temperature coefficient resistor, and resistor R6 is a negative temperature coefficient resistor.

[0093] It should be noted that Figure 4 shows a simplified circuit of the bandgap core module 400. Node A in the figure is connected to the base of Q4, therefore the voltage at point A is V. BE4 (The forward bias voltage of the emitter junction of Q4), and the collector of Q4 is connected to the base of Q3, therefore the voltage at the collector of Q4 is V. BE3 (The forward bias voltage of the emitter junction of Q3). Therefore, the current flowing through R6 is / R6, where For V BE4 -V BE2 Since R5 and R6 are connected in series, the current flowing through R5 and R6 is equal. Therefore, the output voltage is:

[0094] ;

[0095] The bandgap core module 400 of this application differs from the traditional bandgap reference circuit structure in that the resistors with positive and negative temperature coefficients are connected in series on the same branch, which greatly reduces the loss during voltage and current transmission, thereby achieving low temperature drift.

[0096] Further, as shown in Figure 3, in some embodiments of this application, the operational amplifier module 300 includes a sixteenth MOSFET M14, a seventeenth MOSFET M15, an eighteenth MOSFET M16, a nineteenth MOSFET M17, a twentieth MOSFET M19, a twenty-first MOSFET M20, a twenty-second MOSFET M22, a twenty-third MOSFET M23, a twenty-fourth MOSFET M24, a twenty-fifth MOSFET M21, and a fifth transistor Q5. The source of the sixteenth MOSFET M14 is connected to the operating voltage, and the drain of the sixteenth MOSFET M14 is electrically connected to the drain of the fourteenth MOSFET M13. The seventeenth MOSFET M15... The source of the 17th MOSFET M15 is connected to the operating voltage. The gate of the 17th MOSFET M15 is electrically connected to the drain of the 17th MOSFET M15 and the gate of the 16th MOSFET M14. The drain of the 17th MOSFET M15 is electrically connected to the drain of the 15th MOSFET M18. The gate of the 18th MOSFET M16 is electrically connected to the gate of the 17th MOSFET M15. The source of the 18th MOSFET M16 is connected to the operating voltage. The gate of the 18th MOSFET M16 is electrically connected to the gate of the 19th MOSFET M17. The source of the 19th MOSFET M17 is electrically connected to the drain of the 18th MOSFET M16. The drain of the 20th MOSFET M19 is connected to the drain of the 19th MOSFET M14. The drain of MOSFET M17 and the gate of the twentieth MOSFET M19 are electrically connected. The source of the twentieth MOSFET M19 is grounded. The gate of the twentieth MOSFET M19 is electrically connected to the gate of the twenty-first MOSFET M20. The source of the twenty-first MOSFET M20 is grounded. The drain of the twenty-first MOSFET M20 is electrically connected to the drain of the twenty-second MOSFET M22. The source of the twenty-third MOSFET M23 is connected to the operating voltage. The drain of the twenty-third MOSFET M23 is electrically connected to the source of the twenty-second MOSFET M22. The gate of the twenty-third MOSFET M23 is electrically connected to the gate of the twenty-second MOSFET M22 and the sixteenth MOSFET. The drain of M14 is electrically connected; the source of the 24th MOSFET M24 is connected to the operating voltage, and the gate of the 24th MOSFET M24 is connected to the bias voltage (VB1); the drain of the 25th MOSFET M21 is electrically connected to the drain of the 24th MOSFET M24, the source of the 25th MOSFET M21 is grounded, and the gate of the 25th MOSFET M21 is electrically connected to the drain of the 21st MOSFET M20; the base of the 5th transistor Q5 is electrically connected to the drain of the 24th MOSFET M24, the collector of the 5th transistor Q5 is connected to the operating voltage, and the emitter of the 5th transistor Q5 is connected to the output terminal (Vout) of the bandgap reference circuit.

[0097] It should be noted that the bias voltage (VB1) is set and provided by external components according to the actual situation. For the operational amplifier module 300, M14 and M13 constitute an amplifier, with M14 biased by a current mirror formed by M15 and M16. Current flows through M18 after it is turned on; M15 and M18 are connected in series, so their currents are the same. M16 and M17 replicate the current of M15, and M19 is connected in series with M16 and M17, so its current is the same. M20 replicates the current of M19. M23, M22, and M20 constitute an amplifier, as do M24 and M21. The base of Q5 is connected to the drain of M21, and its emitter is connected to the output terminal as a source follower. When the output voltage increases, according to polarity analysis, the drain voltage of the fourteenth MOSFET M13 decreases, causing the drain voltage of M22 to increase, thus lowering the drain voltage of M21. Since Q5 is a source follower, the output voltage decreases. This operational amplifier module 300 can perform negative feedback regulation of the output voltage, making the output voltage more stable.

[0098] Further, as shown in Figure 3, in some embodiments of this application, the operational amplifier module 300 further includes a seventh resistor R0 and a first capacitor Cc. One end of the seventh resistor R0 is electrically connected to the drain of the twenty-fifth MOSFET M21, and the other end of the seventh resistor R0 is electrically connected to one end of the first capacitor Cc. The other end of the first capacitor Cc is electrically connected to the gate of the fourteenth MOSFET M13. Here, the first capacitor Cc is a Miller capacitor, and the seventh resistor R0 is a zero-adjustment resistor; both serve as compensation to ensure stable operation of the operational amplifier module 300.

[0099] The circuit simulation results of the bandgap reference circuit of this application are shown in Figure 6. Figure 6 shows the temperature characteristic curve of the bandgap reference circuit of this application, with the horizontal axis representing temperature (temp) and the vertical axis representing output voltage. The maximum value of the curve is 1.271V and the minimum value is 1.269V. The operating temperature of the circuit is selected as -40~125℃. The simulated temperature characteristic curve is shown in Figure 6 and can be calculated using the temperature coefficient formula.

[0100] ;

[0101] Wherein, the temperature coefficient TC is in ppm / ℃; Tmax and Tmin represent the maximum and minimum temperatures; Vmax represents the maximum value of the bandgap reference voltage Vout within the temperature range [Tmin, Tmax]; Vmin represents the minimum value of the bandgap reference voltage Vout within the temperature range [Tmin, Tmax]; Vav represents the output voltage value at room temperature. Substituting these values ​​into the above formula, the temperature coefficient of the circuit is approximately 9ppm / ℃. The simulated power supply rejection ratio (PSRR) frequency response curve is shown in Figure 7. It can be seen that the reference voltage source proposed in this application has a PSRR of -134.2dB at 1Hz; -76.5dB at 10kHz; and -45dB at 1MHz.

[0102] According to the bandgap reference circuit of this application, the circuit design of the bandgap core module 400 ensures that the positive temperature coefficient voltage and the negative temperature coefficient voltage are in the same branch as the output voltage, eliminating errors during voltage transmission and achieving a low temperature drift effect. Furthermore, the operational amplifier module 300's circuit design avoids the use of a cascode structure, increasing gain while preventing limited output signal swing. A complex startup circuit is unnecessary, and the use of a voltage follower avoids the significant impact of traditional negative feedback on the output voltage. In addition, this application uses a pre-regulator module 100 to effectively suppress power supply fluctuations, significantly improving PSRR. Therefore, this bandgap reference circuit achieves an ultra-high power supply rejection ratio and an extremely low temperature coefficient.

[0103] On the other hand, as shown in Figure 8, based on the above-described bandgap reference circuit, this application embodiment also proposes a method for operating the bandgap reference circuit, which includes the following steps:

[0104] Step S100: The power supply voltage is buffered by the pre-regulator module 100 to obtain the working voltage, and the working voltage is provided for the startup module 200 and the operational amplifier module 300.

[0105] Step S200: Based on the operating voltage, start the bandgap core module 400 via the start module 200;

[0106] Step S300: Based on the operating voltage, output a reference voltage source through the bandgap core module 400 and shut down the startup module 200;

[0107] Step S400: The reference voltage source is adjusted by negative feedback through the operational amplifier module 300;

[0108] Step S500: The influence of power supply voltage fluctuations on the reference voltage source is fed back to the pre-regulator module 100 for readjustment via the pre-regulator module 100.

[0109] Specifically, since power supply fluctuations can affect the output of the bandgap reference circuit, the power supply for the bandgap reference circuit in this application is not directly provided by the power supply voltage. Instead, the pre-regulator module 100 buffers the power supply voltage before supplying power to the circuit, forming a feedback loop that feeds back the influence of the power supply voltage on the output voltage to the pre-regulator module for readjustment, thereby improving PSRR. As shown in Figure 5, EN is the enable terminal, controlled by an external controller sending an enable signal. When a low-level signal is input to the enable terminal, the low-level signal passes through the first inverter and the second inverter, and the output remains low. The first inverter and the second inverter can act as buffers, which enhance the signal and reduce noise. Because the output of the second inverter is connected to the gate of the first MOSFET M5, the gate of the first MOSFET M5 is at a low level and conducts after the system is powered on. The current of the first MOSFET M5 flows through the first resistor R7 and the second resistor R8, generating a voltage that drives the second MOSFET M6 to conduct. After the second MOSFET M6 conducts, a voltage drop appears across its drain and source. The operating voltage of the bandgap reference circuit is output from the source of the second MOSFET M6. When the power supply voltage fluctuates and rises, the output voltage of the bandgap reference circuit rises accordingly, causing the output branch current to rise. This increases the current drawn from the pre-regulator module 100, which in turn strengthens the conduction of the second MOSFET M6, increasing the current in its branch. This increases the voltage drop across the drain and source of the second MOSFET M6, thereby reducing its source voltage and regulating the voltage. This has a significant effect on improving PSRR. Compared with traditional pre-regulator circuits, this pre-regulator module 100 has a simple design, no operational amplifier, and better suppression of power supply fluctuations.

[0110] The operating voltage of the startup module 200 is provided by the pre-regulator module 100. The gate of the thirteenth MOSFET (NMOS) is connected to the bias voltage, the drain is connected to the operating voltage, and the source is connected to the output terminal of the bandgap reference circuit. When the startup module 200 is powered on, the gate of the eighth MOSFET M8 is connected to ground by the third resistor R9 and is turned on. After it is turned on, the drain voltage of the ninth MOSFET M9 decreases, so M7, M9, M10, and M12 are all turned on. The drain of M12 is pulled high, causing the NMOS transistor to turn on. Because the NMOS uses a low threshold voltage transistor, the circuit turns on when the difference between its gate voltage and source voltage is greater than a threshold voltage. At this time, current flows into the output branch to the bandgap core module 400. When the output voltage of the startup module 200 reaches Vout, the base voltages of the fourth transistor Q4 and the third transistor Q3 rise, and the fourth transistor Q4 and the third transistor Q3 turn on, and the bandgap reference circuit begins to work normally. As the output voltage rises after the bandgap reference voltage operates normally, the gate-source voltage of the NMOS transistor falls below the threshold voltage, causing the transistor to turn off and the startup circuit to shut down. The bandgap core module 400 significantly reduces losses during voltage and current transmission by connecting resistors with positive and negative temperature coefficients in series on the same branch, thus achieving a low-temperature-drift reference voltage source. The operational amplifier module 300 provides negative feedback regulation to the reference voltage source, making the output voltage more stable.

[0111] According to the operating method of the bandgap reference circuit in this application, the circuit design of the bandgap core module 400 ensures that the positive temperature coefficient voltage and the negative temperature coefficient voltage are in the same branch as the output voltage, eliminating errors during voltage transmission and achieving a low temperature drift effect. Furthermore, the operational amplifier module 300's circuit design avoids the use of a cascode structure, increasing gain while preventing limited output signal swing. A complex startup circuit is unnecessary, and the use of a voltage follower avoids the significant impact of traditional negative feedback on the output voltage. In addition, this application uses a pre-regulator module 100 to effectively suppress power supply fluctuations, significantly improving PSRR. Therefore, this bandgap reference circuit achieves an ultra-high power supply rejection ratio and an extremely low temperature coefficient.

[0112] On the other hand, embodiments of this application also provide an electronic device, including a bandgap reference circuit as described in the first aspect embodiment.

[0113] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A bandgap reference circuit, characterized in that, include: Pre-regulated voltage module; The startup module is electrically connected to the pre-stabilized voltage module; the bandgap core module is electrically connected to the startup module. An operational amplifier module is electrically connected to both the bandgap core module and the pre-regulator module. The bandgap core module outputs a reference voltage source. The pre-regulator module buffers the power supply voltage to obtain an operating voltage and provides this operating voltage to the startup module and the operational amplifier module. The pre-regulator module also feeds back the impact of power supply voltage fluctuations on the reference voltage source for readjustment. The startup module starts the bandgap core module. The operational amplifier module provides negative feedback regulation of the reference voltage source. The pre-regulator module includes a first inverter with an enable pin connected to its input. Signal; a second inverter, the input terminal of which is electrically connected to the output terminal of the first inverter; a first MOSFET, the gate of which is electrically connected to the output terminal of the second inverter, and the source of the first MOSFET is connected to the power supply voltage; a first resistor, one end of which is electrically connected to the drain of the first MOSFET; a second resistor, one end of which is electrically connected to the other end of the first resistor, and the other end of the second resistor is grounded; a second MOSFET, the gate of which is electrically connected to one end of the second resistor, and the drain of which is electrically connected to the drain of the first MOSFET; the second MOSFET's... The source outputs the operating voltage; the bandgap core module includes: a fourteenth MOS transistor, the drain of which is electrically connected to the operational amplifier module; a second transistor, the collector of which is electrically connected to the source of the fourteenth MOS transistor, the emitter of which is grounded, and the base of which is electrically connected to the gate of the fourteenth MOS transistor; a fifteenth MOS transistor, the drain of which is electrically connected to the operational amplifier module; a third transistor, the collector of which is electrically connected to the source of the fifteenth MOS transistor, and the emitter of which is grounded; and a fourth transistor. The base of the fourth transistor is electrically connected to the base of the second transistor and the gate of the fourteenth MOS transistor. The emitter of the fourth transistor is grounded, and the collector of the fourth transistor is electrically connected to the base of the third transistor. A fifth resistor has one end electrically connected to the collector of the fourth transistor and the other end electrically connected to the base of the fourth transistor. A sixth resistor has one end electrically connected to the other end of the fifth resistor and is connected to the output terminal of the bandgap reference circuit. The sixth resistor is a positive temperature coefficient resistor, and the fifth resistor is a negative temperature coefficient resistor.

2. The bandgap reference circuit according to claim 1, characterized in that, The first inverter includes: a third MOS transistor, the gate of which is connected to the enable signal and the source of which is connected to the power supply voltage; and a fourth MOS transistor, the gate of which is connected to the gate of the third MOS transistor, the drain of which is connected to the drain of the third MOS transistor, the source of which is grounded, and the drain of which is also electrically connected to the input terminal of the second inverter.

3. The bandgap reference circuit according to claim 2, characterized in that, The second inverter includes: a fifth MOS transistor, the gate of which is electrically connected to the drain of the fourth MOS transistor, and the source of which is connected to the power supply voltage; and a sixth MOS transistor, the gate of which is connected to the gate of the fifth MOS transistor, the drain of which is connected to the drain of the fifth MOS transistor, and the source of which is grounded.

4. The bandgap reference circuit according to claim 1, characterized in that, The startup module includes: a seventh MOS transistor, the source of which is connected to the operating voltage; an eighth MOS transistor, the gate of which is electrically connected to the drain of the seventh MOS transistor, and the drain of the eighth MOS transistor is grounded; a third resistor, one end of which is electrically connected to the drain of the seventh MOS transistor, and the other end of which is grounded; a ninth MOS transistor, the source of which is connected to the operating voltage, and the gate of which is electrically connected to both the drain of the ninth MOS transistor and the gate of the seventh MOS transistor; a tenth MOS transistor, the gate of which is electrically connected to the gate of the ninth MOS transistor, and the source of which is connected to the operating voltage; and an eleventh MOS transistor, the drain of which is electrically connected to both the source of the eighth MOS transistor and the drain of the ninth MOS transistor. The source of the eleventh MOSFET is grounded; the collector of the first transistor is electrically connected to the drain of the tenth MOSFET and the gate of the eleventh MOSFET, and the emitter of the first transistor is grounded; the gate of the twelfth MOSFET is electrically connected to the gate of the tenth MOSFET, the source of the twelfth MOSFET is connected to the operating voltage, and the drain of the twelfth MOSFET is electrically connected to the base of the first transistor; a fourth resistor has one end electrically connected to the base of the first transistor and the drain of the twelfth MOSFET, and the other end of the fourth resistor is grounded; the gate of the thirteenth MOSFET is electrically connected to the drain of the twelfth MOSFET, the drain of the thirteenth MOSFET is connected to the operating voltage, and the source of the thirteenth MOSFET is connected to the output terminal of the bandgap reference circuit.

5. The bandgap reference circuit according to claim 1, characterized in that, The operational amplifier module includes: a sixteenth MOS transistor, the source of which is connected to the operating voltage, and the drain of which is electrically connected to the drain of the fourteenth MOS transistor; a seventeenth MOS transistor, the source of which is connected to the operating voltage, and the gate of which is electrically connected to the drain of the seventeenth MOS transistor and the gate of the sixteenth MOS transistor, and the drain of which is electrically connected to the drain of the fifteenth MOS transistor; an eighteenth MOS transistor, the gate of which is electrically connected to the gate of the seventeenth MOS transistor, and the source of which is connected to the operating voltage; a nineteenth MOS transistor, the gate of which is electrically connected to the gate of the eighteenth MOS transistor, and the source of which is electrically connected to the drain of the eighteenth MOS transistor; a twentieth MOS transistor, the drain of which is electrically connected to the drain of the nineteenth MOS transistor and the gate of the twentieth MOS transistor, and the source of which is grounded; and a twenty-first MOS transistor, the gate of which is connected to the twentieth MOS transistor. The gates of the 21st MOSFET are electrically connected, and the source of the 22nd MOSFET is grounded; the drain of the 22nd MOSFET is electrically connected to the drain of the 21st MOSFET; the source of the 23rd MOSFET is connected to the operating voltage, the drain of the 23rd MOSFET is electrically connected to the source of the 22nd MOSFET, and the gate of the 23rd MOSFET is electrically connected to the gate of the 22nd MOSFET and the drain of the 16th MOSFET; the source of the 24th MOSFET is connected to the operating voltage, and the gate of the 24th MOSFET is connected to the bias voltage; the drain of the 25th MOSFET is electrically connected to the drain of the 24th MOSFET, the source of the 25th MOSFET is grounded, and the gate of the 25th MOSFET is electrically connected to the drain of the 21st MOSFET; the base of the 5th transistor is electrically connected to the drain of the 24th MOSFET, the collector of the 5th transistor is connected to the operating voltage, and the emitter of the 5th transistor is connected to the output terminal of the bandgap reference circuit.

6. The bandgap reference circuit according to claim 5, characterized in that, The operational amplifier module further includes: a seventh resistor, one end of which is electrically connected to the drain of the twenty-fifth MOS transistor; and a first capacitor, one end of which is electrically connected to the other end of the seventh resistor, and the other end of which is electrically connected to the gate of the fourteenth MOS transistor.

7. A method for operating a bandgap reference circuit, characterized in that, Based on the bandgap reference circuit as described in any one of claims 1 to 6, the method includes: buffering the power supply voltage through a pre-regulation module to obtain an operating voltage, and providing the operating voltage to a startup module and an operational amplifier module; starting the bandgap core module through the startup module according to the operating voltage; outputting a reference voltage source through the bandgap core module according to the operating voltage, and shutting down the startup module; performing negative feedback regulation on the reference voltage source through the operational amplifier module; and feeding back the influence of power supply voltage fluctuations on the reference voltage source to the pre-regulation module for readjustment through the pre-regulation module; the pre-regulation module includes: a first inverter, the input terminal of which is connected to... The system includes: an enable signal; a second inverter, whose input is electrically connected to the output of the first inverter; a first MOSFET, whose gate is electrically connected to the output of the second inverter, and whose source is connected to the power supply voltage; a first resistor, one end of which is electrically connected to the drain of the first MOSFET; a second resistor, one end of which is electrically connected to the other end of the first resistor, and the other end of the second resistor is grounded; a second MOSFET, whose gate is electrically connected to one end of the second resistor, whose drain is electrically connected to the drain of the first MOSFET, and whose source outputs the operating voltage.

8. An electronic device, characterized in that, Includes the bandgap reference circuit as described in any one of claims 1-6.

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