Chip controller IC driven display screen backlight cooperative scheduling system

Abstract

The application relates to the technical field of display control, and discloses a display screen backlight cooperative scheduling system driven by a chip controller IC, which comprises a feature pre-analysis module, a driving waveform mapping unit, a scheduling control module and a backlight driving chip, the feature pre-analysis module is used for extracting the partition luminance features of a frame to be displayed and determining liquid crystal response delay parameters; the driving waveform mapping unit is used for determining current gain correction parameters of an initial overdrive period; the scheduling control module is used for issuing a communication message containing scheduling parameters in a vertical blanking period; and the backlight driving chip is used for driving a light-emitting diode array to generate a light field by using a current increase before frame synchronization, so that the physical matching of a backlight energy accumulation rate and a liquid crystal pixel transmittance growth curve is realized, and the gray scale drift generated by the luminance transition transient state of the display screen is inhibited.

Description

Technical Field

[0001] This invention relates to a display screen backlight collaborative scheduling system driven by a chip controller IC, belonging to the field of display control technology. Background Technology

[0002] Current high dynamic range display technology typically uses driver integrated circuits to extract the brightness weights of each zone and transmits dimming parameters to the backlight driver integrated circuit according to the communication protocol timing, so that the light output intensity of the backlight array is synchronized with the transmittance state of the pixel molecules. As the display refresh rate increases or a variable refresh mode is introduced, the system generates timing coordination differences. These differences arise from the interference between the communication delay of the protocol bus and the physical response time of the light-emitting diode light source on a microsecond scale, causing the backlight energy build-up process to lag behind the image signal refresh process.

[0003] Visual ghosting and edge halos occur in high-speed motion images. Existing solutions use a fixed time offset for preset triggering, but this method does not consider the physical mismatch between the nonlinear charge-discharge curve of the liquid crystal response and the rising edge shape of the light source, and cannot adapt to the dynamic fluctuation of the refresh rate. Furthermore, the instantaneous concentrated transmission of dimming data increases bus bandwidth load and power consumption. For example, Chinese invention patent CN118711535B discloses a backlight driving circuit, a backlight driving board, and a backlight driving method. This patent focuses on ambient temperature sensing. Adjusting the drive voltage output power in time periods under low-temperature environments solves the problem of cold start flickering in the backlight module. Although the solution improves the stability of hardware operation, it is still essentially a static or quasi-static power compensation solution. It does not address the problem of coordinated scheduling between the display signal and the backlight light field under high-speed dynamic switching. In actual working conditions, simple power stepping or fixed phase compensation cannot adapt to the nonlinear charging and discharging curve of liquid crystal molecules, and it is difficult to eliminate the random communication delay caused by bus load fluctuations. This causes a morphological mismatch between the backlight energy accumulation rate and the liquid crystal pixel transmittance growth curve in the microscopic time domain of a single frame, resulting in transient grayscale drift during brightness transitions.

[0004] Therefore, how to determine the look-ahead compensation phase based on the display refresh rate trend and the physical delay of the link, and perform partition brightness feature preset and backlight drive waveform shaping during the vertical blanking period, becomes the technical problem to be solved by this invention. Summary of the Invention

[0005] To address the problems mentioned in the background art, the technical solution of the present invention is as follows: A display screen backlight collaborative scheduling system driven by a chip controller IC, comprising:

[0006] The feature pre-analysis module is used to extract the partition brightness features of the frame to be displayed, calculate the brightness difference between the current frame and the frame to be displayed, and determine the liquid crystal response delay parameters of the display screen based on the pixel response lookup table.

[0007] The driving waveform mapping unit is connected to the feature pre-analysis module. It is used to receive the liquid crystal response delay parameters, divide the pre-compensation phase into the initial overdrive period and the steady-state maintenance period, and determine the current gain correction parameters corresponding to the initial overdrive period based on the brightness difference.

[0008] The scheduling control module, connected to the drive waveform mapping unit, is used to embed current gain correction parameters, pre-compensation phase, and partition brightness characteristics of the frame to be displayed into the communication message sent during the vertical blanking period.

[0009] The backlight driver chip, connected to the scheduling control module, is used to drive the light-emitting diode array with a driving current increased by the current gain correction parameter at the start time determined by the pre-compensated phase before receiving the frame synchronization signal, so that the energy accumulation rate of the backlight light field at the beginning of a single frame matches the transmittance growth curve of the liquid crystal pixels in the display screen.

[0010] Preferably, it includes a backlight response feedback compensation unit; the backlight response feedback compensation unit is used to send a detection excitation to the backlight driver chip during the vertical blanking period and collect the current sampling signal fed back by the light-emitting diode array; the backlight response feedback compensation unit is also used to invert the physical response step size of the light-emitting diode array based on the slope of the current sampling signal, and iteratively update the pre-compensation phase output by the driving waveform mapping unit accordingly.

[0011] Preferably, when extracting the brightness features of the partitions, the feature pre-analysis module is also used to perform spatial domain weighted filtering on the frame to be displayed in order to identify the brightness gradient of adjacent partitions in the frame to be displayed, and to correct the liquid crystal response delay parameters based on the brightness gradient.

[0012] Preferably, when dividing the initial overdrive period, the driving waveform mapping unit is also used to dynamically adjust the duration ratio of the initial overdrive period in the pre-compensation phase according to the liquid crystal response delay parameter, and the duration ratio increases with the increase of the deflection viscosity coefficient of the liquid crystal molecules.

[0013] Preferably, the scheduling control module has a checksum field in the communication message. The checksum field is used for the backlight driver chip to verify the integrity of the current gain correction parameters and the pre-compensation phase. If the verification fails, the backlight driver chip maintains the driving parameters of the previous frame.

[0014] Preferably, the drive waveform mapping unit follows the following linear compensation rule when determining the current gain correction parameters: ,in, For current gain correction parameters, This is the difference in brightness. For pre-compensation phase, This is a preset proportional adjustment factor.

[0015] Preferably, the backlight driver chip includes a constant current driving circuit and a pulse shaping buffer; the constant current driving circuit outputs a driving current pulse to the pulse shaping buffer; the pulse shaping buffer is used to adjust the rising edge of the driving current pulse during the pre-compensation phase so that the turn-on curve generated by the backlight light field fits the transmittance growth curve of the liquid crystal pixel.

[0016] Preferably, the backlight response feedback compensation unit sets the emission frequency of the detection excitation to an integer multiple of the frame synchronization signal frequency, and the luminous intensity triggered by the detection excitation is less than 0.01 cd / m².

[0017] Preferably, the scheduling control module includes an asynchronous communication interface; the asynchronous communication interface is used to complete the transmission of communication messages during time periods outside of the display of valid rows, and to trigger the backlight driver chip to update the current gain correction parameters in the register using the vertical synchronization signal.

[0018] Preferably, it also includes an energy consumption safety monitoring module; the energy consumption safety monitoring module is connected to the scheduling control module and is used to monitor the instantaneous current value of the light-emitting diode array during the initial overdrive period, and when the instantaneous current value exceeds the preset safety threshold, it feeds back a current limiting signal to the scheduling control module to forcibly reduce the value of the current gain correction parameter.

[0019] Compared with the prior art, the beneficial effects of the present invention are:

[0020] 1. In the backlight collaborative scheduling of the display screen, by constructing a cross-frame timing overlap preset mechanism in the chip controller, the vertical blanking period in the display protocol is used as a logical buffer window to pre-extract the partition brightness features of the frame to be displayed and push them into the backlight drive register. Combined with the line synchronization signal counter reuse technology, the compensation phase, which includes bus communication delay and light source physical response inertia, is mapped to a specific line number offset. This makes the flipping action of the backlight drive signal accurately anchored at the beginning stage of pixel charge filling. This breaks the linear logic limitation of the response after data arrival in traditional backlight control. Even under the variable frequency operation with dynamic fluctuation of refresh rate, it can still ensure that the stable range of the backlight light field and the pixel deflection period are highly aligned in spatial phase, eliminating the edge halos and brightness flicker caused by timing misalignment during high dynamic screen switching.

[0021] 2. A transient energy pattern matching mechanism is introduced. By calculating the brightness energy gradient between the current frame and the frame to be displayed, and determining the corresponding current gain correction parameters based on the deflection hysteresis characteristics of liquid crystal molecules, the system drives the backlight array to perform waveform shaping in the initial stage within the window time defined by the look-ahead compensation phase. By using the controlled overdrive current to compensate for the nonlinear characteristics of the liquid crystal molecule response, the physical coupling of the photon emission flux change rate of the backlight array and the transmittance change rate of the liquid crystal pixels is realized. This enables the backlight energy envelope and the pixel display envelope to achieve real-time overlap in the energy dimension within a single frame, solving the problem that traditional technology can only align at a time point but cannot match the response slope, and eliminating the visual grayscale drift caused by brightness transition transients.

[0022] 3. Construct a physical response mirror closed-loop calibration logic. Utilize the non-display time window during the vertical blanking period to send subthreshold intensity probe excitations to the drive link and collect the characteristic slope of the feedback current. The system uses this electrical characteristic to invert the physical response step size of the light source in real time and performs iterative correction on the look-ahead compensation phase accordingly. This enables the scheduling system to autonomously perceive the characteristic deviation of the LED device caused by temperature fluctuations, voltage ripple, or device aging, realizing the transformation from open-loop prediction to closed-loop calibration. Without adding external sensors, it ensures the timing determinism of the collaborative scheduling logic throughout its entire life cycle and under wide temperature range conditions, avoiding compensation phase failure caused by temperature drift of hardware physical characteristics, and enhancing the system's engineering stability and adaptive calibration capability. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the core signal link and driving principle of the backlight collaborative scheduling system of the present invention;

[0024] Figure 2 This is a detailed system architecture diagram of the integrated feedback compensation and energy consumption monitoring mechanism of the present invention. Detailed Implementation

[0025] The technical solution claimed in this invention will be described in detail below with reference to the accompanying drawings. The following embodiments are intended to explain and illustrate this invention, and are not intended to limit the scope of protection of this invention.

[0026] A display backlight collaborative scheduling system driven by a chip controller IC includes a feature pre-analysis module, a driving waveform mapping unit, a scheduling control module, and a backlight driver chip. The feature pre-analysis module extracts the partitioned brightness features of the frame to be displayed and determines the liquid crystal response delay parameters. The driving waveform mapping unit, connected to the feature pre-analysis module, receives the liquid crystal response delay parameters and divides the pre-compensation phase into an initial overdrive period and a steady-state maintenance period. Simultaneously, it determines the current gain correction parameters corresponding to the initial overdrive period based on the brightness difference. The scheduling control module, connected to the driving waveform mapping unit, embeds the current gain correction parameters and the pre-compensation phase into the communication messages sent during the vertical blanking period. The backlight driver chip, connected to the scheduling control module, uses a drive current adjusted by the current gain correction parameter to drive the LED array to generate a backlight field at the start time determined by the pre-compensated phase before receiving the frame synchronization signal. This invention achieves physical matching between the backlight energy accumulation rate and the liquid crystal pixel transmittance growth curve, suppressing grayscale drift caused by the transient brightness transition of the display screen. Based on the interference between the communication delay of the protocol bus and the physical response time of the light source caused by the increase in display refresh rate, resulting in an application layer challenge where the backlight energy establishment process lags behind the image signal refresh, the system adopts a cross-frame timing overlap preset method. The feature pre-analysis module in the current frame... Extract the next frame within a preset window period before the end of the valid pixel data segment. The average brightness characteristics of the partitions are obtained and encapsulated into a preset message; the driving waveform mapping unit receives the liquid crystal response delay parameters and pre-compensated phase... Divided into an initial overdrive period and a steady-state maintenance period, with pre-compensation phase. Satisfying the relation ,in Pre-compensated phase, unit: , The time taken for logical operations, in units of , The physical response step size for the LED to reach the target stable brightness value, in units of 1. , Bus transmission delay, in units of The scheduling control module utilizes the idle period of the vertical blanking period to push preset messages into the registers of the backlight driver chip in advance. The backlight driver chip then receives the frame synchronization signal before... The drive signal is constantly triggered to flip, so that the flipping action of the backlight drive signal is anchored at the beginning stage of pixel charge filling, eliminating edge vignetting caused by timing misalignment during high dynamic range scene switching.

[0027] Because the transmittance of liquid crystal pixels increases non-linearly with charge injection, a morphological mismatch occurs between the liquid crystal transmittance envelope and the backlight energy envelope in the early stages of a single frame. To address this, the system employs an overdrive preset method for the initial current. When extracting the luminance features of different zones, the feature pre-analysis module calculates the luminance difference between the current frame and the frame to be displayed. The display screen's liquid crystal response delay parameters are determined based on a pixel response lookup table; the drive waveform mapping unit determines the liquid crystal response delay parameters based on the brightness difference. Determine the current gain correction parameters corresponding to the initial overdrive period. Current gain correction parameters Follow the linear compensation rule ,in For current gain correction parameters, This is the difference in brightness. For pre-compensation phase, As a scaling factor, in specific numerical applications, when the scaling factor... Set to 0.85, brightness difference. 128 gray levels with pre-compensated phase for At that time, the current gain correction parameter was calculated. The value is 5.44; the backlight driver chip is in pre-compensated phase. At a given start time, the current gain correction parameter is used. The increased driving current drives the LED array to generate a backlight field with a preset rising slope, matching the backlight energy accumulation rate with the transmittance growth curve of the liquid crystal pixels, thus solving the grayscale drift problem caused by brightness transition transients; proportional adjustment factor The established process is as follows: utilizing a response frequency of not less than A high-precision photoelectric acquisition device monitors the transmittance growth curve of the display panel. A typical grayscale transition sequence covering the grayscale range of 0 to 255 is input into the display system. Simultaneously, the drive current waveform of the LED array is acquired, and the energy integral deviation at the beginning of a single frame is calculated. ; The difference between the actual backlight output energy and the theoretical transmission energy of the liquid crystal pixel within a single frame is calculated during the traversal. In tests with values ​​ranging from 0.5 to 1.5, the values ​​selected minimize the energy integral deviation. The absolute value is the smallest and does not exceed The values ​​are stored in non-volatile memory as calibration constants and are used as current gain correction parameters. Online solutions provide the basis for calculation.

[0028] Considering the technical risk of look-ahead phase failure due to physical response step size shift caused by ambient temperature fluctuations in the backlight driver link, the system adopts a physical response mirror closed-loop calibration method. The system includes a backlight response feedback compensation unit. During the vertical blanking period, this unit sends a detection stimulus with a pulse width lower than the human eye's perception threshold to the backlight driver chip, acquiring the current sampling signal fed back by the LED array. The backlight response feedback compensation unit is based on the characteristic slope of the current sampling signal... Real-time physical response step size of inverted LED array Calculate the corrected pre-compensation phase ,in This is the corrected pre-compensation phase. The pre-compensation phase before correction. For real-time physical response step size, To design the nominal value; the system is based on the characteristic slope Dynamic adjustment of pre-compensation phase based on changing trends This enables the scheduling system to autonomously detect characteristic deviations in LED devices caused by temperature fluctuations, ensuring the timing determinism of the collaborative scheduling logic throughout its entire lifecycle. The backlight response feedback compensation unit utilizes a high-sampling-rate analog-to-digital converter to acquire the current sampling signal flowing through the LED array, and uses differential operations to extract the slope of the current sampling signal change during the detection excitation pulse. Input a preset physical response mapping model to invert the real-time physical response step size The physical response mapping model consists of a slope-time correspondence pre-stored in a lookup table, compared with the physical response step size. The measured value and the design nominal value are compared, and the system corrects the pre-compensation phase according to the linear compensation relationship. According to the corrected pre-compensated phase Recalculate row offset The system locks the communication message download time at a specific scan line position. To address the bus bandwidth load pressure caused by the full transmission of backlight metadata in ultra-high partition display systems, the system adopts a perception threshold-driven differential reconstruction method for backlight metadata. The feature pre-analysis module performs point-by-point differential calculations on the brightness features of adjacent display cycles and filters them using a threshold matrix determined by the human eye's contrast sensitivity function. If the brightness change feature of a partition is lower than the preset perception boundary of the threshold matrix, the partition is determined to be in a resting state. The scheduling control module only generates burst prefetch messages for partitions that are not in a resting state. For partitions in a resting state, the backlight driver chip reuses the register state of the previous cycle. The freed-up blanking time space is allocated to the brightness jump area to perform multi-segment current compensation, alleviating the communication bandwidth bottleneck without increasing the bus operating frequency and reducing the invalid toggling actions of the internal registers of the driver chip.

[0029] Under variable frequency refresh conditions, the blanking period length fluctuates due to the dynamic adjustment of the display frame period with the image content. The system employs a timing anchor point adaptive relocking method. The scheduling control module acquires the real-time fluctuation parameters of the display refresh frequency and applies the pre-compensated phase... Mapped to row number offset based on row synchronization signal period The calculation formula is: ,in This is the row number offset. For pre-compensation phase, The single-line scan cycle is used; the scheduling control module monitors the frame start guide signal during the vertical blanking period, uses the frame start guide signal as the trigger reference, and dynamically adjusts the line number offset based on the refresh rate fluctuation trend. If a refresh rate decrease is detected during the trigger phase, the scheduling control module automatically compensates the trigger time with a correction value that is linearly related to the blanking period increment, ensuring that the pre-modulation action is always locked within the specific physical line spacing before pixel data scanning, thus eliminating brightness fluctuations during frequency conversion. The scheduling control module internally has a 16-bit wide line counter synchronized with the display line scanning frequency. The line counter performs a reset action upon arrival of the vertical synchronization signal pulse and increments the count upon receiving each line synchronization signal pulse from the display data channel. When the count value of the line counter is equal to the value obtained from the pre-compensated phase... Row offset obtained from mapping When the values ​​are equal, the hardware logic gate circuit of the scheduling control module generates a high-level trigger signal, forcing the serial peripheral interface of the backlight driver chip to load the latest scheduling message data from the asynchronous buffer queue, thereby locking the flipping moment of the backlight physical light field at a specific physical position of the image scan line.

[0030] Example 1: When the display refresh rate is 144Hz and the single frame refresh period is... In operation, when the system plays an ultra-high-definition video stream containing high-speed moving objects, the traditional backlight drive command only begins packet transmission at the start of the vertical blanking period. This causes the starting point of backlight energy accumulation to lag behind the starting point of liquid crystal pixel charge filling, resulting in grayscale drift and ghosting at the edges of moving objects. The feature pre-analysis module and the scheduling control module execute cross-frame timing overlap preset actions. The feature pre-analysis module in the current frame... Before the end of the effective pixel data segment Extract the next frame The characteristics of the average brightness of the partitions and the calculation of the brightness difference. The driving waveform mapping unit receives the liquid crystal response delay parameters and converts them into pre-compensated phase. The scheduling control module will include current gain correction parameters after the communication window during the vertical blanking period is opened. Preset messages containing the brightness characteristics of different zones are pushed to the asynchronous buffer register of the backlight driver chip in advance, so that the backlight driver chip can handle the situation before the frame synchronization signal arrives. The drive waveform is constantly flipped based on the preset message, so that the current response of the LED array is always anchored at the starting point of the liquid crystal pixel deflection.

[0031] The system mitigates the shape mismatch of the luminance integral envelope within a single frame through a transient energy shape matching mechanism, and drives the waveform mapping unit to pre-compensate the phase according to the liquid crystal response delay parameters. The process is divided into an initial overdrive period and a steady-state maintenance period, and the calculation formula is used. Determine the current gain correction parameters, where For current gain correction parameters, This is the difference in brightness. Pre-compensated phase, unit: , This is a proportional adjustment factor with a value of 0.85. The backlight driver chip corrects parameters based on the current gain. During the initial overdrive period, the LED array is driven to generate a backlight field with a specific rising slope, causing the backlight energy accumulation rate to coincide with the nonlinear transmittance growth curve of the liquid crystal pixels. Waveform reshaping is then used to adapt the backlight energy envelope to the response characteristics of the liquid crystal molecules. In a continuous 144Hz operating environment, the system utilizes feature data extracted by the feature pre-analysis module and a pre-compensated phase determined by the driving waveform mapping unit. The backlight activation time is aligned with the phase of the pixel activation window, and the current overdrive logic executed by the backlight driver chip eliminates visual glitches caused by brightness transition transients.

[0032] Example 2: In a scenario where the display refresh rate fluctuates dynamically, the R&D team built a physical test platform including a 4K resolution LCD module and a high sampling rate current monitoring circuit. The sampling frequency of the current monitoring circuit is no less than 10MHz. Gaussian white noise with a signal-to-noise ratio of 25dB is superimposed at the signal input to simulate power supply ripple interference. The sampling period is... The setting is based on a trade-off between display refresh rate and bus bandwidth. When the refresh rate is 144Hz, the sampling period is set to... During the experiment, the feature pre-analysis module monitored the brightness difference between the current frame and the frame to be displayed. The R&D team adjusted the ratio adjustment factor. To verify the effectiveness of the scheme, the control group exhibited visible flickering during brightness transitions, while the experimental group implemented a transient energy-morphology matching mechanism based on the formula... Calculate the current gain correction parameters, where For current gain correction parameters, This is the difference in brightness. Pre-compensated phase, unit: , For the proportional adjustment factor, subscript The overdrive state is shown in Table 1, which compares the scheduling parameters and response results under different brightness gradients. See Table 1 for specific data. When the brightness difference... When increasing from 32 gray levels to 255 gray levels, the generated current gain correction parameters It shows an increasing trend, calculated under the condition of 255 gray levels. The value was 10.84. At this point, the measured grayscale drift decreased from 12.42 cd / m² in the control group to 1.85 cd / m² in the experimental group. The data shows that the increased current offset the integral energy deviation caused by the liquid crystal response hysteresis.

[0033] Table 1: Comparison of scheduling parameters and response results under different brightness gradients

[0034]

[0035] To determine the pre-compensation phase During the work window, the R&D team performed boundary stress tests when the pre-compensation phase was set below the physical response step size. At this time, the brightness gain of the LED array is insufficient due to inadequate charging of the junction capacitance, while when the pre-compensation phase exceeds... Subsequently, excessively long over-driving time caused the junction temperature of the LED chip to rise, resulting in a decrease in luminous efficiency. Test records show that when the phase was set to... The system has the smallest response delay deviation, and the stable range of the physical light field is aligned with the pixel deflection period. This experiment, by measuring the brightness gradient, compensation phase, and physical response step size, confirms the effectiveness of the display backlight collaborative scheduling system in suppressing grayscale drift. As the brightness difference increases, the current gain correction parameter and the liquid crystal response characteristics show a correlation change, solving the problem that the backlight energy build-up process lags behind the image signal refresh under high refresh rate display, and completing the verification closed loop from brightness metadata to light field energy form adaptation.

[0036] Example 3: This example combines Figures 1 to 2 A description of a display backlight collaborative scheduling system driven by a chip controller IC is provided, such as... Figure 1As shown, the frame to be displayed is used as input to the feature pre-analysis module. The feature pre-analysis module is used to extract the zonal brightness features and determine the liquid crystal response delay parameters. The liquid crystal response delay parameters are transmitted to the drive waveform mapping unit. The drive waveform mapping unit determines the current gain correction parameters for the initial overdrive period based on these parameters. The current gain correction parameters are sent to the scheduling control module. This module is used to send a communication message containing scheduling parameters during the vertical blanking period. The communication message reaches the backlight driver chip via the transmission path. The backlight driver chip is used to drive the light-emitting diode array with the drive current (specifically, the modulated current) before frame synchronization. Finally, the light-emitting diode array generates the backlight light field.

[0037] like Figure 2 As shown, the feature pre-analysis module receives data from the frame to be displayed and the current frame, and outputs the liquid crystal response delay parameters and partition brightness characteristics to the driving waveform mapping unit. The backlight response feedback compensation unit is connected to the driving waveform mapping unit, the backlight driver chip, and the light-emitting diode array through the dashed path. It sends an updated pre-compensation phase to the driving waveform mapping unit, sends a detection excitation to the backlight driver chip, and receives the current sampling signal from the light-emitting diode array. The driving waveform mapping unit outputs the current gain correction parameters and the pre-compensation phase to the scheduling control module. The energy consumption safety monitoring module is connected to the backlight driver chip and the scheduling control module through the dashed path. It is used to receive the transient current value of the backlight driver chip and send a current limiting signal to the scheduling control module. The scheduling control module transmits the communication message and the vertical blanking period signal to the backlight driver chip. The backlight driver chip outputs the increased driving current to the light-emitting diode array.

[0038] Example 4: In a variable refresh rate display, the refresh rate dynamically fluctuates between 48Hz and 144Hz. The feature pre-analysis module uses the on-chip system's data bus to acquire the frame to be displayed. The pixel stream data enters the pipeline buffer, where the color conversion unit converts the 10-bit wide red, green, and blue components into luminance components. The conversion rules satisfy ,in For the luminance component, The red component, For the green component, Blue component, brightness component The data is written into a partitioned integral array consisting of 64 sets of accumulation registers. At 1080p resolution, the color conversion unit accumulates the brightness values ​​of each partition every 32,400 pixel clock cycles. It then performs a 15-bit right shift operation on the accumulated result using a shift operator to generate the partition's average brightness feature value, completing the process from raw pixel data to partition metadata. The drive waveform mapping unit receives the partition brightness features of the current frame and the frame to be displayed and calculates the grayscale transition vector. When the transition target value of a specific partition is not at a preset integer node in the pixel response lookup table, the system executes a slope-compensated linear interpolation procedure, locking the low-order node adjacent to the target value in the lookup table. and high-level nodes And read the corresponding preset delay parameters. and Using interpolation formulas Determine the liquid crystal response delay parameters, where This refers to the liquid crystal response delay parameter. The target value for brightness, The brightness value of the low-order node. This represents the brightness value of the high-order node. The preset delay parameter is the one corresponding to the low-order node. The preset delay parameters corresponding to the high-order nodes are used to drive the waveform mapping unit according to the liquid crystal response delay parameters. Calculate the pre-compensation phase Absolute timestamp, pre-compensated phase The value is the sum of the logic operation time, the physical response step size, and the bus transmission delay.

[0039] The scheduling control module monitors the line synchronization signal in the display protocol. When the line counter value reaches the preset line offset, the module will initiate a new line synchronization operation. The asynchronous interface of the backlight driver chip is triggered to load registers, including the row offset. For pre-compensation phase The ratio to the single-line scan period is rounded up. After receiving the frame start guide signal at the end of the vertical blanking period, the backlight driver chip starts its internal 100MHz adaptive counter. When the count value decreases to the value corrected by the current gain parameter, the counter is activated. During the corresponding preset period, the charge pump circuit inside the chip increases the driving voltage of the LED array, aligning the rising edge slope of the light field with the deflection rate of the liquid crystal molecules. This is achieved at a refresh rate of 144Hz and a frame period of [missing information]. During operation, the deviation of the starting time of the backlight energy establishment controlled by the chain is within... Within the specified range, the contrast stability problem caused by synchronization signal fluctuations under variable frequency operation was resolved. To address time axis drift caused by frequency refresh rate fluctuations, the scheduling control module uses the master clock to count the interval between the start-guide signals of two consecutive frames, compares the real-time frame period with the reference period to obtain the change in blanking period length, and adjusts the line counter reload threshold based on this variable to ensure the pre-compensated phase... The corresponding time window is anchored at the starting point of pixel charge filling; the frame start guide signal is a vertical synchronization signal pulse or an equivalent timing flag bit. Using an adaptive relocking mechanism, the backlight light field opening time is aligned with the spatial phase of the liquid crystal molecule deflection period under different display refresh frequencies, suppressing the contrast flicker phenomenon induced by blanking period fluctuations.

[0040] Example 5: In the production calibration process of a display backlight collaborative scheduling system driven by a chip controller IC, the method for determining the original data of the pixel response lookup table includes using a high sampling rate photoelectric conversion device to monitor the physical response characteristics of the display module, injecting a step signal into the light-emitting diode array using a constant current driving source under a controlled temperature environment, measuring the time required for the luminous flux to reach 90% of the steady-state brightness, and defining it as the physical response step size. ,in This is the physical response step size; it is achieved by iterating through different brightness differences. A mapping relationship between the liquid crystal response delay parameter and the brightness difference is established with respect to the ambient temperature gradient and stored in the non-volatile memory of the chip controller IC. For brightness differences, this procedure provides the physical basis for calculating scheduling parameters.

[0041] Before the collaborative scheduling system is deployed in a specific hardware environment, a pre-calibration procedure is performed to eliminate the impact of batch differences in components on scheduling accuracy. The backlight driver chip enters self-calibration mode and sends a wide signal to each backlight physical partition. The detection pulse is used by the sampling circuit inside the backlight driver chip to collect the feedback signal from the LED array and calculate the characteristic slope. ,in The characteristic slope satisfies the ratio of the change in sampling current to the sampling time step; the system relies on the characteristic slope Corrected pre-compensation phase The physical components in the equation, and adjust the proportional adjustment factor. To make the backlight energy accumulation rate approach the transmittance growth rate of the liquid crystal pixels, until the measured value of grayscale drift is lower than the preset 1.5 cd / m², where For pre-compensation phase, As a scaling factor, it completes the adaptive parameter calibration of the scheduling system for a specific display panel.

[0042] Example 6: Determining the scaling factor during the integration and debugging of the display module. With current gain correction parameters The methods include placing the system in a constant-temperature environment with a temperature deviation of less than 1°C; the feature pre-analysis module receives a preset brightness transition sequence as an excitation signal, and the system synchronously starts the photoelectric acquisition unit to record the rate of change of light field energy, wherein the response frequency of the photoelectric acquisition unit is not less than 1MHz and the range covers 1cd / m² to 2000cd / m²; the system executes curve fitting logic based on the least squares method, calculates the morphological overlap between the measured backlight rise curve and the liquid crystal transmittance model, and iteratively adjusts the proportional adjustment factor. The value, up to the energy integral deviation at the beginning of a single frame. Meet the conditions ,in As a proportional adjustment factor, For current gain correction parameters, This represents the energy integral deviation; the corresponding proportional adjustment factor at this point. With current gain correction parameters It is embedded in non-volatile storage units to achieve matching between scheduling parameters and physical panel response characteristics.

[0043] When the system faces a situation where communication message transmission is interrupted or a checksum error occurs during the vertical blanking period, the scheduling control module initiates an online fault-tolerant procedure to ensure the stability of the display screen. The system monitors the status register of the asynchronous communication interface in real time. If the cyclic redundancy check code of the preset message does not match the locally calculated value, or if the bus transmission delay... Exceed The scheduling control module sends a signal to the backlight driver chip to block the drive path, whereby... To reduce bus transmission delay, the backlight driver chip reuses the effective frame steady-state current value stored in the on-chip static random access memory to drive the LED array. A redundant buffering mechanism suppresses communication fluctuations without interrupting display refresh, ensuring the LED array can withstand frequency refresh fluctuations exceeding the pre-compensated phase. Maintain luminescence within the coverage area, where To pre-compensate the phase, during switching between displaying high dynamic range (HDR) peak brightness images, the energy consumption safety monitoring module obtains the power supply voltage of the LED array in real time through the hardware sampling circuit built into the backlight driver chip. And according to the power supply voltage Current gain correction parameter Increase the magnitude of the transient sag to determine the system's power margin; if the supply voltage is detected... If the rate of drop exceeds the preset threshold of 0.5V per microsecond, the scheduling control module initiates the current limiting procedure, adjusting the current gain correction parameters to be sent. The backlight response speed is forcibly reduced to 75% of its calculated value to suppress power supply ripple interference induced by transient large current injection. This procedure ensures the hardware operation safety of the drive link while ensuring the backlight response speed.

[0044] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A display screen backlight collaborative scheduling system driven by a chip controller IC, characterized in that, include: The feature pre-analysis module is used to extract the partition brightness features of the frame to be displayed, calculate the brightness difference between the current frame and the frame to be displayed, and determine the liquid crystal response delay parameters of the display screen based on the pixel response lookup table. The driving waveform mapping unit is connected to the feature pre-analysis module. It is used to receive the liquid crystal response delay parameters, divide the pre-compensation phase into the initial overdrive period and the steady-state maintenance period, and determine the current gain correction parameters corresponding to the initial overdrive period based on the brightness difference. The scheduling control module, connected to the drive waveform mapping unit, is used to embed current gain correction parameters, pre-compensation phase, and partition brightness characteristics of the frame to be displayed into the communication message sent during the vertical blanking period. The backlight driver chip, connected to the scheduling control module, is used to drive the light-emitting diode array with a driving current increased by the current gain correction parameter at the start time determined by the pre-compensated phase before receiving the frame synchronization signal, so that the energy accumulation rate of the backlight light field in the start stage of a single frame matches the transmittance growth curve of the liquid crystal pixels in the display screen. Among them, the pre-compensated phase Satisfying the relation ,in Pre-compensated phase, unit: , The time taken for logical operations, in units of , The physical response step size for the LED to reach the target stable brightness value, in units of , To account for bus transmission delay, the drive waveform mapping unit follows the following linear compensation rule when determining the current gain correction parameters: ,in, For current gain correction parameters, This is the difference in brightness. For pre-compensation phase, This is a preset proportional adjustment factor.

2. The display screen backlight collaborative scheduling system driven by a chip controller IC according to claim 1, characterized in that, It includes a backlight response feedback compensation unit; the backlight response feedback compensation unit is used to send a detection excitation to the backlight driver chip during the vertical blanking period and collect the current sampling signal fed back by the light-emitting diode array; The backlight response feedback compensation unit is also used to invert the physical response step size of the LED array based on the slope of the current sampling signal, and to iteratively update the pre-compensated phase output by the drive waveform mapping unit accordingly.

3. The display screen backlight collaborative scheduling system driven by a chip controller IC according to claim 1, characterized in that, When extracting the brightness features of the partitions, the feature pre-analysis module is also used to perform spatial domain weighted filtering on the frame to be displayed in order to identify the brightness gradient of adjacent partitions in the frame to be displayed, and to correct the liquid crystal response delay parameters based on the brightness gradient.

4. The display screen backlight collaborative scheduling system driven by a chip controller IC according to claim 1, characterized in that, When dividing the initial overdrive period, the driving waveform mapping unit is also used to dynamically adjust the duration ratio of the initial overdrive period in the pre-compensation phase according to the liquid crystal response delay parameter, and the duration ratio increases with the increase of the deflection viscosity coefficient of the liquid crystal molecules.

5. A display screen backlight collaborative scheduling system driven by a chip controller IC according to claim 1, characterized in that, The scheduling control module has a checksum field in the communication message. The checksum field is used by the backlight driver chip to verify the integrity of the current gain correction parameters and the pre-compensation phase. If the verification fails, the backlight driver chip maintains the driving parameters of the previous frame.

6. A display screen backlight collaborative scheduling system driven by a chip controller IC according to claim 1, characterized in that, The backlight driver chip includes a constant current drive circuit and a pulse shaping buffer; The constant current drive circuit outputs a drive current pulse to the pulse shaping buffer; The pulse shaping buffer is used to adjust the rising edge of the drive current pulse during the pre-compensation phase so that the turn-on curve generated by the backlight field fits the transmittance growth curve of the liquid crystal pixel.

7. A display screen backlight collaborative scheduling system driven by a chip controller IC according to claim 2, characterized in that, The backlight response feedback compensation unit sets the emission frequency of the detection excitation to an integer multiple of the frame synchronization signal frequency, and the luminous intensity triggered by the detection excitation is less than 0.01 cd / m².

8. A display screen backlight collaborative scheduling system driven by a chip controller IC according to claim 1, characterized in that, The scheduling control module includes an asynchronous communication interface; the asynchronous communication interface is used to complete the transmission of communication messages during time periods outside of the display of valid lines, and to trigger the backlight driver chip to update the current gain correction parameters in the register using the vertical synchronization signal.

9. A display screen backlight collaborative scheduling system driven by a chip controller IC according to claim 1, characterized in that, It also includes an energy consumption safety monitoring module; the energy consumption safety monitoring module is connected to the scheduling control module and is used to monitor the instantaneous current value of the LED array during the initial overdrive period, and when the instantaneous current value exceeds the preset safety threshold, it feeds back a current limiting signal to the scheduling control module to forcibly reduce the value of the current gain correction parameter.

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