Display panel, method for preparing display panel and display device

Abstract

The invention relates to a display panel, a method for preparing the display panel and a display device. The display panel comprises a substrate, a first insulating layer, a plurality of first electrodes, a second insulating layer and a protective layer, wherein the first insulating layer is arranged on one side of the substrate and comprises a plurality of via holes, and each via hole comprises a side wall; the first electrode is arranged on the side, away from the substrate, of the first insulating layer, and part of the first electrode extends to the side wall of the corresponding via hole; the second insulating layers are arranged on the sides, deviating from the substrate, of the first insulating layers and the first electrodes, and a plurality of first openings are formed in a surrounding mode; the protective layers are arranged on the sides, deviating from the substrate, of the second insulating layers; and the orthographic projection of the protective layer on the side wall is at least partially overlapped with the orthographic projections of the plurality of first electrodes on the side wall. According to the display panel, the protective layer covers the side wall of the via hole, so that the problem of dark spot failure on the display panel caused by the via hole can be solved, and the display effect of the display panel can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a method for manufacturing a display panel, and a display device. Background Technology

[0002] In order to ensure transmittance, in addition to the conventional VSS pixel opening, a VSS hole is also added at the ambient light hole on the OLED (Organic Light Emitting Diode) display substrate to ensure transmittance; and an anode via is present in the VSS hole.

[0003] However, the display performance of current OLED display panels needs improvement. Summary of the Invention

[0004] Therefore, it is necessary to provide a display panel, a method for manufacturing the display panel, and a display device that can improve the display effect in order to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides a display panel, including:

[0006] substrate;

[0007] A first insulating layer is disposed on one side of the substrate; the first insulating layer includes a plurality of vias, each via including a sidewall;

[0008] A plurality of first electrodes are disposed on the side of the first insulating layer opposite to the substrate; portions of the first electrodes extend to the sidewall of the corresponding via.

[0009] A second insulating layer is disposed on the side of the first insulating layer and the first electrode facing away from the substrate; the second insulating layer encloses and forms a plurality of first openings, the orthographic projection of the first opening on the substrate being located within the orthographic projection of the corresponding first electrode on the substrate;

[0010] A protective layer is disposed on the side of the second insulating layer opposite to the substrate; the orthographic projection of the protective layer on the sidewall at least partially overlaps with the orthographic projection of the plurality of first electrodes on the sidewall.

[0011] The display panel provided in this application embodiment covers the sidewall of the via with a protective layer to protect the first electrode extending to the sidewall of the via. This reduces the over-etching loss of the second insulating layer in the subsequent VEE process, thereby solving the problem of dark spot failure on the display panel caused by the via and improving the display effect of the display panel.

[0012] In one embodiment, the orthographic projection of the protective layer on the sidewall covers the orthographic projection of the plurality of first electrodes on the sidewall;

[0013] Optionally, the orthographic projection of the sidewall onto the substrate lies within the orthographic projection of the protective layer onto the substrate;

[0014] Optionally, the orthographic projection of the sidewall on the substrate is located within the orthographic projection of the corresponding first electrode on the substrate;

[0015] Optionally, the protective layer comprises an organic material.

[0016] In one embodiment, the distance between the surface of the protective layer located in the via and the substrate on the side opposite to the substrate is not less than the distance between the surface of the first electrode on the first insulating layer and the substrate on the side opposite to the substrate;

[0017] Optionally, the orthographic projection of the sidewall onto the substrate lies within the orthographic projection of the protective layer onto the substrate;

[0018] Optionally, the distance between the surface of the protective layer located in the via and the substrate on the side away from the substrate is less than the distance between the surface of the first insulating layer and / or the second insulating layer located on the first electrode on the side away from the substrate and the substrate, and is greater than the distance between the surface of the first electrode located on the first insulating layer and the substrate on the side away from the substrate.

[0019] Optionally, the distance between the surface of the protective layer located in the via and the substrate on the side opposite to the substrate is equal to the distance between the surface of the first insulating layer and / or the surface of the second insulating layer located on the first electrode and the substrate on the side opposite to the substrate.

[0020] Optionally, the distance between the surface of the protective layer located in the via and the substrate on the side opposite to the substrate is equal to the distance between the surface of the first electrode located on the first insulating layer and the substrate on the side opposite to the substrate;

[0021] Optionally, the distance between the surface of the protective layer located in the via and the substrate on the side opposite to the substrate is greater than the distance between the surface of the first insulating layer and / or the surface of the second insulating layer located on the first electrode and the substrate on the side opposite to the substrate.

[0022] Optionally, the distance between the surface of the protective layer located in the via and the substrate on the side opposite to the substrate is less than the distance between the surface of the first electrode located on the first insulating layer and the substrate on the side opposite to the substrate.

[0023] In one embodiment, the display panel further includes a partition structure disposed on the side of the second insulating layer opposite to the substrate;

[0024] The partition structure encloses and forms multiple light-transmitting openings and multiple isolation openings, and the isolation openings are connected to the corresponding first openings; at least a portion of the multiple vias have their orthogonal projections on the substrate overlapping with the orthogonal projections of the multiple light-transmitting openings on the substrate.

[0025] Optionally, the display panel includes a first display area and a second display area adjacent to the first display area, wherein the light transmittance of the first display area is greater than that of the second display area, the plurality of light-transmitting openings are disposed in the first display area, and the plurality of isolation openings are disposed in the first display area and the second display area;

[0026] Optionally, the protective layer includes a light-transmitting material;

[0027] Optionally, the orthographic projection of the plurality of light-transmitting openings on the substrate covers the orthographic projection of the plurality of vias on the substrate;

[0028] Optionally, the orthographic projection of the same light-transmitting opening on the substrate covers the orthographic projection of at least one of the vias on the substrate.

[0029] In one embodiment, the display panel further includes a plurality of light-emitting functional units and a plurality of second electrodes, wherein at least a portion of the light-emitting functional units is disposed within a corresponding isolation opening; and the second electrodes are disposed on the side of the corresponding light-emitting functional unit away from the substrate.

[0030] The second electrode is electrically connected to the isolation structure;

[0031] Optionally, the partition structure includes an isolator and a blocking portion stacked along a direction away from the substrate, wherein the outer contour of the orthographic projection of the blocking portion on the substrate is located outside the outer contour of the orthographic projection of the isolator on the substrate; the second electrode is electrically connected to the isolator.

[0032] Optionally, the insulator includes at least one metal layer;

[0033] Optionally, the separator includes a first metal layer and a second metal layer stacked along a direction away from the substrate, wherein the outer contour of the orthographic projection of the first metal layer on the substrate is located outside the outer contour of the orthographic projection of the second metal layer on the substrate.

[0034] In one embodiment, the distance between the surface of the protective layer located in the via and the substrate on the side opposite to the substrate is greater than the distance between the surface of the first insulating layer and / or the second insulating layer located on the first electrode and the substrate on the side opposite to the substrate, and the distance between the surface of the protective layer located in the via and the substrate on the side opposite to the substrate is less than the distance between the surface of the partition structure and the substrate on the side opposite to the substrate.

[0035] Alternatively, the distance between the surface of the protective layer located in the via and the substrate on the side away from the substrate is greater than the distance between the surface of the first insulating layer and / or the second insulating layer located on the first electrode and the substrate on the side away from the substrate, and the distance between the surface of the protective layer located in the via and the substrate on the side away from the substrate is not less than the distance between the surface of the partition structure and the substrate on the side away from the substrate.

[0036] Optionally, the distance between the surface of the protective layer located in the via and the substrate on the side away from the substrate is greater than the distance between the surface of the first insulating layer and / or the second insulating layer located on the first electrode and the substrate on the side away from the substrate, and the distance between the surface of the protective layer located in the via and the substrate on the side away from the substrate is equal to the distance between the surface of the partition structure and the substrate on the side away from the substrate.

[0037] Optionally, the outer contour of the protective layer projected onto the substrate is located within the projection range of the light-transmitting opening onto the substrate.

[0038] In one embodiment, the orthogonal projection of the protective layer onto the substrate covers the orthogonal projection of the light-transmitting opening onto the substrate;

[0039] Optionally, the outer contour of the protective layer projected onto the substrate is located outside the outer contour of the light-transmitting opening projected onto the substrate;

[0040] Optionally, the outer contour of the protective layer projected onto the substrate overlaps with the outer contour of the light-transmitting opening projected onto the substrate.

[0041] In one embodiment, the display panel further includes:

[0042] A pixel circuit layer is disposed on the side of the first insulating layer facing the substrate, and the pixel circuit layer includes a plurality of pixel driving units;

[0043] A conductive connection layer is disposed on the side of the first insulating layer facing the pixel circuit layer, and the conductive connection layer includes a plurality of conductive connection structures;

[0044] The pixel driving unit is electrically connected to the first electrode extending to the corresponding via through the corresponding conductive connection structure.

[0045] In one embodiment, the first insulating layer is a planarization layer; and / or, the second insulating layer is a pixel defining layer.

[0046] Secondly, embodiments of this application provide a display panel, including:

[0047] substrate;

[0048] A first insulating layer is disposed on one side of the substrate; the first insulating layer includes a plurality of vias, each via including a sidewall;

[0049] A plurality of first electrodes are disposed on the side of the first insulating layer opposite to the substrate; portions of the first electrodes extend into the sidewall of the corresponding via.

[0050] A second insulating layer is disposed on the side of the first insulating layer and the first electrode facing away from the substrate; the second insulating layer encloses and forms a plurality of first openings, the orthographic projection of the first opening on the substrate being located within the orthographic projection of the corresponding first electrode on the substrate;

[0051] A protective layer is disposed on the side of the second insulating layer opposite to the substrate; the orthographic projection of the protective layer on the sidewall at least partially overlaps with the orthographic projection of the plurality of first electrodes on the sidewall.

[0052] A partition structure is disposed on the side of the second insulating layer away from the substrate; the partition structure encloses and forms a plurality of light-transmitting openings and a plurality of isolation openings, the isolation openings communicating with the corresponding first openings; at least a portion of the plurality of vias have their orthogonal projections on the substrate overlapping with the orthogonal projections of the plurality of light-transmitting openings on the substrate.

[0053] The display panel provided in this application embodiment, by covering the sidewall of the via with a protective layer, helps to increase the thickness of the second insulating layer on the sidewall of the via, which can reduce the corrosion of the first electrode on the sidewall by the etchant in the subsequent VEE process, thereby improving the light transmittance of the light-transmitting opening on the display panel and thus improving the display effect of the display panel.

[0054] Thirdly, embodiments of this application provide a method for manufacturing a display panel, the method comprising:

[0055] Provide substrate;

[0056] A first insulating layer is formed on one side of the substrate; the first insulating layer includes a plurality of vias, each via including a sidewall;

[0057] A plurality of first electrodes are formed on the side of the first insulating layer opposite to the substrate; portions of the first electrodes extend to the sidewall of the corresponding via.

[0058] A second insulating layer is formed on the side of the first insulating layer and the plurality of first electrodes facing away from the substrate; the second insulating layer encloses a plurality of first openings, and the orthographic projection of the first opening on the substrate is located within the orthographic projection of the corresponding first electrode on the substrate;

[0059] A protective layer is formed on the side of the second insulating layer opposite to the substrate; the orthographic projection of the protective layer on the sidewall at least partially overlaps with the orthographic projection of the plurality of first electrodes on the sidewall.

[0060] In one embodiment, the method further includes:

[0061] A partition structure is formed on the side of the second insulating layer opposite to the substrate; the partition structure encloses and forms a plurality of light-transmitting openings and a plurality of isolation openings, the isolation openings communicating with the corresponding first openings; at least a portion of the plurality of vias have their orthogonal projections on the substrate overlapping with the orthogonal projections of the plurality of light-transmitting openings on the substrate.

[0062] In one embodiment, the method further includes:

[0063] A pixel circuit layer is formed on the side of the first insulating layer facing the substrate, and the pixel circuit layer includes a plurality of pixel driving units;

[0064] A conductive connection layer is formed on the side of the first insulating layer facing the pixel circuit layer, and the conductive connection layer includes a plurality of conductive connection structures; wherein, the pixel driving unit is electrically connected to the first electrode extending to the corresponding via through the corresponding conductive connection structure.

[0065] The display panel manufacturing method provided in this application increases the thickness of the second insulating layer on the sidewall of the via by covering the protective layer on the sidewall of the via. This can avoid damage to the first electrode covered by the second insulating layer by the etchant in the subsequent VEE process. On the one hand, it can solve the problem of dark spot failure on the display panel caused by damage to the first electrode. On the other hand, it can also improve the light transmittance of the light port, thereby improving the display effect of the display panel.

[0066] Fourthly, embodiments of this application provide a display device including the display panel described in the first aspect.

[0067] The display device provided in this application includes a display panel. The sidewalls of the vias in the display panel are covered with a protective layer, which can increase the thickness of the second insulating layer on the sidewalls of the vias. This can prevent the etchant in the subsequent VEE process from damaging the first electrode covered by the second insulating layer. On the one hand, it can solve the problem of dark spot failure on the display panel caused by damage to the first electrode. On the other hand, it can also improve the light transmittance of the light port, thereby improving the display effect of the display panel. Attached Figure Description

[0068] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0069] Figure 1 One of the top views of the display panel provided in the embodiments of this application;

[0070] Figure 2 A second top view of the display panel provided in an embodiment of this application;

[0071] Figure 3 One of the partial cross-sectional views of the display panel provided in the embodiments of this application;

[0072] Figure 4 A second partial cross-sectional view of the display panel provided in an embodiment of this application;

[0073] Figure 5 A third partial cross-sectional view of the display panel provided in an embodiment of this application;

[0074] Figure 6 Fourth partial cross-sectional view of the display panel provided in the embodiments of this application;

[0075] Figure 7 Fifth partial cross-sectional view of the display panel provided in the embodiments of this application;

[0076] Figure 8 A partial cross-sectional view of the display panel provided in the embodiments of this application;

[0077] Figure 9 A seventh partial cross-sectional view of the display panel provided in an embodiment of this application;

[0078] Figure 10 Eighth partial cross-sectional view of a display panel provided in an embodiment of this application;

[0079] Figure 11Ninth partial cross-sectional view of the display panel provided in the embodiments of this application;

[0080] Figure 12 Tenth partial cross-sectional view of the display panel provided in the embodiments of this application;

[0081] Figure 13 Eleventh partial cross-sectional view of the display panel provided in the embodiments of this application;

[0082] Figure 14 XII. A partial cross-sectional view of the display panel provided in the embodiments of this application;

[0083] Figure 15 Thirteenth partial cross-sectional view of the display panel provided in the embodiments of this application;

[0084] Figure 16 Fourteenth partial cross-sectional view of a display panel provided in an embodiment of this application;

[0085] Figure 17 Fifteenth partial cross-sectional view of a display panel provided in an embodiment of this application;

[0086] Figure 18 Sixteenth partial cross-sectional view of the display panel provided in the embodiments of this application;

[0087] Figure 19 Seventeenth partial cross-sectional view of the display panel provided in the embodiments of this application;

[0088] Figure 20 Eighteenth partial cross-sectional view of the display panel provided in the embodiments of this application;

[0089] Figure 21 Nineteenth partial cross-sectional view of the display panel provided in the embodiments of this application;

[0090] Figure 22 Twentieth partial cross-sectional view of a display panel provided in an embodiment of this application;

[0091] Figure 23 Twenty-first partial cross-sectional view of the display panel provided in an embodiment of this application;

[0092] Figure 24 Twenty-second partial cross-sectional view of a display panel provided in an embodiment of this application;

[0093] Figure 25 This is one of the flowcharts illustrating a method for manufacturing a display panel according to an embodiment of this application.

[0094] Figure 26 A second schematic flowchart illustrating the method for manufacturing a display panel according to an embodiment of this application;

[0095] Figure 27 The third schematic flowchart illustrates the method for manufacturing a display panel according to an embodiment of this application.

[0096] Explanation of reference numerals in the attached figures:

[0097] 1. Display panel; 10. First display area; 20. Second display area; 10a. Isolation opening; 10b. Light-transmitting opening; 10b1. Via; 11. Substrate; 12. First insulating layer; 13. First electrode; 14. Second insulating layer; 14a. First opening; 15. Protective layer; 16. Conductive connection structure; 17. Isolation structure; 18. Pixel circuit layer; 131. First extension; 132. Second extension; 133. Third extension; 17a. Isolator; 17b. Blocking portion; 17a1. First metal layer; 17a2. Second metal layer; h0. Protective layer backing away from substrate located in the via. The distance between the surface of one side of the plate and the substrate; h1, the distance between the surface of the first insulating layer and / or the second insulating layer on the first electrode facing away from the substrate and the substrate; h2, the distance between the surface of the first electrode on the first insulating layer facing away from the substrate and the substrate; h3, the distance between the surface of the partition structure 17 facing away from the substrate 11 and the substrate; w0, the distance between the surfaces of adjacent partition structures facing away from the substrate; w1, the width of the surface of the protective layer facing away from the substrate; w2, the distance between the outer wall sides of adjacent partition structures; 14a, pixel limiting layer; 14a1, first pixel limiting portion. Detailed Implementation

[0098] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0099] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, this does not indicate any order, quantity, or importance, but is merely used to distinguish different components. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Words such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects.

[0100] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0101] Organic Light Emitting Diode (OLED) display technology is considered the most promising next-generation flat panel display technology. Compared to liquid crystal displays, OLED technology offers advantages such as lower energy consumption, lower cost, self-emissiveness, wide viewing angle, and faster response time. However, see also... Figure 1 and Figure 2 To ensure transmittance, in addition to the conventional VSS isolation opening 10a, an ambient light transmission opening 10b is added to the first display area 10 of the OLED display panel 1 to ensure transmittance. The second display area 20 includes the conventional VSS isolation opening. An anode via 10b1 exists within the light transmission opening 10b. The presence of the anode via 10b1 causes a slope at the point where the anode connects to the isolation opening 10a on the display panel 1 (see...). Figure 3 When the light-transmitting opening 10b is fully opened, during the subsequent B / G / R VEE CVD1 etching, the EL and cathode at the ramp are too thin and lose their etching blocking effect, resulting in the pixel definition layer (PDL) at the ramp being over-etched and missing. The subsequent VEE wet process solution etches the anode and produces anode voids, which further leads to the failure of pixel EL and the generation of pixel dark spots, resulting in poor display effect of display panel 1.

[0102] In view of at least one of the above problems, embodiments of this application provide a display panel, a method for manufacturing the display panel, and a display device, which can reduce the risk of over-etching of the pixel definition layer at the ramp, thereby reducing the risk of generating anode voids and improving the display effect of the display panel.

[0103] Firstly, referring to Figure 1 , Figure 2 , Figure 3As shown in the schematic diagram in Figure 4, this application embodiment provides a display panel 1, which can be an Organic Light-Emitting Diode (OLED) display panel, a Micro Organic Light-Emitting Diode (MicroOLED) display panel, a Light Emitting Diode (LED) display panel, a Quantum Dot Light Emitting Diode (QLED) display panel, a Mini Light Emitting Diode (MiniLED) display panel, a Micro Light Emitting Diode (Micro LED) display panel, or a Liquid Crystal Display (LCD) display panel, etc. This application embodiment uses an OLED display panel as an example for illustration.

[0104] The first display area 10 on the display panel 1 provided in the embodiments of this application will be described below.

[0105] See Figure 1 This application provides a display panel 1, which may include a first display area 10, see [link to relevant documentation]. Figure 2 The first display area 10 on the display panel 1 includes a light-transmitting display area with a light-transmitting opening 10b. An under-display functional device can be disposed on one side of the backlight surface of the display panel 1 in the light-transmitting display area. This under-display functional device can include any one or more of a camera, fingerprint reader, iris reader, and proximity sensor. Disposing of the under-display functional device on the backlight surface of the display panel 1 in the light-transmitting display area ensures that the display panel 1 can display images normally, thus maintaining a high screen-to-body ratio. Furthermore, the light-transmitting display area has good light transmittance, allowing light to reach the under-display functional device.

[0106] For example, such as Figure 2 As shown, the first display area 10 may also include a pixel display area with an isolation opening 10a. The isolation opening 10a and the light-transmitting opening 10b are arranged adjacent to each other. For example, the light transmittance of the display panel 1 in the pixel display area may be less than the light transmittance of the display panel 1 in the light-transmitting display area.

[0107] It should be noted that the display panel 1 may include only a light-transmitting display area, without a pixel display area. This embodiment of the application will be described using an example where both a light-transmitting display area and a pixel display area are provided.

[0108] See Figure 2 and Figure 3 A portion of the light-transmitting opening 10b includes one or more vias 10b1, each of which has a ramp at the connection point with the isolation opening 10a. At least a portion of the orthographic projection of the vias 10b1 onto the substrate 11 overlaps with the orthographic projection of the light-transmitting opening 10b onto the substrate 11, thus eliminating the need for at least a portion of the light-transmitting opening 10b to be staggered from the vias 10b1. This facilitates expanding the coverage area of ​​the light-transmitting opening 10b, increasing light transmittance, and thereby improving the light transmittance of the display panel 1.

[0109] See Figure 4 The partial cross-sectional view of the first display area 10 shown in this application embodiment provides a display panel 1, which includes a substrate 11; a first insulating layer 12 disposed on one side of the substrate 11; the first insulating layer 12 includes a plurality of vias 10b1, and each via 10b1 includes a sidewall; a plurality of first electrodes 13 disposed on the side of the first insulating layer 12 away from the substrate 11; a portion of the first electrode 13 extends to the sidewall of the corresponding via 10b1; a second insulating layer 14 disposed on the side of the first insulating layer 12 and the plurality of first electrodes 13 away from the substrate 11; the second insulating layer 14 surrounds to form a plurality of first openings 14a, the orthographic projection of the first opening 14a on the substrate 11 being located within the orthographic projection of the corresponding first electrode 13 on the substrate 11; a protective layer 15 disposed on the side of the second insulating layer 15 away from the substrate 11; the orthographic projection of the protective layer 15 on the sidewall at least partially overlaps with the orthographic projection of the plurality of first electrodes 13 on the sidewall.

[0110] In some embodiments, substrate 11 may provide support for subsequent layers of film.

[0111] In some embodiments, the first insulating layer 12 may be a planarization layer to provide good planar support for the subsequent formation of the first electrode 13 and the first insulating layer 14.

[0112] In some embodiments, the first electrode 13 and the via 10b1 are respectively provided, and a portion of the first electrode 13 extends into the corresponding via 10b1.

[0113] For example, see Figure 4 The first electrode 13 includes a first extension 131, a second extension 132, and a third extension 133. The first extension 131 covers the sidewall of the via 10b1. The second extension 132 is located at the end of the via 10b1 facing the substrate 11. The third extension 133 is located on the side of the first insulating layer 12 away from the substrate 11. The second extension 132 and the third extension 133 are connected through the first extension 131. The thickness of the first extension 131 is less than the thickness of at least one of the second extension 132 and the third extension 133.

[0114] Understandably, due to the step difference in the sidewall of via 10b1, the thickness of the first extension 131 covering the sidewall of via 10b1 is thinner than that of the second extension 132 and the third extension 133. The thinner the first electrode 131, the more easily it is damaged and forms a void; that is, the first extension 131 is more easily damaged and forms a void.

[0115] In some embodiments, the display panel 1 further includes a protective layer 15 located on the side of the second insulating layer 14 facing away from the substrate 11. The orthographic projection of the protective layer 15 on the sidewall at least partially overlaps with the orthographic projections of the plurality of first electrodes 13 on the sidewall. Based on this, the protective layer 15 can cover a portion of the sidewall of the via 10b1, see [reference needed]. Figure 5 , Figure 6 , Figure 7 , Figure 8 The protective layer 15 can also cover the entire sidewall of the via 10b1, see [link / reference]. Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 This situation can be categorized as follows: the protective layer 15 can completely fill the via 10b1, see [reference]. Figure 4 , Figure 11 ,or Figure 14 ,or Figure 15 ,or Figure 16 ,or Figure 17 ,or Figure 18 ,or Figure 19 The protective layer 15 can also partially fill the via 10b1, see [reference]. Figure 9 Figure 10, or Figure 12 ,or Figure 13 ;

[0116] In some embodiments, the protective layer 15 is made of organic materials; optionally, the protective layer 15 is made of light-transmitting materials; optionally, the protective layer 15 can be a material coated using nanoscale or microscale material coating (Vacuum Printed LiquidNano, VPLN) technology. For example, the filler material of VPLN can be replaced by organic materials such as OC and MLA that do not affect transmittance.

[0117] The display panel provided in this application embodiment covers the sidewall of the via with a protective layer to protect the first electrode extending to the sidewall of the via. This reduces the over-etching loss of the second insulating layer in the subsequent VEE process, thereby solving the problem of dark spot failure on the display panel caused by the via and improving the display effect of the display panel.

[0118] In some embodiments, the orthographic projection of the protective layer 15 on the sidewall covers the orthographic projection of the plurality of first electrodes 13 on the sidewall; that is, the orthographic projection of the plurality of first electrodes 13 on the sidewall lies within the orthographic projection of the protective layer 15 on the sidewall; based on this, when the plurality of first electrodes 13 extend to a portion of the sidewall of the via 10b1 on the first insulating layer 12, see... Figure 9 As shown, the protective layer 15 only needs to cover the sidewall where the first electrode 13 is located. This protects the first electrode at the sidewall and avoids the problem of over-etching due to the thin sidewall.

[0119] Optionally, the orthographic projection of the sidewall onto the substrate 11 lies within the orthographic projection of the protective layer 15 onto the substrate 11; in this case, the protective layer 15 not only covers the second insulating layer 14 on the sidewall, but also covers the second insulating layer 14 connected to the sidewall, as can be seen in [reference needed]. Figure 4 This not only provides complete protection for the first electrode at the sidewall, but also for the first electrode at the sidewall connection point.

[0120] Optionally, the orthographic projection of the sidewall onto the substrate 11 lies within the orthographic projection of the corresponding first electrode 13 onto the substrate 11. In this case, the first electrode 13 passes through the via 10b1 and extends to the portion connected to the sidewall of the via 10b1. Therefore, the protective layer 15 may only cover the second insulating layer 14 on the sidewall. Alternatively, the protective layer 15 may also cover both the second insulating layer 14 on the sidewall and the second insulating layer 14 connected to the sidewall, as described in [reference needed]. Figure 4 This not only provides complete protection for the first electrode at the sidewall, but also for the first electrode at the sidewall connection point.

[0121] Optionally, the protective layer 15 may include organic materials.

[0122] Optionally, when the protective layer 15 fills the via 10b1, the shape of the surface of the protective layer 15 located in the via 10b1 facing away from the substrate 11 can be regular or irregular, and is not limited thereto. For example, Figure 4 , Figures 10-23 It is regular; the surface of protective layer 15 is all horizontal. Figures 5-6 The surface of the protective layer 13 is concave or irregular.

[0123] In some embodiments, the distance between the surface of the protective layer 15 located within the via 10b1 facing away from the substrate 11 and the substrate 11 is not less than the distance between the surface of the first electrode 13 located on the first insulating layer 12 facing away from the substrate 11 and the substrate. Based on this, the orthographic projection of the sidewall onto the substrate 11 lies within the orthographic projection of the protective layer 15 onto the substrate 11, meaning the protective layer 15 can completely cover the sidewall of the via 10b1. Several embodiments of the protective layer 15 filling are described below, including several embodiments where the protective layer 15 partially fills the via 10b1:

[0124] For example, see Figure 10 The distance h0 between the surface of the protective layer 15 located within the via 10b1 facing away from the substrate 11 and the substrate 11 is less than the distance h1 between the surface of the second insulating layer 14 located on the first insulating layer 12 and / or the first electrode 13 facing away from the substrate 11 and the substrate 11, and greater than the distance h2 between the surface of the first electrode 13 located on the first insulating layer 12 facing away from the substrate 11 and the substrate 11. This allows the protective layer 15 to fill the via 10b1, completely covering the first electrode 13 on the sidewall of the via 10b1 and a portion of the second insulating layer 14 on the sidewall of the via 10b1. This arrangement protects a portion of the second insulating layer 14 on the sidewall of the via 10b1, and since this portion of the second insulating layer 14 completely covers the first electrode 13 on the sidewall of the via 10b1, the protective layer 15 also protects the first electrode 13 on the sidewall of the via 10b1.

[0125] For example, see Figure 11 The distance h0 between the surface of the protective layer 15 located in the via 10b1 facing away from the substrate 11 and the substrate 11 is equal to the distance h1 between the surface of the first insulating layer 12 and / or the surface of the second insulating layer 14 located on the first electrode 13 facing away from the substrate 11 and the substrate 11. That is, the surface of the protective layer 15 facing away from the substrate 11 is flush with the surface of the second insulating layer 14 facing away from the substrate 11, so as to fill the protective layer 15 in the via 10b1 and make the protective layer 15 completely cover the first electrode 13 on the sidewall of the via 10b1 and cover all the second insulating layer 14 on the sidewall of the via 10b1. This configuration can protect the entire second insulating layer 14 on the sidewall of via 10b1. The entire second insulating layer 14 can not only completely cover the first electrode 13 on the sidewall of via 10b1, but also cover the extension portion of the first electrode 13 on the sidewall of via 10b1. Therefore, the protective layer 15 provides better protection for the first electrode 13 on the sidewall of via 10b1.

[0126] For example, see Figure 12The distance h0 between the surface of the protective layer 15 facing away from the substrate 11 within the via 10b1 and the substrate 11 is equal to the distance h2 between the surface of the first electrode 13 facing away from the substrate 11 on the first insulating layer 12 and the substrate 11. That is, the surface of the protective layer 15 facing away from the substrate 11 is flush with the surface of the first electrode 13 facing away from the substrate 11, thus filling the via 10b1 with the protective layer 15. The protective layer 15 completely covers the first electrode 13 on the sidewall of the via 10b1 and a portion of the second insulating layer 14 on the sidewall of the via 10b1. This arrangement protects the portion of the second insulating layer 14 on the sidewall of the via 10b1, and since this portion of the second insulating layer 14 completely covers the first electrode 13 on the sidewall of the via 10b1, the protective layer 15 also protects the first electrode 13 on the sidewall of the via 10b1.

[0127] For example, see Figure 13 The distance h0 between the surface of the protective layer 15 located in the via 10b1 facing away from the substrate 11 and the substrate 11 is less than the distance h2 between the surface of the first electrode 13 located on the first insulating layer 12 facing away from the substrate 11 and the substrate 11, so that the protective layer 15 is filled in the via 10b1, and the thickness of the protective layer 15 facing the back plate 11 is the same as the thickness of the protective layer 15 facing the first electrode 13. At this time, the protective layer 15 can completely cover the first electrode 13 on the sidewall of the via 10b1, and cover all the second insulating layer 14 on the sidewall of the via 10b1. This configuration can protect the entire second insulating layer 14 on the sidewall of via 10b1. The entire second insulating layer 14 can not only completely cover the first electrode 13 on the sidewall of via 10b1, but also cover the extension portion of the first electrode 13 on the sidewall of via 10b1, as well as the first electrode 13 extending out of via 10b1. Therefore, the protective layer 15 provides better protection for the first electrode 13 on the sidewall of via 10b1, and also protects the first electrode 13 extending out of via 10b1.

[0128] In the above embodiments, the protective layer 15 can completely cover the first electrode 13 on the sidewall of the via 10b1, and cover part or all of the second insulating layer 14 on the sidewall of the via 10b1. This preserves the second insulating material 14 on the sidewall of the via 10b1 to block the etching reagent, preventing the second insulating layer 14 at the sidewall from being over-etched and lost due to subsequent B / G / R VEE CVD1 etching. This helps increase the thickness of the second insulating layer 14, preventing voids in the first electrode 13 covered by the second insulating layer 14 that could lead to pixel EL failure, resulting in pixel dark spots and affecting the display effect of the display panel. Moreover, the surface of the protective layer 15 facing away from the substrate 11 is flush with the surface of the second insulating layer 14 facing away from the substrate 11, which can reduce the manufacturing difficulty of the display panel 1.

[0129] In some embodiments, the height h0 of the surface of the protective layer 15 facing away from the substrate 11 is greater than the height h1 of the surface of the second insulating layer 14 facing away from the substrate 11, i.e., the case where the protective layer 15 completely fills the via 10b1. See [link to relevant documentation]. Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 The schematic diagram shown below illustrates several embodiments in which the protective layer 15 completely fills the via 10b1:

[0130] For example, see Figure 14The distance h0 between the surface of the protective layer 15 located in the via 10b1 facing away from the substrate 11 and the substrate 11 is greater than the distance h1 between the surface of the first insulating layer 12 and / or the second insulating layer 14 located on the first electrode 13 facing away from the substrate 11 and the substrate 11, and the distance h0 between the surface of the protective layer 15 located in the via 10b1 facing away from the substrate 11 and the substrate 11 is less than the distance h3 between the surface of the partition structure 17 facing away from the substrate 11 and the substrate 11; correspondingly, the orthographic projection of the protective layer 15 on the substrate 11 covers the orthographic projection of the light-transmitting opening 10b on the substrate 11, that is, in the area between adjacent partition structures 17, the width w1 of the surface of the protective layer 15 facing away from the substrate 11 is not less than the distance w0 between the surfaces of adjacent partition structures 17 facing away from the substrate 11. Preferably, the orthographic projection of the protective layer 15 onto the substrate 11 is located outside the orthographic projection of the light-transmitting opening 10b onto the substrate 11. That is, in the region between adjacent partition structures 17, the width w1 of the surface of the protective layer 15 facing away from the substrate 11 is greater than the distance w0 between the surfaces of adjacent partition structures 17 facing away from the substrate 11. Preferably, the orthographic projection of the protective layer 15 onto the substrate 11 overlaps with the orthographic projection of the light-transmitting opening 10b onto the substrate 11. That is, in the region between adjacent partition structures 17, the width w1 of the surface of the protective layer 15 facing away from the substrate 11 is equal to the distance w0 between the surfaces of adjacent partition structures 17 facing away from the substrate 11. It should be noted that w0 refers to the distance between the inner wall sides of adjacent partition structures 17.

[0131] For example, see Figure 15 The distance h0 between the surface of the protective layer 15 located within the via 10b1 facing away from the substrate 11 and the substrate 11 is greater than the distance h1 between the surface of the first insulating layer 12 and / or the second insulating layer 14 located on the first electrode 13 facing away from the substrate 11 and the substrate 11, and the distance h0 between the surface of the protective layer 15 located within the via 10b1 facing away from the substrate 11 and the substrate 11 is less than the distance h3 between the surface of the partition structure 17 facing away from the substrate 11 and the substrate 11. Correspondingly, the outer contour of the orthographic projection of the protective layer 15 on the substrate 11 is within the orthographic projection range of the light-transmitting opening 10b on the substrate 11, that is, in the region between adjacent partition structures 17, the width w1 of the surface of the protective layer 15 facing away from the substrate 11 is less than the distance w0 between the surfaces of adjacent partition structures 17 facing away from the substrate 11. It should be noted that w0 refers to the distance between the inner wall sides of adjacent partition structures 17.

[0132] For example, see Figure 16The distance h0 between the surface of the protective layer 15 located in the via 10b1 facing away from the substrate 11 and the substrate 11 is greater than the distance h1 between the surface of the first insulating layer 12 and / or the second insulating layer 14 located on the first electrode 13 facing away from the substrate 11 and the substrate 11. The distance h0 between the surface of the protective layer 15 located in the via 10b1 facing away from the substrate 11 and the substrate 11 is equal to the distance h3 between the surface of the partition structure 17 facing away from the substrate 11 and the substrate 11. That is, the surface of the protective layer 15 facing away from the substrate 11 is flush with the surface of the partition structure 17 facing away from the substrate 11. Correspondingly, the orthographic projection of the protective layer 15 on the substrate 11 covers the orthographic projection of the light-transmitting opening 10b on the substrate 11. That is, in the area between adjacent partition structures 17, the width w1 of the surface of the protective layer 15 facing away from the substrate 11 is not less than the distance w0 between the surfaces of adjacent partition structures 17 facing away from the substrate 11. It should be noted that w0 refers to the distance between the inner wall sides of adjacent partition structures 17.

[0133] Preferably, the outer contour of the orthographic projection of the protective layer 15 on the substrate 11 is located outside the outer contour of the orthographic projection of the light-transmitting opening 10b on the substrate 11. That is, in the region between adjacent partition structures 17, the width w1 of the surface of the protective layer 15 facing away from the substrate 11 is greater than the distance w0 between the surfaces of adjacent partition structures 17 facing away from the substrate 11. The width w1 of the surface of the protective layer 15 facing away from the substrate 11 refers to the maximum width of the protective layer 15 facing away from the substrate 11.

[0134] Preferably, the outer contour of the protective layer 15 projected onto the substrate 11 overlaps with the outer contour of the light-transmitting opening 10b projected onto the substrate 11. That is, in the region between adjacent partition structures 17, the width w1 of the surface of the protective layer 15 facing away from the substrate 11 is equal to the distance w0 between the surfaces of adjacent partition structures 17 facing away from the substrate 11. It should be noted that w0 refers to the distance between the inner wall sides of adjacent partition structures 17.

[0135] For example, see Figure 17The distance h0 between the surface of the protective layer 15 located within the via 10b1 facing away from the substrate 11 and the substrate 11 is greater than the distance h1 between the surface of the first insulating layer 12 and / or the second insulating layer 14 located on the first electrode 13 facing away from the substrate 11 and the substrate 11. Furthermore, the distance between the surface of the protective layer 15 located within the via 10b1 facing away from the substrate 11 and the substrate 11 is equal to the distance h3 between the surface of the partition structure 17 facing away from the substrate 11 and the substrate 11. The surface of the protective layer 15 facing away from the substrate 11 is flush with the surface of the partition structure 17 facing away from the substrate 11. Correspondingly, the outer contour of the orthographic projection of the protective layer 15 onto the substrate 11 is within the orthographic projection range of the light-transmitting opening 10b onto the substrate 11. That is, within the region between adjacent partition structures 17, the width w1 of the surface of the protective layer 15 facing away from the substrate 11 is less than the distance w0 between the surfaces of adjacent partition structures 17 facing away from the substrate 11. It should be noted that w0 refers to the distance between the inner wall sides of adjacent partition structures 17.

[0136] For example, see Figure 18 The distance h0 between the surface of the protective layer 15 located in the via 10b1 facing away from the substrate 11 and the substrate 11 is greater than the distance h1 between the surface of the first insulating layer 12 and / or the second insulating layer 14 located on the first electrode 13 facing away from the substrate 11 and the substrate 11, and the distance h0 between the surface of the protective layer 15 located in the via 10b1 facing away from the substrate 11 and the substrate 11 is greater than the distance h3 between the surface of the partition structure 17 facing away from the substrate 11 and the substrate 11; correspondingly, the orthographic projection of the protective layer 15 on the substrate 11 covers the orthographic projection of the light-transmitting opening 10b on the substrate 11, that is, in the area between adjacent partition structures 17, the width w1 of the surface of the protective layer 15 facing away from the substrate 11 is not less than the distance w0 between the surfaces of adjacent partition structures 17 facing away from the substrate 11; it should be noted that w0 refers to the distance between the inner wall sides of adjacent partition structures 17.

[0137] Preferably, the outer contour of the orthographic projection of the protective layer 15 on the substrate 11 is located outside the outer contour of the orthographic projection of the light-transmitting opening 10b on the substrate 11. That is, in the region between adjacent partition structures 17, the width w1 of the surface of the protective layer 15 facing away from the substrate 11 is greater than the distance w0 between the surfaces of adjacent partition structures 17 facing away from the substrate 11. It should be noted that w0 refers to the distance between the inner wall sides of adjacent partition structures 17.

[0138] Preferably, the orthographic projection of the outer contour of the protective layer 15 on the substrate 11 overlaps with the orthographic projection of the outer contour of the area between the outer walls of the adjacent partition structures 17 on the substrate 11, that is, the width w1 of the surface of the protective layer 15 facing away from the substrate 11 can be equal to the distance w2 between the outer wall sides of the adjacent partition structures 17 (see...). Figure 13 );

[0139] Preferably, the orthographic projection of the protective layer 15 onto the substrate 11 overlaps with the orthographic projection of the light-transmitting opening 10b onto the substrate 11. That is, in the region between adjacent partition structures 17, specifically, the width w1 of the surface of the protective layer 15 facing away from the substrate 11 is equal to the distance w0 between the surfaces of adjacent partition structures 17 facing away from the substrate 11. It should be noted that w0 refers to the distance between the inner wall sides of adjacent partition structures 17 (see [reference]). Figure 19 ).

[0140] Preferably, the outer contour of the orthographic projection of the protective layer 15 on the substrate 11 is located outside the outer contour of the orthographic projection of the light-transmitting opening 10b on the substrate 11, and the area between the outer walls of the adjacent partition structures 17 is within the orthographic projection range on the substrate 11, that is, the width w1 of the surface of the protective layer 15 facing away from the substrate 11 is greater than the distance w0 between the surfaces of the adjacent partition structures 17 facing away from the substrate 11, and the width w1 of the surface of the protective layer 15 facing away from the substrate 11 is less than the distance w2 between the outer walls of the adjacent partition structures 17 (see...). Figure 20 ).

[0141] For example, see Figure 21 The distance h0 between the surface of the protective layer 15 located within the via 10b1 facing away from the substrate 11 and the substrate 11 is greater than the distance h1 between the surface of the first insulating layer 12 and / or the second insulating layer 14 located on the first electrode 13 facing away from the substrate 11 and the substrate 11, and the distance h0 between the surface of the protective layer 15 located within the via 10b1 facing away from the substrate 11 and the substrate 11 is greater than the distance h3 between the surface of the partition structure 17 facing away from the substrate 11 and the substrate 11. Correspondingly, the outer contour of the orthographic projection of the protective layer 15 on the substrate 11 is within the orthographic projection range of the light-transmitting opening 10b on the substrate 11, that is, in the region between adjacent partition structures 17, the width w1 of the surface of the protective layer 15 facing away from the substrate 11 is less than the distance w0 between the surfaces of adjacent partition structures 17 facing away from the substrate 11. It should be noted that w0 refers to the distance between the inner wall sides of adjacent partition structures 17.

[0142] In the above embodiments, the protective layer 15 fills the via 10b1, completely covering the first electrode 13 on the sidewall of the via 10b1 and partially or completely covering the second insulating layer 14 in the area between adjacent partition structures 17. This allows the second insulating material 14 on the sidewall of the via to act as a barrier against the etching reagent during subsequent etching processes, preventing damage to the first electrode 13 by the etching reagent in the VEE process. This results in a larger thickness for the first electrode 13, avoids corrosion voids on the first electrode 13, and improves the electrical reliability of the first electrode 13. Furthermore, it prevents the etching reagent from expanding the corrosion range along the extension direction of the first electrode 13 on the sidewall, thereby mitigating display black spots and display defects. Moreover, the protective layer 15 covering the entire second insulating layer 14 in the area between adjacent partition structures 17 also reduces the difficulty of display panel fabrication.

[0143] In some embodiments, see Figure 22 The display panel 1 also includes a pixel circuit layer 18, disposed on the side of the first insulating layer 12 facing the substrate 11, and the pixel circuit layer 18 includes a plurality of pixel driving units ( Figure 22 (This is for illustrative purposes only; multiple pixel driving units are not shown.) A conductive connection layer 16 is disposed on the side of the first insulating layer 12 facing the pixel circuit layer 16. The conductive connection layer 16 includes multiple conductive connection structures. Figure 22 (This is for illustrative purposes only; multiple pixel driving units are not shown.) The pixel driving units are electrically connected to the first electrode 13 extending to the corresponding via via through a corresponding conductive connection structure.

[0144] In some embodiments, see Figures 3-22 The display panel 1 also includes a partition structure 17, which can be disposed on the side of the second insulating layer 14 facing away from the substrate 11. The partition structure 17 encloses and forms a plurality of light-transmitting openings 10b and a plurality of isolation openings 10a. The isolation openings 10a communicate with the corresponding first openings 14a. The light-transmitting openings 10b are correspondingly disposed with the first electrode 13. The plurality of light-transmitting openings 10b can be spaced apart, and the isolation openings 10a are correspondingly disposed with the first electrode 13. The plurality of isolation openings 10a can be spaced apart. In this way, by providing light-transmitting openings 10b on the partition structure 17, ambient light can pass through the light-transmitting openings 10b, thereby improving the light transmittance of the display panel 1. The orthographic projections of at least a portion of the plurality of vias 10b1 on the substrate 11 overlap with the orthographic projections of the plurality of light-transmitting openings 10b on the substrate 11.

[0145] In some embodiments, see Figure 1The display panel 1 includes a first display area 10 and a second display area 20 adjacent to the first display area 10. The light transmittance of the first display area 10 is greater than that of the second display area 20. Multiple light-transmitting openings 10b are located in the first display area 10, and multiple isolation openings 10a are disposed in the first display area 10 and the second display area 20. Optionally, the orthographic projection of the multiple light-transmitting openings 10b on the substrate covers the orthographic projection of the multiple vias 10b1 on the substrate 11. Optionally, the orthographic projection of the same light-transmitting opening 10b on the substrate 11 covers the orthographic projection of at least one via 10b1 on the substrate 11, as described above. Figures 1-22 A schematic diagram of any implementation.

[0146] In some embodiments, the display panel 1 further includes a plurality of light-emitting functional units and a plurality of second electrodes ( Figures 3-22 (Not shown in the image) At least a portion of the light-emitting functional part is disposed within the corresponding isolation opening 10a; the second electrode is disposed on the side of the corresponding light-emitting functional part away from the substrate 11; the second electrode is electrically connected to the isolation structure 17.

[0147] The following describes the partition structure 17 on the display panel 1 provided in the embodiments of this application.

[0148] For example, see Figure 23 The partition structure 17 includes an isolator 17a and a blocking portion 17b stacked along a direction away from the substrate 11. The outer contour of the orthographic projection of the blocking portion 17b on the substrate 11 is located outside the outer contour of the orthographic projection of the isolator 17a on the substrate 11. The second electrode is electrically connected to the isolator 17a.

[0149] In some embodiments, the insulator 17a includes at least one metal layer;

[0150] In some embodiments, the isolator 17a includes a first metal layer 17a1 and a second metal layer 17a2 stacked along a direction away from the substrate 11. The outer contour of the orthographic projection of the first metal layer 17a on the substrate 11 is located outside the outer contour of the orthographic projection of the second metal layer 17a2 on the substrate 11. This results in the partition structure 17 forming an "I"-shaped structure, that is, the partition structure 17 has an "eaves" and a "base". Thus, during the formation of the light-transmitting opening 10b, the partition structure 17 can separate two adjacent light-transmitting openings 10b, and also separate two adjacent isolation openings 10a.

[0151] For example, the partition structure 17 can refer to an undercut structure that is larger at the top and smaller at the bottom, capable of separating adjacent light-transmitting openings 10b. The partition structure 17 can also be a structure formed by a single membrane layer, or a structure formed by stacking multiple membrane layers.

[0152] For example, the cross-sectional shape of the partition structure 17 can be an inverted trapezoid with a larger top and a smaller bottom, a "T" shape, or an "I" shape, etc.

[0153] For example, at least one of the insulator 17a and the blocking portion 17b may be made of a conductive material. The material of at least one of the insulator 17a and the blocking portion 17b may include metals such as titanium, silver, copper, aluminum, and molybdenum, or alloys, or conductive oxides, such as any one or more of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), zinc gallium oxide, titanium tantalum oxide, tin oxide, cadmium oxide, and indium oxide. For example, the isolation structure 17 may be a grounding isolation structure, i.e., a VSS isolation structure. In other examples, at least one of the insulator 17a and the blocking portion 17b may be made of an insulating material; this embodiment of the application does not limit this.

[0154] For example, the material of the blocking portion 17b may include at least one of titanium and molybdenum.

[0155] For example, the material of the second metal layer 17a2 in the insulator 17a may include at least one of aluminum, copper, and silver.

[0156] For example, the material of the first metal layer 17a1 and the second isolation portion 17c in the isolation body 17a may include at least one of titanium and molybdenum.

[0157] In embodiments where at least one of the first metal layer 17a1, the second metal layer 17a2, and the blocking portion 17b is made of a conductive material, the second electrode of the light-emitting unit in the second insulating layer 14 ( Figure 23 (Not shown) can be electrically connected to the partition structure 17. This facilitates the electrical connection of the second electrode to the second power line through the partition structure 17, thereby optimizing the wiring layout of the display panel 1.

[0158] In embodiments where the material of the second metal layer 17a2 is a conductive material, the second electrode can be electrically connected to the second metal layer 17a2. Thus, the second electrode located within each isolation opening 10a can be connected via the second metal layer 17a2. Figure 23 (Not shown in the image) are connected as a whole and connected to the second power line to apply power voltage to the second electrode, thereby optimizing the wiring layout of the display panel 1.

[0159] In embodiments where the material of the first metal layer 17a1 is a conductive material, the second electrode of the light-emitting unit ( Figure 17(Not shown) can be electrically connected to the first metal layer 17a1. In this way, each second electrode 1 can be connected to the second power line through the first metal layer 17a1, thereby optimizing the wiring layout of the display panel 1.

[0160] In embodiments where both the first metal layer 17a1 and the second metal layer 17a2 are made of conductive materials, the second electrode of the light-emitting unit ( Figure 23 (Not shown) can be electrically connected to at least one of the first metal layer 17a1 and the second metal layer 17a2, thereby optimizing the wiring layout of the display panel 1. For example, the second electrode of the light-emitting unit is connected to both the first metal layer 17a1 and the second metal layer 17a2, thereby improving the connection stability between the second electrode and the partition structure 17. One of the first electrode 13 and the second electrode can be an anode, and the other of the first electrode 13 and the second electrode can be a cathode. In this embodiment, the first electrode 13 is an anode and the second electrode is a cathode, as an example.

[0161] The composition and preparation of the partition structure mentioned above are detailed in patents CN118251982A, 202410864269.8, PCT / CN2024 / 098407, PCT / CN2024 / 102783, and PCT /

[0162] Further descriptions are provided in CN2024 / 098217, PCT / CN2024 / 100935, PCT / CN2024 / 102785, PCT / CN2024 / 099419, PCT / CN2024 / 099072, and CN116685174A for reference.

[0163] For example, the first electrode 13 can be electrically connected to a pixel driving circuit, which can be electrically connected to a first power line. The second electrode can be electrically connected to a second power line. One of the first and second power lines is used to transmit a high voltage, and the other is used to transmit a low voltage. For example, the first power line is used to transmit a high voltage, and the second power line is used to transmit a low voltage.

[0164] In some embodiments, such as Figure 24As shown, the second insulating layer 14 can be a pixel definition layer (PDL) 14a to provide good planar support for the subsequent formation of the partition structure 17. The pixel definition layer 14a can be disposed between the partition structure 17 and the first electrode 13. The pixel definition layer 14a defines pixel holes corresponding to a plurality of vias 10b1 and a plurality of isolation openings 10a. The orthographic projection of the vias 10b1 on the substrate 11 can be located within the orthographic projection of the light-transmitting openings 10b on the substrate 11, and the orthographic projection of the pixel holes on the substrate 11 can be located within the orthographic projection of the isolation openings 10a on the substrate 11. The light-emitting unit can be located at least partially within the pixel hole. In this way, by providing the pixel definition layer 14a, it is convenient to set the light-emitting unit on the substrate 11.

[0165] For example, such as Figure 24 As shown, the pixel defining layer 14a includes a first pixel defining portion 14a1, which covers the first extension portion 131 (see Figure 14a1). Figure 18 On the first extension 131, due to the step difference, the thickness of the first pixel limiting part 14a1 is thinner than the thickness of the rest of the pixel limiting layer 14a. The thinner the first pixel limiting part 14a1, the easier it is to be damaged and form a hole. That is, the first pixel limiting part 14a1 is more likely to be damaged and form a hole.

[0166] In the display panel shown in any of the above embodiments, by covering the first extension 131 with the protective layer 15, the thickness of the first extension 131 at the sidewall of the via 10b1 is increased, so as to avoid the first extension 131 being damaged and forming a hole, thereby avoiding pixel EL failure and generating pixel dark spots, thus improving the display effect.

[0167] The following describes the preparation method of the display panel 1 provided in the embodiments of this application.

[0168] This application provides a method for manufacturing a display panel 1, which can be used to manufacture the display panel 1 in the above embodiments. See also... Figure 2 The display panel 1 may include a plurality of light-transmitting display areas with light-transmitting openings 10b, the plurality of light-transmitting display areas being spaced apart, and a pixel display area with an isolation opening 10a surrounding each light-transmitting display area.

[0169] See Figure 25 The preparation method may include the following steps:

[0170] S110: Provides a substrate.

[0171] See Figures 3-23 A substrate 11 is provided, which can provide support for the remaining film layers to be applied subsequently.

[0172] S120: A first insulating layer is formed on one side of the substrate; the first insulating layer includes a plurality of vias, and the vias include sidewalls.

[0173] See Figures 3-23 After providing the substrate 11, a first insulating layer 12 may be formed on one side of the substrate 11. The first insulating layer 12 encloses a plurality of vias 10b1. For example, the first insulating layer 12 may be a planarization layer. Optionally, the first insulating layer is a planarization layer.

[0174] S130: A plurality of first electrodes are formed on the side of the first insulating layer away from the substrate; portions of the first electrodes extend to the sidewall of the corresponding via.

[0175] See Figures 3-18 After forming a first insulating layer 12 on one side of the substrate 11, a plurality of first electrodes 13 may be formed on the side of the first insulating layer 12 facing away from the substrate 11, with portions of the first electrodes 13 extending into corresponding vias 10b1. For details, see [link to documentation]. Figure 4 The first electrode 13 includes a first extension 131, a second extension 132, and a third extension 133. The first extension 131 covers the sidewall of the via 10b1. The second extension 132 is located at the end of the via 10b1 facing the substrate 11. The third extension 133 is located on the side of the first insulating layer 12 away from the substrate 11. The second extension 132 and the third extension 133 are connected through the first extension 131. The thickness of the first extension 131 is less than the thickness of at least one of the second extension 132 and the third extension 133.

[0176] S140: A second insulating layer is formed on the side of the first insulating layer and the first electrode away from the substrate; the second insulating layer encloses and forms a plurality of first openings, the orthographic projection of the first opening on the substrate being located within the orthographic projection of the corresponding first electrode on the substrate.

[0177] See Figures 3-23 After providing the first electrode 13, a second insulating layer 14 may be formed on one side of the first insulating layer 12 and the first electrode 13. The second insulating layer 14 has a plurality of vias 10b1. For example, the second insulating layer 14 may include a pixel defining layer 14a. The orthogonal projection of the second insulating layer 14 onto the substrate 11 covers the orthogonal projection of the first electrode 13 onto the substrate 11. The second insulating layer 14 also has pixel holes corresponding to a plurality of isolation openings 10a. The orthogonal projection of the vias 10b1 onto the substrate 11 may lie within the orthogonal projection of the light-transmitting openings 10b onto the substrate 11; the orthogonal projection of the pixel holes onto the substrate 11 may lie within the orthogonal projection of the isolation openings 10a onto the substrate 11. At least a portion of the light-emitting unit may be located within the pixel hole. Thus, by providing the pixel defining layer 14a, it is convenient to provide the light-emitting unit on the substrate 11. Optionally, the second insulating layer is a pixel defining layer.

[0178] For example, see Figures 3-23 As shown, a second insulating layer 14 is formed on one side of the first electrode 13, such that the first pixel defining portion 14a1 in the second insulating layer 14 covers the first extension portion 131 in the first electrode 13. Since there is a step difference in the first extension portion 131, the thickness of the first pixel defining portion 14a1 is thinner than the thickness of the rest of the pixel defining layer 14a. The thinner the pixel defining layer 14a, the easier it is to be damaged and form a hole. That is, the first pixel defining portion 14a1 is more likely to be damaged and form a hole.

[0179] S150: A protective layer is formed on the side of the second insulating layer away from the substrate; the orthographic projection of the protective layer on the sidewall at least partially overlaps with the orthographic projection of the plurality of first electrodes on the sidewall.

[0180] See Figures 3-23 After providing the second insulating layer 14, a protective layer 15 may be formed on one side of the second insulating layer 14, see [reference]. Figure 10 ,or Figure 12 ,or Figure 13 The protective layer 15 can partially fill the via 10b1, see [reference]. Figure 11 ,or Figure 14 ,or Figure 15 ,or Figure 16 ,or Figure 17 The protective layer 15 can completely fill the via 10b1.

[0181] The display panel manufacturing method provided in this application provides a second insulating layer, and then covers the second insulating layer on the sidewall of the via with a protective layer. This reduces the over-etching loss of the second insulating layer in the subsequent VEE process, thereby solving the problem of dark spot failure on the display panel caused by the via and improving the display effect of the display panel.

[0182] In some embodiments, see Figure 26 The preparation method may also include the following steps:

[0183] S160, a partition structure is formed on the side of the second insulating layer away from the substrate; the partition structure encloses and forms a plurality of light-transmitting openings and a plurality of isolation openings, the isolation openings being connected to the corresponding first openings; at least a portion of the vias have their orthogonal projections on the substrate overlapping with the orthogonal projections of the plurality of light-transmitting openings on the substrate.

[0184] See Figures 3-23 After providing the second insulating layer 14, a partition structure 17 may be formed on the side of the second insulating layer 14 facing away from the substrate 11, see [reference]. Figure 23The process may include forming a first metal layer 17a1 on the side of the second insulating layer 14 facing away from the substrate 11; after providing the first metal layer 17a1, a second metal layer 17a2 may be formed on the side of the first metal layer 17a1 facing away from the substrate 11; after providing the second metal layer 17a2, a blocking portion 17b may be formed on one side of the second metal layer 17a2. Later, patterning processing can be performed on the partition structure 17 to form a light-transmitting opening 10b and an isolation opening 10a on the partition structure 17. It is understood that the cross-sectional shape of the partition structure 17 can be an inverted trapezoid (larger at the top and smaller at the bottom), a "T" shape, or an "I" shape, etc. Different fabrication methods can be used for different shapes of partition structures 17.

[0185] The composition and preparation of the partition structure mentioned above are further described in patents CN118251982A, 202311324257.8, 2023107314719, 202311686416.9, 202310707183.X, 202310479495.X, 202310445544.8, 202310731471.9, CN116685174A, and CN116669477A, ​​for reference.

[0186] In some embodiments, the protective layer 15 may partially fill the via 10b1, see [reference needed]. Figure 10 ,or Figure 12 ,or Figure 13 The protective layer 15 can also completely fill the via 10b1, see [reference]. Figure 11 ,or Figure 14 ,or Figure 15 ,or Figure 16 ,or Figure 17 ,or Figure 18 ,or Figure 19 ,or Figure 20 ,or Figure 21 ,or Figure 22 ,or Figure 23 The protective layer 15 is made of organic materials; alternatively, the protective layer 15 may be made of light-transmitting materials. For details regarding the filling method of the protective layer 15, please refer to the foregoing. Figures 10-23 The descriptions in the embodiments are not repeated here.

[0187] For example, in the embodiments of this application, the first insulating layer 14 can be patterned by an etching process (e.g., a first patterning process), and the etching process can include dry etching, wet etching, etc.

[0188] In some embodiments, see Figure 27 The preparation method may also include the following steps:

[0189] S170, a pixel circuit layer is formed on the side of the first insulating layer facing the substrate.

[0190] S180, a conductive connection layer is formed on the side of the first insulating layer facing the pixel circuit layer.

[0191] For example, see Figure 22 Before forming the first insulating layer 12 on one side of the substrate 11, the method may further include forming a pixel circuit layer 18 on one side of the substrate 11, and then forming a conductive connection layer 16 on the side of the first insulating layer 12 facing the pixel circuit layer 18. The pixel circuit layer 18 includes a plurality of pixel driving units, and the conductive connection layer 16 includes a plurality of conductive connection structures. The pixel driving units are electrically connected to a first electrode extending to a corresponding via through a corresponding conductive connection structure. Optionally, the conductive connection layer 16 may be a metal layer.

[0192] This application provides a display device, which includes a display panel 1. The display device can be an electronic paper device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, smart bracelet, smartwatch, supercomputer, navigator, wireless device, personal digital assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, clock, calculator, television monitor, computer monitor, automotive display (e.g., odometer display), cockpit controller and / or display, camera view display (e.g., display of a rearview camera in a vehicle), electronic billboard or sign, projector, and other mobile or fixed terminals.

[0193] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0194] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0195] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, include: substrate; A first insulating layer is disposed on one side of the substrate; the first insulating layer includes a plurality of vias, each via including a sidewall; Multiple first electrodes are disposed on the side of the first insulating layer opposite to the substrate; A portion of the first electrode extends to the sidewall of the corresponding via; A second insulating layer is disposed on the side of the first insulating layer and the plurality of first electrodes facing away from the substrate; The second insulating layer encloses and forms a plurality of first openings, wherein the orthographic projection of the first opening on the substrate is located within the orthographic projection of the corresponding first electrode on the substrate; A protective layer is disposed on the side of the second insulating layer opposite to the substrate; the orthographic projection of the protective layer on the sidewall at least partially overlaps with the orthographic projection of the plurality of first electrodes on the sidewall.

2. The display panel according to claim 1, characterized in that, The orthographic projection of the protective layer on the sidewall covers the orthographic projection of the plurality of first electrodes on the sidewall; Optionally, the orthographic projection of the plurality of first electrodes on the sidewall lies within the orthographic projection of the protective layer on the sidewall; Optionally, the orthographic projection of the sidewall onto the substrate lies within the orthographic projection of the protective layer onto the substrate; Optionally, the orthographic projection of the sidewall on the substrate is located within the orthographic projection of the corresponding first electrode on the substrate; Optionally, the protective layer comprises an organic material.

3. The display panel according to claim 1, characterized in that, The distance between the surface of the protective layer located in the via and the substrate on the side opposite to the substrate is not less than the distance between the surface of the first electrode located on the first insulating layer and the substrate on the side opposite to the substrate; Optionally, the orthographic projection of the sidewall onto the substrate lies within the orthographic projection of the protective layer onto the substrate; Optionally, the distance between the surface of the protective layer located in the via and the substrate on the side away from the substrate is less than the distance between the surface of the first insulating layer and / or the second insulating layer located on the first electrode on the side away from the substrate and the substrate, and is greater than the distance between the surface of the first electrode located on the first insulating layer and the substrate on the side away from the substrate. Optionally, the distance between the surface of the protective layer located in the via and the substrate on the side opposite to the substrate is equal to the distance between the surface of the first insulating layer and / or the surface of the second insulating layer located on the first electrode and the substrate on the side opposite to the substrate. Optionally, the distance between the surface of the protective layer located in the via and the substrate on the side opposite to the substrate is equal to the distance between the surface of the first electrode located on the first insulating layer and the substrate on the side opposite to the substrate; Optionally, the distance between the surface of the protective layer located in the via and the substrate on the side opposite to the substrate is greater than the distance between the surface of the first insulating layer and / or the surface of the second insulating layer located on the first electrode and the substrate on the side opposite to the substrate. Optionally, the distance between the surface of the protective layer located in the via and the substrate on the side opposite to the substrate is less than the distance between the surface of the first electrode located on the first insulating layer and the substrate on the side opposite to the substrate.

4. The display panel according to claim 1, characterized in that, The display panel further includes a partition structure disposed on the side of the second insulating layer away from the substrate; The partition structure encloses and forms multiple light-transmitting openings and multiple isolation openings, and the isolation openings are connected to the corresponding first openings; At least a portion of the plurality of vias have their orthogonal projections on the substrate overlapping with the orthogonal projections of the plurality of light-transmitting openings on the substrate. Optionally, the display panel includes a first display area and a second display area adjacent to the first display area, the light transmittance of the first display area is greater than the light transmittance of the second display area, the plurality of light-transmitting openings are disposed in the first display area, and the plurality of isolation openings are disposed in the first display area and the second display area; Optionally, the protective layer includes a light-transmitting material; Optionally, the orthographic projection of the plurality of light-transmitting openings on the substrate covers the orthographic projection of the plurality of vias on the substrate; Optionally, the orthographic projection of the same light-transmitting opening on the substrate covers the orthographic projection of at least one of the vias on the substrate.

5. The display panel according to claim 4, characterized in that, The display panel further includes a plurality of light-emitting functional units and a plurality of second electrodes, wherein at least a portion of the light-emitting functional units is disposed within the corresponding isolation openings; and the second electrodes are disposed on the side of the corresponding light-emitting functional unit away from the substrate. The second electrode is electrically connected to the isolation structure; Optionally, the partition structure includes an isolator and a blocking portion stacked along a direction away from the substrate, wherein the outer contour of the orthographic projection of the blocking portion on the substrate is located outside the outer contour of the orthographic projection of the isolator on the substrate. The second electrode is electrically connected to the insulator; Optionally, the insulator includes at least one metal layer; Optionally, the separator includes a first metal layer and a second metal layer stacked along a direction away from the substrate, wherein the outer contour of the orthographic projection of the first metal layer on the substrate is located outside the outer contour of the orthographic projection of the second metal layer on the substrate.

6. The display panel according to claim 4, characterized in that, The distance between the surface of the protective layer located in the via and the substrate on the side away from the substrate is greater than the distance between the surface of the first insulating layer and / or the second insulating layer located on the first electrode and the substrate on the side away from the substrate, and the distance between the surface of the protective layer located in the via and the substrate on the side away from the substrate is less than the distance between the surface of the partition structure and the substrate on the side away from the substrate. Alternatively, the distance between the surface of the protective layer located in the via and the substrate on the side away from the substrate is greater than the distance between the surface of the first insulating layer and / or the second insulating layer located on the first electrode and the substrate on the side away from the substrate, and the distance between the surface of the protective layer located in the via and the substrate on the side away from the substrate is not less than the distance between the surface of the partition structure and the substrate on the side away from the substrate. Optionally, the distance between the surface of the protective layer located in the via and the substrate on the side away from the substrate is greater than the distance between the surface of the first insulating layer and / or the second insulating layer located on the first electrode and the substrate on the side away from the substrate, and the distance between the surface of the protective layer located in the via and the substrate on the side away from the substrate is equal to the distance between the surface of the partition structure and the substrate on the side away from the substrate. Optionally, the outer contour of the protective layer projected onto the substrate is located within the projection range of the light-transmitting opening onto the substrate.

7. The display panel according to claim 6, characterized in that, The orthogonal projection of the protective layer on the substrate covers the orthogonal projection of the light-transmitting opening on the substrate; Optionally, the outer contour of the protective layer projected onto the substrate is located outside the outer contour of the light-transmitting opening projected onto the substrate; Optionally, the outer contour of the protective layer projected onto the substrate overlaps with the outer contour of the light-transmitting opening projected onto the substrate.

8. The display panel according to claim 1, characterized in that, The display panel also includes: A pixel circuit layer is disposed on the side of the first insulating layer facing the substrate, and the pixel circuit layer includes a plurality of pixel driving units; A conductive connection layer is disposed on the side of the first insulating layer facing the pixel circuit layer, and the conductive connection layer includes a plurality of conductive connection structures; The pixel driving unit is electrically connected to the first electrode extending to the corresponding via through the corresponding conductive connection structure.

9. The display panel according to any one of claims 1-8, characterized in that, The first insulating layer is a planarization layer; and / or, the second insulating layer is a pixel defining layer.

10. A display panel, characterized in that, include: substrate; A first insulating layer is disposed on one side of the substrate; the first insulating layer includes a plurality of vias, each via including a sidewall; Multiple first electrodes are disposed on the side of the first insulating layer opposite to the substrate; A portion of the first electrode extends into the sidewall of the corresponding via; A second insulating layer is disposed on the side of the first insulating layer and the first electrode that is away from the substrate; The second insulating layer encloses and forms a plurality of first openings, wherein the orthographic projection of the first opening on the substrate is located within the orthographic projection of the corresponding first electrode on the substrate; A protective layer is disposed on the side of the second insulating layer opposite to the substrate; the orthographic projection of the protective layer on the sidewall at least partially overlaps with the orthographic projection of the plurality of first electrodes on the sidewall. A partition structure is disposed on the side of the second insulating layer opposite to the substrate; The partition structure encloses and forms multiple light-transmitting openings and multiple isolation openings, and the isolation openings are connected to the corresponding first openings; At least a portion of the vias have their orthographic projections on the substrate overlapping with the orthographic projections of the plurality of light-transmitting openings on the substrate.

11. A method for manufacturing a display panel, characterized in that, include: Provide substrate; A first insulating layer is formed on one side of the substrate; the first insulating layer includes a plurality of vias, each via including a sidewall; A plurality of first electrodes are formed on the side of the first insulating layer opposite to the substrate; portions of the first electrodes extend to the sidewall of the corresponding via. A second insulating layer is formed on the side of the first insulating layer and the plurality of first electrodes facing away from the substrate; The second insulating layer encloses and forms a plurality of first openings, wherein the orthographic projection of the first opening on the substrate is located within the orthographic projection of the corresponding first electrode on the substrate; A protective layer is formed on the side of the second insulating layer that is opposite to the substrate; The orthographic projection of the protective layer on the sidewall at least partially overlaps with the orthographic projection of the plurality of first electrodes on the sidewall.

12. The method according to claim 11, characterized in that, The method further includes: A partition structure is formed on the side of the second insulating layer opposite to the substrate; the partition structure encloses and forms a plurality of light-transmitting openings and a plurality of isolation openings, the isolation openings communicating with the corresponding first openings; at least a portion of the plurality of vias have their orthogonal projections on the substrate overlapping with the orthogonal projections of the plurality of light-transmitting openings on the substrate.

13. The method according to claim 11 or 12, characterized in that, The method further includes: A pixel circuit layer is formed on the side of the first insulating layer facing the substrate, and the pixel circuit layer includes a plurality of pixel driving units; A conductive connection layer is formed on the side of the first insulating layer facing the pixel circuit layer, and the conductive connection layer includes a plurality of conductive connection structures; wherein, the pixel driving unit is electrically connected to the first electrode extending to the corresponding via through the corresponding conductive connection structure.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 1-10.

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