Display device

Abstract

A display device includes: a display panel having a notch portion and including a display area and a non-display area surrounding the display area; and a printed circuit film attached to the display panel, and the display panel may include: a substrate; at least one panel inorganic layer disposed on the substrate; a light emitting unit disposed on the at least one panel inorganic layer; and an encapsulation unit disposed on the light emitting unit, and the non-display area may include a notched non-display area disposed around the notched portion, and the encapsulation unit may be disposed to an end portion of the notched non-display area.

Description

Technical Field

[0001] This disclosure relates to a device, and in particular, for example, but not limited to, a display device. Background Technology

[0002] With the advancement of information-oriented society, the demand for various types of display devices for displaying images is increasing. Furthermore, various types of display devices, such as liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays, are already in use.

[0003] Among various display devices, OLED devices, which are emission-type displays, offer advantages in viewing angle and contrast compared to LCD devices. Because they do not require an additional backlight unit, OLED devices are lightweight, thin, and consume little power. Furthermore, OLED devices are driven by low voltage and have a fast response time. Specifically, OLED devices have low manufacturing costs.

[0004] OLED devices can be used in displays installed in vehicles.

[0005] The descriptions provided in the discussion of the Related Art section should not be considered prior art merely because they are mentioned in or associated with that section. The discussion of the Related Art section may include information describing one or more aspects of the subject art, and the descriptions in that section do not limit this disclosure. Summary of the Invention

[0006] The inventors of this disclosure have realized that, depending on the driving conditions, displays positioned in front of the driver's seat and the front passenger seat in a vehicle may need to limit the driver's field of view. The display may need to limit the field of view to protect privacy and information.

[0007] The objective of this disclosure is to provide a display device designed to have improved aesthetics.

[0008] Another objective of this disclosure is to provide a display device that can suppress or prevent defects such as marks and scratches in the display device.

[0009] Another objective of this disclosure is to provide a display device that can suppress or prevent defects such as imprints and scratches in the display device caused by a deposition mask.

[0010] Another objective of this disclosure is to provide a display device that improves reliability by suppressing or preventing defects on the display panel.

[0011] The purpose of this disclosure is not limited to the above-described purpose, and other technical problems can be deduced from the following first embodiment.

[0012] One embodiment is a display device comprising: a display panel having a notch and including a display area and a non-display area surrounding the display area; and a printed circuit film attached to the display panel. The display panel may include: a substrate; at least one panel inorganic layer disposed on the substrate; a light-emitting unit disposed on the at least one panel inorganic layer; and an encapsulation unit disposed on the light-emitting unit. The non-display area may include a notched non-display area disposed around the notch, and the encapsulation unit may be disposed at an end of the notched non-display area.

[0013] Another embodiment is a display device comprising: a substrate including a display area having a plurality of sub-pixels and a non-display area surrounding the display area; at least one panel inorganic layer disposed on the substrate; a light-emitting unit disposed on the at least one panel inorganic layer; an encapsulation unit disposed on the light-emitting unit; a display panel including a touch unit disposed on the encapsulation unit; and microlenses disposed on the light-emitting areas of the sub-pixels, wherein the encapsulation unit may extend to the end of the non-display area.

[0014] Details of the implementation methods are included in the detailed description and accompanying drawings.

[0015] According to embodiments of this disclosure, a display device with improved aesthetics can be provided.

[0016] According to embodiments of the present disclosure, a display device can be provided that can suppress or prevent defects such as marks and scratches in the display device.

[0017] According to embodiments of the present disclosure, a display device can be provided that can suppress or prevent defects such as imprints and scratches in the display device caused by a deposition mask.

[0018] According to embodiments of this disclosure, a display device with improved reliability can be provided by suppressing or preventing defects on the display panel.

[0019] According to embodiments of this disclosure, defects in the display device can be prevented or reduced, and because defects such as marks and scratches in the display device can be suppressed or prevented, the lifespan of the display device can be increased, thereby reducing production energy.

[0020] The effects of this disclosure are not limited to those described above, and those skilled in the art can derive other effects not described herein from the following description of the embodiments of this disclosure. Attached Figure Description

[0021] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0022] Figure 1 This is a plan view of a display device according to an embodiment.

[0023] Figure 2 yes Figure 1 A magnified view of the Q1 region.

[0024] Figure 3 Is only shown Figure 1 The image shows the display panel.

[0025] Figure 4 This is a plan view showing the pixel configuration of a display device according to an embodiment.

[0026] Figure 5 It is along Figure 4 The cross-sectional view taken by the V-V' line in the diagram.

[0027] Figure 6 From and Figure 5 Cross-sectional views taken from different angles.

[0028] Figure 7 This is a plan view of the display panel according to the implementation method.

[0029] Figure 8 It is along Figure 7 The cross-sectional view taken from line VIII-VIII' in the diagram.

[0030] Figure 9 It is along Figure 1 The cross-sectional view taken from line A-A' in the diagram.

[0031] Figure 10 It is along Figure 3 The cross-sectional view taken by the B-B' line in the diagram.

[0032] Figure 11 It is along Figure 3 The cross-sectional view taken from the C-C' line.

[0033] Figure 12 This is a schematic diagram illustrating one step of a method for manufacturing a display device according to an embodiment.

[0034] Figure 13 This is a plan view of a display device according to another embodiment.

[0035] Figure 14 yes Figure 13 A magnified view of the Q2 region.

[0036] Figure 15 It is along Figure 14 The cross-sectional view taken by the D-D' line in the diagram.

[0037] Figure 16 This is a cross-sectional view of a display device according to another embodiment.

[0038] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative dimensions and depictions of these elements may be exaggerated.

[0039] Figure Labels

[0040] 1: Display device

[0041] 100: Display panel

[0042] 101: Substrate

[0043] NCP: Notch

[0044] DA: Display Area

[0045] NDA: Non-display area

[0046] NDA1: First Non-Display Area

[0047] NDA2: Second Non-Display Area

[0048] N_NDA: Non-display area of ​​the notch

[0049] E_NDA: Extended non-display area

[0050] PA: Pad area

[0051] SP: Subpixel

[0052] EA: Emitting area

[0053] NEA: Non-luminescent area

[0054] ML: Microlens

[0055] 150: Light-emitting unit

[0056] 170: Packaging Unit Detailed Implementation

[0057] Hereinafter, a first embodiment of the present invention will be described with reference to the accompanying drawings. In this specification, when a component (or region, layer, part, etc.) is referred to as "on another component," "connected to," or "combined to" another component, it means that the component may be directly on, connected to, or combined to another component, or a third component may be present therein.

[0058] The same reference numerals denote the same elements. Furthermore, in the drawings, the thickness, scale, and dimensions of parts are exaggerated for effective description. "And / or" includes all of one or more combinations defined by the relevant parts.

[0059] It should be understood that the terms "first" and "second" are used herein to describe various components, but these components should not be limited by these terms. The terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component without departing from the scope of this disclosure, and vice versa. Unless the context clearly specifies otherwise, singular expressions include plural expressions.

[0060] In addition, terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the structures shown in the figure. These terms are described as relative concepts based on the directions shown in the figure.

[0061] In various embodiments of this disclosure, the terms "comprising" or "including" specify attributes, fixed quantities, steps, processes, elements and / or components or combinations thereof, but do not exclude the presence or addition of other attributes, fixed quantities, steps, processes, elements and / or components or combinations thereof.

[0062] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations associated with this document will be omitted where such descriptions would be deemed to unnecessarily obscure the essential points of the inventive concept. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to that set forth herein, except that they must occur in a specific order, and can be varied as is known in the art. The same reference numerals always denote the same elements. The names of the elements used in the following description may be chosen solely for convenience of writing the specification and may therefore differ from the names used in actual products.

[0063] In the following description, when a detailed description of a well-known function or configuration relevant to this document is determined to unnecessarily obscure the essential points of the inventive concept, its detailed description will be omitted or may be briefly discussed.

[0064] The advantages and features of this disclosure, as well as its implementation methods, will be illustrated by the following exemplary embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided to make this disclosure thorough and complete enough to assist those skilled in the art in fully understanding its scope.

[0065] Any implementation described as an "example" in this article is not necessarily to be interpreted as preferred or superior to other implementations.

[0066] Furthermore, when referring to any size, relative size, etc., it should be assumed that the numerical or corresponding information of an element or feature (e.g., level, range, etc.) includes the range of tolerances or errors that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. Additionally, the term "may" fully encompasses all the meanings of the term "able to".

[0067] When describing temporal relationships, discontinuous cases may be included when the time sequence is described as such as "after", "following", "next", and "before", unless more restrictive terms such as "just", "immediately", or "directly" are used.

[0068] The term “at least one” should be understood to include any and all combinations of one or more of the associated listed items. For example, “at least one of the first element, the second element, and the third element” means a combination of all three listed elements, a combination of any two of the three elements, and each individual element, the first element, the second element, or the third element.

[0069] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It should also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and should not be interpreted in an idealized or overly formal sense unless expressly defined herein. For example, the terms “part” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the functions described herein that would be understood by one of ordinary skill in the art.

[0070] Instead, these implementations may be provided to make this disclosure thorough and complete enough to help those skilled in the art to fully understand the scope of this disclosure.

[0071] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be coupled or combined in part or in whole, and may interoperate and be technology-driven in various ways. Embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0072] Figure 1 This is a plan view of the display device according to the embodiment. Figure 2 yes Figure 1 A magnified view of the Q1 region. Figure 3 Is only shown Figure 1 The image shows the display panel.

[0073] Figure 3 From Figure 2 The diagram omits the flexible film COF, main substrate MB, and driver ICDIC, which are not part of the display panel 100. Figure 3 For ease of explanation, the percentages between components have been adjusted.

[0074] Reference Figures 1 to 3 The display device 1 may be a device that includes both a display function for displaying an image and a touch sensing function for sensing a user's touch, but is not limited thereto. For example, the display device 1 may include one of the display function for displaying an image and the touch sensing function for sensing a user's touch.

[0075] Display device 1 may be a miniature light-emitting diode device or an electroluminescent display device including a touch sensor. The electroluminescent display device including a touch sensor may be an organic light-emitting diode device (OLED), a quantum dot light-emitting diode display device, or an inorganic light-emitting diode device.

[0076] The display device 1 according to this embodiment may also be a display device for vehicles, but is not limited thereto. For example, the description of the display device 1 can be applied without limitation to various types of equipment, as long as the equipment includes a display function.

[0077] When the display device 1 according to this embodiment is a display device for a vehicle, the display device 1 may include functions for operating at least some of the various functions of the vehicle, functions for presenting various information related to the vehicle, etc.

[0078] When the display device 1 according to this embodiment is a vehicle display device, the display device 1 can be installed in the vehicle's dashboard. The display device 1 can be configured to span across the driver's seat and the front passenger seat at the front of the vehicle, but is not limited thereto. Both the driver sitting in the driver's seat and the passenger sitting in the front passenger seat can use the display device 1.

[0079] The display device 1 may use a display panel 100. The display panel 100 may include a display area DA and a non-display area DNA.

[0080] The display area DA can be an area that can display an image when light is emitted outwards. The display area DA may also include functionality for sensing a user's touch. In this case, the display area DA may correspond to a touch sensing area, but is not limited to this.

[0081] The display area DA may correspond to the shape of the display panel 100, but is not limited to it.

[0082] Multiple sub-pixels (SPs) can be set in the display area DA. Multiple sub-pixels (SPs) can be repeatedly set along the first direction DR1 and the second direction DR2.

[0083] The non-display area NDA can be an area that does not display an image because it does not emit light to the outside. The non-display area NDA can be disposed around the display area DA. The non-display area NDA can surround the display area DA, but the embodiments of this disclosure are not limited thereto. The border area of ​​the display device 1 can be defined by the non-display area NDA, but the embodiments of this disclosure are not limited thereto.

[0084] The display panel 100 may be a rigid display panel, but the embodiments disclosed herein are not limited thereto. The display panel 100 may be a flexible display panel whose shape can be deformed, such as a foldable display panel, a bendable display panel, a rollable display panel, and a stretchable display panel.

[0085] The display panel 100 may include a first long side LE1, a second long side LE2, a first short side SE1, and a second short side SE2 that configure the edges of the display panel 100.

[0086] The first long side LE1 and the second long side LE2 extend in the first direction DR1, and the first short side SE1 and the second short side SE2 extend in the direction between the first direction DR1 and the second direction DR2. The first long side LE1 and the second long side LE2 can be connected to each other at both ends through the first short side SE1 and the second short side SE2.

[0087] The first long side LE1 can be located on one side of the second long side LE2. The first long side LE1 and the second long side LE2 can extend parallel to each other, but are not limited thereto.

[0088] The length of the first long side LE1 can be shorter than the length of the second long side LE2. Therefore, the first short side SE1 and the second short side SE2 can extend in directions that intersect each other, but are not limited to this.

[0089] The first direction DR1 and the second direction DR2 can be intersecting directions. The first direction DR1 and the second direction DR2 can be orthogonal to each other, but are not limited thereto. The first direction DR1 and the second direction DR2 are provided for the purpose of more accurately describing this disclosure. The first direction DR1 and the second direction DR2 are relative, but the embodiments of this disclosure are not limited thereto.

[0090] When viewing the floor plan, the first long side LE1 is positioned above the display area DA, and the second long side LE2 is positioned below the display area DA.

[0091] When viewing the floor plan, the first short side SE1 is positioned to the right of the display area DA, and the second short side SE2 is positioned to the left of the display area DA1.

[0092] The display panel 100 may include a curved notch NCP. The notch NCP may be formed in the second long side LE2, but is not limited thereto. In other words, the second long side LE2 extends generally along the first direction DR1, but may also include a notch NCP that curves toward the first long side LE1.

[0093] When setting the recessed NCP, components such as the driver's seat handle can be placed in the recessed NCP, and the display area DA that can be displayed can be maximized or enlarged, thereby improving user convenience and aesthetics.

[0094] The non-display area NDA may include a first non-display area NDA1 set along a first long side LE1, a first short side SE1, and a second short side SE2, and a second non-display area NDA2 set along a second long side LE2. The second non-display area NDA2 may be set along the second long side LE2, which includes a curved notch NCP.

[0095] The first non-display area NDA1 is set on one side and the other side of the first direction DR1 in the display area DA, and therefore, it can be set on one side of the second direction DR2 in the display area DA.

[0096] The second non-display area NDA2 may include a recessed non-display area N_NDA disposed around the recessed portion NCP and an extended non-display area E_NDA disposed around the recessed non-display area N_NDA.

[0097] The extended non-display area E_NDA can extend from the notched non-display area N_NDA along the first direction DR1. The extended non-display area E_NDA can be located between the notched non-display area N_NDA and the first non-display area NDA1. The extended non-display area E_NDA can connect the notched non-display area N_NDA and the first non-display area NDA1 to each other.

[0098] The display device 1 may also include a pad area PA, a gating driver GIP, a main substrate MB, a flexible film COF, a driver IC DIC, a gating control line GCL, a data line DL, a low-potential voltage line VSSL, and a high-potential voltage line VDDL.

[0099] The pad area PA can overlap with the flexible film COF. The pad area PA can be attached to the flexible film COF. In other words, the display panel 100 and the flexible film COF can be attached to each other through the pad area PA.

[0100] The pad area PA can be set in the non-display area NDA. The pad area PA can be set in the second non-display area NDA2. The pad area PA can be set in each of the notch non-display area N_NDA and the extended non-display area E_NDA.

[0101] The pad area PA can include multiple pads. The pad area PA can include a low-potential voltage pad VSSP, a high-potential voltage pad VDDP, a first data pad DP1, and a second data pad PD2. The low-potential pad VSSP, the high-potential pad VDDP, the first data pad DP1, and the second data pad PD2 can be set within the pad area PA.

[0102] exist Figure 3 The diagram illustrates a sequence of low-potential voltage pads VSSP, high-potential voltage pads VDDP, first data pad DP1, and second data pad PD2; however, the implementation is not limited to this. For example, the first data pad DP1 and the second data pad DP2 can be positioned between the low-potential voltage pad VSSP and the high-potential voltage pad VDDP.

[0103] However, the implementation is not limited to this, and the pad region PA in the area where the flexible film COF disposed along the non-display area NDA overlaps with the flexible film COF disposed at both ends may further include a gated control pad (not shown).

[0104] The gating driver GIP can be located in the non-display area NDA. The gating driver GIP can be located on one side of the first direction DR1, or on the other side, but is not limited thereto. When viewed from above, the gating driver GIP can be located to the left or on the other side of the display area DA.

[0105] The strobe driver (GIP) can include multiple transistors (see reference). Figure 9 G120 in the middle). Transistor set in the gating driver GIP (reference). Figure 9 The G120 in the image can be connected to the sub-pixel SP (or pixel) via the gating line GL. The gating driver GIP can apply a gating signal to each sub-pixel SP (or pixel) via the gating line GL.

[0106] A gating control signal can be applied from the driver IC (DIC) to the gating driver (GIP) via the gating control line (GCL). The gating driver (GIP) can generate scan signals and illumination signals (or illumination control signals) based on the gating control signal. The gating driver (GIP) can include a scan driver and an illumination signal driver. The scan driver can generate scan signals in row-sequential order and provide the scan signals to the scan lines to drive at least one or more scan lines connected to each row. The illumination signal driver can generate illumination signals in row-sequential order and provide the illumination signals to the illumination signal lines to drive at least one or more illumination signal lines connected to each row.

[0107] The main substrate MB can be connected to the display panel 100 via a flexible film COF. The main substrate MB can be electrically connected to the sub-pixels SP (or pixels) in the display area DA via the flexible film COF. The main substrate MB can be electrically connected to the flexible film COF. The main substrate MB and the flexible film COF can be electrically connected to each other via multiple pads VSSP, VDDP, and DP.

[0108] On the main substrate MB, various components can be installed to provide various signals such as strobe control signals, drive signals, and data signals to the driver IC DIC. The main substrate MB can be a printed circuit board, but is not limited to this.

[0109] The main substrate MB can be connected to the display panel 100 via a flexible film COF in the second non-display area NDA2. Multiple main substrate MBs can be arranged along the second non-display area NDA2, but are not limited to this. The number of main substrate MBs can be varied according to the design.

[0110] One of the main substrates MB can be disposed around the notch NCP and can be connected to the display panel 100 via the flexible film COF in the non-display area N_NDA of the notch.

[0111] The flexible film COF can be attached to the display panel 100 and the main substrate MB. The flexible film COF can be attached to each of the display panel 100 and the main substrate MB, and can be electrically connected to each of the display panel 100 and the main substrate MB. In other words, the display panel 100 and the main substrate MB can be electrically connected to each other via the flexible film COF. Multiple flexible film COFs can be provided, but their number is not limited to this.

[0112] The flexible film COF can be attached to the display panel 100 in the second non-display area NDA2. The flexible film COF can be repeatedly positioned along the second non-display area NDA2. The flexible film COM can be attached to the display panel 100 across the notched non-display area N_NDA and the extended non-display area E_NDA.

[0113] A main substrate MB can be electrically connected to the display panel 100 via at least one flexible film COF. For example, among a plurality of main substrate MBs disposed along the second non-display area NDA2, the main substrate MBs disposed at both ends can be electrically connected to the display panel 100 via one flexible film COF, and each of the remaining main substrate MBs can be electrically connected to the display panel 100 via two flexible film COFs.

[0114] The flexible film COF can be electrically connected to the pad area PA. In doing so, the flexible film COF can provide gating control signals, drive signals, power supply voltage, data voltage, etc. to the gating driver GIP and multiple sub-pixels SP (or pixels) located in the display area DA.

[0115] The flexible COF (Chip-on-Foil) film can be a flexible insulating film comprising multiple conductive wires. Flexible COF films can include, for example, polycarbonate, polyethylene terephthalate, polyimide, polyamide, polyester, polyacrylate, polymethyl methacrylate, etc., but are not limited to these.

[0116] The driver IC DIC can be mounted on a flexible film COF. The driver IC DIC can be configured in various ways, such as chip-on-glass, chip-on-film, or carrier-based packaging, depending on the mounting method. In this disclosure, the driver IC DIC is described as being mounted on a flexible film COF in a chip-on-film manner, but it is not limited to this.

[0117] The driver IC (DIC) can drive the display device 1. The driver IC (DIC) can process data signals used for displaying images and various drive signals used for processing these data signals. The driver IC (DIC) may include a strobe driver IC, a data driver IC, etc.

[0118] Although not shown, the display device 1 may also include a low-dropout (LDO) regulator and a level shifter. The low-dropout (LDO) regulator and the level shifter may be disposed on the main substrate MB, but are not limited thereto.

[0119] The driver IC DIC can be electrically connected to a low-dropout (LDO) regulator and a level shifter, and can deliver the signals generated in the LDO regulator and the level shifter to the gating driver GIP.

[0120] A gating line GL can extend from the gating driver GIP and can be connected to a sub-pixel SP (or pixel). The gating line GL can electrically connect the gating driver GIP and the sub-pixel SP (or pixel) to each other. The gating line GL can apply a gating signal from the gating driver GIP to each sub-pixel SP (or pixel).

[0121] The strobe control line GCL can be set in the non-display area NDA. The strobe control line GCL can extend from the pad area PA to the strobe driver GIP and can be electrically connected to the strobe driver GIP.

[0122] Multiple strobe control lines (GCLs) can be configured, and multiple strobe control lines (GCLs) can provide at least two different signals.

[0123] The strobe control line GCL applies a strobe control signal to the strobe driver GIP. This strobe control signal can be transmitted from the main board MB or the driver IC DIC. The strobe control line GCL also electrically connects the strobe driver GIP to the main board MB or the driver IC DIC.

[0124] The gate control line GCL can be electrically connected to one of the flexible film COFs located at both ends of a plurality of flexible film COFs connected to the display panel 100 along the second non-display area NDA2. The gate control line GCL can be located at the outermost position among the plurality of lines connected to a flexible film COF, but is not limited thereto.

[0125] The data line DL can extend from the pad area PA and can connect to the sub-pixel SP (or pixel) in the display area DA. The data line DL can apply data signals to each sub-pixel SP (or pixel). The data signals can be applied from the main substrate MB or the driver IC DIC. The data line DL can electrically connect the sub-pixel SP (or pixel) to the main substrate MB or the driver IC DIC.

[0126] The data cable DL may include a first data cable DL1 and a second data cable DL2. The data cable DL may be connected to data pads DP1 and DP2. The first data cable DL1 can contact the first data pad DP1 through a first data contact hole CNT1 to be electrically connected to the first data pad DP1. The second data cable DL2 can contact the second data pad DP2 through a second data contact hole CNT2 to be electrically connected to the second data pad DP2.

[0127] The low-level voltage line VSSL can be positioned within the non-display area NDA in a manner that surrounds the display area DA. The low-level voltage line VSSL can be positioned within the non-display area NDA, with the display area DA and the gating driver GIP interposed between the non-display area NDA. In other words, the gating driver GIP can be positioned between the display area DA and the low-level voltage line VSSL.

[0128] The low-potential voltage line VSSL can apply a low-potential voltage to the sub-pixel SP (or pixel). The low-potential voltage line VSSL is electrically connected to the cathode of the sub-pixel SP (or pixel) (reference). Figure 5 (153 in the middle), and can apply a low potential voltage.

[0129] The low-potential voltage line VSSL can be connected to the pad area PA. The low-potential voltage line VSSL can be physically connected to the low-potential voltage pad VSSP, and can also be electrically connected to the low-potential voltage pad VSSP. The low-potential voltage line VSSL and the low-potential voltage pad VSSP can be formed as a single unit, but are not limited to this.

[0130] A high-potential voltage line VDDL can be disposed in the non-display area NDA between the display area DA and the low-potential voltage line VSSL. The high-potential voltage line VDDL may further include a high-potential connection electrode (not shown). The high-potential connection electrode (not shown) may be disposed in a layer different from the layer on which the high-potential voltage line VDDL is disposed. For example, the high-potential connection electrode (not shown) may be disposed between the second insulating layer 104 and the third insulating layer 105. The high-potential connection electrode (not shown) may cross wiring disposed on the same layer as the layer on which the high-potential voltage line VDDL is disposed to connect the high-potential voltage line VDDL and the anode (reference). Figure 5 151) Electrical connection. The high-potential connection electrode (not shown) can be electrically connected to the anode (reference) across wiring disposed on the same layer as the high-potential voltage line VDDL. Figure 5 151 in the middle).

[0131] The high-potential voltage line VDDL can apply a high-potential voltage to the sub-pixel SP (or pixel). The high-potential voltage line VDDL is electrically connected to the anode (reference). Figure 5 (151 in the middle), and can apply a high potential voltage.

[0132] The high-potential voltage line VDDL can be connected to the pad area PA. The high-potential voltage line VDDL can be physically connected to the high-potential voltage pad VDDP, and can also be electrically connected to the high-potential voltage pad VDDP. The high-potential voltage line VDDL and the high-potential voltage pad VDDP can contact each other through the contact hole S_CNT.

[0133] However, the implementation is not limited to this, and the high-potential voltage line VDDL can be disposed on the same layer as the high-potential voltage pad VDDP to be integrally formed. For example, the high-potential voltage line VDDL may include the same material as the high-potential voltage pad VDDP, and be formed by the same conductive layer as the conductive layer of the high-potential voltage pad VDDP, and can be formed together by the same mask process.

[0134] In this case, a high-potential connection electrode (not shown) may be further included, disposed on a different layer than the high-potential voltage pad VDDP. The high-potential connection electrode (not shown) may cross a trace disposed on the same layer as the high-potential voltage line VDDL, connecting the high-potential voltage line VDDL and the anode (reference). Figure 5 151) Electrical connection.

[0135] The display device 1 may further include a barrier section DMP. The barrier section DMP may be disposed in a non-display area NDA. The barrier section DMP may be configured around the display area DA, but is not limited thereto. The barrier section DMP may be configured such that at least some of it overlaps with the low-potential voltage line VSSL. The barrier section DMP may be disposed in a second non-display area NDA between the display area DA and the pad area PA.

[0136] Figure 4 This is a plan view showing the pixel configuration of a display device according to an embodiment. Figure 4 The plan view shows a portion of the display area DA, which contains pixels PX, in a magnified form.

[0137] Reference Figure 4 The display panel 100 may include a first pixel group PXG1 and a second pixel group PXG2.

[0138] Each of the first pixel group PXG1 and the second pixel group PXG2 can be repeatedly set along the first direction DR1. The first pixel group PXG1 and the second pixel group PXG2 can be alternately and repeatedly set along the second direction DR2.

[0139] Subpixel SP can include (1_1) subpixel SP1_1, (1_2) subpixel SP1_2, (1_3) subpixel SP1_3, (1_4) subpixel SP1_4, (2_1) subpixel SP2_1, (2_2) subpixel SP2_2 and (2_3) subpixel SP2_3.

[0140] The first pixel group PXG1 may include the (1_1)th sub-pixel SP1_1, the (1_2)th sub-pixel SP1_2, the (1_3)th sub-pixel SP1_3, and the (1_4)th sub-pixel SP1_4. The (1_1)th sub-pixel SP1_1, the (1_2)th sub-pixel SP1_2, the (1_3)th sub-pixel SP1_3, and the (1_4)th sub-pixel SP1_4 are arranged parallel to each other along a first direction.

[0141] Sub-pixel SP1_1 (1_1) can emit red R light, sub-pixel SP1_2 (1_2) can emit green G light, sub-pixel SP1_3 (1_3) can emit blue B light, and sub-pixel SP1_4 (1_4) can emit red R light.

[0142] Each of the (1_1) sub-pixel SP1_1, (1_2) sub-pixel SP1_2, (1_3) sub-pixel SP1_3 and (1_4) sub-pixel SP1_4 may include light-emitting regions EA1_1, EA1_2, EA1_3 and EA1_4, and non-light-emitting regions NEA1_1, NEA1_2, NEA1_3 and NEA1_4 disposed around the light-emitting regions EA1_1, EA1_2, EA1_3 and EA1_4.

[0143] The (1_1) sub-pixel SP1_1 may include the (1_1) luminous region EA1_1 and the (1_1) non-luminous region NEA1_1 disposed around the (1_1) luminous region EA1_1.

[0144] The (1_2) sub-pixel SP1_2 may include the (1_2) luminous region EA1_2 and the (1_2) non-luminous region NEA1_2 disposed around the (1_2) luminous region EA1_2.

[0145] The (1_3) sub-pixel SP1_3 may include the (1_3) luminous region EA1_3 and the (1_3) non-luminous region NEA1_3 disposed around the (1_3) luminous region EA1_3.

[0146] The (1_4) sub-pixel SP1_4 may include the (1_4) luminous region EA1_4 and the (1_4) non-luminous region NEA1_4 disposed around the (1_4) luminous region EA1_1.

[0147] The second pixel group PXG2 may include a (2_1) sub-pixel SP2_1, a (2_2) sub-pixel SP2_2, and a (2_3) sub-pixel SP2_3. The (2_1) sub-pixel SP2_1, the (2_2) sub-pixel SP2_2, and the (2_3) sub-pixel SP2_3 may be arranged parallel to each other along the second direction.

[0148] Sub-pixel SP2_1 (2_1) can emit blue B light, sub-pixel SP2_2 (2_2) can emit red R light, and sub-pixel SP2_3 (2_3) can emit green G light.

[0149] Each of the (2_1) sub-pixel SP2_1, the (2_2) sub-pixel SP2_2, and the (2_3) sub-pixel SP2_3 may include light-emitting regions EA2_1, EA2_2, and EA2_3 and non-light-emitting regions NEA2_1, NEA2_2, and NEA2_3 disposed around the light-emitting regions EA2_1, EA2_2, and EA2_3.

[0150] The (2_1) sub-pixel SP2_1 may include the (2_1) luminous region EA2_1 and the (2_1) non-luminous region NEA2_1 disposed around the (2_1) luminous region EA2_1.

[0151] The (2_2) sub-pixel SP2_2 may include the (2_2) luminous region A2_2 and the (2_2) non-luminous region A2_2 disposed around the (2_2) luminous region A2_2.

[0152] The (2_3) sub-pixel SP2_1 may include the (2_3) luminous region A2_3 and the (2_3) non-luminous region A2_3 disposed around the (2_3) luminous region A2_3.

[0153] When viewed in a planar view, the subpixel may not be positioned below the (1_1) subpixel SP1_1 (on the other side of the second direction DR2).

[0154] When viewed in a planar view, the (2_1) sub-pixel SP2_1 can be positioned below the (1_2) sub-pixel SP1_2 (on the other side of the second direction DR2).

[0155] When viewed in a planar view, the (2_2)th sub-pixel SP2_2 can be positioned below the (1_3)th sub-pixel SP1_3 (on the other side of the second direction DR2).

[0156] When viewed in a planar view, the (2_3) sub-pixel SP2_3 can be positioned below the (1_4) sub-pixel SP1_4 (on the other side of the second direction DR2).

[0157] Figure 1 The sub-pixel shown (reference) Figure 1 In this context, SP can refer to one of the following: (1_1) sub-pixel SP1_1, (1_2) sub-pixel SP1_2, (1_3) sub-pixel SP1_3, (1_4) sub-pixel SP1_4, (2_1) sub-pixel SP2_1, (2_2) sub-pixel SP2_2, and (2_3) sub-pixel SP2_3.

[0158] Microlenses ML can be set on sub-pixels (1_1), (1_2), (1_3), (1_4), (1_1), (2_2), and (2_3) respectively. Microlenses ML can also be set on each sub-pixel SP (SP1_1, SP1_2, SP1_3, SP1_4, SP2_1, SP2_2, SP2_3).

[0159] The illustration shows one microlens ML on each subpixel SP, but is not limited to this. For example, depending on the design of each subpixel SP, the microlens ML on each subpixel SP can be set in two or more. When there are multiple openings (light-emitting areas EA) configured in a subpixel SP, a microlens ML can be set in each opening, or multiple microlenses ML can be set in one opening.

[0160] Each sub-pixel SP (SP1_1, SP1_2, SP1_3, SP1_4, SP2_1, SP2_2, SP2_3) may include a light-emitting area (EA1_1, EA1_2, EA1_3, EA1_4, EA2_1, EA2_2, EA2_3) and a non-light-emitting area NEA (NEA1_1, NEA1_2, NEA1_3, NEA1_4, NEA2_1, NEA2_2, NEA2_3) set around the light-emitting area EA.

[0161] In the following text, reference will be made to Figure 5 The cross-sectional structure of the display area DA of the display panel 100, including sub-pixels SP (SP1_1, SP1_2, SP1_3, SP1_4, SP2_1, SP2_2, SP2_3), is described.

[0162] Figure 5 It is along Figure 4 The cross-sectional view taken by the V-V' line in the diagram. Figure 6 From and Figure 5 Cross-sectional views taken from different angles.

[0163] Reference Figures 4 to 6 The display panel 100 may include a substrate 101, a thin-film transistor 120, a storage electrode 140, a light-emitting unit 150, a packaging unit 170, and a touch unit 180. However, the embodiments disclosed herein are not limited thereto.

[0164] The substrate 101 may provide space on its upper portion in which various components can be disposed. The substrate 101 may correspond to the planar shape of the display panel 100. In other words, the substrate 101 may include a notch NCP. The substrate 101 may substantially and equally include the display area DA and the non-display area NDA of the display panel 100.

[0165] The substrate 101 may include one or more plastic materials, but is not limited thereto, and may include glass materials.

[0166] The substrate 101 may be a multi-substrate substrate, including multiple substrates such as a first substrate 101a, a second substrate 101b, and a third substrate 103c. Each substrate includes a plastic material, such as polyimide, but the embodiments disclosed herein are not limited thereto. For example, the substrate 101 may be a single substrate consisting of a single layer.

[0167] Substrate 101 may include a rigid substrate. However, substrate 101 is not limited to this, and substrate 101 may include a flexible substrate.

[0168] A buffer layer 102 may be disposed on the substrate 101. The buffer layer 102 may minimize or delay the dispersion of moisture or oxygen that has permeated into the substrate 101. The buffer layer 102 may be formed by alternating deposition of silicon oxide (SiOx) or silicon nitride (SiNx) at least once, and embodiments of this disclosure are not limited thereto.

[0169] In this disclosure, a buffer layer 102 is shown to be formed as a multilayer consisting of three layers; however, the number of layers forming the buffer layer 102 is not limited thereto, and the buffer layer 102 may be formed as a single layer.

[0170] A first light-shielding layer 126 may be disposed on the buffer layer 102. The first light-shielding layer 126 can prevent or reduce light transmission through the semiconductor layer 123 of the thin-film transistor 120. For example, the semiconductor layer 123 may be disposed overlapping the first light-shielding layer 126. The first light-shielding layer 126 may be formed as a single-layer structure or as a multilayer structure formed of one of molybdenum (Mo), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof, but the embodiments of this disclosure are not limited thereto.

[0171] A first insulating layer 103 may be disposed on the first light-shielding layer 126. The first insulating layer 103 can prevent electrical short circuits between the components of the thin-film transistor 120 and the first light-shielding layer 126. The first insulating layer 103 may be formed of the same material as the buffer layer 102; however, embodiments of the present disclosure are not limited thereto. For example, the first insulating layer 103 may be formed of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx); however, embodiments of the present disclosure are not limited thereto.

[0172] The thin-film transistor 120 may be disposed on the first insulating layer 103. The thin-film transistor 120 may include a source 121, a gate 122, a semiconductor layer 123, and a drain 124.

[0173] Semiconductor layer 123 may be disposed on first insulating layer 103. Semiconductor layer 123 may include metal oxide semiconductor such as IGZO (indium gallium zinc oxide) or silicon-based semiconductor material such as amorphous silicon or polycrystalline silicon; however, embodiments of this disclosure are not limited thereto. Semiconductor layer 123 may include source region, drain region, and channel region between source region and drain region.

[0174] Polycrystalline semiconductor layers can have better mobility, consume less power, and have superior reliability than amorphous semiconductor and oxide semiconductor layers. Therefore, driving transistors can be formed from polycrystalline semiconductor layers; however, embodiments of this disclosure are not limited thereto.

[0175] The second insulating layer 104 may be disposed on the semiconductor layer 123. The second insulating layer 104 may be formed of the same material as the first insulating layer 103, however, embodiments of the present disclosure are not limited thereto. The second insulating layer 104 can prevent electrical short circuits between another component of the thin-film transistor 120 and the semiconductor layer 123.

[0176] Gate 122 may be disposed on the second insulating layer 104. Gate 122 may be disposed on the second insulating layer 104 to overlap with the channel region of semiconductor layer 123. Gate 122 may be formed as a single-layer structure or a multilayer structure formed of one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd) and / or alloys thereof, but embodiments of the present disclosure are not limited thereto. Gate 122 may be disposed together with a gate line, but embodiments of the present disclosure are not limited thereto.

[0177] The third insulating layer 105 may be disposed on the gate 122. The third insulating layer 105 may be formed of the same material as the first insulating layer 103 or the second insulating layer 104, but the embodiments of this disclosure are not limited thereto.

[0178] The storage electrode 140 may be spaced apart from the thin-film transistor 120. The storage electrode 140 may include a first storage electrode 141 and a second storage electrode 142.

[0179] The first storage electrode 141 may be formed of the same material as the gate 122 and disposed on the same layer as the gate 122, but the embodiments of this disclosure are not limited thereto.

[0180] A second storage electrode 142 may be disposed on the first storage electrode 141. The second storage electrode 142 may be disposed on the third insulating layer 105, and a capacitor may be formed if the third insulating layer 105 between the first storage electrode 141 and the second storage electrode 142 serves as a dielectric. The second storage electrode 142 may be formed of the same material as the first storage electrode 141, but embodiments of this disclosure are not limited thereto.

[0181] A fourth insulating layer 106 may be disposed on the second storage electrode 142. The fourth insulating layer 106 may be formed of the same material as the first insulating layer 103, the second insulating layer 104 and the third insulating layer 105, but the embodiments of this disclosure are not limited thereto.

[0182] The source 121 and drain 124 can be disposed on the fourth insulating layer 106.

[0183] The source 121 and drain 124 can be electrically connected to the semiconductor layer 123 through contact holes. The source 121 and drain 124 can be formed of a metallic material. For example, the source 121 and drain 124 can be formed as a single-layer structure or a multi-layer structure of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but the embodiments of this disclosure are not limited thereto.

[0184] The source 121 and drain 124 can be disposed together with the data line. For example, the data line can be formed of the same material as the source 121 and drain 124, and can be formed on the same layer as the layers of the source 121 and drain 124, but the embodiments of this disclosure are not limited thereto.

[0185] The thin-film transistor 120 may be a driving transistor, although it is not shown. The display panel 100 may also include a switching transistor, but the embodiments of this disclosure are not limited thereto.

[0186] The first protective layer 111 can be disposed on the source 121 and the drain 124.

[0187] The first protective layer 111 can planarize the upper part of the thin-film transistor 120 and protect the thin-film transistor 120. The first protective layer 111 can be formed of an organic material. For example, the first protective layer 111 can be formed of an organic material including acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin, but the embodiments of this disclosure are not limited thereto.

[0188] The second protective layer 112 may be disposed on the first protective layer 111. The second protective layer 112 may be formed of the same material as the first protective layer 111, but the embodiments disclosed herein are not limited thereto.

[0189] The connecting electrode 145 can be disposed between the first protective layer 111 and the second protective layer 112.

[0190] The connection electrode 145 can electrically connect the thin-film transistor 120 and the light-emitting unit 150. The connection electrode 145 can be formed of the same material as the source electrode 121 and the drain electrode 124, but the embodiments of this disclosure are not limited thereto.

[0191] The connecting electrode 145 can be electrically connected to the drain electrode 124 by contacting the drain electrode 124 through a contact hole formed on the first protective layer 111.

[0192] The connecting electrode 145 may be formed in a single-layer structure or in a multilayer structure formed of one of molybdenum (Mi), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but the embodiments of the present invention are not limited thereto.

[0193] The light-emitting unit 150 may be formed on the second protective layer 112. The light-emitting unit 150 may include an anode 151, an organic layer 152, and a cathode 153.

[0194] The anode 151 may be disposed on the second protective layer 112. The anode 151 may be electrically connected to the thin-film transistor 120 through contact holes formed on the first protective layer 111 and the second protective layer 112.

[0195] The anode 151 may be a reflective electrode that reflects light, but the embodiments of this disclosure are not limited thereto. The anode 151 may include a metallic material with high reflectivity, such as an APC alloy (Ag / Pd / Cu), a deposited structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), and a deposited structure of aluminum (Al) and ITO (ITO / Al / ITO), and may be formed in a single-layer or multi-layer structure, but the embodiments of this disclosure are not limited thereto.

[0196] An organic layer 152 may be disposed on the anode 151. The organic layer 152 may include one or more light-emitting structures (or light-emitting elements or components) deposited on the anode 151 in a sequence of hole transport layers and electron transport layers, or in reverse order. For example, the hole transport layer may include a hole transport layer, a hole injection layer, an electron blocking layer, a P-type charge generation layer, etc., but embodiments of this disclosure are not limited thereto. For example, the electron transport layer may include an electron transport layer, an electron injection layer, a hole blocking layer, an N-type charge generation layer, etc., but embodiments of this disclosure are not limited thereto.

[0197] The organic layer 152 can be an organic light-emitting layer, an inorganic light-emitting layer, a quantum dot light-emitting layer, a micro light-emitting diode, a micro-mini light-emitting diode, etc., but the embodiments of this disclosure are not limited to these. For example, the organic layer 152 of the display panel 100 according to the embodiments of this disclosure may include an organic light-emitting layer. The organic layer 152 may include a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer, but the embodiments of this disclosure are not limited to these. The organic layer 152 may also include a white light-emitting layer, but the embodiments of this disclosure are not limited to these.

[0198] The cathode 153 may be disposed on the organic layer 152. The cathode 153 may be a transparent electrode that transmits light, but the embodiments of this disclosure are not limited thereto. For example, the cathode 153 may include a transparent conductive material or metal, such as ITO (indium tin oxide) or IZO (indium zinc oxide), through which visible light is transmitted, but the embodiments of this disclosure are not limited thereto.

[0199] A capping layer 156 may be further disposed on the cathode 153. The capping layer 156 can minimize or reduce damage to the cathode 153 of the light-emitting diode EL and the organic layer 152 beneath the cathode 153 caused by external light sources. The capping layer 156 may be formed as an organic layer or an inorganic layer.

[0200] The capping layer 156 can be provided using a material such as lithium fluoride (LiF) as an inorganic layer, and may also include an organic layer, but the embodiments disclosed herein are not limited thereto. For example, the capping layer 156 can be formed in a deposition structure of inorganic and organic layers, wherein the thicknesses of the organic and inorganic layers can be different from each other. In this case, the thickness of the organic layer can be greater than the thickness of the inorganic layer. As another example, the capping layer 156 can have two or more layers formed by depositing materials with different refractive indices. This can improve the luminous efficiency of the display panel 100.

[0201] A dam 154 can be provided to expose the anode 151. The dam 154 can define an opening (or a light-emitting region EA) of the sub-pixel SP and can be configured to cover the edge of the anode 151. An organic layer 152 can be disposed within the opening of the sub-pixel SP. In other words, the organic layer 152 can be disposed on the anode 151 exposed by the dam 154.

[0202] The dam portion 154 can be formed of an organic material, such as a material including black pigment, benzocyclobutene resin, polyimide resin, acrylic resin, or photosensitive polymer, but the embodiments disclosed herein are not limited thereto. When the dam portion 154 is formed of a material including black pigment, black dye, etc., the dam portion 154 can be a black dam portion. When the dam portion 154 is formed of a material including black pigment, black dye, etc., the dam portion 154 can block light from the outside or light reflected from the outside, thereby further improving the brightness of the display device.

[0203] The spacer 155 may be further provided on the embankment 154. The spacer 155 may be formed of the same material as the embankment 154, but the embodiments of this disclosure are not limited thereto. The spacer 155 can suppress or prevent marks or scratches on the display panel 100 by preventing or reducing mask sagging during the masking process.

[0204] The encapsulation unit 170 may be disposed on the embankment 154 or the light-emitting unit 150. The encapsulation unit 170 may include one or more insulating layers. For example, the encapsulation unit 170 may include a first inorganic encapsulation layer 171, a first organic encapsulation layer 172 disposed on the first inorganic encapsulation layer 171, and a second inorganic encapsulation layer 173 disposed on the organic encapsulation layer 172. The encapsulation unit 170 may include one or more inorganic material layers or one or more organic material layers. For example, the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173 may include inorganic materials, and the organic encapsulation layer 172 may include organic materials, but the embodiments of this disclosure are not limited thereto.

[0205] Even if the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173 are configured to extend to the end of the non-display area NDA, the organic encapsulation layer 172 can terminate inside the barrier portion DMP. In other words, the organic encapsulation layer 172 can not extend beyond the barrier portion DMP and can be disposed inside the area surrounded by the barrier portion DMP.

[0206] The touch unit 180 may be disposed on the packaging unit 170. The touch unit 180 may include a touch buffer layer 181, a first touch electrode 182, a first touch insulating layer 183, a black background BM, a second touch insulating layer 184, a second touch electrode 185, and a third touch insulating layer 186.

[0207] A touch buffer layer 181 may be disposed on the encapsulation unit 170. For example, the touch buffer layer 181 may be disposed on the second inorganic encapsulation layer 173. The touch buffer layer 181 may be formed of the same material as the buffer layer 102, but embodiments of this disclosure are not limited thereto.

[0208] The first touch electrode 182 can be disposed on the touch buffer layer 181.

[0209] The first touch insulating layer 183 may be disposed on the first touch electrode 182. The first touch insulating layer 183 may be formed of silicon oxide (SiOx) or silicon nitride (SiNx), or in the form of a multilayer structure of silicon oxide (SiOx) and silicon nitride (SiNx), but the embodiments disclosed herein are not limited thereto.

[0210] The black background BM can be disposed on the first touch insulating layer 183. The black background BM can include a material that can absorb light. The black background BM can include, but is not limited to, black pigment or black dye. The black background BM can prevent or reduce light leakage defects that may occur between sub-pixels SP.

[0211] The second touch insulating layer 184 may be disposed on the black base BM. The second touch insulating layer 184 may include an organic insulating material. For example, the second touch insulating layer 184 may be formed of acrylic acid, benzocyclobutene (BCB), polyimide (PI) or polyamide (PA), but is not limited thereto.

[0212] The second touch electrode 185 may be disposed on the second touch insulating layer 184. The second touch electrode 185 may include a first a touch electrode 185a extending in a first direction DR1 and a first b touch electrode 185b extending in a second direction DR2 different from the first direction.

[0213] The first touch electrode 182 can be electrically connected to the first a touch electrode 185a through a contact hole formed on the second touch insulating layer 184. For example, the first a touch electrode 185a and the first touch electrode 182 can extend in the first direction DR1.

[0214] The first touch electrode 182 and the second touch electrode 185 may include metallic materials. For example, the first touch electrode 182 and the second touch electrode 185 may be formed of titanium (Ti), nickel (Ni), aluminum (Al) or alloys thereof, and may be formed in a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but the embodiments of this disclosure are not limited thereto.

[0215] One of the first touch electrode 182 and the second touch electrode 185 may include a touch sensing function, and the other of the first touch electrode 182 and the second touch electrode 185 may include a touch driving function, but is not limited thereto.

[0216] The third touch insulating layer 186 may be disposed on the second touch electrode 185. The third touch insulating layer 186 may include, but is not limited to, the same material as the first touch insulating layer 183.

[0217] The microlens ML can be disposed on the third touch insulating layer 186. The microlens ML can be hemispherical or semi-circular, but is not limited to these. The shape of the microlens ML can vary depending on the size and shape of the light-emitting region EA.

[0218] By configuring microlenses (ML), a wide viewing angle can be ensured, brightness can be improved, and light leakage and reflection can be blocked, thereby preventing or reducing light leakage.

[0219] The center of the microlens ML may not be aligned with the center of the light-emitting region EA corresponding to the microlens ML. However, some components of the light-emitting unit 150 may be tilted, and accordingly, the light emitted from the light-emitting region EA may propagate toward the microlens ML.

[0220] A lens protective layer 190 may be disposed on the microlens ML. The lens protective layer 190 may include, but is not limited to, an organic insulating material. The lens protective layer 190 protects the microlens ML by covering it.

[0221] The refractive index of the lens protective layer 190 can be less than that of the microlens ML. Therefore, due to the difference between the refractive index of the microlens ML and the refractive index of the lens protective layer 190, the reflection of light passing through the microlens ML in the direction of the substrate 101 can be prevented or reduced.

[0222] In the region where the light-emitting unit 150 is disposed, the second protective layer 112 may be formed such that some regions of the upper surface of the second protective layer 112 are inclined. At least some regions of the light-emitting unit 150 may be disposed on the second protective layer 112, and at least some regions of the second protective layer 112 are inclined. Therefore, each of the anode 151 and the organic layer 152 may be inclined in at least some regions. Each of the anode 151 and the organic layer 152 may be inclined toward the microlens ML in at least some regions.

[0223] More specifically, each of the anode 151 and the organic layer 152 may be disposed on the second protective layer 112, at least some regions of the second protective layer 112 being inclined. Each of the anode 151 and the organic layer 152 may be disposed on the second protective layer 112 which is inclined over the entire region, but is not limited thereto.

[0224] The second protective layer 112 may include inclined surfaces in some areas. For example, the inclined surfaces of the second protective layer 112 may be formed by a slot mask process, but are not limited thereto.

[0225] The anode 151 and organic layer 152 disposed on the inclined second protective layer 112 can be configured to be inclined (tilted) corresponding to the inclined second protective layer 112. Therefore, some areas of the cathode 153 disposed on the organic layer 152 can be inclined.

[0226] For example, the anode 151 and the organic layer 152 may be tilted relative to the thickness direction (third direction DR3) of the display panel 100 in the (1_1) light-emitting region EA1_1, the (2_1) light-emitting region EA2_1 and their surroundings. That is, the direction in which the upper surface of the anode 151 and the upper surface of the organic layer 152 face may be tilted relative to the thickness direction (third direction DR3) of the display panel 100.

[0227] In the (1_1) luminescent region EA1_1, the (2_1) luminescent region EA2_1 and their surroundings, the tilt directions of the anode 151 and the organic layer 152 can be different.

[0228] exist Figure 5 In the above, the anode 151 and organic layer 152 surrounding the (1_1) luminescent region EA1_1 of the (1_1) sub-pixel SP1_1 and the (2_1) luminescent region EA2_1 of the (2_1) sub-pixel SP2_1 have been described, and all of its descriptions can be applied to each sub-pixel SP.

[0229] Therefore, the light emitted from each sub-pixel SP can be tilted relative to the thickness direction (third direction DR3) of the display panel 100. For a description, see [reference]. Figure 7 and Figure 8 The view in the middle.

[0230] Figure 7 This is a plan view of the display panel according to the implementation method. Figure 8 It is along Figure 7 The cross-sectional view taken from line VIII-VIII' in the diagram. Figure 7 and Figure 8 Each of them and Figure 4 and Figure 5 It is roughly the same, but it is a schematic diagram showing the paths of light L1 and L2 emitted from light-emitting unit 150.

[0231] refer to Figure 7 and Figure 8 The microlens ML and its corresponding luminescent region EA may be misaligned. More specifically, the center of the microlens ML and the center of the luminescent region EA may be misaligned.

[0232] The center EC1 of the (1_1) luminous region EA1_1 of the (1_1) sub-pixel SP1_1 and the center LC1 of the microlens ML set in the (1_1) sub-pixel SP1_1 may not be aligned. When viewed in a planar view, the center LC1 of the microlens ML can be misaligned from the center EC1 of the (1_1) luminous region EA1_1 to the other side of the first direction DR1 (the left side of the plane).

[0233] The description of the misalignment of sub-pixel (1_1) SP1_1 can be applied substantially equivalently to the remaining sub-pixels (SP1_1, SP1_3, and SP1_4) of the first pixel group PXG1. However, in each of the remaining sub-pixels (SP1_1, SP1_2, SP1_3, and SP1_4) of the first pixel group PXG1, the degree of misalignment between the microlens ML and the luminous region EA can differ from one another.

[0234] However, but not limited to, the direction of the misalignment between the center LC1 of the microlens ML and the center EC1 of the (1_1) luminescent region EA1_1 can vary according to the design.

[0235] The center EC2 of the luminous region EA2_1 of the (2_1) sub-pixel SP2_1 and the center LC2 of the microlens ML set in the (2_1) sub-pixel SP2_1 may not be aligned. When viewed in a planar view, the center LC2 of the microlens ML can be misaligned from the center EC2 of the luminous region EA2_1 of the (2_1) sub-pixel SP2_1 to one side of the first direction DR1 (the right side on the plane).

[0236] The description of the misalignment of sub-pixel (2_1) SP2_1 can be applied substantially equally to the remaining sub-pixels SP2_2 and SP2_3 of the second pixel group PXG2. However, in each of the sub-pixels SP2_1, SP2_2, and SP2_3 of the second pixel group PXG2, the degree of misalignment between the microlens ML and the luminous region EA can differ from one another.

[0237] However, but not limited to, the direction of the misalignment between the center LC2 of the microlens ML and the center EC2 of the (2_1) luminescent region EA2_1 can vary according to the design.

[0238] The opening (or light-emitting area EA) of the sub-pixel SP and the light-emitting unit 150 disposed around the opening can be tilted relative to the thickness direction (third direction DR3), and the light L1 and L2 emitted from the light-emitting unit 150 can travel in the direction tilted relative to the thickness direction (third direction DR3).

[0239] Because the microlens ML and the light-emitting region EA are misaligned, even if the light L1 and L2 emitted from the light-emitting unit 150 travel at an angle relative to the thickness direction (third direction DR3), each light L1 and L2 can travel toward the microlens ML.

[0240] Subpixels SP1_1, SP1_2, SP1_3, and SP1_4, located in the first pixel group PGX1, emit light L1 towards the left (the other side on the first direction DR1) when viewed in a planar view. Subpixels SP2_1, SP2_2, and SP2_3, located in the second pixel group PXG2, emit light L2 towards the right (one side on the first direction) when viewed in a planar view.

[0241] In other words, light L1 emitted from sub-pixels SP1_1, SP1_2, SP1_3, and SP1_4 of the first pixel group PXG1 can travel at an angle relative to the thickness direction (third direction DR3) towards the opposite side of the first direction DR1. Light L2 emitted from sub-pixels SP2_1, SP2_2, and SP2_3 of the second pixel group PXG2 can travel at an angle relative to the thickness direction (third direction DR3) towards the first direction DR1.

[0242] The direction and degree of misalignment between the microlens ML and the luminescent region EA can be changed according to the direction of light travel emitted from the sub-pixels SP of each pixel group PXG1 and PXG2.

[0243] When viewed in a plan view, the sub-pixels SP1_1, SP1_2, SP1_3, and SP1_4 set in the first pixel group PXG1 and the sub-pixels SP2_1, SP2_2, and SP2_3 set in the second pixel group PGX2 can emit light in each different direction. Therefore, it is possible to distinguish between the image displayed to the driver sitting in the driver's seat and the image displayed to the front passenger sitting in the front passenger seat, and each image can be controlled. Furthermore, the images displayed to the driver and the passenger can be different from each other.

[0244] Even if the display panel 100 includes a notch NCP, the portion of the mask covering the notch NCP during the deposition of the inorganic insulating layer can be omitted. By omitting the portion of the mask covering the notch NCP, marks or scratches on the display panel 100 that may be caused by the corresponding portion of the mask can be suppressed and prevented. Furthermore, defects can be prevented or reduced, the lifespan of the display device 1 can be improved, and the manufacturing energy consumed in manufacturing the display device 1 can be reduced.

[0245] By omitting the portion of the mask covering the notch NCP, at least one of the inorganic insulating layers disposed on the substrate 101 can extend to the end of the notch non-display area N_NDA surrounding the notch NCP. Here, the end of the notch non-display area N_NDA can refer to the end (or end point) of the substrate 101, and therefore to the end (or end point) of the inorganic layer disposed on the substrate 101.

[0246] For example, the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173 can be disposed on the substrate 101 by chemical vapor deposition (CVD), and if the portion of the mask covering the notch NCP is omitted, the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173 can extend around the notch NCP to the end of the notch non-display area N_NDA.

[0247] However, not limited thereto, at least one of the inorganic insulating layers disposed on the substrate 101 may extend to the end of the non-display area NDA in all regions of the non-display area NDA.

[0248] The cross-sectional structure of the non-display area NDA of the display device 1 will be described below. The same content provided in the description of the cross-sectional structure of the display area DA will be briefly explained or omitted.

[0249] Figure 9 It is along Figure 1 A cross-sectional view of line A-A'. Figure 9 The cross-sectional structure of the first non-display area NDA1 is shown.

[0250] Reference Figure 1 , Figure 5 and Figure 9 The display panel 100 may include a substrate 101, a buffer layer 102, a first insulating layer 103, a second insulating layer 104, a third insulating layer 105, a fourth insulating layer 106, a first protective layer 111, a second protective layer 112, a dam 154, an encapsulation unit 170, a touch buffer layer 181, a first touch insulating layer 183, and a third touch insulating layer 186, which are sequentially disposed in the first non-display area NDA1.

[0251] In the first non-display area NDA1, the display panel 100 may further include a gating control transistor G120, a low-potential voltage line VSSL, a barrier section DMP, and a crack-resistant pattern CSP.

[0252] The gating control transistor G120 has a configuration substantially the same as that of the transistor 120 of the sub-pixel SP, and can be formed together with the transistor 120 of the sub-pixel SP using the same process, but is not limited thereto.

[0253] The gating control transistor G120 may include a control source G121, a control gate G122, a control semiconductor layer G123, and a control drain G124.

[0254] The low-potential voltage line VSSL can be disposed on the fourth insulating layer 106 in the non-display area NDA. The low-potential voltage line VSSL can be disposed on the same layer as the source 121 and drain 124, and the low-potential voltage line VSSL can include the same material as the source 121 and drain 124, and the low-potential voltage line VSSL can be formed using the same mask and process as the source 121 and drain 124, but is not limited thereto.

[0255] Although not shown, the low-potential voltage line VSSL may also include an additional low-potential connection electrode for contacting the cathode 153. The low-potential connection electrode may be disposed on a different layer than the low-potential voltage line VSSL and may be made of a different material than, but is not limited to, the low-potential voltage line VSSL. Through the low-potential connection electrode, the low-potential voltage line VSSL can be electrically connected across other wiring disposed on the same layer to the anode 151 of the light-emitting unit 150 disposed in the display area DA.

[0256] The barrier section DMP may include a first barrier DM1 and a second barrier DM2. The first barrier DM1 and the second barrier DM2 may overlap with the low-potential voltage line VSSL. The first barrier DM1 may be located outside the second barrier DM2, but is not limited thereto.

[0257] The first barrier DM1 can be formed as a multi-layer structure. Each layer of the first barrier DM1 may include the same material as the second protective layer 112, the dam 154 and the spacer 155, and each layer of the first barrier DM1 may be formed using the same process with the second protective layer 112, the dam 154 and the spacer 155 using a mask, but is not limited thereto.

[0258] The second barrier DM2 can be formed as a multi-layer structure. Each layer of the second barrier DM2 may include the same material as the second protective layer 112 and the embankment 154, and each layer of the second barrier DM2 may be formed using the same process with the second protective layer 112 and the embankment 154 through a mask, but is not limited thereto.

[0259] The crack-resistant pattern CSP can be located at the outermost position of the non-display area NDA. Although not shown, multiple crack-resistant patterns can be provided, but are not limited to this. The crack-resistant pattern CSP can be defined as follows: at least one of the inorganic layers provided on the substrate 101 is recessed.

[0260] For example, the crack-resistant pattern CSP can be defined as follows: the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 are recessed, but it is not limited thereto. For example, at least one of the first protective layer 111, the second protective layer 112, and the dam 154 can be further provided around the crack-resistant pattern CSP. In this case, the crack-resistant pattern CSP can be defined by further recessing at least one of the first protective layer 111, the second protective layer 112, and the dam 154, and by recessing the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186. At least some of the inorganic layers disposed on the substrate 101 can extend to the end of the non-display area NDA. In other words, at least some of the inorganic layers disposed on the substrate 101 can extend to the end of the substrate 101.

[0261] The buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can extend to the end of the first non-display area NDA1.

[0262] In other words, in the first non-display area NDA1, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can extend to the end of the substrate 101.

[0263] In the first non-display area NDA1, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can substantially cover the entire area of ​​the substrate 101.

[0264] The ends (or sides) of each of the substrate 101, buffer layer 102, first insulating layer 103, second insulating layer 104, third insulating layer 105, fourth insulating layer 106, first inorganic encapsulation layer 171, second inorganic encapsulation layer 173, touch buffer layer 181, first touch insulating layer 183 and third touch insulating layer 186 may be aligned with each other, but are not limited thereto.

[0265] In the first non-display area NDA1, at least one of the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 may not extend to the end of the substrate 101, but is not limited thereto.

[0266] For example, in the first non-display area NDA1, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, and the fourth insulating layer 106 can extend to the end of the substrate 101; the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173 can extend to the barrier portion DMP; and the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can extend to a short distance before the barrier portion DMP. That is, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, and the fourth insulating layer 106 can be disposed between the barrier portion DMP and the crack-resistant pattern CSP, while the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can be not disposed between the barrier portion DMP and the crack-resistant pattern CSP.

[0267] Figure 10 It is along Figure 3 The cross-sectional view taken by the B-B' line in the diagram. Figure 11 It is along Figure 3 The cross-sectional view taken from the C-C' line.

[0268] Figure 10 and Figure 11 The cross-sectional structure of the second non-display area NDA2 is shown. Figure 10 and Figure 11 The cross-sectional structure of the notched non-display region N_NDA of the second non-display region NDA2 is shown; however, its description can be applied substantially equivalently to the extended non-display region E_NDA. However, the notched non-display region N_NDA and the extended non-display region E_NDA may have their own different cross-sectional structures, but are not limited thereto.

[0269] Reference Figure 3 , Figure 5 , Figure 10 and Figure 11In the notched non-display area N_NDA, the display panel 100 may include a substrate 101, a buffer layer 102, a first insulating layer 103, a second insulating layer 104, a third insulating layer 105, a fourth insulating layer 106, a first protective layer 111, a second protective layer 112, a dam 154, an encapsulation unit 170, a touch buffer layer 181, a first touch insulating layer 183, and a third touch insulating layer 186 arranged sequentially.

[0270] In the recessed non-display area N_NDA, the display panel 100 may also include a high-potential voltage line VDDL, a low-potential voltage line VSSL, a barrier portion DMP, multiple pads VSSP, VDDP and DP disposed in the pad area PA, data lines DL (DL1 and DL2) and a crack-resistant pattern CSP.

[0271] The high-potential voltage line VDDL can be disposed on the buffer layer 102 in the non-display area NDA and can be covered by the first insulating layer 103. The high-potential voltage line VDDL may include the same material as the first light-shielding layer 126 and can be formed using the same process with the first light-shielding layer 126 through a mask, but is not limited thereto.

[0272] Although not shown, the high-potential voltage pad VDDP may be disposed on the same layer as the source 121 and drain 124, may include the same material as the source 121 and drain 124, and may be formed with the source 121 and drain 124 using a mask through the same process, but is not limited thereto.

[0273] In this case, the high-potential voltage pad VDDP can be electrically connected to the high-potential voltage line VDDL by contacting the contact hole S_CNT that exposes the high-potential voltage line VDDL.

[0274] The high-potential voltage line VDDL may further include a high-potential connection electrode (not shown). The high-potential connection electrode (not shown) may be disposed on a layer different from the layer of the high-potential voltage line VDDL. For example, the high-potential connection electrode (not shown) may be disposed between the second insulating layer 104 and the third insulating layer 105. The high-potential connection electrode (not shown) may electrically connect the high-potential voltage line VDDL and the anode 151 across wiring disposed on the same layer as the high-potential voltage line VDDL.

[0275] When the high-potential voltage line VDDL is formed on the same layer as the high-potential voltage pad VDDP and is integrally formed with the high-potential voltage pad VDDP, the high-potential voltage line VDDL may further include a high-potential connection electrode (not shown). The high-potential connection electrode (not shown) may electrically connect the high-potential voltage line VDDL and the anode 151 across wiring disposed on the same layer as the high-potential voltage line VDDL.

[0276] The first data pad DP1 and the second data pad DP2 can be disposed on the fourth insulating layer 106. The first data pad DP1 and the second data pad DP2 can be disposed on the same layer as the source 121 and the drain 124, and can include the same material as the source 121 and the drain 124, and can be formed using the same mask and the same process as the source 121 and the drain 124, but are not limited thereto.

[0277] The first data line DL1 may be disposed on the second insulating layer 104 in the non-display area NDA and may be covered by the third insulating layer 105. The first data line DL1 may include the same material as the gate 122 and may be formed together with the gate 122 using a mask through the same process, but is not limited thereto.

[0278] The display panel 100 may also include a first data connection line (not shown). The first data connection line (not shown) may be disposed on a different layer than the first data line DL1, and the first data line DL1 may be electrically connected to the thin-film transistor 120 of the display area DA.

[0279] The second data line DL2 may be disposed on the third insulating layer 105 in the non-display area NDA and may be covered by the fourth insulating layer 106. The second data line DL2 may include the same material as the second storage electrode 142 and may be formed together with the second storage electrode 142 using a mask through the same process, but is not limited thereto.

[0280] The display panel 100 may also include a first data connection line (not shown). The first data connection line (not shown) may be disposed on a different layer than the first data line DL1, and the first data line DL1 may be electrically connected to the thin-film transistor 120 of the display area DA.

[0281] The first data line DL1 can be electrically connected to the first data pad DP1 by contacting the first data pad DP1 through the first data contact hole CNT1. The second data line DL2 can be electrically connected to the second data pad DP2 by contacting the second data pad DP2 through the second data contact hole CNT2.

[0282] The crack-resistant pattern CSP can be set outside the pad area PA. The crack-resistant pattern CSP can be set between the ends of the pad area PA and the second non-display area NDA2.

[0283] At least some of the inorganic layers disposed on the substrate 101 can extend to the end of the second non-display area NDA2. In other words, at least some of the inorganic layers disposed on the notched non-display area N_NDA and the extended non-display area E_NDA on the substrate 101 can extend to the end of the substrate 101.

[0284] In the notched non-display area N_NDA, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can extend to the end of the substrate 101.

[0285] In the notched non-display area N_NDA, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can substantially cover the entire area of ​​the substrate 101 except for the pad area PA.

[0286] The ends (or side surfaces) of each of the substrate 101, buffer layer 102, first insulating layer 103, second insulating layer 104, third insulating layer 105, fourth insulating layer 106, first inorganic encapsulation layer 171, second inorganic encapsulation layer 173, touch buffer layer 181, first touch insulating layer 183 and third touch insulating layer 186 may be aligned with each other, but are not limited thereto.

[0287] However, multiple pads VSSP, VDDP, and DP may not be covered by multiple inorganic layers. Multiple inorganic layers disposed on the fourth insulating layer 106 may expose multiple pads VSSP, VDDP, and DP. Multiple inorganic layers disposed on the fourth insulating layer 106 may not be disposed within the pad area PA.

[0288] For example, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can be disposed at the ends of the substrate 101 in the notched non-display area N_NDA, but may not be disposed in the pad area PA. Therefore, the plurality of pads VSSP, VDDP, and DP disposed on the fourth insulating layer 106 can be exposed and can be electrically connected to the flexible film COF when the display panel 100 is attached to the flexible film COF.

[0289] However, in the extended non-display area E_NDA, at least one of the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 may not extend to the end of the substrate 101, but is not limited thereto.

[0290] For example, in the extended non-display area E_NDA, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, and the fourth insulating layer 106 can extend to the end of the substrate 101; the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173 can extend to the barrier portion DMP; and the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can extend to a short distance before the barrier portion DMP. That is, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, and the fourth insulating layer 106 can be disposed between the barrier portion DMP and the crack-resistant pattern CSP, while the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 may not be disposed between the barrier portion DMP and the crack-resistant pattern CSP.

[0291] Figure 12 This is a schematic diagram illustrating one step of a method for manufacturing a display device according to an embodiment.

[0292] Reference Figures 10 to 12 During the deposition of inorganic layers on the substrate 101, including the notched NCP, the protrusions of the mask M used to cover the notched NCP can be omitted. Therefore, the area around the notched NCP on the substrate 101 can be left open instead of being covered by the mask M.

[0293] Since the protrusions of the mask M are omitted, defects such as marks and scratches that may occur due to the protrusions of the mask M can be suppressed or prevented. In addition, defects in the display device 1 can be prevented or reduced, the lifespan of the display device 1 can be increased, and the manufacturing energy consumed in manufacturing the display device 1 can be reduced.

[0294] In other words, since the substrate 101 and the display panel 100 include the notch NCP, improved aesthetics and convenience can be provided to the user. During the manufacturing process of the display panel, a portion (protrusion) of the mask M used to cover the notch NCP can be omitted, thus suppressing or preventing marks and scratches on the display panel. This improves the reliability of the display device 1.

[0295] Furthermore, since a portion (protrusion) of the mask M used to cover the notch NCP is omitted, in the notch non-display area N-NDA, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can extend to the end of the substrate 101.

[0296] exist Figure 12 In the diagram, the mask M is shown not to overlap with the substrate 101, but this is not a limitation; the mask M may be configured to overlap with a portion of the substrate 101. For example, the mask M may overlap with the edge of the substrate 101 in the remaining area except for the notch NCP.

[0297] Other embodiments of this disclosure will now be described. Among the components included in these other embodiments, those referenced are... Figures 1 to 12 Components that are substantially the same as those described will be given the same reference numerals, and redundant components may be omitted or described briefly.

[0298] Figure 13 This is a plan view of a display device according to another embodiment. Figure 14 yes Figure 13 A magnified view of the Q2 region. Figure 15 It is along Figure 14 The cross-sectional view taken by the D-D' line in the diagram.

[0299] Figure 14 This is a diagram of the display device 2 according to another embodiment, in which the flexible film COF, main substrate MB, and driver IC DIC are omitted in the Q2 region.

[0300] Reference Figures 13 to 15 In the display device 2 according to this disclosure, a separate gating driver GIP may not be provided in the non-display area NDA (see reference). Figure 1 ), and set the pixel gating driver GIA in the display area DA.

[0301] Multiple pixel gating drivers (GIAs) can be configured, and each pixel gating driver (GIA) can be connected to multiple sub-pixels (SPs). Pixel gating drivers (GIAs) can be configured on adjacent sub-pixels (SPs).

[0302] For example, the pixel gating driver GIA can be positioned between adjacent subpixels SP along the first direction DR1. The subpixels SP and the pixel gating driver GIA can be repeatedly and alternately positioned along the first direction DR1. The subpixels SP can be repeatedly and continuously positioned along the second direction DR2. The pixel gating driver GIA can be repeatedly and continuously positioned along the second direction DR2.

[0303] Pixel gating driver GIA can function in conjunction with gating driver GIP (see reference). Figure 1 The function is roughly the same. The pixel gating driver GIA can include at least one transistor.

[0304] The pixel gating driver (GIA) can be electrically connected to its adjacent sub-pixel (SP).

[0305] The pixel gating driver GIA receives gating control signals from the driver IC DIC via the gating control line GCL_2. The pixel gating driver GIA can then generate scan signals and emission signals (or emission control signals) based on the gating control signals. In doing so, the pixel gating driver GIA can control the operation of adjacent sub-pixels SP.

[0306] Because the pixel gating driver GIA is set in the display area DA, the non-display area NDA or border area can be minimized or reduced, thus providing the user with an improved aesthetic.

[0307] The display device 2 may also include a gating control line GCL_2 and a gating control pad GCP.

[0308] The gating control line GCL_2 can be set in the non-display area NDA. The gating control line GCL_2 can be set in the second non-display area NDA2, but is not limited to this. The gating control line GCL_2 can be set along the extension direction of the second non-display area NDA2.

[0309] The gating control line GCL_2 can be electrically connected to multiple pixel gating drivers GIA located in the display area DA.

[0310] The gating control pad GCP can be set in the pad area PA. The diagram shows the gating control pad GCP set between the high-potential voltage pad VDDP and the data pad DP in the pad area PA; however, it is not limited to this, and the setting position of the gating control pad GCP can vary depending on the design.

[0311] The gating control pad GCP may be made of the same material as, but is not limited to, the gating control line GCL_2. The gating control pad GCP and the gating control line GCL may be integrally formed, but are not limited to.

[0312] The gating control pad GCP and gating control line GCL can be set on the fourth insulating layer 106 in the non-display area NDA. The gating control pad GCP and gating control line GCL can be connected to the source 121 (see source 121). Figure 5 ) and drain 124 (see Figure 5The layers are disposed on the same layer, and may include the same material as the source 121 and drain 124, and may be formed together using a mask through the same process, but are not limited thereto.

[0313] In this configuration, at least some of the inorganic layers disposed on the substrate 101 can extend to the end of the second non-display area NDA2. In other words, at least some of the inorganic layers disposed on the notched non-display area N_NDA and the extended non-display area E_NDA on the substrate 101 can extend to the end of the substrate 101.

[0314] In the notched non-display area N_NDA, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can extend to the end of the substrate 101.

[0315] In the notched non-display area N_NDA, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can substantially cover the entire area of ​​the substrate 101 except for the pad area PA.

[0316] The ends (or side surfaces) of each of the substrate 101, buffer layer 102, first insulating layer 103, second insulating layer 104, third insulating layer 105, fourth insulating layer 106, first inorganic encapsulation layer 171, second inorganic encapsulation layer 173, touch buffer layer 181, first touch insulating layer 183 and third touch insulating layer 186 may be aligned with each other, but are not limited thereto.

[0317] However, multiple pads VSSP, VDDP, and DP may not be covered by multiple inorganic layers. Multiple inorganic layers disposed on the fourth insulating layer 106 may expose multiple pads VSSP, VDDP, and DP. Multiple inorganic layers disposed on the fourth insulating layer 106 may not be disposed within the pad area PA.

[0318] For example, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can be disposed at the end of the substrate 101 in the notched non-display area N_NDA, but may not be disposed in the pad area PA. Therefore, the plurality of pads VSSP, VDDP, and DP disposed on the fourth insulating layer 106 can be exposed and can be electrically connected to the flexible film COF when the display panel 100 is attached to the flexible film COF.

[0319] exist Figure 15 The diagram shows only a cross-sectional view of the notched non-display area N_NDA; however, its description can be applied equivalently to the extended non-display area E_NDA.

[0320] In this case, since the substrate 101 includes a notch NCP, it can provide users with improved aesthetics and convenience.

[0321] The protrusion of mask M can also be omitted (see reference). Figure 12 As a result, it is possible to suppress and prevent marks or scratches caused by the protrusion of the mask M.

[0322] During the manufacturing process of the display panel, a portion (protrusion) of the mask M used to cover the notch NCP can be omitted, thus suppressing or preventing defects such as marks and scratches on the display panel. This improves the reliability of the display device 2. Furthermore, defects can be prevented or reduced, increasing the lifespan of the display device 2 and reducing the manufacturing energy required to manufacture it.

[0323] Figure 16 This is a cross-sectional view of a display device according to another embodiment.

[0324] Figure 16 A cross-section of the notched non-display area N_NDA in the second non-display area NDA2 is shown.

[0325] Reference Figure 16 In the display device 3 according to this embodiment, the buffer layer 102, the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 disposed on the substrate 101 can extend to the end of the substrate 101.

[0326] In this case, the inorganic layer formed by chemical vapor deposition (CVD) can be disposed outside the end of the non-display area NDA and can cover at least one side surface of one of the inorganic layers disposed in the lower inorganic layer (the side surface exposed on the end of the non-display area NDA).

[0327] For example, the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173 can be formed by chemical vapor deposition (CVD), and the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173 can cover the side surface of the fourth insulating layer 106 at the end of the notch non-display area N_NDA. However, the implementation is not limited to this, and the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173 can cover at least one side surface of one of the other inorganic layers disposed below the fourth insulating layer 106.

[0328] In this case, since the substrate 101 uses a notched NCP, it can provide users with improved aesthetics and convenience.

[0329] The protrusion of mask M can also be omitted (see reference). Figure 12 As a result, it is possible to suppress and prevent marks or scratches caused by the protrusion of the mask M.

[0330] Because mask M (reference) is omitted Figure 12 The protrusion of ) so that in the mask M (reference) Figure 12 At least one inorganic layer formed by chemical deposition around the exposed notch NCP can be formed to cover the exposed side surface of at least one of the inorganic layers disposed in the lower part of the non-display area NDA.

[0331] During the manufacturing process of the display panel, a portion (protrusion) of the mask M used to cover the notch NCP can be omitted, thus suppressing or preventing defects such as marks and scratches on the display panel. This improves the reliability of the display device 3. Furthermore, defects can be prevented or reduced, increasing the lifespan of the display device 3 and reducing the manufacturing energy required to manufacture it.

[0332] The display device according to various embodiments of the present disclosure can be described as follows.

[0333] One embodiment is a display device comprising: a display panel having a notch and including a display area and a non-display area surrounding the display area; and a printed circuit film attached to the display panel. The display panel may include: a substrate; at least one panel inorganic layer disposed on the substrate; a light-emitting unit disposed on the at least one panel inorganic layer; and an encapsulation unit disposed on the light-emitting unit. The non-display area may include a notched non-display area disposed around the notch, and the encapsulation unit may be disposed at an end of the notched non-display area.

[0334] According to various embodiments of this disclosure, the non-display area may further include an extended non-display area extending from the notched non-display area, and the printed circuit film may be provided in multiple forms, and at least one printed circuit film may be attached to the extended non-display area.

[0335] According to various embodiments of this disclosure, the recessed non-display area may include a pad area to which a printed circuit film is attached.

[0336] According to various embodiments of this disclosure, the encapsulation unit may include a first inorganic encapsulation layer on the at least one panel inorganic layer, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer, wherein each of the first inorganic encapsulation layer and the second inorganic encapsulation layer may extend to the end of the notch non-display area.

[0337] According to various embodiments of this disclosure, the first inorganic encapsulation layer and the second inorganic encapsulation layer may not be disposed in the pad area.

[0338] According to various embodiments of this disclosure, the display device may further include: a low-potential voltage line, a high-potential voltage line, and a data line electrically connected to the pad area, and the high-potential voltage line may be disposed between the low-potential voltage line and the display area in the non-display area below the display area.

[0339] According to various embodiments of this disclosure, low-potential voltage lines may surround the display area.

[0340] According to various embodiments of this disclosure, a non-display area on the left or right side of the display area may further include a gating driver between a low-potential voltage line and the display area.

[0341] According to various embodiments of the present disclosure, the display device may further include: a pixel gating driver disposed in the display area; and a gating control line that electrically connects the pad area and the pixel gating driver to each other.

[0342] According to various embodiments of this disclosure, the gating control line can be positioned between the low-potential voltage line and the display area.

[0343] According to various embodiments of this disclosure, the display device may further include: a barrier portion disposed in the non-display area and overlapping with the low-potential voltage line, and the organic encapsulation layer may terminate inside the barrier portion.

[0344] According to various embodiments of this disclosure, the display device may further include: a crack-resistant pattern disposed between an end of the display panel and the barrier portion, the crack-resistant pattern being able to penetrate at least one inorganic layer of the panel.

[0345] Another embodiment is a display device comprising: a substrate including a display area having a plurality of sub-pixels and a non-display area surrounding the display area; at least one panel inorganic layer disposed on the substrate; a light-emitting unit disposed on the at least one panel inorganic layer; an encapsulation unit disposed on the light-emitting unit; a display panel including a touch unit disposed on the encapsulation unit; and microlenses disposed on the light-emitting areas of the sub-pixels, wherein the encapsulation unit may extend to the end of the non-display area.

[0346] According to various embodiments of this disclosure, the center of the microlens and the center of the light-emitting region may be misaligned.

[0347] According to various embodiments of the present disclosure, a plurality of sub-pixels may include a first pixel group, wherein the center of the microlens is offset toward the other side in a first direction relative to the center of the light-emitting region; and a second pixel group, wherein the center of the microlens is offset toward the side in the first direction relative to the center of the light-emitting region.

[0348] According to various embodiments of the present disclosure, each of the first pixel group and the second pixel group may extend along a first direction, and the first pixel group and the second pixel group may be spaced apart in a second direction intersecting the first direction.

[0349] According to various embodiments of the present disclosure, the light-emitting unit may further include an anode disposed on at least one inorganic layer of a panel, wherein the anode may be tilted toward the microlens.

[0350] According to various embodiments of the present disclosure, the substrate may include a notch, the non-display area may include a notch non-display area disposed around the notch, and the packaging unit may be disposed at the end of the notch non-display area.

[0351] According to various embodiments of the present disclosure, the display device may further include: a plurality of printed circuit films, the non-display area may further include an extended non-display area extending from the notched non-display area, and at least one printed circuit film may be attached to the extended non-display area.

[0352] According to various embodiments of this disclosure, the non-display area may include a pad area, a printed circuit film is attached to the pad area, and the packaging unit may include a first inorganic packaging layer on at least one panel inorganic layer, an organic packaging layer on the first inorganic packaging layer, and a second inorganic packaging layer on the organic packaging layer. Each of the first inorganic packaging layer and the second inorganic packaging layer may extend to the end of the notched non-display area, and the first inorganic packaging layer and the second inorganic packaging layer may not be disposed in the pad area.

[0353] Embodiments of this disclosure have been described with reference to the accompanying drawings. Those skilled in the art will recognize that this disclosure may be implemented in other specific forms without departing from its technical concept or essential characteristics. The described embodiments are to be considered illustrative in all respects and not restrictive. Therefore, the scope of this disclosure is indicated by the appended claims rather than by the foregoing description. All variations falling within the meaning and equivalents of the claims are included within the scope of this disclosure.

[0354] Cross-references to related applications

[0355] This application claims priority to Korean Patent Application No. 10-2024-0113416, filed on August 23, 2024, the entire contents of which are incorporated herein by reference for all purposes.

Claims

1. A display device, the display device comprising: A display panel having a notch, a display area, and a non-display area surrounding the display area; as well as A printed circuit film, which is connected to the display panel. The display panel includes: substrate; At least one inorganic panel layer, wherein the at least one inorganic panel layer is disposed on the substrate; Light-emitting unit, the light-emitting unit being disposed on the at least one inorganic layer of the panel; and The encapsulation unit is disposed on the light-emitting unit. The non-display area includes a recessed non-display area disposed around the recess, and The encapsulation unit is disposed at the end of the non-display area of ​​the notch.

2. The display device according to claim 1, in, The non-display area also includes an extended non-display area extending from the notched non-display area, and The printed circuit films are arranged in multiple quantities, and at least one printed circuit film is attached to the extended non-display area.

3. The display device according to claim 1, in, The non-display area of ​​the notch includes a pad area, and the printed circuit film is attached to the pad area.

4. The display device according to claim 3, in, The encapsulation unit includes a first inorganic encapsulation layer on the at least one inorganic layer of the panel, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer. Each of the first inorganic encapsulation layer and the second inorganic encapsulation layer extends to the end of the non-display area of ​​the notch.

5. The display device according to claim 4, in, The first inorganic encapsulation layer and the second inorganic encapsulation layer are not disposed in the pad area.

6. The display device according to claim 4, further comprising: A low-potential voltage line, a high-potential voltage line, and a data line are provided, wherein the low-potential voltage line, the high-potential voltage line, and the data line are electrically connected to the pad area. In the non-display area below the display area, the high-potential voltage line is disposed between the low-potential voltage line and the display area.

7. The display device according to claim 6, in, The low-potential voltage line surrounds the display area.

8. The display device according to claim 7, in, The non-display area on the left or right side of the display area also includes a gating driver disposed between the low-potential voltage line and the display area.

9. The display device according to claim 7, further comprising: A pixel gating driver, wherein the pixel gating driver is disposed in the display area; as well as A gating control line electrically connects the pad area and the pixel gating driver to each other.

10. The display device according to claim 9, in, The gating control line is positioned between the low-potential voltage line and the display area.

11. The display device according to claim 6, further comprising: A barrier portion is disposed in the non-display area and overlaps with the low-potential voltage line. The organic encapsulation layer terminates on the inner side of the barrier portion.

12. The display device according to claim 11, further comprising: A crack-resistant pattern is provided between the end of the display panel and the barrier portion. The anti-crack pattern penetrates at least one inorganic layer of the panel.

13. A display device, the display device comprising: A substrate, the substrate including a display area having a plurality of sub-pixels and a non-display area surrounding the display area; At least one inorganic panel layer, wherein the at least one inorganic panel layer is disposed on the substrate; A light-emitting unit, wherein the light-emitting unit is disposed on the at least one inorganic layer of the panel; The encapsulation unit is disposed on the light-emitting unit; The display panel includes a touch unit disposed on the encapsulation unit; as well as A microlens, wherein the microlens is disposed on the light-emitting area of ​​the sub-pixel. The encapsulation unit extends to the end of the non-display area.

14. The display device according to claim 13, in, The center of the microlens is misaligned with the center of the light-emitting area.

15. The display device according to claim 14, in, The plurality of sub-pixels includes a first pixel group, in which the center of the microlens is offset to one side relative to the center of the light-emitting area in a first direction; And a second pixel group, in which the center of the microlens is offset relative to the center of the light-emitting area in the first direction toward the other side.

16. The display device according to claim 15, in, Each pixel group in the first pixel group and the second pixel group extends along the first direction, and The first pixel group and the second pixel group are spaced apart in a second direction that intersects with the first direction.

17. The display device according to claim 14, in, The light-emitting unit further includes an anode disposed on the at least one inorganic layer of the panel, and The anode is tilted toward the microlens.

18. The display device according to claim 13, in, The substrate includes a notch. The non-display area includes a recessed non-display area disposed around the recess, and The encapsulation unit is positioned up to the end of the non-display area of ​​the notch.

19. The display device according to claim 18, further comprising: Multiple printed circuit films, The non-display area further includes an extended non-display area extending from the notched non-display area, and At least one of the plurality of printed circuit films is attached to the extended non-display area.

20. The display device according to claim 19, in, The non-display area includes a pad area, and one of the plurality of printed circuit films is attached to the pad area. The encapsulation unit includes a first inorganic encapsulation layer on the at least one inorganic layer of the panel, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer. Each of the first inorganic encapsulation layer and the second inorganic encapsulation layer extends to the end of the non-display area of ​​the notch, and The first inorganic encapsulation layer and the second inorganic encapsulation layer are not disposed in the pad area.

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