Display device

Abstract

The present disclosure provides a display device including: a substrate including a display area of a display screen and a non-display area around the display area; a plurality of pixels disposed in the display area; a microlens disposed on the plurality of pixels; and a light blocking pattern on a surface of the microlens, in which the plurality of pixels each include a plurality of sub-pixels, the microlens is disposed in each of the plurality of sub-pixels, the plurality of sub-pixels of the pixel are disposed in a first direction, and the plurality of pixels are disposed in the first direction and a second direction intersecting the first direction.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0111090, filed on August 20, 2024, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates to display devices. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is increasing, and various types of display devices are being used, such as liquid crystal display (LCD) devices and organic light-emitting diode (OLED) display devices.

[0005] In display devices, OLED displays, as a self-emissive type, offer the following advantages: wider viewing angles and higher contrast compared to LCD devices; and because they do not require a separate backlight, they are lighter, thinner, and consume less power. Furthermore, OLED displays can be driven at low voltages, have fast response times, and, in particular, have low manufacturing costs.

[0006] OLED displays can also be used in vehicles. In vehicle-mounted displays, those in front of the driver's seat and front passenger seat need to limit the driver's field of vision based on driving conditions. The display also needs to limit the field of vision based on user privacy and information protection requirements. Summary of the Invention

[0007] This disclosure aims to provide a display device with an improved aesthetic design.

[0008] This disclosure also aims to provide a display device in which the path of light emitted from the light-emitting part can be easily blocked or controlled.

[0009] This disclosure also aims to provide a display device in which the cutoff point of emitted light can be achieved at a specific viewing angle.

[0010] This disclosure also aims to provide a display device in which light leakage defects can be prevented and controlled.

[0011] This disclosure also aims to provide a display device in which the reduction in brightness of the display device is minimized, thereby minimizing the reduction in luminous efficiency.

[0012] This disclosure is also intended to provide a display device in which the manufacturing process and design for manufacturing the display device can be further simplified.

[0013] The purpose of this disclosure is not limited to the above-described purposes, and other technical purposes can be deduced from the following embodiments.

[0014] According to one embodiment of the present disclosure, a display device is provided, the display device comprising: a substrate including a display area of ​​a display screen and a non-display area surrounding the display area; a plurality of pixels disposed in the display area; microlenses disposed on the plurality of pixels; and a light-blocking pattern disposed on the surface of the microlenses, wherein each of the plurality of pixels includes a plurality of sub-pixels, the microlenses are disposed on each of the plurality of sub-pixels, the plurality of sub-pixels of the pixel are arranged along a first direction, and the plurality of pixels are disposed in the first direction and a second direction intersecting the first direction.

[0015] According to another embodiment of the present disclosure, a display device is provided, comprising: a substrate including a display area of ​​a display screen and a non-display area surrounding the display area; a thin-film transistor disposed on the substrate; a protective layer disposed on the thin-film transistor; a light-emitting portion disposed on the protective layer; a microlens disposed on the light-emitting portion; and a light-blocking pattern disposed on the microlens. The display device further comprises a plurality of pixels disposed in the display area, and each of the plurality of pixels includes a plurality of sub-pixels, wherein the microlens is disposed on each of the plurality of sub-pixels, and the light-blocking pattern is directly disposed on the surface of the microlens.

[0016] Details of other embodiments are included in the detailed description and accompanying drawings.

[0017] According to embodiments of this disclosure, a display device with improved aesthetics can be provided.

[0018] According to embodiments of this disclosure, the path of light emitted from the light-emitting part can be easily blocked or controlled.

[0019] According to the embodiments of this disclosure, the cutoff zero point of emitted light can be achieved from a specific viewing angle.

[0020] According to the embodiments of this disclosure, light leakage defects can be prevented or controlled.

[0021] According to embodiments of this disclosure, the reduction in brightness of the display device can be minimized, thereby minimizing the reduction in luminous efficiency.

[0022] According to embodiments of this disclosure, the manufacturing process and design for manufacturing display devices can be further simplified.

[0023] According to embodiments of this disclosure, the manufacturing process and design for manufacturing display devices can be further simplified, thereby reducing production energy consumption.

[0024] However, the effects that can be obtained from this disclosure are not limited to those described above, and other effects not mentioned will be clearly understood by those skilled in the art to which this disclosure pertains based on the following description. Attached Figure Description

[0025] Figure 1 This is a plan view of a display device according to one embodiment.

[0026] Figure 2 yes Figure 1 A magnified view of region Q1 in the image.

[0027] Figure 3 Is only shown Figure 2 The view of the display panel.

[0028] Figure 4 This is a plan view showing the pixel arrangement of a display panel according to one embodiment.

[0029] Figure 5 It is along Figure 4 A cross-sectional view of line D-D' in the diagram.

[0030] Figure 6 yes Figure 5 Cross-sectional views of the touch area taken from different angles.

[0031] Figure 7 It is along Figure 1 A cross-sectional view of line A-A' in the diagram.

[0032] Figure 8 It is along Figure 3 A cross-sectional view of line B-B' in the diagram.

[0033] Figure 9 It is along Figure 3 A cross-sectional view of line C-C' in the diagram.

[0034] Figure 10 This is a schematic diagram illustrating the path of light emitted from a display panel according to one embodiment.

[0035] Figure 11 and Figure 12 This is a graph showing the brightness of a display device according to a viewing angle, based on one embodiment.

[0036] Figure 13 This is a plan view showing the pixel arrangement of a display panel according to another embodiment.

[0037] Figure 14 It is along Figure 13 A cross-sectional view of line E-E' in the diagram.

[0038] Figure 15 This is a graph showing the brightness of a display device according to a viewing angle, based on another embodiment.

[0039] Figure 16 This is a plan view showing the pixel arrangement of a display panel according to yet another embodiment.

[0040] Figure 17 It is along Figure 16 A cross-sectional view of line F-F' in the diagram.

[0041] Figure 18 This is a graph showing the brightness of a display device according to a viewing angle, based on yet another embodiment.

[0042] Figure 19 This is a plan view showing the pixel arrangement of a display panel according to yet another embodiment.

[0043] Figure 20 yes Figure 19 A cross-sectional view of line G-G' in the diagram.

[0044] Figure 21 This is a plan view showing the pixel arrangement of a display panel according to yet another embodiment.

[0045] Figure 22 It is along Figure 21 A cross-sectional view of line H-H' in the diagram.

[0046] Figure 23 This is a plan view of a display device according to yet another embodiment.

[0047] Figure 24 yes Figure 23 A magnified view of region Q2 in the image.

[0048] Figure 25 It is along Figure 24 A cross-sectional view of line K-K' in the diagram. Detailed Implementation

[0049] In the following description, embodiments will be illustrated with reference to the accompanying drawings. In this disclosure, when a first component (or region, layer, portion, etc.) is described as being "on," "connected," or "coupled" to a second component, it means that the first component can be directly connected / coupled to the second component, or that a third component can be disposed between the first component and the second component.

[0050] The same reference numerals indicate the same parts. Additionally, in the drawings, the thickness, scale, and dimensions of parts are exaggerated for effective description of the technical content. The term "and / or" includes all one or more combinations that can be defined by associated configurations.

[0051] Terms such as "first" and "second" can be used to describe various components, but these components are not limited by the terms used. Terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the implementation, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, the singular includes the plural.

[0052] Terms such as "below," "under," "above," and "on top" are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative concepts and are described relative to the directions indicated by the markings in the drawings.

[0053] It should be understood that terms such as “comprising” or “having” are intended to specify the presence of features, numbers, steps, operations, components, parts or combinations thereof described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0054] Figure 1 This is a plan view of a display device according to one embodiment. Figure 2 yes Figure 1 A magnified view of region Q1 in the image. Figure 3 Is only shown Figure 2 The view of the display panel.

[0055] Figure 3 yes Figure 2 The view omitting the flexible film COF, motherboard MB, and driver IC DIC, except for the display panel 100, is as follows. Figure 3 In this document, the ratios between components have been adjusted for ease of description.

[0056] Reference Figures 1 to 3 The display device 1 may be a device that includes both a display function for displaying video and a touch sensing function for sensing a user's touch, but is not limited thereto. For example, the display device 1 may include only one of the display function for displaying an image and the touch sensing function for sensing a user's touch.

[0057] Display device 1 may be an electroluminescent display device or a micro-light-emitting diode display device including a touch sensor. The electroluminescent display device including a touch sensor may be an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode display device, or an inorganic light-emitting diode display device.

[0058] The display device 1 according to this embodiment may be a vehicle display device, but is not limited thereto. For example, the description of the display device 1 may be applied without being limited to the type of device, as long as the display device includes a display function.

[0059] When the display device 1 according to this embodiment is a vehicle display device, the display device 1 may include functions such as operating at least some of the various functions of the vehicle, displaying various information about the vehicle, etc.

[0060] When the display device 1 according to this embodiment is a vehicle display device, the display device 1 can be installed on the vehicle's dashboard. The display device 1 can be configured to span between the driver's seat and the front passenger seat located in the front row of the vehicle, but is not limited thereto.

[0061] Both the driver in the driver's seat and the passenger co-driver in the front passenger seat can use the display device 1. The display device 1 can provide different images to each of them. However, embodiments of this disclosure are not limited thereto, and the display device 1 can provide the same image to both the driver in the driver's seat and the passenger co-driver in the front passenger seat.

[0062] The display device 1 may include a display panel 100. The display panel 100 may include a display area DA and a non-display area NDA.

[0063] The display area DA can be an area that emits light outward to display on a screen. The display area DA can also include the function of sensing the user's touch. In this case, the display area DA can correspond to the touch sensing area, but is not limited to this.

[0064] The display area DA may correspond to the shape of the display panel 100, but is not limited to it.

[0065] The display panel 100 may include multiple pixels PX. The multiple pixels PX can be set in the display area DA. The multiple pixels PX can be repeatedly set in the first direction DR1 and the second direction DR2.

[0066] The non-display area NDA can be an area that does not emit light to the outside and therefore does not display a screen. The non-display area NDA can be located around the display area DA. The non-display area NDA can surround the display area DA, but the embodiments of this disclosure are not limited thereto. The border area of ​​the display device 1 can be defined by the non-display area NDA, but the embodiments of this disclosure are not limited thereto.

[0067] The display panel 100 may be a rigid display panel, but is not limited thereto. The display panel 100 may be a flexible display panel whose shape can be deformed, such as a foldable, bendable, rollable, or stretchable display panel.

[0068] The display panel 100 may include a first long edge LE1, a second long edge LE2, a first short edge SE1, and a second short edge SE2 forming the edges of the display panel 100.

[0069] The first long edge LE1 and the second long edge LE2 can extend along the first direction DR1, and the first short edge SE1 and the second short edge SE2 can extend along the direction between the first direction DR1 and the second direction DR2. The two ends of the first long edge LE1 and the second long edge LE2 can be connected by the first short edge SE1 and the second short edge SE2.

[0070] The first long edge LE1 may be located on one side of the second long edge LE2 in the second direction DR2. The first long edge LE1 and the second long edge LE2 may extend parallel to each other, but are not limited thereto.

[0071] The length of the first long edge LE1 can be shorter than the length of the second long edge LE2. Therefore, the first short edge SE1 and the second short edge SE2 can extend in the intersecting direction, but are not limited thereto.

[0072] The first direction DR1 and the second direction DR2 may be intersecting directions. The first direction DR1 and the second direction DR2 may be orthogonal, but are not limited thereto. The first direction DR1 and the second direction DR2 are provided to clarify the description of the invention; the first direction DR1 and the second direction DR2 are relative, and the embodiments of this disclosure are not limited thereto.

[0073] In the plan view, the first long edge LE1 can be set above the display area DA, and the second long edge LE2 can be set below the display area DA.

[0074] In the plan view, the first short edge SE1 can be set on the right side of the display area DA, and the second short edge SE2 can be set on the left side of the display area DA.

[0075] The display panel 100 may include a curved notch NCP. The notch NCP may be formed at the second long edge LE2, but is not limited thereto. That is, the second long edge LE2 may extend entirely along the first direction DR1, but may include a notch NCP that curves toward the first long edge LE1.

[0076] Because of the recessed NCP, components such as the driver's seat handle can be placed on the corresponding part to maximize the display area DA of the screen, thereby improving user convenience and aesthetics.

[0077] The non-display area NDA may include a first non-display area NDA1 set along a first long edge LE1, a first short edge SE1, and a second short edge SE2, and a second non-display area NDA2 set along a second long edge LE2. The second non-display area NDA2 may be set along the second long edge LE2, which includes a curved notch NCP.

[0078] The first non-display area NDA1 can be set on one side and the other side of the display area DA in the first direction DR1, and on one side of the display area DA in the second direction DR2.

[0079] The second non-display area NDA2 may include a notched non-display area N_NDA disposed around the notch NCP and an extended non-display area E_NDA disposed around the notched non-display area N_NDA.

[0080] The extended non-display area E_NDA can extend from the notched non-display area N_NDA along the first direction DR1. The extended non-display area E_NDA can be located between the notched non-display area N_NDA and the first non-display area NDA1. The extended non-display area E_NDA can connect the notched non-display area N_NDA to the first non-display area NDA1.

[0081] The display device 1 may also include a pad area PA, a gate drive unit GIP, a motherboard MB, a flexible film COF, a driver ICDIC, a gate line GL, a gate control line GCL, a data line DL, a low-potential voltage line VSSL, and a high-potential voltage line VDDL.

[0082] The pad area PA can overlap with the flexible film COF. The pad area PA can be attached to the flexible film COF. In other words, the display panel 100 and the flexible film COF can be attached through the pad area PA.

[0083] The pad area PA can be set in the non-display area NDA. The pad area PA can be set in the second non-display area NDA2. The pad area PA can be set in each of the notch non-display area N_NDA and the extended non-display area E_NDA.

[0084] The pad area PA can include multiple pads. The pad area PA can include a low-potential voltage pad VSSP, a high-potential voltage pad VDDP, a first data pad DP1, and a second data pad DP2. The low-potential voltage pad VSSP, the high-potential voltage pad VDDP, the first data pad DP1, and the second data pad DP2 can be set in the pad area PA.

[0085] However, embodiments of this disclosure are not limited thereto, and the pad region PA disposed in the region where it overlaps with the flexible film COF disposed at both ends of the flexible film COF disposed along the non-display region NDA may also include a gate control pad (not shown).

[0086] The gate driving unit GIP can be disposed in the non-display area NDA. The gate driving unit GIP can be disposed at at least one side and the other side of the display area DA in the first direction DR1, but is not limited thereto. In a plan view, the gate driving unit GIP can be disposed on one side and the other side of the display area DA.

[0087] The gate drive unit (GIP) may include multiple transistors G120 (see...) Figure 7 Transistor G120 is located in the gate drive unit GIP (see...). Figure 7 The gate drive unit (GIP) can be connected to the pixel PX via the gate line GL. The gate drive unit (GIP) can apply a gate signal to each pixel PX via the gate line GL.

[0088] The gate drive unit (GIP) can receive gate control signals from the driver IC (DIC) via the gate control line (GCL). The GIP can then generate scan signals and light emission signals (or light emission control signals) based on the gate control signals.

[0089] The gate driving unit (GIP) may include a scan driver and a light emission signal driver. The scan driver can generate scan signals in row-sequential order and supply the scan signals to scan lines to drive one or more scan lines connected to each pixel row (PX). The light emission signal driver can generate light emission signals in row-sequential order and supply the light emission signals to light emission signal lines to drive one or more light emission signal lines connected to each pixel row (PX).

[0090] The motherboard MB can be connected to the display panel 100 via a flexible film COF. The motherboard MB can also be electrically connected to the pixel PX of the display area DA via the flexible film COF. The motherboard MB and the flexible film COF can be electrically connected via multiple pads: VSSP, VDDP, and DP.

[0091] The motherboard (MB) can have various types of components for supplying various signals to the driver IC (DIC), such as gate control signals, drive signals, data signals, etc. The motherboard (MB) can be a printed circuit board, but is not limited to this.

[0092] The motherboard MB can be connected to the display panel 100 via the flexible film COF in the second non-display area NDA2. Multiple motherboards can be configured along the second non-display area NDA2, but are not limited to this. The number of motherboard MBs can vary depending on the design.

[0093] At least one of the motherboards MB can be positioned around the notch NCP and connected to the display panel 100 via a flexible film COF in the notch non-display area N_NDA.

[0094] The flexible film COF can be connected to the display panel 100 and the motherboard MB. The flexible film COF can be attached to each of the display panel 100 and the motherboard MB, and is electrically connected to each of them. That is, the display panel 100 and the motherboard MB can be electrically connected via the flexible film COF. Multiple flexible films can be used, but this is not a limitation.

[0095] The flexible film COF can be attached to the display panel 100 in the second non-display area NDA2. The flexible film COF can be repeatedly set along the second non-display area NDA2. The flexible film COF can be attached to the display panel 100 across the notched non-display area N_NDA and the extended non-display area E_NDA.

[0096] A single motherboard MB can be electrically connected to the display panel 100 via at least one flexible film COF. For example, among a plurality of motherboard MBs disposed along the second non-display area NDA2, the motherboard MBs located at both ends can be electrically connected to the display panel 100 via one flexible film COF, and the remaining motherboard MBs can be electrically connected to the display panel 100 via two flexible film COFs.

[0097] The flexible film COF can be electrically connected to the pad area PA. Therefore, the flexible film COF can supply gate control signals, drive signals, power voltage, data voltage, etc. to the multiple pixels PX and gate drive units GIP disposed in the display area DA.

[0098] The flexible COF (Chip-on-Foil) film can be a flexible insulating film. Flexible COF films can include, for example, polycarbonate, polyethylene terephthalate, polyimide, polyamide, polyester, polyacrylate, polymethyl methacrylate, etc., but are not limited to these.

[0099] The driver IC DIC can be mounted on a flexible film COF. Depending on the mounting method, the driver IC DIC can be mounted using methods such as chip-on-glass, chip-on-film, and tape-and-carrier packaging. In this disclosure, the driver IC DIC is described as being mounted on a flexible film COF using a chip-on-film method, but it is not limited to this.

[0100] The driver IC (DIC) can drive the display device 1. The driver IC (DIC) can process data signals used for displaying images, various drive signals used for processing data signals, etc. The driver IC (DIC) may include gate driver ICs, data driver ICs, etc.

[0101] Gate lines GL can extend from gate drive units GIP and connect to pixels PX. Gate lines GL can electrically connect gate drive units GIP and pixels PX. Gate lines GL can apply gate signals from gate drive units GIP to each pixel PX.

[0102] The gate control line (GCL) can be located in the non-display area (NDA). The GCL can extend from the pad area (PA) to the gate drive unit (GIP) and can be electrically connected to the gate drive unit (GIP).

[0103] The gate control line (GCL) applies a gate control signal to the gate driver unit (GIP). This gate control signal can be sent from the motherboard (MB) or the driver IC (DIC). The GCL electrically connects the gate driver unit (GIP) to the motherboard (MB) or the driver IC (DIC).

[0104] The gate control line (GCL) can be electrically connected to one of the multiple flexible film COFs (COFs) connected to the display panel 100 along the second non-display area NDA2, and located at both ends of the flexible film COF. The gate control line (GCL) can be located at the outermost edge of the multiple lines connected to a flexible film COF, but is not limited thereto.

[0105] The data line DL can extend from the pad area PA and connect to the pixel PX of the display area DA. The data line DL applies data signals to each pixel PX. These data signals can be applied from the motherboard MB or the driver IC DIC. The data line DL electrically connects the pixel PX to the motherboard MB or the driver IC DIC.

[0106] The data cable DL may include a first data cable DL1 and a second data cable DL2. The data cable DL can be connected to data pads DP1 and DP2. The first data cable DL1 can be electrically connected to the first data pad DP1 through a first data contact hole CNT1. The second data cable DL2 can be electrically connected to the second data pad DP2 through a second data contact hole CNT2.

[0107] A low-potential voltage line VSSL can be positioned within the non-display area NDA to surround the display area DA. The gate drive unit GIP is located between the display area DA and the low-potential voltage line VSSL.

[0108] The low-potential voltage line VSSL can apply a low-potential voltage to the pixel PX. The low-potential voltage line VSSL can be electrically connected to the cathode electrode 153 of the pixel PX (see [link to documentation]). Figure 5 To apply a low potential voltage.

[0109] The low-potential voltage line VSSL can be connected to the pad area PA. The low-potential voltage line VSSL can be physically connected to the low-potential voltage pad VSSP, and electrically connected to the low-potential voltage pad VSSP. The low-potential voltage line VSSL and the low-potential voltage pad VSSP can be formed as a single unit, but are not limited to this.

[0110] A high-potential voltage line VDDL can be positioned between the display area DA and the low-potential voltage line VSSL. The high-potential voltage line VDDL can apply a high-potential voltage to the pixel PX. The high-potential voltage line VDDL can be electrically connected to the anode electrode 151 of the pixel PX (see [reference]). Figure 5 To apply a high potential voltage.

[0111] The high-potential voltage line VDDL can be connected to the pad area PA. The high-potential voltage line VDDL can be physically connected to the high-potential voltage pad VDDP, and also electrically connected to the high-potential voltage pad VDDP. The high-potential voltage line VDDL can contact the high-potential voltage pad VDDP through the high-potential contact hole S_CNT.

[0112] However, embodiments of this disclosure are not limited thereto, and the high-potential voltage line VDDL and the high-potential voltage pad VDDP can be integrally formed. For example, the high-potential voltage line VDDL can be formed of the same material and the same conductive layer as the high-potential voltage pad VDDP, and the high-potential voltage line VDDL and the high-potential voltage pad VDDP can be formed together using the same masking process.

[0113] Display device 1 may further include a dam section DMP. The dam section DMP may be disposed in a non-display area NDA. The dam section DMP may be disposed around the display area DA, but is not limited thereto. At least a portion of the dam section DMP may be disposed to overlap with a low-potential voltage line VSSL. The dam section DMP may be disposed in a second non-display area NDA2 between the display area DA and the pad area PA.

[0114] Figure 4This is a plan view showing the pixel arrangement of a display panel according to one embodiment. Figure 4 The plan view is an enlarged view showing a portion of the flat surface structure of the display area DA in which pixels PX are disposed.

[0115] Reference Figure 4 The display panel 100 may include a first pixel PX1 and a second pixel PX2. The first pixel PX1 and the second pixel PX2 may be set in the display area DA.

[0116] Each of the first pixel PX1 and the second pixel PX2 can be repeatedly set in the first direction DR1. The first pixel PX1 and the second pixel PX2 can be repeatedly set alternately in the second direction DR2.

[0117] Each pixel PX1 or PX2 may include sub-pixels SP (SP1_1, SP1_2, SP1_3, SP2_1, SP2_2, and SP2_3). The first pixel PX1 may include sub-pixels SP1_1 (1_1), SP1_2 (1_2), and SP1_3 (1_3). The second pixel PX2 may include sub-pixels SP2_1 (2_1), SP2_2 (2_2), and SP2_3 (2_3).

[0118] The first pixel PX1 and the second pixel PX2 can have essentially the same configuration. In the following description, the description of the first pixel PX1 and its sub-pixels SP1_1, SP1_2 and SP1_3 can be applied in the same way to the second pixel PX2 and its sub-pixels SP2_1, SP2_2 and SP2_3.

[0119] Subpixels SP1_1, SP1_2, and SP1_3 can be set in a row on the first direction DR1.

[0120] Subpixel SP1_1 (1_1) can emit red (R) light, subpixel SP1_2 (1_2) can emit green (G) light, and subpixel SP1_3 (1_3) can emit blue (B) light. However, the color of the light emitted by each subpixel SP1_1, SP1_2, or SP1_3 is not limited to this and can be a variety of colors.

[0121] Sub-pixels SP1_1, SP1_2, and SP1_3 may include light-emitting regions EA1_1, EA1_2, and EA1_3, as well as non-light-emitting regions NEA1_1, NEA1_2, and NEA1_3 respectively disposed around the light-emitting regions EA1_1, EA1_2, and EA1_3.

[0122] Subpixel SP1_1 can include a light-emitting area EA1_1 and a non-light-emitting area NEA1_1 surrounding the light-emitting area EA1_1.

[0123] Subpixel SP1_2 can include a light-emitting area EA1_2 and a non-light-emitting area NEA1_2 disposed around the light-emitting area EA1_2.

[0124] The 1_3 sub-pixel SP1_3 may include a 1_3 luminous area EA1_3 and a 1_3 non-luminous area NEA1_3 disposed around the 1_3 luminous area EA1_3.

[0125] Subpixels 2_1 SP2_1, 2_2 SP2_2, and 2_3 SP2_3 can be set in a row on the first direction DR1.

[0126] Subpixel SP2_1 (2_1) can emit red (R) light, subpixel SP2_2 (2_2) can emit green (G) light, and subpixel SP2_3 (2_3) can emit blue (B) light. However, the color of the light emitted by each subpixel SP2_1, SP2_2, or SP2_3 is not limited to this and can be a variety of colors.

[0127] Sub-pixels SP2_1, SP2_2, and SP2_3 may include light-emitting regions EA2_1, EA2_2, and EA2_3, as well as non-light-emitting regions NEA2_1, NEA2_2, and NEA2_3 disposed around the light-emitting regions EA2_1, EA2_2, and EA2_3.

[0128] The 2_1 sub-pixel SP2_1 may include a 2_1 luminous area EA2_1 and a 2_1 non-luminous area NEA2_1 disposed around the 2_1 luminous area EA2_1.

[0129] The 2_2 sub-pixel SP2_2 may include a 2_2 luminous area EA2_2 and a 2_2 non-luminous area NEA2_2 disposed around the 2_2 luminous area EA2_2.

[0130] The 2_3 sub-pixel SP2_3 may include a 2_3 luminous area EA2_3 and a 2_3 non-luminous area NEA2_3 disposed around the 2_3 luminous area EA2_3.

[0131] A microlens ML (ML1 or ML2) can be set on each of pixels PX1 and PX2. The first microlens ML1 can be set on the first pixel PX1, and the second microlens ML2 can be set on the second pixel PX2.

[0132] Microlenses ML can be set on sub-pixels SP. Microlenses ML can correspond to each sub-pixel SP.

[0133] The first microlens ML1 can be disposed on the first pixel PX1, and on each of the 1_1 sub-pixel SP1_1, 1_2 sub-pixel SP1_2 and 1_3 sub-pixel SP1_3.

[0134] The second microlens ML2 can be set on the second pixel PX2, and on each of the sub-pixels SP2_1, SP2_2, and SP2_3.

[0135] Microlenses ML1 and ML2 can control the path of light emitted from pixels PX1 and PX2, respectively. Microlenses ML1 and ML2 can control the path of light emitted from pixels PX1 and PX2 in different directions.

[0136] For example, the first microlens ML1 can adjust the light emitted from the first pixel PX1 to travel to the other side in the first direction DR1 in the planar view. Similarly, the second microlens ML2 can adjust the light emitted from the second pixel PX2 to travel to the other side in the first direction DR1 in the planar view.

[0137] By arranging microlenses ML, the path of light emitted from each pixel PX1 or PX2 can be easily controlled.

[0138] Light-blocking patterns BP (BP1 and BP2) can be set on the microlens ML. The light-blocking pattern BP can include a first light-blocking pattern BP1 and a second light-blocking pattern BP2. The first light-blocking pattern BP1 can be set on the first microlens ML1, and the second light-blocking pattern BP2 can be set on the second microlens ML2. The first light-blocking pattern BP1 can be set on each of the first microlenses ML1, and the second light-blocking pattern BP2 can be set on each of the second microlenses ML2.

[0139] Light-blocking patterns (BPs) can include materials capable of absorbing and blocking light. For example, light-blocking patterns (BPs) can include black pigments and / or dyes, but are not limited to these.

[0140] The light-blocking pattern BP can block light from emitting part 150 (see...) Figure 5 The light emitted is shaped by the path of the light blocking pattern BP. Therefore, the image and video provided from each pixel PX1 or PX2 can be displayed at the desired viewing angle. In other words, by arranging the light-blocking pattern BP, the viewing angle of the screen displayed on the display device can be controlled or blocked more smoothly.

[0141] The light-blocking pattern BP can be set in the non-emitting area NEA, but is not limited to this, and some of the light-blocking patterns BP can be set to extend to the emitting area EA.

[0142] The first light-blocking pattern BP1 and the second light-blocking pattern BP2 can be disposed at the same position on the microlens ML. The first light-blocking pattern BP1 can be disposed on one side of the first microlens ML1 in the first direction DR1, and the second light-blocking pattern BP2 can be disposed on one side of the second microlens ML2 in the first direction DR1.

[0143] By arranging a light-blocking pattern BP on the microlens ML, the shape of the microlens ML used for viewing angle control does not need to be changed. Therefore, by arranging the light-blocking pattern BP on the microlens ML, which can be formed through a relatively simple process, the manufacturing process and design of the display device can be simplified. Furthermore, the production energy required for manufacturing the display device can be reduced.

[0144] The microlens ML may include dividing lines DV (DV1 and DV2). The dividing lines DV may include a first dividing line DV1 and a second dividing line DV2.

[0145] The dividing line DV can refer to a virtual line that divides the microlens ML into two parts. The microlens ML can be divided into two substantially equal parts by the dividing line DV, but is not limited to this. The two parts of the microlens ML divided by the dividing line DV can include, but are not limited to, symmetrical shapes, and the two parts of the microlens ML divided by the dividing line DV can have different shapes and sizes.

[0146] In such Figure 4 In the plan view, the dividing line DV can pass through the center EC (EC1 and EC2) of the luminous region EA, but is not limited to this.

[0147] The first center EC1 can refer to the center of each of the light-emitting areas EA1_1, EA1_2, and EA1_3 of the sub-pixels SP1_1, SP1_2, and SP1_3 of the first pixel PX1.

[0148] The second center EC2 can refer to the center of each of the light-emitting areas EA2_1, EA2_2, and EA2_3 of the sub-pixels SP2_1, SP2_2, and SP2_3 of the second pixel PX2.

[0149] The first microlens ML1 may include a first dividing line DV1, and the second microlens ML2 may include a second dividing line DV2.

[0150] Each dividing line DV1 or DV2 can be, for example... Figure 4The planar diagram extends along the second direction DR2 and has thickness in the thickness direction (third direction DR3). Each dividing line DV1 or DV2 may be substantially the same, but is not limited to this, and the flat surface shape of each dividing line DV1 or DV2 may vary depending on the shape of each microlens ML1 or ML2.

[0151] Each microlens ML1 or ML2 can be divided into two parts (a first part and a second part) according to each dividing line DV1 or DV2. The first part (or first side) and the second part (or second side) of each microlens ML1 or ML2 can be respectively set on one side and the other side of each dividing line DV1 or DV2 in the first direction DR1.

[0152] The first light-blocking pattern BP1 and the second light-blocking pattern BP2 can be disposed on two identical portions of microlenses ML1 and ML2 divided by dividing lines DV1 and DV2. For example, the first light-blocking pattern BP1 can be disposed on the first portion of the first microlens ML1 located on one side (or the first side) of the first dividing line along the first direction DR1 of the two portions divided by the first dividing line DV1. Similarly, the second light-blocking pattern BP2 can be disposed on the first portion of the second microlens ML2 located on one side (or the first side) of the second dividing line DV2 along the first direction DR1 of the two portions divided by the second dividing line DV2.

[0153] The first light-blocking pattern BP1 can block a portion of the light emitted from the first pixel PX1 that travels toward the first direction DR1 in the planar view, and the second light-blocking pattern BP2 can block a portion of the light emitted from the second pixel PX2 that travels toward the first direction DR1 in the planar view.

[0154] By arranging the light-blocking pattern BP and microlenses ML, it is easier to control or block the path of light emitted from the display panel 100 and prevent light leakage defects that may occur between pixels PX. Therefore, the quality of images and videos displayed on each pixel PX1 or PX2 can be improved, and the display device 1 (see...) can be made more efficient. Figure 1 To minimize the reduction in brightness, thereby minimizing the reduction in luminous efficiency.

[0155] One microlens ML is shown as being disposed in each subpixel SP, but embodiments of this disclosure are not limited thereto. For example, depending on the design of each subpixel SP, the microlens ML disposed on each subpixel SP may be two or more microlenses. When an opening (light-emitting region EA) formed in a subpixel SP is configured as multiple openings, the microlens ML may be disposed in each opening, or multiple microlenses ML may be disposed in one opening.

[0156] In the following text, reference will be made to Figure 5 The description includes the cross-sectional structure of the display area DA of the display panel 100, which includes pixels PX.

[0157] Figure 5 It is a cross-sectional view along line D-D' in 4. Figure 6 yes Figure 5 Cross-sectional views of the touch portion taken from different angles. Figure 7 It is along Figure 1 A cross-sectional view of line A-A' in the diagram. Figure 8 It is along Figure 3 A cross-sectional view of line B-B' in the diagram. Figure 9 It is along Figure 3 A cross-sectional view of line C-C' in the diagram.

[0158] Figure 7 The cross-sectional structure of the first non-display area NDA1 is shown. Figure 8 and Figure 9 The cross-sectional structure of the notched non-display area N_NDA of the second non-display area NDA2 is shown. Figure 8 and Figure 9 The description can also be applied in essentially the same way to the extended non-display area E_NDA.

[0159] First, refer to Figures 4 to 6 Describes the cross-section of the display area DA.

[0160] The display panel 100 may include a substrate 101, a thin-film transistor 120, a storage electrode 140, a light-emitting portion 150, a packaging portion 170, and a touch portion 180 in the display area DA. However, the embodiments of the present disclosure are not limited thereto.

[0161] The substrate 101 can provide space on which various components can be mounted. The substrate 101 can correspond to Figure 1 The display panel 100 has a flat surface shape. That is, the substrate 101 may include a notched NCP. The substrate 101 may include the display area DA and the non-display area NDA of the display panel 100 in substantially the same manner.

[0162] The substrate 101 may include one or more plastic materials, but is not limited thereto, and may include glass materials.

[0163] The substrate 101 may be a multi-substrate comprising a first substrate 101a, a second substrate 101b, and a third substrate 103c, each substrate comprising a plastic material such as polyimide, but embodiments of the present disclosure are not limited thereto. For example, the substrate 101 may be a single substrate formed from a single layer.

[0164] Substrate 101 may include a rigid substrate. However, embodiments of this disclosure are not limited thereto, and substrate 101 may include a flexible substrate.

[0165] A buffer layer 102 can be disposed on the substrate 101. The buffer layer 102 can minimize or delay the diffusion of moisture or oxygen permeating the substrate 101. The buffer layer 102 can be constructed by alternating stacks of silicon nitride (SiN). x ) and silicon oxide (SiO) x It may be formed at least once, but the implementation of this disclosure is not limited thereto.

[0166] This disclosure describes the buffer layer 102 as being formed as multiple layers consisting of three layers, but the number of layers forming the buffer layer 102 is not limited thereto, and the buffer layer 102 may be formed as a single layer.

[0167] A light-blocking layer 126 may be disposed on the buffer layer 102. The light-blocking layer 126 can prevent light from being transmitted to the semiconductor layer 123 of the thin-film transistor 120. For example, the semiconductor layer 123 may be disposed overlapping the light-blocking layer 126. The light-blocking layer 126 may be formed via a single layer or multiple layers of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd) and copper (Cu), but embodiments of the present disclosure are not limited thereto.

[0168] A first insulating layer 103 may be disposed on the light-blocking layer 126. The first insulating layer 103 can prevent short circuits between components of the thin-film transistor 120 and the light-blocking layer 126. The first insulating layer 103 may be formed of the same material as the buffer layer 102, but embodiments of the present disclosure are not limited thereto. For example, the first insulating layer 103 may be made of materials such as silicon nitride (SiN). x ) or silicon oxide (SiO) x The inorganic materials are formed, but the embodiments of the present disclosure are not limited thereto.

[0169] The thin-film transistor 120 may be disposed on the first insulating layer 103. The thin-film transistor 120 may include a source electrode 121, a gate electrode 122, a semiconductor layer 123, and a drain electrode 124.

[0170] Semiconductor layer 123 may be disposed on first insulating layer 103. Semiconductor layer 123 may include metal oxide semiconductors such as indium gallium zinc oxide (IGZO) and silicon-based semiconductor materials such as amorphous silicon or polycrystalline silicon, but embodiments of this disclosure are not limited thereto. Semiconductor layer 123 may include a source region, a drain region, and a channel region between the source region and the drain region.

[0171] Because polycrystalline semiconductor layers have higher mobility than amorphous semiconductor layers and oxide semiconductor layers, power consumption can be lower and reliability can be superior. Therefore, semiconductor layer 123 can be formed of a polycrystalline semiconductor layer, but embodiments of this disclosure are not limited thereto.

[0172] A second insulating layer 104 may be disposed on the semiconductor layer 123. The second insulating layer 104 may be formed of the same material as the first insulating layer 103, but embodiments of the present disclosure are not limited thereto. The second insulating layer 104 can prevent short circuits between the semiconductor layer 123 and another component of the thin-film transistor 120.

[0173] A gate electrode 122 may be disposed on the second insulating layer 104. The gate electrode 122 may be disposed on the second insulating layer 104 to overlap with the channel region of the semiconductor layer 123. The gate electrode 122 may be formed via a single layer or multiple layers made of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or compounds thereof, but embodiments of the present disclosure are not limited thereto. The gate electrode 122 may be disposed together with the gate line, but embodiments of the present disclosure are not limited thereto.

[0174] A third insulating layer 105 may be provided on the gate electrode 122. The third insulating layer 105 may be formed of the same material as the first insulating layer 103 or the second insulating layer 104, but the embodiments of the present disclosure are not limited thereto.

[0175] The storage electrode 140 may be spaced apart from the thin-film transistor 120. The storage electrode 140 may include a first storage electrode 141 and a second storage electrode 142.

[0176] The first storage electrode 141 may be formed of the same material as the gate electrode 122 and formed on the same layer, but the embodiments of the present disclosure are not limited thereto.

[0177] The second storage electrode 142 may be disposed on the first storage electrode 141. The second storage electrode 142 may be disposed on the third insulating layer 105, and the third insulating layer 105 between the first storage electrode 141 and the second storage electrode 142 may serve as a dielectric to generate a capacitor. The second storage electrode 142 may be formed of the same material as the first storage electrode 141, but embodiments of this disclosure are not limited thereto.

[0178] A fourth insulating layer 106 may be disposed on the second storage electrode 142. The fourth insulating layer 106 may be formed of the same material as the first insulating layer 103, the second insulating layer 104 or the third insulating layer 105, but the embodiments of the present disclosure are not limited thereto.

[0179] A source electrode 121 and a drain electrode 124 can be disposed on the fourth insulating layer 106.

[0180] The source electrode 121 and drain electrode 124 can be electrically connected to the semiconductor layer 123 through contact holes. The source electrode 121 and drain electrode 124 can be formed of a metallic material. For example, the source electrode 121 and drain electrode 124 can be formed via a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof, but embodiments of this disclosure are not limited thereto.

[0181] The source electrode 121 and the drain electrode 124 can be disposed together with the data line. For example, the data line can be formed of the same material as the source electrode 121 and the drain electrode 124 and formed on the same layer, but the embodiments of this disclosure are not limited thereto.

[0182] The thin-film transistor 120 may be a driving transistor, although not shown. The display panel 100 may also include a switching transistor, but the embodiments of this disclosure are not limited thereto.

[0183] A first protective layer 111 may be provided on the source electrode 121 and the drain electrode 124.

[0184] The first protective layer 111 can planarize the upper portion of the thin-film transistor 120 and protect the thin-film transistor 120. The first protective layer 111 can be formed of an organic material. For example, the first protective layer 111 can be formed of an organic material including acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin, but the embodiments of this disclosure are not limited thereto.

[0185] A second protective layer 112 may be disposed on the first protective layer 111. The second protective layer 112 may be formed of the same material as the first protective layer 111, but the embodiments of the present disclosure are not limited thereto.

[0186] A connecting electrode 145 can be provided between the first protective layer 111 and the second protective layer 112.

[0187] The connection electrode 145 can electrically connect the thin-film transistor 120 to the light-emitting part 150. The connection electrode 145 can be formed of the same material as the source electrode 121 and the drain electrode 124, but the embodiments of this disclosure are not limited thereto.

[0188] The connecting electrode 145 can contact the drain electrode 124 through the contact hole formed in the first protective layer 111, and can be electrically connected to the drain electrode 124.

[0189] The connecting electrode 145 may be formed via a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but the embodiments of this disclosure are not limited thereto.

[0190] The light-emitting part 150 may be disposed on the second protective layer 112. The light-emitting part 150 may include an anode electrode 151, an organic layer 152, and a cathode electrode 153.

[0191] The anode electrode 151 may be disposed on the second protective layer 112. The anode electrode 151 may be electrically connected to the thin-film transistor 120 through contact holes formed in the first protective layer 111 and the second protective layer 112.

[0192] The anode electrode 151 may be a reflective electrode that reflects light, but the embodiments of this disclosure are not limited thereto. The anode electrode 151 may include a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and indium tin oxide (ITO) (ITO / Al / ITO), or an APC alloy, and may be formed from a single layer or multiple layers, but the embodiments of this disclosure are not limited thereto.

[0193] For example, the cathode electrode 153 may include materials such as indium tin oxide (ITO) or indium zinc oxide (IZO), but embodiments of this disclosure are not limited thereto.

[0194] Organic layer 152 may be disposed on anode electrode 151. Organic layer 152 may include one or more light-emitting structures (or light-emitting elements or components) stacked on anode electrode 151 in the order of hole transfer layer and electron transfer layer, or in reverse order. For example, hole transfer layer may include hole transport layer, hole injection layer, electron blocking layer, p-type charge generation layer, etc., but the embodiments of this disclosure are not limited thereto. For example, electron transfer layer may include electron transport layer, electron injection layer, hole blocking layer, n-type charge generation layer, etc., but the embodiments of this disclosure are not limited thereto.

[0195] The organic layer 152 may be an organic light-emitting layer, an inorganic light-emitting layer, a quantum dot light-emitting layer, a micro light-emitting diode, or a miniature light-emitting diode, etc., but the embodiments of this disclosure are not limited to these. For example, the organic layer 152 of the display panel 100 according to one embodiment of this disclosure may include an organic light-emitting layer. The organic layer 152 may include a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer, but the embodiments of this disclosure are not limited to these. The organic layer 152 may also include a white light-emitting layer, but the embodiments of this disclosure are not limited to these.

[0196] The cathode electrode 153 may be disposed on the organic layer 152. The cathode electrode 153 may be a transparent electrode that transmits light, but the embodiments of this disclosure are not limited thereto. For example, the cathode electrode 153 may include a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or a metal that transmits visible light, but the embodiments of this disclosure are not limited thereto.

[0197] A capping layer 156 can also be provided on the cathode electrode 153. The capping layer 156 can minimize damage to the cathode electrode 153 of the light-emitting part 150 and the organic layer 152 located below the cathode electrode 153 by the external light source. The capping layer 156 can be formed of an organic film or an inorganic film.

[0198] The capping layer 156 can be formed using materials such as LiF as inorganic films, and may also include organic films, but embodiments of this disclosure are not limited thereto. For example, the capping layer 156 may be formed from a stacked structure of organic and inorganic films, and the thickness of the organic film may differ from the thickness of the inorganic film. In this case, the thickness of the organic film may be greater than the thickness of the inorganic film. As another example, the capping layer 156 can be formed from two or more layers by stacking materials with different refractive indices. Therefore, the light efficiency of the display panel 100 can be improved.

[0199] A dam 154 can be provided to expose the anode electrode 151. The dam 154 can define an opening (or light-emitting region EA) of the sub-pixel SP and can be configured to cover the edge of the anode electrode 151. An organic layer 152 can be disposed in the opening of the sub-pixel SP. That is, the organic layer 152 can be disposed on the anode electrode 151 exposed through the dam 154.

[0200] However, embodiments of this disclosure are not limited thereto, and the organic layer 152 may be disposed both in the opening (light-emitting area EA) of the sub-pixel SP and on the embankment 154. That is, the organic layer 152 may be disposed in the entire display area DA of the display panel 100.

[0201] The dam 154 can be formed of a material containing black pigment or an organic material such as benzocyclobutene resin, polyimide resin, acrylic resin, photosensitive polymer, etc., but the embodiments of this disclosure are not limited thereto. When the dam 154 is formed of a material containing black pigment or black dye, the dam 154 can be an opaque dam. When the dam 154 is formed of a material containing black pigment or black dye, it can block external light or light reflected from the outside, thereby further increasing the brightness of the display device.

[0202] Spacers (not shown) may also be provided on the dam 154. The spacers (not shown) may be formed of the same material as the dam 154, but embodiments of this disclosure are not limited thereto. The spacers (not shown) can prevent the mask from sagging during the masking process, thereby suppressing or preventing defects such as embossing, scratches, etc. on the display panel 100.

[0203] The encapsulation portion 170 may be disposed on the dam 154 or the light-emitting portion 150. The encapsulation portion 170 may include one or more insulating layers. For example, the encapsulation portion 170 may include a first inorganic encapsulation layer 171, an organic encapsulation layer 172 formed on the first inorganic encapsulation layer 171, and a second inorganic encapsulation layer 173 formed on the organic encapsulation layer 172. The encapsulation portion 170 may include one or more inorganic layers and one or more organic layers. For example, the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173 may include inorganic materials, and the organic encapsulation layer 172 may include organic materials, but the embodiments of this disclosure are not limited thereto.

[0204] The first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173 can be configured to extend around the dam section DMP, and the organic encapsulation layer 172 can terminate inside the dam section DMP. That is, the organic encapsulation layer 172 can be disposed within the region surrounded by the dam section DMP without extending beyond the dam section DMP.

[0205] The touch portion 180 may be disposed on the encapsulation portion 170. The touch portion 180 may include a touch buffer layer 181, a first touch electrode 182, a first touch insulating layer 183, a black matrix BM, a second touch insulating layer 184, a second touch electrode 185, and a third touch insulating layer 186.

[0206] A touch buffer layer 181 may be disposed on the encapsulation portion 170. For example, the touch buffer layer 181 may be disposed on the second inorganic encapsulation layer 173. The touch buffer layer 181 may be formed of the same material as the buffer layer 102, but embodiments of the present disclosure are not limited thereto.

[0207] The first touch electrode 182 can be disposed on the touch buffer layer 181.

[0208] The first touch insulating layer 183 can be disposed on the first touch electrode 182. The first touch insulating layer 183 can be made of silicon oxide (SiO2). x ), silicon nitride (SiN) x It may be formed in multiple layers or in combination, but the implementation of this disclosure is not limited thereto.

[0209] The black matrix BM can be disposed on the first touch insulating layer 183. The black matrix BM can include a material capable of absorbing light. The black matrix BM can include, but is not limited to, black pigments or dyes. The black matrix BM can prevent light leakage defects that may occur between sub-pixels SP.

[0210] The second touch insulating layer 184 may be disposed on the black matrix BM. The second touch insulating layer 184 may include an organic insulating material. For example, the second touch insulating layer 184 may be formed of propylene, benzocyclobutene (BCB), polyimide (PI) or polyamide (PA), but is not limited thereto.

[0211] The second touch electrode 185 may be disposed on the second touch insulating layer 184. The second touch electrode 185 may include a 2a touch electrode 185a extending in the first direction DR1 and a 2b touch electrode 185b extending in a second direction DR2 different from the first direction DR1.

[0212] The second touch electrode 182 can be electrically connected to the 2a touch electrode 185a through a contact hole formed in the second touch insulating layer 184. For example, the 2a touch electrode 185a and the first touch electrode 182 can extend in the first direction DR1.

[0213] The first touch electrode 182 and the second touch electrode 185 may include metallic materials. For example, the first touch electrode 182 and the second touch electrode 185 may be formed of titanium (Ti), nickel (Ni), aluminum (Al) or alloys thereof, and may be formed of a three-layer structure such as titanium (Ti) / aluminum (Al) / titanium (Ti), but embodiments of the present disclosure are not limited thereto.

[0214] One of the first touch electrode 182 and the second touch electrode 185 may include a touch detection function, and the other may include a touch driving function, but the embodiments of this disclosure are not limited thereto.

[0215] The third touch insulating layer 186 may be disposed on the second touch electrode 185. The third touch insulating layer 186 may be formed of the same material as the first touch insulating layer 183, but is not limited thereto.

[0216] Microlenses ML (ML1 and ML2) can be disposed on the third touch insulating layer 186. Microlenses ML can be hemispherical or semi-cylindrical, but are not limited to these shapes. The shape of microlenses ML can vary depending on the size, shape, etc. of the light-emitting region EA.

[0217] Microlenses ML1 and ML2 can control the path of light emitted from pixels PX1 and PX2, respectively. Microlenses ML1 and ML2 can control the path of light emitted from pixels PX1 and PX2 in different directions.

[0218] Therefore, pixels PX1 and PX2 can display different images and videos, and display device 1 (see...) Figure 1 It can display two or more different images and videos depending on the viewing angle.

[0219] In addition, by arranging microlenses ML (ML1 and ML2), a wide viewing angle can be ensured, brightness can be increased, and light leakage and reflection can be blocked, thereby preventing light leakage.

[0220] Each microlens ML (ML1 or ML2) may include dividing lines DV (DV1 or DV2). (See planar diagram). Figure 4 The cross section orthogonally intercepted by each dividing line DV1 or DV2 in (see) Figure 5 In this embodiment, each dividing line DV1 or DV2 can be aligned with the center EC1 or EC2 of each luminescent region EA. However, embodiments of this disclosure are not limited thereto, and depending on the shape of the microlens ML and the shape of the luminescent region EA, each dividing line DV1 or DV2 may not be aligned with the center EC1 or EC2 of each luminescent region EA.

[0221] Light-blocking patterns BP (BP1 and BP2) can be set on the microlens ML. The first light-blocking pattern BP1 can be set on the first microlens ML1, and the second light-blocking pattern BP2 can be set on the second microlens ML2.

[0222] Each light-blocking pattern BP1 or BP2 can be directly set on each microlens ML1 or ML2. Each light-blocking pattern BP1 or BP2 can be in direct contact with each microlens ML1 or ML2, but is not limited thereto.

[0223] The area on the surface of the first microlens ML1 exposed by the first light-blocking pattern BP1 can directly contact the lens protective layer 190. The area on the surface of the second microlens ML2 exposed by the second light-blocking pattern BP2 can directly contact the lens protective layer 190.

[0224] Here, the surface of each microlens ML1 or ML2 can refer to the dome-shaped upper surface of the area other than the lower surface facing the third touch insulating layer 186.

[0225] The first light-blocking pattern BP1 and the second light-blocking pattern BP2 can be set on the two identical parts of the microlenses ML1 and ML2, which are divided by dividing lines DV1 and DV2.

[0226] For example, the first light-blocking pattern BP1 can be disposed on the first microlens ML1 located on one side (or the first side) of the first microlens ML1 in the first direction DR1, which is divided into two parts by the first dividing line DV1, and the second light-blocking pattern BP2 can be disposed on the second microlens ML2 located on one side (or the first side) of the second dividing line DV2 in the first direction DR1, which is divided into two parts by the second dividing line DV2.

[0227] Therefore, the first light-blocking pattern BP1 can block a portion of the light emitted from the first pixel PX1 that travels toward the first direction DR1 in the planar view, and the second light-blocking pattern BP2 can block a portion of the light emitted from the second pixel PX2 that travels toward the first direction DR1 in the planar view.

[0228] Because the light-blocking pattern BP is disposed on the microlens ML, it can more easily block or control the path of light emitted from the pixel PX. In other words, since the light-blocking pattern BP is disposed on the microlens ML, it can be positioned at the end of the path of light emitted from the pixel PX, thus ultimately blocking and controlling the path of light emitted from the pixel PX, thereby facilitating light blocking and control.

[0229] Lens protection layer 190 can be disposed on microlenses ML (ML1 and ML2) and light-blocking pattern BP. Lens protection layer 190 may include, but is not limited to, organic insulating material. Lens protection layer 190 can protect microlenses ML by covering them.

[0230] The refractive index of the lens protective layer 190 can be less than that of the microlens ML. Therefore, due to the difference in refractive index between the microlens ML and the lens protective layer 190, light that has passed through the microlens ML can be prevented from being reflected toward the substrate 101.

[0231] The cross-sectional structure of the non-display area NDA of the display device 1 will be described below. Content identical to that described in the cross-sectional structure of the display area DA will be briefly described or omitted.

[0232] Subsequently, further reference Figure 1 , Figure 3 as well as Figures 7 to 9 The display panel 100 may also include a gate control transistor G120, a low potential voltage line VSSL, a dam DMP, multiple pads VSSP, VDDP and DP disposed in the pad area PA, data lines DL (DL1 and DL2) and crack prevention pattern CSP disposed in the non-display area NDA.

[0233] The gate control transistor G120 may have a substantially the same configuration as the thin-film transistor 120 of the sub-pixel SP, and may be formed together with the thin-film transistor 120 of the sub-pixel SP by the same process, but is not limited thereto.

[0234] The gate control transistor G120 may include a control source electrode G121, a control gate electrode G122, a control semiconductor layer G123, and a control drain electrode G124.

[0235] A photoblocking layer (not shown) may also be provided below the gate control transistor G120. One of the control source electrode G121 and the control drain electrode G124 may be electrically connected to the photoblocking layer (not shown), but is not limited thereto.

[0236] The low-potential voltage line VSSL can be disposed on the fourth insulating layer 106. The low-potential voltage line VSSL can be formed of the same metal layer as the source electrode 121 and drain electrode 124 of the thin-film transistor 120, but is not limited thereto.

[0237] The display panel 100 may also include a low-potential connection electrode CE. The low-potential connection electrode CE can connect the low-potential voltage line VSSL to the cathode electrode 153.

[0238] A low-potential connection electrode CE can be disposed on the second protective layer 112. A dam 154 can be disposed on the low-potential connection electrode CE. The low-potential connection electrode CE can be disposed on the same layer as the anode electrode 151 and can include the same material as the anode electrode 151. The low-potential connection electrode CE and the anode electrode 151 can be formed together using the same process with a mask, but the embodiments of this disclosure are not limited thereto.

[0239] The display panel 100 may also include an exposed portion OP. The exposed portion OP can expose at least a portion of the low-potential voltage line VSSL by recessing the first protective layer 111 and the second protective layer 112.

[0240] The exposed part OP may be defined by a first protective layer 111 and a second protective layer 112. The exposed part OP may be defined by the side surface of the first protective layer 111, the side surface of the second protective layer 112, and the side surface of the second dam DM2.

[0241] The low-potential connection electrode CE can be electrically connected to the low-potential voltage line VSSL exposed in the exposed part OP. At least a portion of the low-potential connection electrode CE can be disposed on the second protective layer 112 and can extend from the second protective layer 112 toward the low-potential voltage line VSSL.

[0242] The low-potential connection electrode CE can also be disposed on the side surface of the defined exposed portion OP of the first protective layer 111 and the side surface of the second protective layer 112, and can also be disposed on the low-potential voltage line VSSL exposed through the exposed portion OP and the fourth insulating layer 106. Therefore, the low-potential connection electrode CE can contact the low-potential voltage line VSSL.

[0243] The low-potential connection electrode CE can be electrically connected to the cathode electrode 153. The low-potential connection electrode CE and the cathode electrode 153 can be electrically connected to each other in the overlapping area through the low-potential contact hole C_CNT. The low-potential contact hole C_CNT can be defined by passing through the dam 154 in the overlapping area of ​​the low-potential connection electrode CE and the cathode electrode 153, and can expose the low-potential connection electrode CE.

[0244] The dam section DMP may include a first dam DM1 and a second dam DM2. The first dam DM1 and the second dam DM2 may overlap with a first low-potential voltage line VSSL1 or a second low-potential voltage line VSSL2.

[0245] In the second non-display area NDA2, the first dam DM1 and the second dam DM2 may overlap with the first low-potential voltage line VSSL1. In the first non-display area NDA1, the first dam DM1 and the second dam DM2 may overlap with the second low-potential voltage line VSSL2.

[0246] The first dam DM1 can be located outside the second dam DM2, but is not limited to this.

[0247] The first dam DM1 can be formed as a multi-layered structure. Each layer of the first dam DM1 may include the same material as the second protective layer 112 and the dike 154, and each layer of the first dam DM1, the second protective layer 112 and the dike 154 may be formed together using the same process with a mask, but the embodiments of this disclosure are not limited thereto.

[0248] The second dam DM2 can be formed as a multi-layered structure. Each layer of the second dam DM2 may include the same material as the embankment 154 and the spacer (not shown), and each layer of the second dam DM2, the embankment 154 and the spacer (not shown) may be formed together using the same process with a mask, but embodiments of this disclosure are not limited thereto.

[0249] The crack prevention pattern CSP can be disposed at the outermost edge of the non-display area NDA. The crack prevention pattern CSP can be defined by making at least one of the inorganic films disposed on the substrate 101 recessed.

[0250] For example, the crack prevention pattern CSP can be defined by recessing the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, and the fourth insulating layer 106, but is not limited thereto.

[0251] A crack dummy pattern (DUP) can also be formed on the crack prevention pattern (CSP). The crack dummy pattern (DUP) can fill the recessed crack prevention pattern (CSP). The crack dummy pattern (DUP) can be formed from multiple layers. For example, the crack dummy pattern (DUP) can be formed from three layers. Each layer of the crack dummy pattern (DUP) can include the same material as the first protective layer 111, the second protective layer 112, and the dam 154.

[0252] The high-potential voltage line VDDL can be disposed on the buffer layer 102 and covered by the first insulating layer 103. The high-potential voltage line VDDL may include the same material as the light-blocking layer 126, and the high-potential voltage line VDDL and the light-blocking layer 126 can be formed together using the same process with a mask, but the embodiments of this disclosure are not limited thereto.

[0253] Although not shown, the high-potential voltage pad VDDP can be disposed on the same layer as the source electrode 121 and the drain electrode 124, can include the same material as the source electrode 121 and the drain electrode 124, and can be formed together with a mask using the same process as the source electrode 121 and the drain electrode 124, but is not limited thereto.

[0254] In this case, the high-potential voltage pad VDDP can be electrically connected to the high-potential voltage line VDDL through the high-potential contact hole S_CNT that exposes the high-potential voltage line VDDL.

[0255] However, the embodiments of this disclosure are not limited thereto, and the high potential voltage line VDDL can be disposed on the same layer as the source electrode 121 and the drain electrode 124, and can include the same material as the source electrode 121 and the drain electrode 124, and the high potential voltage line VDDL, the source electrode 121 and the drain electrode 124 can be formed together using a mask through the same process.

[0256] The first data pad DP1 and the second data pad DP2 can be disposed on the fourth insulating layer 106. The first data pad DP1 and the second data pad DP2 can be disposed on the same layer as the source electrode 121 and the drain electrode 124, and can include the same material as the source electrode 121 and the drain electrode 124, and can be formed together using a mask using the same process as the source electrode 121 and the drain electrode 124, but are not limited thereto.

[0257] The first data line DL1 may be disposed on the second insulating layer 104 and covered by the third insulating layer 105. The first data line DL1 may include the same material as the gate electrode 122 and may be formed together with the gate electrode 122 using a mask through the same process, but is not limited thereto.

[0258] The second data line DL2 may be disposed on the third insulating layer 105 and covered by the fourth insulating layer 106. The second data line DL2 may include the same material as the second storage electrode 142 and may be formed together with the second storage electrode 142 using a mask through the same process as the second storage electrode 142, but is not limited thereto.

[0259] The first data line DL1 can be electrically connected to the first data pad DP1 through the first data contact hole CNT1. The second data line DL2 can be electrically connected to the second data pad DP2 through the second data contact hole CNT2.

[0260] Crack prevention pattern (CSP) can be positioned outside the pad area (PA). CSP can also be positioned between the end of the pad area (PA) and the non-display area (NDA).

[0261] However, multiple pads VSSP, VDDP, and DP may not be covered by multiple inorganic films. Multiple inorganic films disposed on the fourth insulating layer 106 can expose multiple pads VSSP, VDDP, and DP. Multiple inorganic films disposed on the fourth insulating layer 106 may not be disposed within the pad area PA.

[0262] Therefore, the flexible film COF can be configured such that at least a portion of it is arranged to overlap with and be attached to the display panel 100, and the flexible film COF can be electrically connected to a plurality of pads VSSP, VDDP and DP of the pad area PA.

[0263] Figure 10 This is a schematic diagram illustrating the path of light emitted from a display panel according to one embodiment. Figure 11 and Figure 12 This is a graph showing the brightness of a display device according to a viewing angle, based on one embodiment.

[0264] Figure 11 and Figure 12 The brightness is shown based on the viewing angle, but Figure 12 The effect of light leakage due to reflected light is shown according to the viewing angle.

[0265] Reference Figure 4 and Figure 10 The first light-blocking pattern BP1 can be set on the first microlens ML1, and the second light-blocking pattern BP2 can be set on the second microlens ML2.

[0266] The first light-blocking pattern BP1 and the second light-blocking pattern BP2 can be set on the two identical parts of the microlenses ML1 and ML2, which are divided by dividing lines DV1 and DV2.

[0267] The first light-blocking pattern BP1 and the second light-blocking pattern BP2 can be respectively disposed on one side (or the first side) of the microlenses ML1 and ML2 in the first direction, which are divided by dividing lines DV1 and DV2.

[0268] The first light-blocking pattern BP1 can block a portion of the first light L1 emitted from the first pixel PX1 that travels on one side of the first direction DR1 in the plan view.

[0269] The second light-blocking pattern BP2 can block a portion of the second light L2 emitted from the second pixel PX2 that travels toward the first direction DR1 in the plan view.

[0270] In addition, each light-blocking pattern BP can block light emitted from the sub-pixel SP on which each light-blocking pattern BP is provided, and can also block light emitted from the sub-pixel SP located around the corresponding sub-pixel SP and incident on the microlens ML of the adjacent sub-pixel SP due to internal reflection of the display panel 100.

[0271] For example, the third light L3 emitted from the first sub-pixel SP1_1 can be reflected inside the display panel 100 and incident on the second microlens ML2 of the second sub-pixel SP2_1. When the path of the third light L3 incident on the second microlens ML2 of the second sub-pixel SP2_1 travels in an undesired direction (towards the side facing the first direction DR1), the third light L3 can be blocked by the second light-blocking pattern BP2 set on the second sub-pixel SP2_1.

[0272] Further reference Figure 11 and Figure 12 ,exist Figure 11 and Figure 12 In the diagram, the horizontal axis represents the viewing angle (°), and the vertical axis represents the brightness (%). Figure 11 The brightness is shown based on the viewing angle.

[0273] Figure 11 The graph can have a bell-shaped curve with a peak at a viewing angle of approximately 0 degrees. However, embodiments of this disclosure are not limited to this, and the viewing angle of the peak of each graph can vary depending on the design of the display device.

[0274] By arranging light-blocking patterns BP1 and BP2 on microlenses ML1 and ML2 to block part of the light emitted from the first pixel PX1 and the second pixel PX2, brightness can be blocked or controlled in some viewing areas.

[0275] Figure 11 The graph can include points where the brightness suddenly decreases (blocks) in a specific viewing area.

[0276] For example, in Figure 11 In the curve graph, the brightness suddenly decreases and converges to 0 at a point near a 30-degree viewing angle, and the brightness continuously converges to 0 at angles after that point. In this case, the light-blocking pattern BP can be set on the microlens ML in the region from a point near a 30-degree viewing angle to the viewing angle after that point. However, the embodiments of this disclosure are not limited to this, and the point where the brightness suddenly decreases in each curve graph can vary depending on the arrangement design of the light-blocking pattern BP.

[0277] By arranging a light-blocking pattern BP, the first light L1 emitted from the first pixel PX1 and the second light L2 emitted from the second pixel PX2 can be blocked (intercepted) at certain viewing angles.

[0278] By arranging light-blocking patterns (BP), it is easier to block brightness to 0 at a specific viewing angle.

[0279] Furthermore, by arranging the light-blocking pattern BP, it is not necessary to change the shape of the microlens ML to be more convex in order to block brightness within a certain viewing angle range, thereby minimizing the reduction in brightness. In addition, the processing of the microlens ML can be simplified, and furthermore, the overall processing of the display device can be simplified.

[0280] exist Figure 12 In the diagram, curve X represents the brightness of a pixel with a light-blocking pattern BP, and curve Y represents the brightness of a pixel without a light-blocking pattern BP.

[0281] exist Figure 12 In the curve diagram, curve Y can represent the light leakage defect caused by internal reflection of light emitted from adjacent sub-pixels SP (e.g., third light L3) at viewing angles between 30 and 40 degrees and between 70 and 90 degrees.

[0282] However, as shown in curve X, when a light-blocking pattern BP is set, the light-blocking pattern BP can block light traveling along an undesirable path. Therefore, light leakage defects caused by internal reflection at undesirable viewing angles (e.g., between 30 and 90 degrees) can be suppressed or prevented.

[0283] By arranging a light-blocking pattern BP on a microlens ML, even when light emitted from an adjacent sub-pixel SP (e.g., the third light L3) is emitted from another sub-pixel SP due to internal reflection, light traveling along an unwanted path can be blocked, thereby preventing and controlling light leakage defects, etc.

[0284] Other embodiments of this disclosure will be described below. For the components included in these other embodiments, those referenced are... Figures 1 to 12 The content described is essentially the same, the same figure labels are given, and repeated content is omitted or briefly described.

[0285] Figure 13 This is a plan view showing the pixel arrangement of a display panel according to another embodiment. Figure 14 It is along Figure 13 A cross-sectional view of line E-E' in the diagram. Figure 15 This is a graph showing the brightness of a display device according to a viewing angle, based on another embodiment.

[0286] Reference Figures 13 to 15 The display panel 100_1 according to this embodiment may include microlenses ML1 and ML2 and light-blocking patterns BP (BP1_1 and BP2_1), and the light-blocking patterns BP (BP1_1 and BP2_1) may be disposed on the other side of the microlenses ML1 and ML2 in the first direction DR1. Figure 15 In the diagram, the horizontal axis represents the viewing angle (°), and the vertical axis represents the brightness (%).

[0287] Each microlens ML1 or ML2 can be divided into two parts (a first part and a second part) according to each dividing line DV1 or DV2. The first part (or the first side) and the second part (or the second side) of each microlens ML1 or ML2 can be respectively set on one side and the other side of each dividing line DV1 or DV2 in the first direction DR1.

[0288] The first light-blocking pattern BP1_1 and the second light-blocking pattern BP2_1 can be disposed on two identical portions of microlenses ML1 and ML2, which are divided by dividing lines DV1 and DV2. For example, the first light-blocking pattern BP1_1 can be disposed on the second portion of the first microlens ML1, which is located on the other side (or the second side) of the first dividing line DV1 along the first direction DR1. Similarly, the second light-blocking pattern BP2_1 can be disposed on the second portion of the second microlens ML2, which is located on the other side (or the second side) of the second dividing line DV2 along the first direction DR1.

[0289] The first light-blocking pattern BP1_1 can block a portion of the light emitted from the first pixel PX1 that travels to the other side of the first direction DR1 in the planar view, and the second light-blocking pattern BP2_1 can block a portion of the light emitted from the second pixel PX2 that travels to the other side of the first direction DR1 in the planar view.

[0290] Figure 15 The curve can have a bell-shaped curve with a peak at a viewing angle of approximately 0 degrees. Figure 15 The graph can include points where the brightness suddenly decreases (blocks) in a specific viewing area.

[0291] By arranging light-blocking patterns BP1_1 and BP2_1 on microlenses ML1 and ML2 to block part of the light emitted from the first pixel PX1 and the second pixel PX2, brightness can be blocked or controlled in some viewing areas.

[0292] For example, in Figure 15 In the curve, the brightness suddenly decreases and converges to 0 at a point near a viewing angle of -30 degrees, and the brightness continuously converges to 0 at angles after that point. In this case, the light blocking pattern BP can be set on the microlens ML in the region from a point near a viewing angle of -30 degrees to the viewing angle after that point.

[0293] By arranging a light-blocking pattern BP, light emitted from the first pixel PX1 and light emitted from the second pixel PX2 can be blocked (intercepted) at certain viewing angles.

[0294] By arranging light-blocking patterns (BP), it is easier to block brightness to zero at a specific viewing angle. Furthermore, the viewing angle at which brightness is blocked can be easily adjusted depending on the placement of the light-blocking patterns (BP).

[0295] Even under these conditions, by arranging the light-blocking pattern BP, the path of light emitted from the pixel PX can be ultimately blocked and controlled, thus easily blocking and controlling the light. Therefore, light leakage defects can be suppressed or prevented, minimizing the reduction in luminous efficiency, and also simplifying the manufacturing process and design of the display device.

[0296] Figure 16 This is a plan view showing the pixel arrangement of a display panel according to yet another embodiment. Figure 17 It is along Figure 16 A cross-sectional view of line F-F' in the diagram. Figure 18 This is a graph showing the brightness of a display device according to a viewing angle, based on yet another embodiment. Figure 18 In the diagram, the horizontal axis represents the viewing angle (°), and the vertical axis represents the brightness (%).

[0297] Reference Figures 16 to 18 The display panel 100_2 according to this embodiment may include microlenses ML1 and ML2 and light-blocking patterns BP (BP1, BP2, BP3_2 and BP4_2). The light-blocking pattern BP may include a first light-blocking pattern BP1 and a second light-blocking pattern BP2, and also includes a third light-blocking pattern BP3_2 and a fourth light-blocking pattern BP4_2.

[0298] The first light-blocking pattern BP1 and the second light-blocking pattern BP2 can be disposed on one side of the microlenses ML1 and ML2 in the first direction DR1.

[0299] The third light-blocking pattern BP3_2 can be disposed on the first microlens ML1, and the fourth light-blocking pattern BP4_2 can be disposed on the second microlens ML2. The third light-blocking pattern BP3_2 and the fourth light-blocking pattern BP4_2 can be disposed on the opposite side of the microlenses ML1 and ML2 in the first direction DR1.

[0300] The first light-blocking pattern BP1 and the third light-blocking pattern BP3_2 disposed on the first microlens ML1 can be disposed separately. The second light-blocking pattern BP2 and the fourth light-blocking pattern BP4_2 disposed on the second microlens ML2 can be disposed separately.

[0301] Each microlens ML1 or ML2 can be divided into two parts (a first part and a second part) according to each dividing line DV1 or DV2. The first part (or the first side) and the second part (or the second side) of each microlens ML1 or ML2 can be respectively set on one side and the other side of each dividing line DV1 or DV2 in the first direction DR1.

[0302] The first light-blocking pattern BP1 and the second light-blocking pattern BP2 can be disposed on two identical portions of microlenses ML1 and ML2 divided by dividing lines DV1 and DV2. For example, the first light-blocking pattern BP1 can be disposed on the first portion of the first microlens ML1 located on one side (or the first side) of the first dividing line DV1 along the first direction DR1. Similarly, the second light-blocking pattern BP2 can be disposed on the first portion of the second microlens ML2 located on one side (or the first side) of the second dividing line DV2 along the first direction DR1.

[0303] The third light-blocking pattern BP3_2 and the fourth light-blocking pattern BP4_2 can be disposed on two identical portions of microlenses ML1 and ML2, which are divided by dividing lines DV1 and DV2. For example, the third light-blocking pattern BP3_2 can be disposed on the second portion of the first microlens ML1, which is located on the other side (or the second side) of the first dividing line DV1 along the first direction DR1, among the two portions divided by the first dividing line DV1. Similarly, the fourth light-blocking pattern BP4_2 can be disposed on the second portion of the second microlens ML2, which is located on the other side (or the second side) of the second dividing line DV2 along the first direction DR1, among the two portions divided by the second dividing line DV2.

[0304] The first light-blocking pattern BP1 can block a portion of the light emitted from the first pixel PX1 that travels toward the first direction DR1 in the planar view, and the second light-blocking pattern BP2 can block a portion of the light emitted from the second pixel PX2 that travels toward the first direction DR1 in the planar view.

[0305] The third light-blocking pattern BP3_2 can block a portion of the light emitted from the first pixel PX1 that travels to the other side of the first direction DR1 in the planar view, and the fourth light-blocking pattern BP4_2 can block a portion of the light emitted from the second pixel PX2 that travels to the other side of the first direction DR1 in the planar view.

[0306] Figure 18 The curve can have a bell-shaped curve with a peak at a viewing angle of approximately 0 degrees. Figure 18 The graph can include points where the brightness suddenly decreases (blocks) in a specific viewing area.

[0307] By arranging light-blocking patterns BP1, BP2, BP3_2 and BP4_2 on microlenses ML1 and ML2 to block part of the light emitted from the first pixel PX1 and the second pixel PX2, brightness can be blocked or controlled in some viewing areas.

[0308] For example, in Figure 18 In the curve, the brightness suddenly decreases and converges to 0 at a point near a viewing angle of -30 degrees and a point near a viewing angle of 30 degrees, and the brightness continuously converges to 0 at angles after the corresponding points. In this case, the light blocking pattern BP can be set on the microlens ML in the region from a point near a viewing angle of -30 degrees and a point near a viewing angle of 30 degrees to the viewing angles after those points.

[0309] By arranging a light-blocking pattern BP, light emitted from the first pixel PX1 and light emitted from the second pixel PX2 can be blocked (intercepted) at certain viewing angles.

[0310] By arranging light-blocking patterns (BP), it is easier to block brightness to zero at a specific viewing angle. Furthermore, the viewing angle at which brightness is blocked can be easily adjusted depending on the placement of the light-blocking patterns (BP).

[0311] Even under these conditions, by arranging the light-blocking pattern BP, the path of light emitted from the pixel PX can be ultimately blocked and controlled, thus easily blocking and controlling the light. Therefore, light leakage defects can be suppressed or prevented, minimizing the reduction in luminous efficiency, and also simplifying the manufacturing process and design of the display device.

[0312] Figure 19 This is a plan view showing the pixel arrangement of a display panel according to yet another embodiment. Figure 20 It is along Figure 19 A cross-sectional view of line G-G' in the diagram.

[0313] Reference Figure 19 and Figure 20 The display panel 100_3 according to this embodiment may include microlenses ML1 and ML2 and light blocking patterns BP (BP1_3 and BP2_3), and the light blocking patterns BP (BP1_3 and BP2_3) may be disposed along the edges of microlenses ML1 and ML2.

[0314] Each microlens ML1 or ML2 can be divided into two parts (a first part and a second part) according to each dividing line DV1 or DV2. The first part (or the first side) and the second part (or the second side) of each microlens ML1 or ML2 can be respectively set on one side and the other side of each dividing line DV1 or DV2 in the first direction DR1.

[0315] The first light-blocking pattern BP1_3 and the second light-blocking pattern BP2_3 can be disposed on both the first and second portions of the microlenses ML1 and ML2, which are divided by dividing lines DV1 and DV2. The first light-blocking pattern BP1_3 and the second light-blocking pattern BP2_3 can be disposed such that a portion of them intersects with the dividing lines DV1 and DV2.

[0316] For example, a first light-blocking pattern BP1_3 can be disposed on the first microlens ML1 and along the edge of the first microlens ML1. The first light-blocking pattern BP1_3 can be configured to expose a portion of the first microlens ML1 and surround the exposed portion of the first microlens ML1. Additionally, a second light-blocking pattern BP2_3 can be disposed on the second microlens ML2 and along the edge of the second microlens ML2. The second light-blocking pattern BP2_3 can be configured to expose a portion of the second microlens ML2 and surround the exposed portion of the first microlens ML2.

[0317] The first light-blocking pattern BP1_3 and the second light-blocking pattern BP2_3 are shown to be integrally formed, but are not limited thereto, and each of the first light-blocking pattern BP1_3 and the second light-blocking pattern BP2_3 may be formed as multiple separate patterns.

[0318] By arranging a light-blocking pattern BP, the first light-blocking pattern BP1_3 can block a portion of the light emitted from the first pixel PX1 that travels toward one side and the other side in the planar direction DR1, and the first light-blocking pattern BP1_3 also blocks a portion of the light emitted from the first pixel PX1 that travels toward one side and the other side in the planar direction DR2.

[0319] The second light-blocking pattern BP2_3 can block a portion of the light emitted from the second pixel PX2 that travels on one side and the other side of the light in the planar view toward the first direction DR1, and the second light-blocking pattern BP2_3 also blocks a portion of the light emitted from the second pixel PX2 that travels on one side and the other side of the light in the planar view toward the second direction DR2.

[0320] By arranging light-blocking patterns BP1_3 and BP2_3 on microlenses ML1 and ML2 to block part of the light emitted from the first pixel PX1 and the second pixel PX2, brightness can be blocked or controlled in some viewing areas.

[0321] By arranging a portion of the light-blocking pattern BP to intersect with the dividing lines DV1 and DV2, light emitted from the first pixel PX1 and light emitted from the second pixel PX2 can be blocked from certain viewing angles. The light travels not only towards one side and the other side of the first direction DR1 but also towards one side and the other side of the second direction DR2.

[0322] By arranging light-blocking patterns (BP), it is easier to block brightness to zero at a specific viewing angle. Furthermore, the viewing angle at which brightness is blocked can be easily adjusted depending on the placement of the light-blocking patterns (BP).

[0323] Even under these conditions, by arranging the light-blocking pattern BP, the path of light emitted from the pixel PX can be ultimately blocked and controlled, thus easily blocking and controlling the light. Therefore, light leakage defects can be suppressed or prevented, minimizing the reduction in luminous efficiency, and also simplifying the manufacturing process and design of the display device.

[0324] Figure 21 This is a plan view showing the pixel arrangement of a display panel according to yet another embodiment. Figure 22 It is along Figure 21 A cross-sectional view of line H-H' in the diagram.

[0325] Reference Figure 21 and Figure 22 In the display panel 100_4 according to this embodiment, the first dividing line DV1 of the first microlens ML1 and the first center EC1 of the light-emitting areas EA1_1, EA1_2, and EA1_3 of the first pixel PX1 may not be aligned, and the second dividing line DV2 of the second microlens ML2 and the second center EC2 of the light-emitting areas EA2_1, EA2_2, and EA2_3 of the second pixel PX2 may not be aligned. Furthermore, at least a portion of the light-emitting portion 150 may be configured to be inclined in the thickness direction (third direction DR3).

[0326] Specifically, in the region where the light-emitting portion 150 is provided, a portion of the upper surface of the second protective layer 112 may be formed as an inclination. The light-emitting portion 150 may be provided on at least a portion of the inclination of the second protective layer 112. Therefore, at least a portion of each of the anode electrode 151 and the organic layer 152 may be tilted. At least a portion of each of the anode electrode 151 and the organic layer 152 may be tilted (inclination) toward the microlens ML.

[0327] Each of the anode electrode 151 and the organic layer 152 may be disposed on at least a portion of the inclined second protective layer 112. The organic layer 152 may be disposed on the inclined second protective layer 112 over the entire region, but is not limited thereto.

[0328] The anode electrode 151 and the organic layer 152 disposed on the inclined second protective layer 112 can be configured to be inclined (tilted) corresponding to the inclined second protective layer 112. Therefore, a portion of the cathode electrode 153 disposed on the organic layer 152 can be configured to be inclined.

[0329] The anode electrode 151 and the organic layer 152 can be configured to be inclined in the thickness direction (third direction DR3) of the display panel 100, including the light-emitting regions EA1_1 (1_1), EA2_1 (2_1), and their periphery. The upper surfaces of the anode electrode 151 and the organic layer 152 can be inclined in the thickness direction (third direction DR3) of the display panel 100. The orientation of the upper surfaces of the anode electrode 151 and the organic layer 152 can be inclined in the thickness direction (third direction DR3) of the display panel 100.

[0330] The upper surface of the anode electrode 151 and the upper surface of the organic layer 152 may be tilted relative to the upper surface of the first protective layer 111.

[0331] The anode electrode 151 and organic layer 152 of the first pixel PX1 can be tilted in the same direction as the anode electrode 151 and organic layer 152 of the second pixel PX2. The anode electrode 151 and organic layer 152 of the first pixel PX1 can be tilted at the same slope as the anode electrode 151 and organic layer 152 of the second pixel PX2, but are not limited thereto, and can have different slopes.

[0332] By adjusting the arrangement of the light-blocking pattern BP and the degree of tilt of the anode electrode 151 and organic layer 152 of each pixel PX1 or PX2, it is easier to control the brightness according to the viewing angle.

[0333] The upper surface of the anode electrode 151 and the upper surface of the organic layer 152 of the first pixel PX1 can be tilted toward the first microlens ML1, and the upper surface of the anode electrode 151 and the upper surface of the organic layer 152 of the second pixel PX2 can be tilted toward the second microlens ML2.

[0334] Therefore, the light emitted from each sub-pixel SP can tilt in the thickness direction (third direction DR3) of the display panel 100.

[0335] The first center EC1 of the 1_1 light-emitting area EA1_1 of the 1_1 sub-pixel SP1_1 and the first dividing line DV1 of the first microlens ML1 disposed on the 1_1 sub-pixel SP1_1 may not be aligned. In the planar view, the dividing line DV1 of the first microlens ML1 may deviate from the first center EC1 of the 1_1 light-emitting area EA1_1 to the other side (left side in the planar view) in the first direction DR1.

[0336] The description of the misalignment of subpixel SP1_1 can also be applied in substantially the same way to the remaining subpixels SP1_2 and SP1_3 of the first pixel PX1. However, the degree of misalignment between the microlens ML and the light-emitting region EA can differ in each of the subpixels SP1_1, SP1_2, and SP1_3 of the first pixel PX1.

[0337] However, the implementation of this disclosure is not limited thereto, and the direction and degree of misalignment between the first dividing line DV1 of the first microlens ML1 and the first center EC1 of the luminescent region EA1_1 can vary according to the design.

[0338] The second center EC2 of the 2_1 luminous region EA2_1 of the 2_1 sub-pixel SP2_1 and the second dividing line DV2 of the second microlens ML2 disposed on the 2_1 sub-pixel SP2_1 may not be aligned. In the plan view, the second dividing line DV2 of the second microlens ML2 may deviate from the second center EC2 of the 2_1 luminous region EA2_1 to the other side (left side in the plan view) in the first direction DR1.

[0339] The description of the misalignment of subpixel SP2_1 can also be applied in essentially the same way to the remaining subpixels SP2_2 and SP2_3 of the second pixel PX2. However, the degree of misalignment between the microlens ML and the luminous region EA can differ in each of the subpixels SP2_1, SP2_2, and SP2_3 of the second pixel PX2.

[0340] However, the implementation of this disclosure is not limited thereto, and the direction and degree of misalignment between the second dividing line DV2 of the second microlens ML2 and the second center EC2 of the 2_1 light-emitting region EA2_1 can vary according to the design.

[0341] The opening (or light-emitting area EA) of the sub-pixel SP and the light-emitting part 150 disposed around the opening can be configured to tilt relative to the thickness direction (third direction DR3), and the light L1 and L2 emitted from the light-emitting part 150 can travel in the direction tilted relative to the thickness direction (third direction DR3).

[0342] Because the microlens ML and the light-emitting area EA are misaligned, even when the light L1 and L2 emitted from the light-emitting part 150 travel at the same time while tilted relative to the thickness direction (third direction DR3), each beam of light L1 or L2 can travel toward the microlens ML1 or ML2 of each pixel PX1 or PX2.

[0343] Subpixels SP1_1, SP1_2, and SP1_3 located in the first pixel PX1 can emit light L1 to the left side of the planar view (the other side on the first direction DR1). Subpixels SP2_1, SP2_2, and SP2_3 located in the second pixel PX2 can emit light L2 to the left side of the planar view (the other side on the first direction DR1).

[0344] In other words, light L1 emitted from sub-pixels SP1_1, SP1_2, and SP1_3 of the first pixel PX1 can travel simultaneously while tilted relative to the thickness direction (third direction DR3) to the other side of the first direction DR1. Light L2 emitted from sub-pixels SP2_1, SP2_2, and SP2_3 of the second pixel PX2 can also travel simultaneously while tilted relative to the thickness direction (third direction DR3) to the other side of the first direction DR1.

[0345] The direction and degree of misalignment between the microlens ML and the luminous region EA can vary depending on the direction of travel of light emitted from the sub-pixels SP of each pixel PX1 or PX2.

[0346] Light L1 emitted from the first pixel PX1 can be emitted toward the first microlens ML1, which does not have the first light-blocking pattern BP1. Light L2 emitted from the second pixel PX2 can be emitted toward the second microlens ML2, which does not have the second light-blocking pattern BP2.

[0347] In addition, since the light-emitting parts 150 of some pixels PX1 and PX2 are tilted, the path of light emitted from each pixel PX1 or PX2 can be more easily controlled.

[0348] Even under these conditions, by arranging the light-blocking pattern BP, it is easier to block the brightness to zero at a specific viewing angle. Furthermore, by arranging the light-blocking pattern BP on the microlens ML, the path of light emitted from the pixel PX can be ultimately blocked and controlled, thus easily blocking and controlling the light. Therefore, light leakage defects can be suppressed or prevented, minimizing the reduction in luminous efficiency, and also simplifying the manufacturing process and design of the display device.

[0349] Figure 23 This is a plan view of a display device according to yet another embodiment. Figure 24 yes Figure 23 A magnified view of region Q2 in the image. Figure 25 It is along Figure 24 A cross-sectional view of line K-K' in the diagram.

[0350] Figure 24 This is a diagram of a display device 5 according to another embodiment, in which the flexible film COF, the motherboard MB, and the driver ICDIC are omitted from region Q2.

[0351] Reference Figures 23 to 25 In the display device 5 according to this embodiment, the gate driving unit GIP (see...) Figure 1 It is not necessary to set it separately in the non-display area NDA, and the pixel gate driving unit GIA can be set in the display area DA.

[0352] A pixel gate driving unit (GIA) can be configured as multiple pixel gate drivers, and each pixel gate driving unit (GIA) can be connected to each of the multiple pixels (PX). Pixel gate driving units (GIAs) can be disposed around pixels (PX). Pixel gate driving units (GIAs) can be disposed between adjacent pixels (PX).

[0353] For example, a pixel gate driving unit GIA can be disposed between adjacent pixels PX in the first direction DR1. Pixels PX and pixel gate driving units GIA can be disposed alternately and repeatedly in the first direction DR1. Pixels PX can be disposed continuously and repeatedly in the second direction DR2. Pixel gate driving units GIA can be disposed continuously and repeatedly in the second direction DR2.

[0354] The pixel gate drive unit (GIA) can perform the same actions as the gate drive unit (GIP) (see [link]). Figure 1 They serve essentially the same function. The pixel gate drive unit (GIA) can include at least one transistor.

[0355] The pixel gate drive unit (GIA) can be electrically connected to the adjacent pixel (PX).

[0356] The pixel gate driving unit (GIA) receives gate control signals from the driver IC (DIC) via the gate control line (GCL_5). The GIA can then generate scan signals and emission signals (or emission control signals) based on these gate control signals. Therefore, it can control the driving of adjacent pixels (PX).

[0357] Since the pixel gate drive unit (GIA) is located in the display area (DA), the non-display area (NDA) or the border area can be minimized, thereby providing the user with an improved aesthetic.

[0358] The display device 5 may also include a gate control line GCL_5 and a gate control pad GCP.

[0359] The gate control line GCL_5 can be located in the non-display area NDA and the display area DA. The gate control line GCL_5 can be located in the second non-display area NDA2, but is not limited thereto. The gate control line GCL_5 can be located in the extension direction of the second non-display area NDA2.

[0360] The gate control line GCL_5 can be partially disposed in the second non-display area NDA2, and can extend from the second non-display area NDA2 to the pixel gate driving unit GIA of the display area DA. The gate control line GCL_5 can be electrically connected to multiple pixel gate driving units GIA disposed in the display area DA.

[0361] The gate control pad (GCP) can be located within the pad region PA. Within the pad region PA, the gate control pad (GCP) is shown positioned between the high-potential voltage pad (VDDP) and the data pad (DP), but is not limited to this, and the arrangement of the gate control pad (GCP) can vary depending on the design.

[0362] The gate control pad (GCP) may include, but is not limited to, the same material as the gate control line (GCL_5). The gate control pad (GCP) and the gate control line (GCL_5) may be integrally formed, but are not limited to this.

[0363] The gate control pad GCP and gate control line GCL_5 can be disposed on the fourth insulating layer 106. The gate control pad GCP and gate control line GCL_5 can be disposed at the source electrode 121 (see...). Figure 5 ) and drain electrode 124 (see Figure 5 On the same layer, and may include the same material as the source electrode 121 and drain electrode 124, and the gate control pad GCP, gate control line GCL, source electrode 121 and drain electrode 124 may be formed together using a mask through the same process, but the embodiments of this disclosure are not limited thereto.

[0364] Multiple pads VSSP, VDDP, DP, and GCP may not be covered by multiple inorganic films. Multiple inorganic films disposed on the fourth insulating layer 106 may expose multiple pads VSSP, VDDP, DP, and GCP. Multiple inorganic films disposed on the fourth insulating layer 106 may not be disposed within the pad area PA.

[0365] For example, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can be disposed in the notched non-display area N_NDA up to the end of the substrate 101, but may not be disposed in the pad area PA. Therefore, the multiple pads VSSP, VDDP, DP, and GCP disposed on the fourth insulating layer 106 can be exposed, and the display panel 100_5 can be adhered to and electrically connected to the flexible film COF.

[0366] Due to the gate drive unit GIP (see Figure 1Since the pixel gate drive unit (GIA) is omitted from the non-display area NDA and is located in the display area DA, the non-display area NDA can be reduced, thereby reducing the bezel area and increasing the display area DA.

[0367] Even under these conditions, by arranging the light-blocking pattern BP, it is easier to block the brightness to zero at a specific viewing angle. Furthermore, by arranging the light-blocking pattern BP on the microlens ML, the path of light emitted from the pixel PX can be ultimately blocked and controlled, thus easily blocking and controlling the light. Therefore, light leakage defects can be suppressed or prevented, minimizing the reduction in luminous efficiency, and also simplifying the manufacturing process and design of the display device.

[0368] The display device according to various embodiments of the present disclosure can be described as follows.

[0369] According to embodiments of the present disclosure, a display device is provided, the display device comprising: a substrate including a display area of ​​a display screen and a non-display area surrounding the display area; a plurality of pixels disposed in the display area; microlenses disposed on the plurality of pixels; and a light-blocking pattern disposed on the surface of the microlenses, wherein each of the plurality of pixels includes a plurality of sub-pixels, the microlenses are disposed in each of the plurality of sub-pixels, the plurality of sub-pixels of the pixels are disposed along a first direction, and the plurality of pixels are disposed in the first direction and a second direction intersecting the first direction.

[0370] According to various embodiments of the present disclosure, a microlens may include a first portion located on a first side and a second portion located on a second side, the second side being the side opposite to the first side relative to a dividing line, and a light-blocking pattern may be disposed on one of the first portion and the second portion of the microlens.

[0371] According to various embodiments of this disclosure, the first portion of the microlens may be located on one side of the first direction, and the second portion may be located on the other side of the first direction.

[0372] According to various embodiments of this disclosure, a light-blocking pattern may be disposed on a first portion of a microlens, and the light-blocking pattern may restrict a portion of the light emitted from a sub-pixel from traveling toward one side in a first direction.

[0373] According to various embodiments of this disclosure, light-blocking patterns can be directly disposed on the surface of the microlens.

[0374] According to various embodiments of the present disclosure, the display device may further include a lens protection layer disposed on a microlens, wherein the surface of the microlens exposed by the light blocking pattern can be in direct contact with the lens protection layer.

[0375] According to various embodiments of this disclosure, a microlens may include a first portion located on a first side and a second portion located on a second side, the second side being the side opposite to the first side relative to the dividing line, and a light-blocking pattern may be disposed on the first portion and the second portion of the microlens.

[0376] According to various embodiments of this disclosure, the light-blocking pattern can be integrally disposed across the first and second portions of the microlens.

[0377] According to some embodiments of this disclosure, the light-blocking pattern can be set along the edge of the microlens.

[0378] According to various embodiments of the present disclosure, the light blocking pattern may include a first light blocking pattern disposed on a first portion of the microlens and a second light blocking pattern disposed on a second portion of the microlens, wherein the first light blocking pattern and the second light blocking pattern may be separated.

[0379] According to various embodiments of the present disclosure, the display device may further include a light-emitting portion between a substrate and a microlens, wherein the light-emitting portion may include an anode electrode, an organic layer on the anode electrode, and a cathode electrode between the organic layer and the microlens.

[0380] According to various embodiments of the present disclosure, the display device may further include a dam disposed between the anode electrode and the cathode electrode, wherein the dam may define the light-emitting area of ​​a sub-pixel.

[0381] According to various embodiments of this disclosure, the center of the light-emitting region may not be aligned with the dividing line of the microlens, and the dividing line of the microlens may be located at one of the two sides in the first direction relative to the center.

[0382] According to various embodiments of the present disclosure, the display device may further include a protective layer between the substrate and the light-emitting portion, wherein the upper surface of the anode electrode may be inclined relative to the upper surface of the protective layer.

[0383] According to various embodiments of this disclosure, the upper surface of the anode electrode may be tilted toward the microlens.

[0384] According to various embodiments of this disclosure, a sub-pixel may further include a non-light-emitting region disposed around the light-emitting region, wherein a light-blocking pattern may be disposed in the non-light-emitting region.

[0385] According to embodiments of the present disclosure, a display device is provided, comprising: a substrate including a display area of ​​a display screen and a non-display area surrounding the display area; a thin-film transistor disposed on the substrate; a protective layer disposed on the thin-film transistor; a light-emitting portion disposed on the protective layer; a microlens disposed on the light-emitting portion; and a light-blocking pattern disposed on the microlens. The display device further comprises a plurality of pixels disposed in the display area, and each of the plurality of pixels includes a plurality of sub-pixels, wherein the microlens is disposed on each of the plurality of sub-pixels, and the light-blocking pattern is directly disposed on the surface of the microlens.

[0386] According to various embodiments of the present disclosure, a microlens may include a first portion located on a first side and a second portion located on a second side, the second side being the side opposite to the first side relative to a dividing line, and a light-blocking pattern may be disposed on one of the first portion and the second portion of the microlens.

[0387] According to various embodiments of this disclosure, a microlens may include a first portion located on a first side and a second portion located on a second side, the second side being the side opposite to the first side relative to the dividing line, and a light-blocking pattern may be disposed on the first portion and the second portion of the microlens.

[0388] According to various embodiments of the present disclosure, the display device may further include a lens protection layer disposed on a microlens, wherein the surface of the microlens exposed by the light blocking pattern can be in direct contact with the lens protection layer.

[0389] Although embodiments have been described above with reference to the accompanying drawings, those skilled in the art to which this disclosure pertains will understand that the technical configurations described above can be implemented in other specific forms without altering their technical spirit or essential characteristics. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. Furthermore, the scope of the embodiments is determined by the appended claims rather than the detailed description. Additionally, the meaning and scope of the claims, as well as all modifications or alterations derived from their equivalents, should be interpreted as being included within the scope of the embodiments.

[0390] Description of reference numerals in the attached figures

[0391] 1: Display device

[0392] 100: Display panel

[0393] 101: Substrate

[0394] NCP: Notch

[0395] DA: Display Area

[0396] NDA: Non-display area

[0397] NDA1: First Non-Display Area

[0398] NDA2: Second Non-Display Area

[0399] N_NDA: Non-display area of ​​the notch

[0400] E_NDA: Extended non-display area

[0401] PA: Pad area

[0402] PX: pixel

[0403] SP: Subpixel

[0404] EA: Emitting area

[0405] NEA: Non-luminescent area

[0406] ML: Microlens

[0407] BP: Light-blocking pattern

[0408] DV: Divider line

[0409] EC: Center

[0410] 150: Light-emitting part

[0411] 170: Packaging Department

Claims

1. A display device, comprising: A substrate, the substrate including a display area of ​​a display screen and a non-display area surrounding the display area; Multiple pixels are set in the display area; Microlenses disposed on the plurality of pixels; as well as A light-blocking pattern is disposed on the surface of the microlens. Each of the plurality of pixels includes a plurality of sub-pixels. The microlens is disposed on each of the plurality of sub-pixels. Multiple subpixels of a pixel are arranged along a first direction, and The plurality of pixels are disposed in the first direction and in the second direction intersecting the first direction.

2. The display device according to claim 1, wherein, The microlens includes a first portion located on a first side and a second portion located on a second side, the second side being the side opposite to the first side relative to the dividing line, and The light-blocking pattern is disposed on one of the first and second portions of the microlens.

3. The display device according to claim 2, wherein, The first portion of the microlens is located on one side of the first direction, and the second portion of the microlens is located on the other side of the first direction.

4. The display device according to claim 3, wherein, The light-blocking pattern is disposed on the first portion of the microlens, and The light-blocking pattern restricts a portion of the light emitted from the sub-pixel from traveling toward one side in the first direction.

5. The display device according to claim 3, wherein, The light-blocking pattern is disposed on the second part of the microlens, and The light-blocking pattern restricts a portion of the light emitted from the sub-pixel from traveling toward the other side in the first direction.

6. The display device according to claim 1, wherein, The light-blocking pattern is directly disposed on the surface of the microlens.

7. The display device according to claim 6 further includes a lens protective layer disposed on the microlens. in, The surface of the microlens exposed by the light-blocking pattern is in direct contact with the lens protective layer.

8. The display device according to claim 1, wherein, The microlens includes a first portion located on a first side and a second portion located on a second side, the second side being the side opposite to the first side relative to the dividing line, and The light-blocking pattern is disposed on the first and second portions of the microlens.

9. The display device according to claim 8, wherein, The light-blocking pattern is integrally disposed across the first and second portions of the microlens.

10. The display device according to claim 9, wherein, The light-blocking pattern is set along the edge of the microlens.

11. The display device according to claim 8, wherein, The light-blocking pattern includes a first light-blocking pattern disposed on a first portion of the microlens and a second light-blocking pattern disposed on a second portion of the microlens. The first light-blocking pattern and the second light-blocking pattern are separated.

12. The display device according to claim 1, further comprising a light-emitting portion between the substrate and the microlens. in, The light-emitting part includes an anode electrode, an organic layer on the anode electrode, and a cathode electrode between the organic layer and the microlens.

13. The display device according to claim 12, further comprising a dam disposed between the anode electrode and the cathode electrode. in, The embankment defines the light-emitting area of ​​the sub-pixel.

14. The display device according to claim 13, wherein, The center of the light-emitting area is not aligned with the dividing line of the microlens, and the dividing line of the microlens is located on one side and the other side of the first direction relative to the center.

15. The display device according to claim 14, further comprising a protective layer between the substrate and the light-emitting portion. in, The upper surface of the anode electrode is inclined relative to the upper surface of the protective layer.

16. The display device according to claim 15, wherein, The upper surface of the anode electrode is inclined toward the microlens.

17. The display device according to claim 13, wherein, The sub-pixel also includes a non-light-emitting region disposed around the light-emitting region. The light-blocking pattern is disposed in the non-light-emitting area.

18. A display device, comprising: A substrate, the substrate including a display area of ​​a display screen and a non-display area surrounding the display area; Thin-film transistors disposed on the substrate; A protective layer disposed on the thin-film transistor; The light-emitting part is disposed on the protective layer; Microlenses disposed on the light-emitting part; as well as The light-blocking pattern is set on the microlens, and The display device further includes a plurality of pixels disposed in the display area, and each of the plurality of pixels includes a plurality of sub-pixels. The microlens is disposed on each of the plurality of sub-pixels, and The light-blocking pattern is directly disposed on the surface of the microlens.

19. The display device according to claim 18, wherein, The microlens includes a first portion located on a first side and a second portion located on a second side, the second side being the side opposite to the first side relative to the dividing line, and The light-blocking pattern is disposed on one of the first and second portions of the microlens.

20. The display device according to claim 18, wherein, The microlens includes a first portion located on a first side and a second portion located on a second side, the second side being the side opposite to the first side relative to the dividing line, and The light-blocking pattern is disposed on the first and second portions of the microlens.

21. The display device according to claim 18, further comprising a lens protective layer disposed on the microlens, in, The surface of the microlens exposed by the light-blocking pattern is in direct contact with the lens protective layer.

22. The display device according to claim 20, wherein, The light-blocking pattern is integrally disposed across the first and second portions of the microlens.

23. The display device according to claim 20, wherein, The light-blocking pattern includes a first light-blocking pattern disposed on a first portion of the microlens and a second light-blocking pattern disposed on a second portion of the microlens. The first light-blocking pattern and the second light-blocking pattern are separated.

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