Display device

Abstract

A display device according to an embodiment of the present specification includes: a substrate including a display area including a first pixel and a second pixel each having a plurality of sub-pixels, and a non-display area surrounding the display area; a first microlens corresponding to each of the plurality of sub-pixels of the first pixel on the substrate; a second microlens corresponding to each of the plurality of sub-pixels of the second pixel on the substrate; a first light shielding pattern on a surface of the first microlens; a second light shielding pattern on a surface of the second microlens; wherein the plurality of sub-pixels of the first pixel and the plurality of sub-pixels of the second pixel are arranged in a first direction; the first pixel and the second pixel are arranged adjacent to each other in a second direction intersecting with the first direction, and each of the first micro lens and the second micro lens comprises a first part located on the first side and a second part located on the second side; a first light shielding pattern disposed on a first portion of the first microlens; and a second light shielding pattern disposed on a second portion of the second microlens.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0111091, filed on August 20, 2024, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This specification relates to a display device. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is increasing, and various types of display devices (such as liquid crystal display (LCD) devices and organic light-emitting diode (OLED) display devices) are being utilized.

[0005] Among these display devices, OLED displays have the advantage of wider viewing angles and higher contrast due to their self-emissive nature, and are lighter, thinner, and consume less power than LCD devices because they do not require a separate backlight. Furthermore, OLED displays can be driven with low voltage, have fast response times, and, most importantly, have low manufacturing costs.

[0006] OLED displays can also be used in vehicle-mounted displays. In vehicles, displays located in front of the driver's seat and front passenger seat need to limit the driver's field of vision based on driving conditions. The viewing angle also needs to be limited based on user privacy and information protection requirements. Summary of the Invention

[0007] This specification relates to display devices that provide an improved aesthetic design.

[0008] This specification also relates to providing display devices capable of displaying different images depending on the viewing angle.

[0009] This specification also relates to a display device that, when a vehicle display is applied, can provide images in various ways that can be viewed by each of the driver sitting in the driver's seat and the front passenger sitting in the front passenger seat.

[0010] This specification also relates to providing a display device in which the path of light emitted from a light-emitting portion can be easily controlled.

[0011] This specification also relates to a display device in which light leakage defects can be prevented and controlled.

[0012] This specification also relates to a display device in which the reduction in brightness of the display device can be minimized, thereby minimizing the reduction in luminous efficiency.

[0013] This specification also relates to a display device in which crosstalk between different images can be suppressed or prevented when different images are displayed according to the viewing angle.

[0014] The purpose of this specification is not limited to the above-described purposes, and other technical purposes can be inferred from the following embodiments.

[0015] According to one embodiment of this specification, a display device is provided, comprising: a substrate including a display area and a non-display area surrounding the display area, the display area including a first pixel and a second pixel, each of the first pixel and the second pixel including a plurality of sub-pixels; a first microlens corresponding to each of the plurality of sub-pixels of the first pixel on the substrate; a second microlens corresponding to each of the plurality of sub-pixels of the second pixel on the substrate; a first light-shielding pattern on a surface of the first microlens; and a second light-shielding pattern on a surface of the second microlens, wherein the plurality of sub-pixels of the first pixel and the plurality of sub-pixels of the second pixel are arranged in a first direction, the first pixel and the second pixel are arranged adjacent to each other in a second direction intersecting the first direction, each of the first microlens and the second microlens includes a first portion located at a first side and a second portion located at a second side, the second side being a side opposite to the first side relative to a dividing line, the first light-shielding pattern being disposed on the first portion of the first microlens, and the second light-shielding pattern being disposed on the second portion of the second microlens.

[0016] According to another embodiment of this specification, a display device is provided, comprising: a substrate, the substrate including a display area and a non-display area surrounding the display area, the display area including a first pixel and a second pixel, each of the first pixel and the second pixel including a plurality of sub-pixels; a thin-film transistor disposed on the substrate; a protective layer disposed on the thin-film transistor; a light-emitting portion disposed on the protective layer and including an anode electrode, an organic layer and a cathode electrode; an encapsulation layer disposed on the light-emitting portion; a microlens disposed on the encapsulation layer and including a first microlens corresponding to the first pixel and a second microlens corresponding to the second pixel; and a light-shielding diagram. According to the plan, the light-shielding pattern includes a first light-shielding pattern disposed on the first microlens and a second light-shielding pattern disposed on the second microlens. The plurality of sub-pixels of the first pixel and the plurality of sub-pixels of the second pixel are arranged in the first direction. The first pixel and the second pixel are arranged adjacent to each other in a second direction intersecting the first direction. The positions of the first light-shielding pattern on the first microlens and the positions of the second light-shielding pattern on the second microlens are different. The first light-shielding pattern restricts some light emitted from the first pixel that travels towards one side in the first direction, and the second light-shielding pattern restricts some light emitted from the second pixel that travels towards the other side in the first direction.

[0017] Further details regarding other embodiments are included in the detailed description and accompanying drawings.

[0018] According to embodiments of this specification, an improved aesthetic can be provided for display devices.

[0019] According to embodiments of this specification, different images can be displayed depending on the viewing angle.

[0020] According to embodiments of this specification, when a vehicle display is applied, images that can be viewed by each of the driver sitting in the driver's seat and the front passenger sitting in the front passenger seat can be provided in different ways.

[0021] According to the embodiments of this specification, the path of light emitted from the light-emitting part can be easily controlled.

[0022] According to the embodiments in this specification, light leakage defects can be prevented or controlled.

[0023] According to the embodiments of this specification, the reduction in brightness of the display device can be minimized, thereby minimizing the reduction in luminous efficiency.

[0024] According to embodiments of this specification, crosstalk between different images can be suppressed or prevented when displaying different images according to the viewing angle.

[0025] According to embodiments of this specification, crosstalk between different images can be suppressed or prevented based on the viewing angle, thereby improving the quality of the image displayed on the display device and reducing power consumption in response to the need for lower power consumption required to display the image.

[0026] However, the effects that can be obtained from this specification are not limited to those described above, and those skilled in the art to which this specification pertains will be able to clearly understand other effects not mentioned based on the following description. Attached Figure Description

[0027] Figure 1 This is a plan view of a display device according to one embodiment.

[0028] Figure 2 yes Figure 1 A magnified view of region Q1 in the image.

[0029] Figure 3 Is only shown Figure 2 The view of the display panel.

[0030] Figure 4 This is a plan view illustrating the pixel arrangement of a display panel according to one embodiment.

[0031] Figure 5 It is along Figure 4 A cross-sectional view of line D-D' in the diagram.

[0032] Figure 6 It was captured from different angles. Figure 5 A cross-sectional view of the touch portion.

[0033] Figure 7 It is along Figure 1 A cross-sectional view of line A-A' in the diagram.

[0034] Figure 8 It is along Figure 3 A cross-sectional view of line B-B' in the diagram.

[0035] Figure 9 It is along Figure 3 A cross-sectional view of line C-C' in the diagram.

[0036] Figure 10 This is a schematic diagram illustrating the path of light emitted from a display panel according to one embodiment.

[0037] Figure 11 This is a graph showing the brightness of a display device according to one embodiment.

[0038] Figure 12This is an enlarged view showing the pixel arrangement of a display panel according to another embodiment.

[0039] Figure 13 It is along Figure 12 A cross-sectional view of line E-E' in the diagram.

[0040] Figure 14 This is a plan view of a display device according to yet another embodiment.

[0041] Figure 15 yes Figure 14 A magnified view of region Q2 in the image.

[0042] Figure 16 It is along Figure 15 A cross-sectional view of line F-F' in the diagram. Detailed Implementation

[0043] In the following description, embodiments will be described with reference to the accompanying drawings. In the specification, when a first component (or region, layer, portion, etc.) is described as being "on," "connected to," or "coupled to" a second component, it means that the first component may be directly connected to / coupled to the second component, or that a third component may be disposed therebetween.

[0044] The same reference numerals indicate the same parts. Additionally, in the drawings, the thickness, scale, and dimensions of parts are exaggerated for effective description of the technical content. The term "and / or" includes all or one combination that can be defined by the associated configuration.

[0045] Terms such as "first" and "second" may be used to describe various components, but these components are not limited by these terms. Terms are used only for the purpose of distinguishing one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the embodiment. Unless the context clearly indicates otherwise, the singular includes the plural.

[0046] Terms such as "below," "on the lower side," "above," and "on the upper side" are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative concepts and are described with respect to the orientation of the markings in the drawings.

[0047] It should be understood that terms such as “comprising” or “having” are intended to specify the presence of features, quantities, steps, operations, components, parts or combinations thereof described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, parts or combinations thereof.

[0048] Figure 1 This is a plan view of a display device according to one embodiment. Figure 2 yes Figure 1A magnified view of region Q1 in the image. Figure 3 Is only shown Figure 2 The view of the display panel.

[0049] Figure 3 yes Figure 2 The view omits the flexible film COF, motherboard MB, and driver IC DIC, excluding the display panel 100. Figure 3 In this document, the ratios between components have been adjusted for ease of description.

[0050] refer to Figures 1 to 3 The display device 1 may be a device that includes both a display function for displaying video and a touch sensing function for sensing user touch, but is not limited thereto. For example, the display device 1 may include only one of a display function for displaying an image and a touch sensing function for sensing user touch.

[0051] Display device 1 can be an electroluminescent display device or a micro-light-emitting diode display device including a touch sensor. The electroluminescent display device including a touch sensor can be an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode display device, or an inorganic light-emitting diode display device.

[0052] The display device 1 in this embodiment can be a vehicle display device, but is not limited thereto. For example, the description of the display device 1 can be applied without limiting the type of device, as long as the display device includes display functionality.

[0053] When the display device 1 according to this embodiment is a vehicle display device, the display device 1 may include functions for operating at least some of the various functions of the vehicle and functions for displaying various information about the vehicle.

[0054] When the display device 1 according to this embodiment is a vehicle display device, the display device 1 can be installed on the vehicle's dashboard. The display device 1 can be installed across the driver's seat and the front passenger seat installed in the front seats of the vehicle, but is not limited thereto.

[0055] Both the driver (in the driver's seat) and the passenger (co-driver) (in the front passenger seat) can use display device 1. Display device 1 can provide different images to the driver and the passenger (co-driver). However, embodiments of this specification are not limited thereto, and display device 1 can provide the same image to both the driver and the passenger (co-driver).

[0056] Display device 1 may include display panel 100. Display panel 100 may include display area DA and non-display area NDA.

[0057] The display area DA can be an area that emits light outward to display on the screen. The display area DA can also include the function of sensing user touch. In this case, the display area DA can correspond to the touch sensing area, but is not limited to this.

[0058] The display area DA may correspond to the shape of the display panel 100, but is not limited to it.

[0059] The display panel 100 may include a plurality of pixels PX. The plurality of pixels PX may be set in the display area DA. The plurality of pixels PX may be repeatedly set in the first direction DR1 and the second direction DR2.

[0060] The non-display area NDA can be an area that does not emit light to the outside so as not to display a screen. The non-display area NDA can be located around the display area DA. The non-display area NDA can surround the display area DA, but the embodiments in this specification are not limited thereto. The border area of ​​the display device 1 can be defined by the non-display area NDA, but the embodiments in this specification are not limited thereto.

[0061] The display panel 100 may be a rigid display panel, but is not limited thereto. The display panel 100 may also be a flexible display panel whose shape can be deformed, such as a foldable, bendable, rollable, or stretchable display panel.

[0062] The display panel 100 may include a first long edge LE1, a second long edge LE2, a first short edge SE1, and a second short edge SE2 forming the edges of the display panel 100.

[0063] The first long edge LE1 and the second long edge LE2 may extend in the first direction DR1, and the first short edge SE1 and the second short edge SE2 may extend in the direction between the first direction DR1 and the second direction DR2. The first long edge LE1 and the second long edge LE2 may have two ends connected by the first short edge SE1 and the second short edge SE2.

[0064] The first long edge LE1 can be located on one side of the second long edge LE2 in the second direction DR2. The first long edge LE1 and the second long edge LE2 can extend parallel to each other, but are not limited thereto.

[0065] The length of the first long edge LE1 can be less than the length of the second long edge LE2. Therefore, the first short edge SE1 and the second short edge SE2 can extend in the intersecting direction, but are not limited thereto.

[0066] The first direction DR1 and the second direction DR2 may be intersecting directions. The first direction DR1 and the second direction DR2 may be orthogonal, but are not limited thereto. The first direction DR1 and the second direction DR2 are provided to illustrate the description of the invention; the first direction DR1 and the second direction DR2 are relative, and the embodiments described herein are not limited thereto.

[0067] In the plan view, the first long edge LE1 can be set above the display area DA, and the second long edge LE2 can be set below the display area DA.

[0068] In the plan view, the first short edge SE1 can be set on the right side of the display area DA, and the second short edge SE2 can be set on the left side of the display area DA.

[0069] The display panel 100 may include a curved notch NCP. The notch NCP may be formed at the second long edge LE2, but is not limited thereto. That is, the second long edge LE2 may extend entirely in the first direction DR1, but may include a notch NCP that curves toward the first long edge LE1.

[0070] Because of the recessed NCP, components such as the driver's seat handle can be placed on the corresponding part to maximize the display area DA that can be displayed on the screen, thereby improving user convenience and aesthetics.

[0071] The non-display area NDA may include a first non-display area NDA1 disposed along a first long edge LE1, a first short edge SE1, and a second short edge SE2, and a second non-display area NDA2 disposed along a second long edge LE2. The second non-display area NDA2 may be disposed along the second long edge LE2, which includes a curved notch NCP.

[0072] The first non-display area NDA1 can be disposed on one side and the other side of the display area DA in the first direction DR1, and on one side of the display area DA in the second direction DR2.

[0073] The second non-display area NDA2 may include a notched non-display area N_NDA surrounding the notch NCP, and an extended non-display area E_NDA surrounding the notched non-display area N_NDA.

[0074] The extended non-display area E_NDA can extend from the notched non-display area N_NDA in the first direction DR1. The extended non-display area E_NDA can be located between the notched non-display area N_NDA and the first non-display area NDA1. The extended non-display area E_NDA can connect the notched non-display area N_NDA to the first non-display area NDA1.

[0075] The display device 1 may also include a pad area PA, a gate drive unit GIP, a motherboard MB, a flexible film COF, a driver ICDIC, a gate line GL, a gate control line GCL, a data line DL, a low-potential voltage line VSSL, and a high-potential voltage line VDDL.

[0076] The pad area PA can overlap with the flexible film COF. The pad area PA can be attached to the flexible film COF. In other words, the display panel 100 and the flexible film COF can be attached through the pad area PA.

[0077] The pad area PA can be set in the non-display area NDA. The pad area PA can be set in the second non-display area NDA2. The pad area PA can be set in each of the notched non-display area N_NDA and the extended non-display area E_NDA.

[0078] The pad area PA can include multiple pads. The pad area PA can include a low-potential voltage pad VSSP, a high-potential voltage pad VDDP, a first data pad DP1, and a second data pad DP2. The low-potential voltage pad VSSP, the high-potential voltage pad VDDP, the first data pad DP1, and the second data pad DP2 can be set in the pad area PA.

[0079] However, the embodiments described herein are not limited thereto, and the pad region PA disposed in the region overlapping with the flexible film COF disposed at both ends of the flexible film COF disposed along the non-display region NDA may also include a gate control pad (not shown).

[0080] The gate driving unit GIP can be disposed in the non-display area NDA. The gate driving unit GIP can be disposed on at least one side of the display area DA in the first direction DR1, but is not limited thereto. In a plan view, the gate driving unit GIP can be disposed on the left side and the other side of the display area DA.

[0081] The gate drive unit (GIP) may include multiple transistors G120 (see...) Figure 7 Transistor G120 is located in the gate drive unit GIP (see...). Figure 7 The gate drive unit (GIP) can be connected to the pixel PX via the gate line GL. The gate drive unit (GIP) can apply the gate signal to each pixel PX via the gate line GL.

[0082] The gate drive unit (GIP) can receive gate control signals from the driver IC (DIC) via the gate control line (GCL). The GIP can then generate scan signals and light emission signals (or light emission control signals) based on the gate control signals.

[0083] The gate driving unit (GIP) may include a scan driver and a light emission signal driver. The scan driver can generate scan signals in a row-by-row manner and supply scan signals to scan lines to drive one or more scan lines connected to each pixel row (PX). The light emission signal driver can generate light emission signals in a row-by-row manner and supply light emission signals to light emission signal lines to drive one or more light emission signal lines connected to each pixel row (PX).

[0084] The motherboard MB can be connected to the display panel 100 via a flexible film COF. The motherboard MB can also be electrically connected to the pixel PX of the display area DA via the flexible film COF. The motherboard MB and the flexible film COF can be electrically connected via multiple pads: VSSP, VDDP, and DP.

[0085] The motherboard (MB) can have various types of components for supplying various signals to the driver IC (DIC), such as gate control signals, drive signals, and data signals. The motherboard (MB) can be a printed circuit board, but is not limited to this.

[0086] The motherboard MB can be connected to the display panel 100 via a flexible film COF in the second non-display area NDA2. Multiple motherboards can be provided along the second non-display area NDA2, but are not limited to this. The number of motherboard MBs can vary depending on the design.

[0087] At least one motherboard MB can be set around the notch NCP and connected to the display panel 100 via a flexible film COF in the notch non-display area N_NDA.

[0088] The flexible film COF can be attached to the display panel 100 and the motherboard MB. The flexible film COF can be attached to and electrically connected to each of the display panel 100 and the motherboard MB. That is, the display panel 100 and the motherboard MB can be electrically connected via the flexible film COF. The flexible film COF can be provided as multiple flexible films, but is not limited to this.

[0089] The flexible film COF can be attached to the display panel 100 in the second non-display area NDA2. The flexible film COF can be repeatedly set along the second non-display area NDA2. The flexible film COF can be attached to the display panel 100 across the notched non-display area N_NDA and the extended non-display area E_NDA.

[0090] A single motherboard MB can be electrically connected to the display panel 100 via at least one flexible film COF. For example, among a plurality of motherboard MBs disposed along the second non-display area NDA2, the motherboard MBs located at both ends can be electrically connected to the display panel 100 via one flexible film COF, and the remaining motherboard MBs can be electrically connected to the display panel 100 via two flexible film COFs.

[0091] The flexible film COF can be electrically connected to the pad area PA. Therefore, the flexible film COF can supply gate control signals, drive signals, power supply voltage, data voltage, etc. to the multiple pixels PX and gate drive units GIP disposed in the display area DA.

[0092] The flexible COF (Chip-on-Foil) film can be a flexible insulating film. Flexible COF films can include, for example, polycarbonate, polyethylene terephthalate, polyimide, polyamide, polyester, polyacrylate, polymethyl methacrylate, etc., but are not limited to these.

[0093] The driver IC DIC can be mounted on a flexible film COF. The driver IC DIC can be mounted using methods such as chip-on-glass, chip-on-film, or carrier packaging, depending on the mounting method. In this disclosure, the driver IC DIC is described as being mounted on a flexible film COF using a chip-on-film method, but it is not limited to this.

[0094] A driver IC (DIC) can drive a display device 1. A driver IC (DIC) can process data signals used for displaying images, as well as various drive signals used for processing these data signals. A driver IC (DIC) may include a gate driver IC, a data driver IC, etc.

[0095] Gate lines GL can extend from gate drive units GIP and connect to pixels PX. Gate lines GL can electrically connect gate drive units GIP and pixels PX. Gate lines GL can apply gate signals from gate drive units GIP to each pixel PX.

[0096] The gate control line (GCL) can be located in the non-display area (NDA). The gate control line (GCL) can extend from the pad area (PA) to the gate drive unit (GIP) and can be electrically connected to the gate drive unit (GIP).

[0097] The gate control line (GCL) applies gate control signals to the gate driver unit (GIP). These gate control signals can be transmitted from the motherboard (MB) or the driver IC (DIC). The GCL electrically connects the gate driver unit (GIP) to the motherboard (MB) or the driver IC (DIC).

[0098] The gate control line (GCL) can be electrically connected to one of the multiple flexible film COFs (COFs) connected to the display panel 100 along the second non-display area NDA2, and located at both ends of the flexible film COF. The gate control line (GCL) can be located at the outermost edge of the multiple lines connected to a flexible film COF, but is not limited thereto.

[0099] The data line DL extends from the pad area PA and can connect to the pixel PX in the display area DA. The data line DL applies data signals to each pixel PX. These data signals can be applied from the motherboard MB or the driver IC DIC. The data line DL electrically connects the pixel PX to the motherboard MB or the driver IC DIC.

[0100] The data cable DL may include a first data cable DL1 and a second data cable DL2. The data cable DL can be connected to data pads DP1 and DP2. The first data cable DL1 can be electrically connected to and in contact with the first data pad DP1 through a first data contact hole CNT1. The second data cable DL2 can be electrically connected to and in contact with the second data pad DP2 through a second data contact hole CNT2.

[0101] A low-potential voltage line VSSL can be positioned within the non-display area NDA to surround the display area DA. The low-potential voltage line VSSL can be positioned within the non-display area NDA, with the display area DA and the gate drive unit GIP inserted between them. In other words, the gate drive unit GIP can be positioned between the display area DA and the low-potential voltage line VSSL.

[0102] The low-potential voltage line VSSL can apply a low-potential voltage to the pixel PX. The low-potential voltage line VSSL can be electrically connected to the cathode electrode 153 of the pixel PX (see [link to documentation]). Figure 5 To apply a low potential voltage.

[0103] The low-potential voltage line VSSL can be connected to the pad area PA. The low-potential voltage line VSSL can be physically connected to the low-potential voltage pad VSSP and electrically connected to the low-potential voltage pad VSSP. The low-potential voltage line VSSL and the low-potential voltage pad VSSP can be formed as a single unit, but are not limited to this.

[0104] A high-potential voltage line VDDL can be positioned between the display area DA and the low-potential voltage line VSSL. The high-potential voltage line VDDL can apply a high-potential voltage to the pixel PX. The high-potential voltage line VDDL can be electrically connected to the anode electrode 151 of the pixel PX (see [reference]). Figure 5 To apply a high potential voltage.

[0105] The high-potential voltage line VDDL can be connected to the pad area PA. The high-potential voltage line VDDL can be physically connected to the high-potential voltage pad VDDP and electrically connected to the high-potential voltage pad VDDP. The high-potential voltage line VDDL can contact the high-potential voltage pad VDDP through the high-potential contact hole S_CNT.

[0106] However, the embodiments described in this specification are not limited thereto, and the high-potential voltage line VDDL and the high-potential voltage pad VDDP can be formed integrally. For example, the high-potential voltage line VDDL can be formed of the same material and the same conductive layer as the high-potential voltage pad VDDP, and the high-potential voltage line VDDL and the high-potential voltage pad VDDP can be formed together using the same masking process.

[0107] Display device 1 may further include a dam portion DMP. The dam portion DMP may be disposed in a non-display area NDA. The dam portion DMP may be configured to surround the display area DA, but is not limited thereto. At least a portion of the dam portion DMP may be configured to overlap with a low-potential voltage line VSSL. The dam portion DMP may be disposed between the display area DA and the pad area PA in the second non-display area NDA2.

[0108] Figure 4 This is an enlarged view showing the pixel arrangement of a display panel according to one embodiment. Figure 4 The plan view is an enlarged view showing a portion of the flat surface structure of the display area DA in which pixels PX are disposed.

[0109] refer to Figure 4 The display panel 100 may include a first pixel PX1 and a second pixel PX2. The first pixel PX1 and the second pixel PX2 may be set in the display area DA.

[0110] Each of the first pixel PX1 and the second pixel PX2 can be repeatedly set in the first direction DR1. The first pixel PX1 and the second pixel PX2 can be alternately repeated in the second direction DR2.

[0111] Each pixel PX1 or PX2 may include sub-pixels SP (SP1_1, SP1_2, SP1_3, SP2_1, SP2_2 and SP2_3).

[0112] The first pixel PX1 may include sub-pixels SP1_1 (1_1), SP1_2 (1_2), and SP1_3 (1_3). Sub-pixels SP1_1 (1_1), SP1_2 (1_2), and SP1_3 (1_3) may be arranged in a row in the first direction.

[0113] Subpixel SP1_1 (1_1) can emit red (R) light, subpixel SP1_2 (1_2) can emit green (G) light, and subpixel SP1_3 (1_3) can emit blue (B) light. However, the color of the light emitted by each subpixel SP1_1, SP1_2, or SP1_3 is not limited to this and can be diverse.

[0114] Sub-pixels SP1_1, SP1_2, and SP1_3 can each include luminous regions EA1_1, EA1_2, and EA1_3, and non-luminous regions NEA1_1, NEA1_2, and NEA1_3 surrounding the luminous regions EA1_1, EA1_2, and EA1_3.

[0115] Subpixel SP1_1 can include a light-emitting area EA1_1 and a non-light-emitting area NEA1_1 surrounding the light-emitting area EA1_1.

[0116] Subpixel SP1_2 can include a light-emitting region EA1_2 and a non-light-emitting region NEA1_2 surrounding the light-emitting region EA1_2.

[0117] The 1_3 sub-pixel SP1_3 may include a 1_3 luminous region EA1_3 and a 1_3 non-luminous region NEA1_3 set around the 1_3 luminous region EA1_3.

[0118] The second pixel PX2 may include sub-pixels SP2_1 (2_1), SP2_2 (2_2), and SP2_3 (2_3). Sub-pixels SP2_1 (2_1), SP2_2 (2_2), and SP2_3 (2_3) may be arranged in a row on the first direction DR1.

[0119] Subpixel SP2_1 (2_1) can emit red (R) light, subpixel SP2_2 (2_2) can emit green (G) light, and subpixel SP2_3 (2_3) can emit blue (B) light. However, the color of the light emitted by each subpixel SP2_1, SP2_2, or SP2_3 is not limited to this and can be diverse.

[0120] Sub-pixels SP2_1 (2-1), SP2_2 (2-2), and SP2_3 (2-3) can each include luminescent regions EA2_1, EA2_2, and EA2_3, and non-luminescent regions NEA2_1, NEA2_2, and NEA2_3 surrounding the luminescent regions EA2_1, EA2_2, and EA2_3.

[0121] The 2_1 sub-pixel SP2_1 may include a 2_1 luminous region EA2_1 and a 2_1 non-luminous region NEA2_1 set around the 2_1 luminous region EA2_1.

[0122] The 2_2 sub-pixel SP2_2 may include a 2_2 luminous region EA2_2 and a 2_2 non-luminous region NEA2_2 set around the 2_2 luminous region EA2_2.

[0123] The 2_3 sub-pixel SP2_3 may include a 2_3 luminous region EA2_3 and a 2_3 non-luminous region NEA2_3 set around the 2_3 luminous region EA2_3.

[0124] Microlenses ML (ML1 and ML2) can be disposed on each of pixels PX1 and PX2. The first microlens ML1 can be disposed on the first pixel PX1, and the second microlens ML2 can be disposed on the second pixel PX2.

[0125] Microlenses ML can be set on sub-pixels SP. Microlenses ML can correspond to each sub-pixel SP.

[0126] The first microlens ML1 can be disposed on the first pixel PX1 and on each of the sub-pixels SP1_1, SP1_2, and SP1_3.

[0127] The second microlens ML2 can be set on the second pixel PX2 and on each of the sub-pixels SP2_1, SP2_2, and SP2_3.

[0128] Microlenses ML1 and ML2 can control the path of light emitted from pixels PX1 and PX2, respectively. Microlenses ML1 and ML2 can control the path of light emitted from pixels PX1 and PX2 in different directions.

[0129] For example, the first microlens ML1 can control the light emitted from the first pixel PX1 to travel to the other side in the first direction DR1 in the planar diagram, and the second microlens ML2 can control the light emitted from the second pixel PX2 to travel to the other side in the first direction DR1 in the planar diagram.

[0130] Therefore, pixels PX1 and PX2 can display different images and videos, and display device 1 (see...) Figure 1 It can display two different images and videos depending on the viewing angle.

[0131] When display device 1 (see Figure 1When used in a vehicle, the screen displayed to the driver (DRIVER) in the driver's seat and the screen displayed to the passenger (CO-DRIVER) in the front passenger seat can be controlled separately, and different screens can be displayed to the driver and the passenger (CO-DRIVER).

[0132] However, the embodiments described herein are not limited thereto, and one of pixels PX1 and PX2 may provide a screen for display to both the driver and the passenger co-driver.

[0133] Light-shielding patterns BP (BP1 and BP2) can be disposed on microlenses ML. The light-shielding patterns BP (BP1 and BP2) can include a first light-shielding pattern BP1 and a second light-shielding pattern BP2. The first light-shielding pattern BP1 can be disposed on a first microlens ML1, and the second light-shielding pattern BP2 can be disposed on a second microlens ML2.

[0134] The light-blocking pattern BP can include materials capable of absorbing and blocking light. For example, the light-blocking pattern BP can include black pigments and / or dyes, but is not limited to this.

[0135] The light-blocking pattern BP can block light from the luminous part 150 (see...) Figure 5 The path of some of the light emitted. Therefore, each pixel PX1 or PX2 can display a different image, and the user can receive different images and videos depending on the viewing angle.

[0136] The light-shielding pattern BP can be set in the non-luminous area NEA, but is not limited to this, and some light-shielding patterns BP can be set to extend to the luminous area EA.

[0137] The first light-blocking pattern BP1 and the second light-blocking pattern BP2 can be disposed at different positions on the microlens ML. The first light-blocking pattern BP1 can be disposed on one side of the first microlens ML1 in the first direction DR1, and the second light-blocking pattern BP2 can be disposed on the other side of the second microlens ML2 in the first direction DR1.

[0138] The microlens ML may include dividing lines DV (DV1 and DV2). The dividing lines DV may include a first dividing line DV1 and a second dividing line DV2.

[0139] The dividing line DV can refer to a virtual line that divides the microlens ML into two parts. The microlens ML can be divided into two substantially equal parts by the dividing line DV, but is not limited to this. The two parts of the microlens ML divided by the dividing line DV can include, but are not limited to, symmetrical shapes, and the two parts of the microlens ML divided by the dividing line DV can have different shapes and sizes.

[0140] In such Figure 4 In the plan view, the dividing line DV can pass through the center EC (EC1 and EC2) of the luminous region EA, but is not limited to this.

[0141] The first center EC1 can refer to the center of each of the light-emitting areas EA1_1, EA1_2, and EA1_3 of the sub-pixels SP1_1, SP1_2, and SP1_3 of the first pixel PX1.

[0142] The second center EC2 can refer to the center of each of the light-emitting areas EA2_1, EA2_2, and EA2_3 of the sub-pixels SP2_1, SP2_2, and SP2_3 of the second pixel PX2.

[0143] The first microlens ML1 may include a first dividing line DV1, and the second microlens ML2 may include a second dividing line DV2.

[0144] Each dividing line DV1 or DV2 can be, for example... Figure 4 The planar diagram extends along the second direction DR2 and has thickness in the thickness direction (the third direction DR3). Each dividing line DV1 or DV2 may be substantially the same, but is not limited to this, and the flat surface shape of each dividing line DV1 or DV2 may vary depending on the shape of each microlens ML1 or ML2.

[0145] Each microlens ML1 or ML2 can be divided into two parts (a first part and a second part) according to each dividing line DV1 or DV2. The first part and the second part of each microlens ML1 or ML2 can be respectively set on one side and the other side of each dividing line DV1 or DV2 in the first direction DR1.

[0146] The first light-shielding pattern BP1 and the second light-shielding pattern BP2 can be disposed on two different portions of microlenses ML1 and ML2 divided by dividing lines DV1 and DV2. For example, in the two portions of the first microlens ML1 divided by the first dividing line DV1, the first light-shielding pattern BP1 can be disposed on the first portion of the first microlens ML1 located on one side (or the first side) of the first dividing line DV1 in the first direction DR1. Furthermore, in the two portions of the second microlens ML2 divided by the second dividing line DV2, the second light-shielding pattern BP2 can be disposed on the second portion of the second microlens ML2 located on the other side (or the second side) of the second dividing line DV2 in the first direction DR1.

[0147] The first light-blocking pattern BP1 can block some light emitted from the first pixel PX1 that travels to one side in the first direction DR1 in the planar view, and the second light-blocking pattern BP2 can block some light emitted from the second pixel PX2 that travels to the other side in the first direction DR1 in the planar view.

[0148] Because of the light-shielding pattern BP and microlenses ML, the path of light emitted from the display panel 100 can be more easily controlled, and light leakage defects that may occur between pixels PX can be prevented. Therefore, even when the first pixel PX1 and the second pixel PX2 display different screens, crosstalk that may occur between images and videos displayed on each pixel PX1 or PX2 can be suppressed or prevented. Furthermore, the quality of images and videos displayed on each pixel PX1 or PX2 can be improved, and the display device 1 can be minimized (see [reference]). Figure 1 The brightness of the light is reduced, thereby minimizing the reduction in luminous efficiency.

[0149] A microlens ML is shown as being disposed in each sub-pixel SP, but embodiments described herein are not limited thereto. For example, depending on the design of each sub-pixel SP, the microlens ML disposed on each sub-pixel SP can be provided as two or more microlenses. When an opening (light-emitting region EA) formed in a sub-pixel SP is provided as multiple openings, the microlens ML can be disposed in each opening, or multiple microlenses ML can be disposed in one opening.

[0150] In the following text, reference will be made to Figure 5 Describes the cross-sectional structure of the display area DA of the display panel 100 containing pixels PX.

[0151] Figure 5 It is along Figure 4 A cross-sectional view of line D-D' in the diagram. Figure 6 It was captured from different angles. Figure 5 A cross-sectional view of the touch portion.

[0152] Figure 7 It is along Figure 1 A cross-sectional view of line A-A' in the diagram. Figure 8 It is along Figure 3 A cross-sectional view of line B-B' in the diagram. Figure 9 It is along Figure 3 A cross-sectional view of line C-C' in the diagram.

[0153] Figure 7 The cross-sectional structure of the first non-display area NDA1 is shown. Figure 8 and Figure 9 The cross-sectional structure of the notched non-display area N_NDA of the second non-display area NDA2 is shown. Figure 8 and Figure 9 The description can also be applied in essentially the same way to the extended non-display area E_NDA.

[0154] First, refer to Figures 4 to 6 Describes the cross-section of the display area DA.

[0155] The display panel 100 may include a substrate 101, a thin-film transistor 120, a storage electrode 140, a light-emitting portion 150, an encapsulation portion 170, and a touch portion 180 in the display area DA. However, the embodiments described in this specification are not limited thereto.

[0156] The substrate 101 can provide space on which various components can be mounted. The substrate 101 can correspond to Figure 1 The display panel 100 has a flat surface shape. That is, the substrate 101 may include a notched NCP. The substrate 101 may include the display area DA and the non-display area NDA of the display panel 100 in substantially the same manner.

[0157] The substrate 101 may include one or more plastic materials, but is not limited thereto, and may include glass materials.

[0158] The substrate 101 may be a multi-substrate substrate comprising a first substrate 101a, a second substrate 101b, and a third substrate 103c, each of which comprises a plastic material such as polyimide; however, the embodiments described herein are not limited thereto. For example, the substrate 101 may be a single substrate formed from a single layer.

[0159] Substrate 101 may include a rigid substrate. However, the embodiments described herein are not limited thereto, and substrate 101 may include a flexible substrate.

[0160] A buffer layer 102 may be disposed on the substrate 101. The buffer layer 102 may minimize or delay the diffusion of moisture or oxygen through the substrate 101. The buffer layer 102 may be formed by alternatingly stacking silicon nitride (SiNx) and silicon oxide (SiOx) at least once, but the embodiments in this specification are not limited thereto.

[0161] This specification describes the buffer layer 102 as being formed as multiple layers consisting of three layers, but the number of layers forming the buffer layer 102 is not limited to this, and the buffer layer 102 can be formed as a single layer.

[0162] A light-shielding layer 126 may be disposed on the buffer layer 102. The light-shielding layer 126 prevents light from being transmitted to the semiconductor layer 123 of the thin-film transistor 120. For example, the semiconductor layer 123 may be configured to overlap with the light-shielding layer 126. The light-shielding layer 126 may be formed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof, but the embodiments described herein are not limited thereto.

[0163] A first insulating layer 103 may be disposed on the light-shielding layer 126. The first insulating layer 103 can prevent short circuits between components of the thin-film transistor 120 and the light-shielding layer 126. The first insulating layer 103 may be formed of the same material as the buffer layer 102, but the embodiments described herein are not limited thereto. For example, the first insulating layer 103 may be formed of inorganic materials such as silicon nitride (SiNx) or silicon oxide (SiOx), but the embodiments described herein are not limited thereto.

[0164] The thin-film transistor 120 may be disposed on the first insulating layer 103. The thin-film transistor 120 may include a source electrode 121, a gate electrode 122, a semiconductor layer 123, and a drain electrode 124.

[0165] Semiconductor layer 123 may be disposed on first insulating layer 103. Semiconductor layer 123 may include metal oxide semiconductor (e.g., indium gallium zinc oxide (IGZO)) and silicon-based semiconductor materials (e.g., amorphous silicon or polycrystalline silicon), but the embodiments described herein are not limited thereto. Semiconductor layer 123 may include a source region, a drain region, and a channel region between the source region and the drain region.

[0166] Because polycrystalline semiconductor layers have higher mobility than amorphous semiconductor layers and oxide semiconductor layers, power consumption can be lower and reliability can be excellent. Therefore, driving transistors can be formed from polycrystalline semiconductor layers, but the embodiments in this specification are not limited thereto.

[0167] The second insulating layer 104 may be disposed on the semiconductor layer 123. The second insulating layer 104 may be formed of the same material as the first insulating layer 103, but the embodiments described herein are not limited thereto. The second insulating layer 104 can prevent short circuits between the semiconductor layer 123 and another component of the thin-film transistor 120.

[0168] The gate electrode 122 may be disposed on the second insulating layer 104. The gate electrode 122 may be disposed on the second insulating layer 104 to overlap with the channel region of the semiconductor layer 123. The gate electrode 122 may be formed of a single layer or multiple layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or compounds thereof, but the embodiments described herein are not limited thereto. The gate electrode 122 may be disposed together with the gate line, but the embodiments described herein are not limited thereto.

[0169] The third insulating layer 105 may be disposed on the gate electrode 122. The third insulating layer 105 may be formed of the same material as the first insulating layer 103 or the second insulating layer 104, but the embodiments in this specification are not limited thereto.

[0170] The storage electrode 140 may be spaced apart from the thin-film transistor 120. The storage electrode 140 may include a first storage electrode 141 and a second storage electrode 142.

[0171] The first storage electrode 141 may be formed of the same material as the gate electrode 122 and formed on the same layer, but the embodiments in this specification are not limited thereto.

[0172] The second storage electrode 142 may be disposed on the first storage electrode 141. The second storage electrode 142 may be disposed on the third insulating layer 105, and the third insulating layer 105 between the first storage electrode 141 and the second storage electrode 142 may serve as a dielectric to generate a capacitor. The second storage electrode 142 may be formed of the same material as the first storage electrode 141, but the embodiments described herein are not limited thereto.

[0173] The fourth insulating layer 106 may be disposed on the second storage electrode 142. The fourth insulating layer 106 may be formed of the same material as the first insulating layer 103, the second insulating layer 104 or the third insulating layer 105, but the embodiments in this specification are not limited thereto.

[0174] The source electrode 121 and the drain electrode 124 can be disposed on the fourth insulating layer 106.

[0175] The source electrode 121 and drain electrode 124 can be electrically connected to the semiconductor layer 123 through contact holes. The source electrode 121 and drain electrode 124 can be formed of a metallic material. For example, the source electrode 121 and drain electrode 124 can be formed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but the embodiments in this specification are not limited thereto.

[0176] The source electrode 121 and the drain electrode 124 can be disposed together with the data line. For example, the data line can be formed of the same material as the source electrode 121 and the drain electrode 124 and formed on the same layer, but the embodiments in this specification are not limited thereto.

[0177] The thin-film transistor 120 may be a driving transistor, although it is not shown. However, the display panel 100 may also include a switching transistor, but the embodiments described herein are not limited thereto.

[0178] The first protective layer 111 can be disposed on the source electrode 121 and the drain electrode 124.

[0179] The first protective layer 111 can planarize the upper part of the thin-film transistor 120 and protect the thin-film transistor 120. The first protective layer 111 can be formed of an organic material. For example, the first protective layer 111 can be formed of an organic material including acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin, but the embodiments in this specification are not limited thereto.

[0180] The second protective layer 112 may be disposed on the first protective layer 111. The second protective layer 112 may be formed of the same material as the first protective layer 111, but the embodiments described herein are not limited thereto.

[0181] The connecting electrode 145 can be disposed between the first protective layer 111 and the second protective layer 112.

[0182] The connection electrode 145 can electrically connect the thin-film transistor 120 to the light-emitting portion 150. The connection electrode 145 can be formed of the same material as the source electrode 121 and the drain electrode 124, but the embodiments in this specification are not limited thereto.

[0183] The connecting electrode 145 can contact the drain electrode 124 through a contact hole formed in the first protective layer 111, and can be electrically connected to the drain electrode 124.

[0184] The connecting electrode 145 may be formed of a single layer or multiple layers of any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but the embodiments in this specification are not limited thereto.

[0185] The light-emitting portion 150 may be disposed on the second protective layer 112. The light-emitting portion 150 may include an anode electrode 151, an organic layer 152, and a cathode electrode 153.

[0186] The anode electrode 151 may be disposed on the second protective layer 112. The anode electrode 151 may be electrically connected to the thin-film transistor 120 through a contact hole formed in the second protective layer 112.

[0187] The anode electrode 151 may be a reflective electrode that reflects light, but the embodiments described herein are not limited thereto. The anode electrode 151 may comprise a metallic material with high reflectivity, such as a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and indium tin oxide (ITO) (ITO / Al / ITO), or an APC alloy, and may be formed from a single layer or multiple layers, but the embodiments described herein are not limited thereto.

[0188] For example, the cathode electrode 153 may include materials such as indium tin oxide (ITO) or indium zinc oxide (IZO), but the embodiments in this specification are not limited thereto.

[0189] Organic layer 152 may be disposed on anode electrode 151. Organic layer 152 may include one or more light-emitting structures (or one or more light-emitting elements) stacked on anode electrode 151, which may employ a hole transfer layer and an electron transfer layer in either the order of hole transfer layer and electron transfer layer or the reverse order of hole transfer layer. For example, hole transfer layer may include hole transport layer, hole injection layer, electron blocking layer, p-type charge generation layer, etc., but the embodiments of this specification are not limited thereto. For example, electron transfer layer may include electron transport layer, electron injection layer, hole blocking layer, n-type charge generation layer, etc., but the embodiments of this specification are not limited thereto.

[0190] The organic layer 152 may be an organic light-emitting layer, an inorganic light-emitting layer, a quantum dot light-emitting layer, a micro light-emitting diode, a miniature light-emitting diode, etc., but the embodiments in this specification are not limited to these. For example, the organic layer 152 of the display panel 100 according to one embodiment of this specification may include an organic light-emitting layer. The organic layer 152 may be a white light-emitting layer, but the embodiments in this specification are not limited to this.

[0191] The cathode electrode 153 may be disposed on the organic layer 152. The cathode electrode 153 may be a transparent electrode that transmits light, but the embodiments described herein are not limited thereto. For example, the cathode electrode 153 may include a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a metal that transmits visible light, but the embodiments described herein are not limited thereto.

[0192] A capping layer 156 may be further disposed on the cathode electrode 153. The capping layer 156 can minimize damage to the cathode electrode 153 of the light-emitting element EL and the organic layer 152 located below the cathode electrode 153 by the external light source. The capping layer 156 may be formed of an organic or inorganic film.

[0193] The capping layer 156 can be an inorganic film made of materials such as LiF, and may further include an organic film, but the embodiments described herein are not limited thereto. For example, the capping layer 156 may be formed of a stacked structure of organic and inorganic films, and the thickness of the organic film may be different from the thickness of the inorganic film. In this case, the thickness of the organic film may be greater than the thickness of the inorganic film. As another example, the capping layer 156 may be formed of two or more layers by stacking materials with different refractive indices. Therefore, the luminous efficiency of the display panel 100 can be improved.

[0194] A dam 154 can be provided to expose the anode electrode 151. The dam 154 can define an opening (or light-emitting region EA) of the sub-pixel SP and can be configured to cover the edge of the anode electrode 151. An organic layer 152 can be disposed in the opening of the sub-pixel SP. That is, the organic layer 152 can be disposed on the anode electrode 151 exposed by the dam 154.

[0195] However, the embodiments described in this specification are not limited to this, and the organic layer 152 can be disposed on both the opening (light-emitting area EA) of the sub-pixel SP and the embankment 154. That is, the organic layer 152 can be disposed in the entire display area DA of the display panel 100.

[0196] The dam 154 can be formed of a material containing black pigment or an organic material, such as benzocyclobutene resin, polyimide resin, acrylic resin, photosensitive polymer, etc., but the embodiments in this specification are not limited thereto. When the dam 154 is formed of a material containing black pigment or black dye, the dam 154 can be an opaque dam. When the dam 154 is formed of a material containing black pigment or black dye, it can block external light or light reflected from the outside, thereby further improving the brightness of the display device.

[0197] Spacers (not shown) may be further provided on the embankment 154. The spacers (not shown) may be formed of the same material as the embankment 154, but the embodiments described herein are not limited thereto. The spacers (not shown) can prevent mask sagging during the masking process, thereby suppressing or preventing defects such as embossing and scratches on the display panel 100.

[0198] The encapsulation portion 170 may be disposed on the embankment portion 154 or the light-emitting portion 150. The encapsulation portion 170 may include one or more insulating layers. For example, the encapsulation portion 170 may include a first inorganic encapsulation layer 171, an organic encapsulation layer 172 formed on the first inorganic encapsulation layer 171, and a second inorganic encapsulation layer 173 formed on the organic encapsulation layer 172. The encapsulation portion 170 may include one or more inorganic layers and one or more organic layers. For example, the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173 may include inorganic materials, and the organic encapsulation layer 172 may include organic materials, but the embodiments in this specification are not limited thereto.

[0199] The first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173 can be configured to extend around the dam portion DMP, and the organic encapsulation layer 172 can terminate inside the dam portion DMP. That is, the organic encapsulation layer 172 can be disposed inside the region surrounded by the dam portion DMP without extending beyond the dam portion DMP.

[0200] The touch portion 180 may be disposed on the package portion 170. The touch portion 180 may include a touch buffer layer 181, a first touch electrode 182, a first touch insulating layer 183, a black matrix BM, a second touch insulating layer 184, a second touch electrode 185, and a third touch insulating layer 186.

[0201] Touch buffer layer 181 may be disposed on encapsulation portion 170. For example, touch buffer layer 181 may be disposed on second inorganic encapsulation layer 173. Touch buffer layer 181 may be formed of the same material as buffer layer 102, but the embodiments in this specification are not limited thereto.

[0202] The first touch electrode 182 can be disposed on the touch buffer layer 181.

[0203] The first touch insulating layer 183 may be disposed on the first touch electrode 182. The first touch insulating layer 183 may be formed of silicon oxide (SiOx), silicon nitride (SiNx) or multiple layers thereof, but the embodiments in this specification are not limited thereto.

[0204] The black matrix BM can be disposed on the first touch insulating layer 183. The black matrix BM can include a material capable of absorbing light. The black matrix BM can include, but is not limited to, black pigments or dyes. The black matrix BM can prevent light leakage defects that may occur between sub-pixels SP.

[0205] The second touch insulating layer 184 may be disposed on the black matrix BM. The second touch insulating layer 184 may include an organic insulating material. For example, the second touch insulating layer 184 may be formed of acrylic acid, benzocyclobutene (BCB), polyimide (PI), or polyamide (PA), but is not limited thereto.

[0206] The second touch electrode 185 may be disposed on the second touch insulating layer 184. The second touch electrode 185 may include a 1a touch electrode 185a extending in the first direction DR1 and a 1b touch electrode 185b extending in the second direction DR2, which is different from the first direction.

[0207] The first touch electrode 182 can be electrically connected to the 2a touch electrode 185a through a contact hole formed in the second touch insulating layer 184. For example, the 2a touch electrode 185a and the first touch electrode 182 can extend in the first direction DR1.

[0208] The first touch electrode 182 and the second touch electrode 185 may comprise metallic materials. For example, the second touch electrode 185 and the first touch electrode 182 may be formed of titanium (Ti), nickel (Ni), aluminum (Al), or alloys thereof and may be formed of three layers (e.g., titanium (Ti) / aluminum (Al) / titanium (Ti)), but the embodiments described herein are not limited thereto.

[0209] One of the first touch electrode 182 and the second touch electrode 185 may include a touch detection function, and the other may include a touch driving function, but the embodiments in this specification are not limited thereto.

[0210] The third touch insulating layer 186 may be disposed on the second touch electrode 185. The third touch insulating layer 186 may be formed of the same material as the first touch insulating layer 183, but is not limited thereto.

[0211] Microlenses ML (ML1 and ML2) can be disposed on the third touch insulating layer 186. Microlenses ML can be hemispherical or semi-cylindrical, but are not limited to these. The shape of microlenses ML can vary depending on the size, shape, etc. of the light-emitting region EA.

[0212] Microlenses ML1 and ML2 can control the path of light emitted from pixels PX1 and PX2, respectively. Microlenses ML1 and ML2 can control the path of light emitted from pixels PX1 and PX2 in different directions.

[0213] Therefore, pixels PX1 and PX2 can display different images and videos, and display device 1 (see...) Figure 1 It can display two different images and videos depending on the viewing angle.

[0214] In addition, by arranging microlenses ML (ML1 and ML2), a wide viewing angle can be ensured, brightness can be improved, and leakage light and reflected light can be blocked, thereby preventing light leakage.

[0215] Each microlens ML (ML1 or ML2) may include dividing lines DV (DV1 or DV2). In an orthogonal planar diagram (see...) Figure 4 The cross-section cut by each dividing line DV1 or DV2 in (see) Figure 5 In this embodiment, each dividing line DV1 or DV2 may be aligned with the center EC1 or EC2 of each luminescent region EA. However, the embodiments described herein are not limited thereto, and depending on the shape of the microlens ML and the shape of the luminescent region EA, each dividing line DV1 or DV2 may not be aligned with the center EC1 or EC2 of each luminescent region EA.

[0216] The light-shielding patterns BP (BP1 and BP2) can be set on the microlens ML. The first light-shielding pattern BP1 can be set on the first microlens ML1, and the second light-shielding pattern BP2 can be set on the second microlens ML2. The light-shielding pattern BP may not be set on the second microlens ML2, but is not limited thereto.

[0217] Each light-shielding pattern BP1 or BP2 can be directly set on each microlens ML1 or ML2. Each light-shielding pattern BP1 or BP2 can be in direct contact with each microlens ML1 or ML2, but is not limited thereto.

[0218] The area of ​​the surface of the first microlens ML1 exposed by the first light-shielding pattern BP1 can directly contact the lens protective layer 190. The area of ​​the surface of the second microlens ML2 exposed by the second light-shielding pattern BP2 can directly contact the lens protective layer 190.

[0219] Here, the surface of each microlens ML1 or ML2 may refer to the upper surface having a dome shape, which is the area excluding the lower surface facing the third touch insulating layer 186.

[0220] The first light-blocking pattern BP1 and the second light-blocking pattern BP2 can be set on two different parts of the microlenses ML1 and ML2, which are divided by dividing lines DV1 and DV2I.

[0221] For example, in the two parts of the first microlens ML1 divided by the first dividing line DV1, the first light-shielding pattern BP1 can be disposed on the first microlens ML1 located on one side (or the first side) of the first dividing line DV1 in the first direction DR1, and in the two parts of the second microlens ML2 divided by the second dividing line DV2, the second light-shielding pattern BP2 can be disposed on the second microlens ML2 located on the other side (or the second side) of the second dividing line DV2 in the first direction DR1.

[0222] Therefore, the first light-blocking pattern BP1 can block some of the light emitted from the first pixel PX1 that travels to one side in the first direction DR1 in the planar diagram, and the second light-blocking pattern BP2 can block some of the light emitted from the second pixel PX2 that travels to the other side in the first direction DR1 in the planar diagram.

[0223] Because the light-blocking pattern BP is disposed on the microlens ML, it can more easily block or control the path of light emitted from the pixel PX. In other words, because the light-blocking pattern BP is disposed on the microlens ML, it can be positioned at the end of the path along which the light emitted from the pixel PX travels, so that the path of the light emitted from the pixel PX can ultimately be blocked and controlled, thereby facilitating the blocking and control of light.

[0224] Lens protective layer 190 may be disposed on microlenses ML (ML1 and ML2) and light-shielding pattern BP. Lens protective layer 190 may include, but is not limited to, organic insulating material. Lens protective layer 190 protects microlenses ML by covering them.

[0225] The refractive index of the lens protective layer 190 can be less than that of the microlens ML. Therefore, due to the difference in refractive index between the microlens ML and the lens protective layer 190, light that has passed through the microlens ML can be prevented from being reflected toward the substrate 101.

[0226] The cross-sectional structure of the non-display area NDA of display device 1 will be described below. Content identical to that described in the cross-sectional structure of the display area DA will be briefly described or omitted.

[0227] Subsequently, further reference Figure 1 , Figure 3 and Figures 7 to 9 The display panel 100 may also include a gate control transistor G120, a low potential voltage line VSSL, a dam section DMP, multiple pads VSSP, VDDP and DP disposed in the pad area PA, data lines DL (DL1 and DL2) and anti-crack pattern CSP disposed in the non-display area NDA.

[0228] The gate control transistor G120 may have a configuration substantially the same as that of the thin-film transistor 120 of the sub-pixel SP, and may be formed together with the thin-film transistor 120 of the sub-pixel SP by the same process, but is not limited thereto.

[0229] The gate control transistor G120 may include a control source electrode G121, a control gate electrode G122, a control semiconductor layer G123, and a control drain electrode G124.

[0230] A light-shielding layer (not shown) may be further disposed below the gate control transistor G120. One of the control source electrode G121 and the control drain electrode G124 may be electrically connected to and in contact with the light-shielding layer (not shown), but is not limited thereto.

[0231] The low-potential voltage line VSSL can be disposed on the fourth insulating layer 106. The low-potential voltage line VSSL can be formed of the same metal layer as the source electrode 121 and drain electrode 124 of the thin-film transistor 120, but is not limited thereto.

[0232] The display panel 100 may also include a low-potential connection electrode CE. The low-potential connection electrode CE can connect the low-potential voltage line VSSL to the cathode electrode 153.

[0233] A low-potential connection electrode CE can be disposed on the second protective layer 112. A dam 154 can be disposed on the low-potential connection electrode CE. The low-potential connection electrode CE can be disposed on the same layer as the anode electrode 151, and can include the same material as the anode electrode 151. The low-potential connection electrode CE and the anode electrode 151 can be formed together using the same process and a mask, but the embodiments in this specification are not limited thereto.

[0234] The display panel 100 may also include an exposed portion OP. The exposed portion OP can expose at least a portion of the low-potential voltage line VSSL by recessing the first protective layer 111 and the second protective layer 112.

[0235] The exposed portion OP can be defined by a first protective layer 111 and a second protective layer 112. The exposed portion OP can be defined by the side surface of the first protective layer 111, the side surface of the second protective layer 112, and the side surface of the second dam portion DM2.

[0236] The low-potential connection electrode CE can be electrically connected to and in contact with the low-potential voltage line VSSL exposed in the exposed portion OP. At least a portion of the low-potential connection electrode CE can be disposed on the second protective layer 112 and can extend from the second protective layer 112 toward the low-potential voltage line VSSL.

[0237] The low-potential connection electrode CE can be further disposed on the side surface of the defined exposed portion OP of the first protective layer 111 and the side surface of the second protective layer 112, and can be further disposed on the fourth insulating layer 106 and the low-potential voltage line VSSL exposed by the exposed portion OP. Therefore, the low-potential connection electrode CE can contact the low-potential voltage line VSSL.

[0238] The low-potential connection electrode CE can be electrically connected to the cathode electrode 153. The low-potential connection electrode CE and the cathode electrode 153 can be electrically connected and contacted to each other through a low-potential contact hole C_CNT in the overlapping area. The low-potential contact hole C_CNT can be defined by passing through the embankment 154 in the area where the low-potential connection electrode CE and the cathode electrode 153 overlap, and can expose the low-potential connection electrode CE.

[0239] The dam section DMP may include a first dam section DM1 and a second dam section DM2. The first dam section DM1 and the second dam section DM2 may overlap with a first low-potential voltage line VSSL1 or a second low-potential voltage line VSSL2.

[0240] In the second non-display area NDA2, the first dam section DM1 and the second dam section DM2 may overlap with the first low-potential voltage line VSSL1. In the first non-display area NDA1, the first dam section DM1 and the second dam section DM2 may overlap with the second low-potential voltage line VSSL2.

[0241] The first dam section DM1 can be located outside the second dam section DM2, but is not limited to this.

[0242] The first dam section DM1 can be formed as a multi-layered structure. Each layer of the first dam section DM1 may include the same material as the second protective layer 112 and the embankment 154, and each layer of the first dam section DM1, the second protective layer 112 and the embankment 154 can be formed together using the same process and a single mask, but the embodiments in this specification are not limited thereto.

[0243] The second dam section DM2 can be formed as a multi-layered structure. Each layer of the second dam section DM2 may include the same material as the embankment 154 and the spacer (not shown), and each layer of the second dam section DM2, the embankment 154 and the spacer (not shown) may be formed together using the same process with a single mask, but the embodiments described herein are not limited thereto.

[0244] The anti-crack pattern CSP can be disposed at the outermost edge of the non-display area NDA. The anti-crack pattern CSP can be defined by making at least one recess in the inorganic film disposed on the substrate 101.

[0245] For example, the crack-resistant pattern CSP can be defined by recessing the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, and the fourth insulating layer 106, but is not limited thereto.

[0246] The crack dummy pattern DUP can be further disposed on the crack-resistant pattern CSP. The crack dummy pattern DUP can fill the recessed crack-resistant pattern CSP. The crack dummy pattern DUP can be formed from multiple layers. For example, the crack dummy pattern DUP can be formed from three layers. The layers of the crack dummy pattern DUP can include the same material as the first protective layer 111, the second protective layer 112, and the embankment 154.

[0247] The high-potential voltage line VDDL can be disposed on the buffer layer 102 and covered by the first insulating layer 103. The high-potential voltage line VDDL may include the same material as the light-shielding layer 126, and the high-potential voltage line VDDL and the light-shielding layer 126 can be formed together using a mask in the same process, but the embodiments in this specification are not limited thereto.

[0248] Although not shown, the high-potential voltage pad VDDP can be disposed on the same layer as the source electrode 121 and the drain electrode 124, can include the same material as the source electrode 121 and the drain electrode 124, and can be formed together with a mask using the same process as the source electrode 121 and the drain electrode 124, but is not limited thereto.

[0249] In this configuration, the high-potential voltage pad VDDP can be electrically connected to and contacted with the high-potential voltage line VDDL via the high-potential contact hole S_CNT that exposes the high-potential voltage line VDDL.

[0250] However, the embodiments in this specification are not limited thereto, and the high potential voltage line VDDL can be disposed on the same layer as the source electrode 121 and the drain electrode 124, and can include the same material as the source electrode 121 and the drain electrode 124, and the high potential voltage line VDDL, the source electrode 121 and the drain electrode 124 can be formed together using a mask in the same process.

[0251] The first data pad DP1 and the second data pad DP2 can be disposed on the fourth insulating layer 106. The first data pad DP1 and the second data pad DP2 can be disposed on the same layer as the source electrode 121 and the drain electrode 124, and can include the same material as the source electrode 121 and the drain electrode 124, and can be formed together using a mask using the same process as the source electrode 121 and the drain electrode 124, but are not limited thereto.

[0252] The first data line DL1 may be disposed on the second insulating layer 104 and covered by the third insulating layer 105. The first data line DL1 may include the same material as the gate electrode 122 and may be formed together with the gate electrode 122 using a mask through the same process as the gate electrode 122, but is not limited thereto.

[0253] The second data line DL2 may be disposed on the third insulating layer 105 and covered by the fourth insulating layer 106. The second data line DL2 may include the same material as the second storage electrode 142 and may be formed together with the second storage electrode 142 using a mask through the same process, but is not limited thereto.

[0254] The first data line DL1 can be electrically connected and contacted with the first data pad DP1 through the first data contact hole CNT1. The second data line DL2 can be electrically connected and contacted with the second data pad DP2 through the second data contact hole CNT2.

[0255] The crack-resistant pattern CSP can be set outside the pad area PA. The crack-resistant pattern CSP can be set between the end of the pad area PA and the non-display area NDA2.

[0256] However, multiple pads VSSP, VDDP, and DP may not be covered by multiple inorganic films. Multiple inorganic films disposed on the fourth insulating layer 106 can expose multiple pads VSSP, VDDP, and DP. Multiple inorganic films disposed on the fourth insulating layer 106 may not be disposed within the pad area PA.

[0257] Therefore, the flexible film COF can be configured such that at least a portion thereof is set to overlap with and be attached to the display panel 100, and the flexible film COF can be electrically connected to and in contact with a plurality of pads VSSP, VDDP and DP of the pad area PA.

[0258] Figure 10 This is a schematic diagram illustrating the path of light emitted from a display panel according to one embodiment. Figure 11 This is a graph showing the brightness of a display device according to one embodiment.

[0259] refer to Figure 4 , Figure 10 and Figure 11 The first light-blocking pattern BP1 can be set on the first microlens ML1, and the second light-blocking pattern BP2 can be set on the second microlens ML2.

[0260] The first light-blocking pattern BP1 and the second light-blocking pattern BP2 can be set on two different parts of the microlenses ML1 and ML2, which are divided by dividing lines DV1 and DV2.

[0261] In the two portions of the first microlens ML1 divided by the first dividing line DV1, the first light-shielding pattern BP1 can be disposed on the first microlens ML1 located on one side (or the first side) of the first dividing line DV1 in the first direction DR1. Furthermore, in the two portions of the second microlens ML2 divided by the second dividing line DV2, the second light-shielding pattern BP2 can be disposed on the second microlens ML2 located on the other side (or the second side) of the second dividing line DV2 in the first direction DR1.

[0262] The first pixel PX1 can emit a first light L1 to display a first screen to the driver sitting in the driver's seat. A first light-shielding pattern BP1 can block some of the first light L1 emitted from the first pixel PX1 that travels to one side in a first direction DR1 in the plan view. The first light-shielding pattern BP1 can also block some of the first light L1 that travels towards the passenger (CO-DRIVER) sitting in the front passenger seat.

[0263] The second pixel PX2 can emit a second light L2 to display a second screen to the passenger (CO-DRIVER) sitting in the front passenger seat. A second light-shielding pattern BP2 can block some of the second light L2 emitted from the second pixel PX2 that travels towards the other side in the first direction DR1 in the plan view. The second light-shielding pattern BP2 can also block some of the second light L2 that travels towards the driver (DRIVER) sitting in the driver's seat.

[0264] Furthermore, due to the internal reflection of the display panel 100, each light-shielding pattern BP can block light emitted from the sub-pixel SP on which each light-shielding pattern BP is set, and light emitted from the sub-pixel SP set around the corresponding sub-pixel SP and incident on the microlens ML of the adjacent sub-pixel SP.

[0265] For example, Figure 11 The fourth light L4 emitted from sub-pixel SP (not shown) can be reflected inside the display panel 100 and emitted from sub-pixel SP2_1. When the path of the fourth light L4 emitted from sub-pixel SP2_1 faces the driver, the fourth light L4 can be blocked by the second microlens ML2 disposed in sub-pixel SP2_1.

[0266] The first pixel PX1 and the second pixel PX2 can be controlled independently to display different screens. The screen displayed by each of the first pixel PX1 and the second pixel PX2 can be identified based on the viewing angle. That is, the user can identify the screen displayed by the first pixel PX1 or the screen displayed by the second pixel PX2 based on the viewing angle.

[0267] When the first pixel PX1 and the second pixel PX2 display different screens depending on the viewing angle, crosstalk between screens can be suppressed or prevented by arranging light-blocking patterns BP1 and BP2.

[0268] exist Figure 11 In the diagram, the horizontal axis represents the viewing angle, and the vertical axis represents the brightness. Figure 11 In the middle, curve Figure X The curve Y represents the brightness of the first pixel PX1, and the curve Y represents the brightness of the second pixel PX2.

[0269] curve Figure X Curve Y represents the brightness of the screen recognized by the driver (DRIVER) while seated in the driver's seat, and curve Y represents the brightness of the screen recognized by the passenger (CO-DRIVER) while seated in the front passenger seat.

[0270] curve Figure X Y can have different peak values ​​depending on the viewing angle. For example, the curve Figure X A bell-shaped curve can have a peak at a viewing angle between -20 and -30 degrees, and curve Y can also have a bell-shaped curve with a peak at a viewing angle between 20 and 30 degrees. However, the embodiments in this specification are not limited to this, and the viewing angle of the peak of each curve can vary depending on the design of the display device.

[0271] Because the light-blocking patterns BP1 and BP2 are set on the microlenses ML1 and ML2 to block some of the light emitted from the first pixel PX1 and the second pixel PX2, the curve Figure X And the curve Y can be found on the curve Figure X The regions of view where Y and Y can overlap include points where brightness suddenly decreases.

[0272] For example, in the curve Figure X In the graph Y, the brightness abruptly decreases and converges to 0 at a point between -10 and 0, and the brightness continuously converges to 0 at angles after that point. However, the embodiments in this specification are not limited to this, and the point where the brightness abruptly decreases in each graph can vary according to the design.

[0273] Because of the light-blocking pattern BP, the first light L1 emitted by the first pixel PX1 may be blocked at some viewing angles, and the second light L2 emitted by the second pixel PX2 may be blocked at other viewing angles.

[0274] Therefore, the curve Figure X The area overlapping with Y can be reduced, and crosstalk on each screen provided to the driver and passenger co-driver can be suppressed or prevented, thereby improving the quality of each screen.

[0275] Other embodiments of this specification will be described below. Among the components included in these other embodiments, those referenced are... Figures 1 to 11 The content described is essentially the same, the same reference numerals are given, and overlapping content may be omitted or briefly described.

[0276] Figure 12 This is an enlarged view showing the pixel arrangement of a display panel according to another embodiment. Figure 13It is along Figure 12 A cross-sectional view of line E-E' in the diagram.

[0277] refer to Figure 12 and Figure 13 In the display panel 100_1 according to this embodiment, the first dividing line DV1 of the first microlens ML1 and the first center EC1 of the light-emitting areas EA1_1, EA1_2, and EA1_3 of the first pixel PX1 may not be aligned, and the second dividing line DV2 of the second microlens ML2 and the second center EC2 of the light-emitting areas EA2_1, EA2_2, and EA2_3 of the second pixel PX2 may not be aligned. Furthermore, at least a portion of the light-emitting portion 150 may be configured to be tilted in the thickness direction (third direction DR3).

[0278] Specifically, in the region where the light-emitting portion 150 is disposed, a portion of the upper surface of the second protective layer 112 may be formed as inclined. The light-emitting portion 150 may be disposed on at least a portion of the inclined second protective layer 112. Therefore, at least a portion of each of the anode electrode 151 and the organic layer 152 may be tilted. At least a portion of each of the anode electrode 151 and the organic layer 152 may be tilted (inclined) toward the microlens ML.

[0279] Each of the anode electrode 151 and the organic layer 152 may be disposed on at least a portion of the inclined second protective layer 112. The organic layer 152 may be disposed on the inclined second protective layer 112 over the entire region, but is not limited thereto.

[0280] The anode electrode 151 and the organic layer 152 disposed on the inclined second protective layer 112 can be configured to be inclined (skewed) corresponding to the inclined second protective layer 112. Therefore, a portion of the cathode electrode 153 disposed on the organic layer 152 can be configured to be inclined.

[0281] The anode electrode 151 and the organic layer 152 can be configured to be inclined in the thickness direction (third direction DR3) of the display panel 100 within the 1_1 light-emitting region EA1_1, the 2_1 light-emitting region EA2_1 and their surrounding area. The upper surfaces of the anode electrode 151 and the organic layer 152 can be inclined in the thickness direction (third direction DR3) of the display panel 100. The facing direction of the upper surfaces of the anode electrode 151 and the organic layer 152 can be inclined in the thickness direction (third direction DR3) of the display panel 100.

[0282] The upper surface of the anode electrode 151 and the upper surface of the organic layer 152 may be tilted relative to the upper surface of the first protective layer 111.

[0283] The anode electrode 151 and organic layer 152 of the first pixel PX1 can be tilted in a different direction than the anode electrode 151 and organic layer 152 of the second pixel PX2. For example, in the 1-1 light-emitting region EA1_1, the 2-1 light-emitting region EA2_1 and their surroundings, the anode electrode 151 and organic layer 152 can be tilted in opposite directions.

[0284] The upper surface of the anode electrode 151 and the upper surface of the organic layer 152 of the first pixel PX1 can be tilted toward the first microlens ML1, and the upper surface of the anode electrode 151 and the upper surface of the organic layer 152 of the second pixel PX2 can be tilted toward the second microlens ML2.

[0285] Therefore, the light emitted from each sub-pixel SP can be skewed in the thickness direction (third direction DR3) of the display panel 100.

[0286] The first center EC1 of the 1_1 light-emitting area EA1_1 of sub-pixel SP1_1 may not be aligned with the first dividing line DV1 of the first microlens ML1 disposed on the 1_1 sub-pixel SP1_1. In the plan view, the dividing line DV1 of the first microlens ML1 may be misaligned along the first direction DR1 from the first center EC1 of the 1_1 light-emitting area EA1_1 to the other side (the left side in the plan view).

[0287] The description of misalignment of subpixel SP1_1 can also be applied in essentially the same way to the remaining subpixels SP1_2 and SP1_3 of the first pixel PX1. However, the degree of misalignment between the microlens ML and the luminous region EA can differ in each of the subpixels SP1_1, SP1_2, and SP1_3 of the first pixel PX1.

[0288] However, the embodiments described in this specification are not limited thereto, and the direction in which the first dividing line DV1 of the first microlens ML1 is not aligned with the first center EC1 of the 1_1 light-emitting region EA1_1 can be varied according to the design.

[0289] The second center EC2 of the 2_1 luminous region EA2_1 of sub-pixel SP2_1 and the second dividing line DV2 of the second microlens ML2 disposed on sub-pixel SP2_1 may be misaligned. In the plan view, the second dividing line DV2 of the second microlens ML2 may be misaligned along the first direction DR1 from the second center EC2 of the 2_1 luminous region EA2_1 to one side (the right side in the plan view).

[0290] The description of the misalignment of subpixel SP2_1 can also be applied in essentially the same way to the remaining subpixels SP2_2 and SP2_3 of the second pixel PX2. However, the degree of misalignment between the microlens ML and the luminous region EA can differ in each of the subpixels SP2_1, SP2_2, and SP2_3 of the second pixel PX2.

[0291] However, the embodiments described herein are not limited thereto, and the direction in which the second dividing line DV2 of the second microlens ML2 is not aligned with the second center EC2 of the 2_1 light-emitting region EA2_1 can be varied according to the design.

[0292] The opening (or light-emitting area EA) of the sub-pixel SP and the light-emitting portion 150 arranged around the opening can be set to be skewed relative to the thickness direction (third direction DR3), and the light L1 and L2 emitted from the light-emitting portion 150 can travel in the direction skewed relative to the thickness direction (third direction DR3).

[0293] Because the microlens ML and the light-emitting area EA are misaligned, even when the light L1 and L2 emitted from the light-emitting portion 150 travel at an angle relative to the thickness direction (third direction DR3), each light L1 or L2 can travel toward the microlens ML of each pixel PX.

[0294] Subpixels SP1_1, SP1_2, and SP1_3 located in the first pixel PX1 can emit light L1 to the left (on the other side of the first direction DR1) in the planar view. Subpixels SP2_1, SP2_2, and SP2_3 located in the second pixel PX2 can emit light L2 to the right (on one side of the first direction DR1) in the planar view.

[0295] In other words, light L1 emitted from sub-pixels SP1_1, SP1_2, and SP1_3 of the first pixel PX1 can travel at an angle relative to the thickness direction (third direction DR3) towards the other side of the first direction DR1. Light L2 emitted from sub-pixels SP2_1, SP2_2, and SP2_3 of the second pixel PX2 can travel at an angle relative to the thickness direction (third direction DR3) towards the first direction DR1.

[0296] The direction and degree of misalignment between the microlens ML and the luminous region EA can vary depending on the direction of travel of light emitted from the sub-pixels SP of each pixel PX1 or PX2.

[0297] Since the sub-pixels SP1_1, SP1_2, and SP1_3 set in the first pixel PX1 and the sub-pixels SP2_1, SP2_2, and SP2_3 set in the second pixel PX2 can emit light in different directions, the screen displayed to the driver sitting in the driver's seat and the screen displayed to the passenger co-driver sitting in the front passenger seat can be controlled separately in different ways, and different screens can be displayed to the driver and the passenger co-driver.

[0298] Light L1 emitted from the first pixel PX1 can be emitted toward the first microlens ML1, which does not have the first light-blocking pattern BP1. Light L2 emitted from the second pixel PX2 can be emitted toward the second microlens ML2, which does not have the second light-blocking pattern BP2.

[0299] The light-blocking patterns BP1 or BP2 can block and absorb light emitted from each pixel PX1 or PX2 that travels in an undesirable direction. Even in this case, because the light-blocking pattern BP is set on the microlens ML, crosstalk that may occur between the image and video displayed on each pixel PX1 or PX2 can be suppressed or prevented.

[0300] Furthermore, since the light-emitting portion 150 of some pixels PX1 and PX2 is skewed, it is easier to control the path of light emitted from each pixel PX1 or PX2, and it is easier to display different images and videos according to the viewing angle.

[0301] Figure 14 This is a plan view of a display device according to yet another embodiment. Figure 15 yes Figure 14 A magnified view of region Q2 in the image. Figure 16 It is along Figure 15 A cross-sectional view of line F-F' in the diagram.

[0302] Figure 15 This is a view of region Q2 of display device 2 according to yet another embodiment, from which the flexible film COF, motherboard MB, and driver IC DIC are omitted.

[0303] refer to Figures 14 to 16 In the display device 2 according to this embodiment, the gate driving unit GIP (see...) Figure 1 It is not necessary to set it separately in the non-display area NDA, and the pixel gate driving unit GIA can be set in the display area DA.

[0304] A pixel gate driving unit (GIA) can be provided as multiple pixel gate drivers, and each pixel gate driving unit (GIA) can be connected to each pixel in the multiple pixels (PX). Pixel gate driving units (GIAs) can be arranged around the pixels (PX). Pixel gate driving units (GIAs) can be arranged between adjacent pixels (PX).

[0305] For example, a pixel gate driving unit GIA can be disposed between adjacent pixels PX in the first direction DR1. Pixels PX and pixel gate driving units GIA can be disposed alternately in the first direction DR1. Pixels PX can be disposed continuously and repeatedly in the second direction DR2. Pixel gate driving units GIA can be disposed continuously and repeatedly in the second direction DR2.

[0306] The pixel gate drive unit (GIA) can perform the same actions as the gate drive unit (GIP) (see [link]). Figure 1 They serve essentially the same function. The pixel gate drive unit (GIA) can include at least one transistor.

[0307] The pixel gate drive unit (GIA) can be electrically connected to the adjacent pixel (PX).

[0308] The pixel gate driving unit (GIA) receives gate control signals from the driver IC (DIC) via the gate control line (GCL_2). The GIA can then generate scan signals and emission signals (or emission control signals) based on the gate control signals. Therefore, it can control the driving of adjacent pixels (PX).

[0309] Since the pixel gate drive unit (GIA) is located in the display area (DA), the non-display area (NDA) or border area can be minimized, thereby providing users with improved aesthetics.

[0310] Display device 2 may also include gate control line GCL_2 and gate control pad GCP.

[0311] The gate control line GCL_2 can be located in the non-display area NDA and the display area DA. The gate control line GCL_2 can be located in the second non-display area NDA2, but is not limited thereto. The gate control line GCL_2 can be located in the extension direction of the second non-display area NDA2.

[0312] The gate control line GCL_2 can be partially disposed in the second non-display area NDA2, and can extend from the second non-display area NDA2 to the pixel gate driving unit GIA disposed in the display area DA. The gate control line GCL_2 can be electrically connected to multiple pixel gate driving units GIA disposed in the display area DA.

[0313] The gate control pad (GCP) can be located within the pad region PA. Within the pad region PA, the gate control pad (GCP) is shown positioned between the high-potential voltage pad (VDDP) and the data pad (DP), but is not limited to this, and the arrangement of the gate control pad (GCP) can vary depending on the design.

[0314] The gate control pad (GCP) may include, but is not limited to, the same material as the gate control line (GCL_2). The gate control pad (GCP) and the gate control line (GCL_2) may be integrally formed, but are not limited to.

[0315] The gate control pad GCP and gate control line GCL_2 can be disposed on the fourth insulating layer 106. The gate control pad GCP and gate control line GCL_2 can be disposed at the source electrode 121 (see...). Figure 5 ) and drain electrode 124 (see Figure 5 On the same layer, and may include the same material as the source electrode 121 and drain electrode 124, and the gate control pad GCP, gate control line GCL, source electrode 121 and drain electrode 124 may be formed together using a mask in the same process, but the embodiments in this specification are not limited thereto.

[0316] Multiple pads VSSP, VDDP, DP, and GCP may not be covered by multiple inorganic films. Multiple inorganic films disposed on the fourth insulating layer 106 may expose multiple pads VSSP, VDDP, DP, and GCP. Multiple inorganic films disposed on the fourth insulating layer 106 may not be disposed within the pad area PA.

[0317] For example, the first inorganic encapsulation layer 171, the second inorganic encapsulation layer 173, the touch buffer layer 181, the first touch insulating layer 183, and the third touch insulating layer 186 can be disposed in the notched non-display area N_NDA up to the end of the substrate 101, but they can also be excluded from the pad area PA. Therefore, the multiple pads VSSP, VDDP, DP, and GCP disposed on the fourth insulating layer 106 can be exposed, and the display panel 100_2 can be adhered to and electrically connected to the flexible film COF.

[0318] Due to the gate drive unit GIP (see Figure 1 The pixel gate drive unit (GIA) is omitted from the non-display area NDA, and is located in the display area DA. Therefore, the non-display area NDA can be reduced, thereby reducing the bezel area and increasing the display area DA.

[0319] Even in this case, the light-shielding patterns BP1 and BP2 (see...) Figure 5 It can also block and absorb light emitted from each pixel PX and traveling in an undesirable direction. Even in this case, due to the light-blocking pattern BP (see...), Figure 5 The microlens ML is positioned on the microlens, thus suppressing or preventing PX at each pixel (see...). Figure 5 This refers to the potential crosstalk between the images and videos displayed on the screen.

[0320] The following describes various embodiments of the display device described in this specification.

[0321] According to embodiments of this specification, a display device is provided, comprising: a substrate including a display area and a non-display area surrounding the display area, the display area including a first pixel and a second pixel, each of the first pixel and the second pixel including a plurality of sub-pixels; a first microlens corresponding to each of the plurality of sub-pixels of the first pixel on the substrate; a second microlens corresponding to each of the plurality of sub-pixels of the second pixel on the substrate; a first light-shielding pattern on the surface of the first microlens; and a second light-shielding pattern on the surface of the second microlens, wherein the plurality of sub-pixels of the first pixel and the plurality of sub-pixels of the second pixel are arranged in a first direction, the first pixel and the second pixel are arranged adjacent to each other in a second direction intersecting the first direction, each of the first microlens and the second microlens including a first portion located on a first side relative to a dividing line and a second portion located on a second side as a side opposite to the first side, the first light-shielding pattern being disposed on the first portion of the first microlens, and the second light-shielding pattern being disposed on the second portion of the second microlens.

[0322] According to various embodiments of this specification, the first light-shielding pattern can be directly disposed on the first portion of the first microlens, and the second light-shielding pattern can be directly disposed on the second portion of the second microlens.

[0323] According to various embodiments of this specification, the display device may further include a lens protection layer on a first microlens and a second microlens, wherein the surface of the first microlens exposed by the first light-shielding pattern may contact the lens protection layer, and the surface of the second microlens exposed by the second light-shielding pattern may contact the lens protection layer.

[0324] According to various embodiments of this specification, the display device may further include a light-emitting portion located between a substrate and a first microlens, wherein the light-emitting portion may include an anode electrode, an organic layer located between the anode electrode and the first microlens, and a cathode electrode located between the organic layer and the first microlens.

[0325] According to various embodiments of this specification, the display device may further include a dam disposed between an anode electrode and a cathode electrode, wherein the dam may define a first light-emitting region of the first pixel and a second light-emitting region of the second pixel, wherein the first light-emitting region may include a first center and the second light-emitting region may include a second center, wherein the first center may not be aligned with the dividing line of the first microlens and the second center may not be aligned with the dividing line of the second microlens.

[0326] According to various embodiments of this specification, the dividing line of the first microlens may be located on a second side relative to the first center, and the dividing line of the second microlens may be located on a first side relative to the second center.

[0327] According to various embodiments of this specification, the display device may further include a protective layer located between the substrate and the light-emitting portion, wherein the upper surface of the anode electrode of the first pixel and the upper surface of the anode electrode of the second pixel may be skewed relative to the upper surface of the protective layer.

[0328] According to various embodiments of this specification, the upper surface of the anode electrode of the first pixel and the upper surface of the anode electrode of the second pixel may be tilted toward opposite sides.

[0329] According to various embodiments of this specification, the upper surface of the anode electrode of the first pixel may be tilted toward the first microlens, and the upper surface of the anode electrode of the second pixel may be tilted toward the second microlens.

[0330] According to various embodiments of this specification, the display device may further include a pad area and low-potential voltage lines and high-potential voltage lines electrically connected to the pad area, wherein, in a non-display area below the display area, the high-potential voltage lines may be located between the low-potential voltage lines and the display area.

[0331] According to various embodiments of this specification, the low-potential voltage line may surround the display area.

[0332] According to various embodiments of this specification, the non-display area located to the left or right of the display area may further include a gate driving unit located between the low-potential voltage line and the display area.

[0333] According to various embodiments of this specification, the display device may further include a pixel gate driving unit located in the display area and a gate control line electrically connecting the pad area to the pixel gate driving unit, wherein the gate control line may be located between a low-potential voltage line and the display area.

[0334] According to embodiments of this specification, a display device is provided, comprising: a substrate including a display area and a non-display area surrounding the display area, the display area including a first pixel and a second pixel, each of the first pixel and the second pixel including a plurality of sub-pixels; a thin-film transistor disposed on the substrate; a protective layer disposed on the thin-film transistor; a light-emitting portion disposed on the protective layer and including an anode electrode, an organic layer and a cathode electrode; an encapsulation layer disposed on the light-emitting portion; a microlens disposed on the encapsulation layer and including a first microlens corresponding to the first pixel and a second microlens corresponding to the second pixel; and a light-shielding pattern including a first light-shielding pattern disposed on the first microlens and a second light-shielding pattern disposed on the second microlens, wherein a plurality of sub-pixels of the first pixel and a plurality of sub-pixels of the second pixel are arranged in a first direction, the first pixel and the second pixel are disposed adjacent to each other in a second direction intersecting the first direction, the positions of the first light-shielding pattern disposed on the first microlens and the positions of the second light-shielding pattern disposed on the second microlens are different, the first light-shielding pattern restricts some light emitted from the first pixel from traveling toward one side in the first direction, and the second light-shielding pattern restricts some light emitted from the second pixel from traveling toward the other side in the first direction.

[0335] According to various embodiments of this specification, each of the first microlens and the second microlens includes a first portion located on one side of a first direction relative to the dividing line that divides the first microlens and the second microlens, and a second portion located on the other side of the first direction as the side opposite to the first side. A first light-shielding pattern may be disposed on the first portion of the first microlens, and a second light-shielding pattern may be disposed on the second portion of the second microlens.

[0336] According to various embodiments of this specification, the first light-blocking pattern can be directly disposed on the first portion of the first microlens, and the second light-blocking pattern can be directly disposed on the second portion of the second microlens.

[0337] According to various embodiments of this specification, the display device may further include a lens protection layer on a first microlens and a second microlens, wherein the surface of the first microlens exposed by a first light-shielding pattern may contact the lens protection layer, and the surface of the second microlens exposed by a second light-shielding pattern may contact the lens protection layer.

[0338] According to various embodiments of this specification, the display device may further include a light-emitting portion located between the substrate and the microlens, wherein the light-emitting portion may include an anode electrode, an organic layer located between the anode electrode and the microlens, and a cathode electrode located between the organic layer and the microlens.

[0339] According to various embodiments of this specification, the display device may further include a dam disposed between the anode electrode and the cathode electrode, wherein the dam may define a first light-emitting region of the first pixel and a second light-emitting region of the second pixel, wherein the first light-emitting region may include a first center and the second light-emitting region may include a second center, wherein the first center may be misaligned with the dividing line of the first microlens and the second center may be misaligned with the dividing line of the second microlens.

[0340] According to various embodiments of this specification, the dividing line of the first microlens may be located on the opposite side of the first direction relative to the first center, and the dividing line of the second microlens may be located on the side of the first direction relative to the second center.

[0341] Although embodiments have been described above with reference to the accompanying drawings, those skilled in the art will understand that the above-described technical configurations can be performed in other specific forms without altering their technical spirit or essential characteristics. Therefore, it should be understood that the above embodiments are illustrative rather than restrictive in all respects. Furthermore, the scope of the embodiments is determined by the appended claims rather than the detailed description. Additionally, the meaning and scope of the claims, as well as all changes or modifications derived from their equivalents, should be interpreted as being included within the scope of the embodiments.

[0342] Explanation of reference numerals in the attached figures

[0343] 1: Display device

[0344] 100: Display device

[0345] 101: Substrate

[0346] NCP: Notch

[0347] DA: Display Area

[0348] NDA: Non-display area

[0349] NDA1: First Non-Display Area

[0350] NDA2: Second Non-Display Area

[0351] N_NDA: Non-display area of ​​the notch

[0352] E_NDA: Extended non-display area

[0353] PA: Pad area

[0354] PX: pixel

[0355] SP: Subpixel

[0356] EA: Emitting area

[0357] NEA: Non-luminescent area

[0358] ML: Microlens

[0359] BP: Light-blocking pattern

[0360] DV: Divider line

[0361] EC: Center

[0362] 150: Light-emitting part

[0363] 170: Package section

Claims

1. A display device, comprising: A substrate, the substrate including a display area and a non-display area surrounding the display area, the display area including a first pixel and a second pixel, each of the first pixel and the second pixel including a plurality of sub-pixels; A first microlens, the first microlens corresponding to each of the plurality of sub-pixels of the first pixel on the substrate; A second microlens, the second microlens corresponding to each of the plurality of sub-pixels of the second pixel on the substrate; A first light-blocking pattern is located on the surface of the first microlens; The second light-shielding pattern is located on the surface of the second microlens; Wherein, the plurality of sub-pixels of the first pixel and the plurality of sub-pixels of the second pixel are arranged in a first direction; The first pixel and the second pixel are arranged adjacent to each other in a second direction that intersects with the first direction. Each of the first microlens and the second microlens includes a first portion located on a first side and a second portion located on a second side, the second side being the side opposite to the first side relative to the dividing line; The first light-blocking pattern is disposed on the first portion of the first microlens; and The second light-shielding pattern is disposed on the second portion of the second microlens.

2. The display device according to claim 1, wherein, The first light-shielding pattern is directly disposed on the first portion of the first microlens, and The second light-shielding pattern is directly disposed on the second portion of the second microlens.

3. The display device according to claim 1 further includes a lens protective layer on the first microlens and the second microlens. in, The surface of the first microlens exposed by the first light-shielding pattern is in contact with the lens protective layer, and the surface of the second microlens exposed by the second light-shielding pattern is in contact with the lens protective layer.

4. The display device according to claim 1 further includes a light-emitting portion located between the substrate and the first microlens. in, The light-emitting portion includes an anode electrode, an organic layer located between the anode electrode and the first microlens, and a cathode electrode located between the organic layer and the first microlens.

5. The display device according to claim 4 further includes a retaining wall disposed between the anode electrode and the cathode electrode. in, The embankment defines a first light-emitting region of the first pixel and a second light-emitting region of the second pixel; The first luminescent region includes a first center, and the second luminescent region includes a second center; and The first center is not aligned with the dividing line of the first microlens, and the second center is not aligned with the dividing line of the second microlens.

6. The display device according to claim 5, wherein, The dividing line of the first microlens is located on the second side relative to the first center, and the dividing line of the second microlens is located on the first side relative to the second center.

7. The display device according to claim 6, further comprising a protective layer located between the substrate and the light-emitting portion. in, The upper surface of the anode electrode of the first pixel and the upper surface of the anode electrode of the second pixel are skewed relative to the upper surface of the protective layer.

8. The display device according to claim 7, wherein, The upper surface of the anode electrode of the first pixel and the upper surface of the anode electrode of the second pixel are tilted to opposite sides.

9. The display device according to claim 8, wherein, The upper surface of the anode electrode of the first pixel is skewed toward the first microlens, and the upper surface of the anode electrode of the second pixel is skewed toward the second microlens.

10. The display device according to claim 1, further comprising: solder pad area; And low-potential voltage lines and high-potential voltage lines electrically connected to the pad area. In the non-display area below the display area, the high-potential voltage line is located between the low-potential voltage line and the display area.

11. The display device according to claim 10, wherein, The low-potential voltage line surrounds the display area.

12. The display device according to claim 10, wherein, The non-display area located to the left or right of the display area also includes a gate driving unit located between the low-potential voltage line and the display area.

13. The display device according to claim 10, further comprising: A pixel gate driving unit located in the display area; and a gate control line electrically connecting the pad area to the pixel gate driving unit. The gate control line is located between the low-potential voltage line and the display area.

14. A display device, comprising: A substrate, the substrate including a display area and a non-display area surrounding the display area, the display area including a first pixel and a second pixel, each of the first pixel and the second pixel including a plurality of sub-pixels; A thin-film transistor disposed on the substrate; A protective layer is disposed on the thin-film transistor; The light-emitting portion is disposed on the protective layer and includes an anode electrode, an organic layer, and a cathode electrode; An encapsulation layer is disposed on the light-emitting portion; A microlens, wherein the microlens is disposed on the encapsulation layer and includes a first microlens corresponding to the first pixel and a second microlens corresponding to the second pixel; as well as The light-blocking pattern includes a first light-blocking pattern disposed on the first microlens and a second light-blocking pattern disposed on the second microlens; Wherein, the plurality of sub-pixels of the first pixel and the plurality of sub-pixels of the second pixel are arranged in the first direction; The first pixel and the second pixel are arranged adjacent to each other in a second direction that intersects with the first direction. The first light-blocking pattern is positioned differently on the first microlens than the second light-blocking pattern is positioned differently on the second microlens; and The first light-blocking pattern restricts some of the light emitted from the first pixel from traveling toward one side in the first direction, and the second light-blocking pattern restricts some of the light emitted from the second pixel from traveling toward the other side in the first direction.

15. The display device according to claim 14, wherein, Each of the first microlens and the second microlens includes a first portion located on one side in the first direction and a second portion located on the other side in the first direction, the other side being the side opposite to the first side relative to the dividing line separating the first microlens and the second microlens. The first light-blocking pattern is disposed on the first portion of the first microlens, and the second light-blocking pattern is disposed on the second portion of the second microlens.

16. The display device according to claim 15, wherein, The first light-blocking pattern is directly disposed on the first portion of the first microlens, and the second light-blocking pattern is directly disposed on the second portion of the second microlens.

17. The display device according to claim 14, further comprising a lens protective layer on the first microlens and the second microlens. in, The surface of the first microlens exposed by the first light-shielding pattern is in contact with the lens protective layer, and the surface of the second microlens exposed by the second light-shielding pattern is in contact with the lens protective layer.

18. The display device according to claim 14, further comprising a light-emitting portion located between the substrate and the microlens. in, The light-emitting portion includes an anode electrode, an organic layer located between the anode electrode and the microlens, and a cathode electrode located between the organic layer and the microlens.

19. The display device according to claim 18, further comprising a retaining wall disposed between the anode electrode and the cathode electrode. in, The embankment defines a first light-emitting region of the first pixel and a second light-emitting region of the second pixel; The first luminescent region includes a first center, and the second luminescent region includes a second center; and The first center is not aligned with the dividing line of the first microlens, and the second center is not aligned with the dividing line of the second microlens.

20. The display device according to claim 19, wherein, The dividing line of the first microlens is located on a first side in the first direction relative to the first center, and the dividing line of the second microlens is located on a second side in the first direction opposite to the first side relative to the second center.

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