Display panel, manufacturing method thereof and display device

Abstract

The invention provides a display panel, a manufacturing method thereof and a display device, a pixel defining layer comprises a plurality of first retaining walls and a plurality of second retaining walls, the first retaining walls and the second retaining walls are arranged in a crossed mode, the height of the first retaining walls is smaller than that of the second retaining walls, and the orthographic projection of a via hole connected with a light-emitting device on a substrate is located in the orthographic projection of the second retaining walls on the substrate. The second retaining wall has a large thickness, so that the via hole is arranged below the second retaining wall, and a better covering effect on the via hole is achieved. Besides, the via hole is arranged below the second retaining wall, so that the width of the anode can be properly increased, the opening area of the sub-pixel is increased, and the brightness of the sub-pixel is improved.

Description

Display panel, manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a display device. Background Art

[0002] With the continuous development of display technology in recent years, display devices have become an indispensable and important part of human-computer interaction. Current display devices primarily include organic light-emitting diode (OLED) displays and liquid crystal displays (LCD). OLED displays boast advantages such as greater lightness, sensitivity, high brightness, vivid colors, wide viewing angles, and power efficiency, and are therefore gaining a growing market share.

[0003] OLED devices emit light through the injection and recombination of charge carriers. With the rapid development of the OLED display industry, the requirements for OLED device brightness and display quality are becoming increasingly stringent. Inkjet printing is a key process in the manufacture of OLED displays, but existing inkjet printing processes, due to equipment performance limitations, struggle to meet the demands for display device imaging precision and quality. For example, in actual production, problems such as color mixing between adjacent sub-pixels and ink overflow due to low sub-pixel aperture ratios often occur, severely hindering the development of OLED display technology.

[0004] Summary of the Invention

[0005] According to a first aspect of the present disclosure, a display panel is provided, comprising:

[0006] substrate;

[0007] A driving circuit layer is located on the base substrate;

[0008] a flat layer, located on a side of the driving circuit layer away from the base substrate; the flat layer includes a plurality of via holes;

[0009] a pixel defining layer located on the flat surface; the pixel defining layer comprising: a plurality of first retaining walls and a plurality of second retaining walls, the plurality of first retaining walls extending along a first direction and arranged along a second direction, the plurality of second retaining walls extending along the second direction and arranged along the first direction; the first direction and the second direction intersecting; the plurality of first retaining walls and the plurality of second retaining walls forming a plurality of openings;

[0010] a light-emitting device layer, located on a side of the pixel defining layer away from the planar layer; the light-emitting device layer includes a plurality of light-emitting devices, with one light-emitting device correspondingly disposed in each of the openings; one of the via holes corresponds to one of the light-emitting devices, and the light-emitting device is electrically connected to the driving circuit layer through the corresponding via hole;

[0011] The height of the first retaining wall is smaller than the height of the second retaining wall, and the orthographic projection of the via hole on the base substrate is located within the orthographic projection of the second retaining wall on the base substrate.

[0012] In some embodiments of the present disclosure, the orthographic projection of the via hole on the base substrate is located within the orthographic projection of the base substrate at an intersection of the first retaining wall and the second retaining wall.

[0013] In some embodiments of the present disclosure, the width of the first retaining wall in the second direction is greater than the width of the second retaining wall in the first direction.

[0014] In some embodiments of the present disclosure, the display panel further includes:

[0015] a dielectric layer, located on a side of the pixel defining layer facing away from the planar layer;

[0016] an encapsulation layer, located on a side of the pixel defining layer and the light-emitting device layer facing away from the planar layer;

[0017] Wherein, the refractive index of the packaging layer is greater than the refractive index of the dielectric layer.

[0018] In some embodiments of the present disclosure, the dielectric layer includes a plurality of dielectric units, and a size of an orthographic projection of the via hole on the base substrate is larger than a size of an orthographic projection of the dielectric unit on the base substrate.

[0019] In some embodiments of the present disclosure, the plurality of dielectric units are respectively arranged along four edges of the opening.

[0020] In some embodiments of the present disclosure, there is a set distance between adjacent dielectric units; and the set distance is smaller than a width of the dielectric unit.

[0021] In some embodiments of the present disclosure, the dielectric unit located on the side of the first retaining wall away from the flat layer is a first dielectric unit, and the dielectric unit located on the side of the second retaining wall away from the flat layer is a second dielectric unit;

[0022] The width of the first medium unit is equal to the width of the second medium unit.

[0023] In some embodiments of the present disclosure, the distance between two rows of the first dielectric units arranged at two adjacent edges of the openings on the same first retaining wall is greater than the width of the first dielectric unit;

[0024] The distance between two rows of the second dielectric units arranged at two adjacent edges of the opening on the same second blocking wall is smaller than the width of the second dielectric unit.

[0025] In some embodiments of the present disclosure, the spacing between adjacent first dielectric units located at the same edge of the opening is greater than the spacing between adjacent second dielectric units.

[0026] In some embodiments of the present disclosure, the first dielectric unit and the second dielectric unit have the same height.

[0027] In some embodiments of the present disclosure, the height of the first dielectric unit is greater than that of the second dielectric unit; and the surface of the first dielectric unit facing away from the first retaining wall is flush with the surface of the second dielectric unit facing away from the second retaining wall.

[0028] In some embodiments of the present disclosure, the dielectric unit is one of a cylinder, a cone, or a hemisphere.

[0029] In some embodiments of the present disclosure, the width of the dielectric unit first decreases and then increases in a direction away from the pixel defining layer.

[0030] According to a second aspect of the embodiments of the present disclosure, a display device is provided, comprising any one of the above-mentioned display panels.

[0031] According to a third aspect of the embodiments of the present disclosure, a method for manufacturing a display panel is provided, comprising:

[0032] forming a driving circuit layer on the base substrate;

[0033] forming a flat layer on a side of the driving circuit layer facing away from the base substrate; the flat layer includes a plurality of via holes;

[0034] forming an anode layer of a light-emitting device layer on the flat layer; the anode layer comprises a plurality of mutually separated anodes;

[0035] A pixel defining layer is formed on the planar layer; the pixel defining layer comprises: a plurality of first retaining walls and a plurality of second retaining walls, the plurality of first retaining walls extending along a first direction and arranged along a second direction, the plurality of second retaining walls extending along the second direction and arranged along the first direction; the first direction and the second direction intersect; the plurality of first retaining walls and the plurality of second retaining walls form a plurality of openings, each opening corresponding to one of the anodes;

[0036] forming a dielectric layer on a side of the pixel defining layer away from the planar layer; forming a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer and a cathode layer of a light emitting device layer in sequence on a side of the anode and the pixel defining layer away from the planar layer; or forming a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer and a cathode layer of a light emitting device layer in sequence on a side of the anode and the pixel defining layer away from the planar layer; and forming a dielectric layer on a side of the anode layer away from the pixel defining layer;

[0037] forming an encapsulation layer on a side of the light-emitting device layer facing away from the planar layer;

[0038] The height of the first retaining wall is smaller than that of the second retaining wall, the orthographic projection of the via hole on the base substrate is located within the orthographic projection of the second retaining wall on the base substrate, and the refractive index of the packaging layer is greater than that of the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments of the present disclosure. Obviously, the drawings introduced below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] FIG1 is a schematic diagram of a top view of a display panel according to an embodiment of the present disclosure;

[0041] FIG2 is a schematic diagram of a cross-sectional structure of the display panel along the II' direction in FIG1;

[0042] FIG3 is a schematic diagram of a top view of a display panel in the related art;

[0043] FIG4 is a schematic diagram of the outgoing light of an OLED device in the related art;

[0044] FIG5 is a second schematic diagram of a top view of a display panel provided in an embodiment of the present disclosure;

[0045] FIG6 is a schematic diagram of a cross-sectional structure of the display panel along the II' direction in FIG5;

[0046] FIG7 is a schematic diagram of a cross-sectional structure of another display panel provided by an embodiment of the present disclosure;

[0047] FIG8 is a schematic diagram of one of the outgoing light rays of the OLED device provided in an embodiment of the present disclosure;

[0048] FIG9 is a schematic diagram of one of the outgoing light rays of the OLED device provided in an embodiment of the present disclosure;

[0049] FIG10 is a third schematic diagram of the outgoing light of the OLED device provided in an embodiment of the present disclosure;

[0050] FIG11 is a schematic diagram of a cross-sectional structure of the display panel along the XX′ direction in FIG5 ;

[0051] FIG12 is a schematic diagram of a cross-sectional structure of the display panel along the YY' direction in FIG5;

[0052] FIG13 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present disclosure;

[0053] FIG. 14 is a second flowchart of the display panel manufacturing method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0054] In order to make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, the present disclosure will be further described below with reference to the accompanying drawings and examples. However, the example embodiments can be implemented in various forms and should not be understood as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided to make the present disclosure more comprehensive and complete, and to fully convey the concepts of the example embodiments to those skilled in the art. The same figure marks in the figures represent the same or similar structures, and their repeated descriptions will be omitted. The words expressing position and direction described in the present disclosure are all explained using the accompanying drawings as examples, but changes can be made as needed, and all changes are included in the scope of protection of the present disclosure. The drawings of the present disclosure are only used to illustrate relative position relationships and do not represent true proportions.

[0055] An OLED display panel uses OLED devices as sub-pixels. OLED devices are current-type light-emitting devices that emit light through the injection and recombination of carriers. The most basic structure of an OLED device consists of an anode, a cathode, and a light-emitting layer located between the anode and cathode. The light-emitting layer typically uses an organic light-emitting material, and multiple organic light-emitting materials are typically required to produce light of different colors from the OLED device. Under the influence of an electric field, holes generated at the anode and electrons generated at the cathode migrate to the light-emitting layer, generating energy excitons that excite the light-emitting molecules and ultimately produce light of a specific color.

[0056] Inkjet printing is a key process in the manufacture of OLED displays. However, due to performance limitations of existing inkjet printing equipment, problems such as color mixing between adjacent pixels and ink overflow due to low pixel aperture ratios often occur, severely restricting the development of display devices. In light of this, embodiments of the present disclosure provide a display panel that increases the aperture area of ​​sub-pixels, prevents crosstalk, and improves luminance.

[0057] FIG1 is a schematic diagram of a top view of a display panel provided by an embodiment of the present disclosure; FIG2 is a schematic diagram of a cross-sectional structure of the display panel along the II′ direction in FIG1 .

[0058] As shown in Figures 1 and 2, the display panel provided by the embodiment of the present disclosure includes: a base substrate 11, a driving circuit layer 12, a planar layer 13, a pixel defining layer 2, a light emitting device layer 3 and an encapsulation layer 5. The light emitting device layer 3 includes a plurality of light emitting devices p.

[0059] The base substrate 11 has the function of supporting and bearing, and is usually a glass substrate. When applied to a flexible display device, the base substrate 11 may also be a flexible substrate, which is not limited here.

[0060] The drive circuit layer 12 is located on the base substrate 11 and includes multiple pixel circuits. Each pixel circuit is connected to a light-emitting device p, and is used to control the light emission of the light-emitting device p. The drive circuit layer 12 includes multiple thin-film transistors (TFTs), capacitors, resistors, and other components, and is typically manufactured using thin-film technology.

[0061] Planarization layer 13 is located on the side of drive circuit layer 12 facing away from substrate 11. Planarization layer 13 covers the surface of drive circuit layer 12, providing insulation and protection, as well as a flat surface. Planarization layer 13 can be made of inorganic materials such as silicon oxide and silicon nitride, or organic materials, without limitation.

[0062] As shown in FIG. 3 , the planar layer 13 includes a plurality of via holes h, one via hole h corresponds to one light emitting device p, and the light emitting device p is electrically connected to the driving circuit layer 12 through the corresponding via hole h.

[0063] The pixel defining layer 2 is located on the planar layer 13 and is used to define the positions of the sub-pixels, that is, the positions of the light emitting devices p. The pixel defining layer 2 includes a plurality of openings k, and one light emitting device p is disposed in each opening k.

[0064] The pixel defining layer 2 generally has a relatively large thickness, and a plurality of openings k are formed by an etching process, thereby further forming functional film layers of the light-emitting device in the openings.

[0065] The light-emitting device layer 3 is located on a side of the pixel defining layer 2 facing away from the planar layer 13 , and the light-emitting device layer 3 includes a plurality of light-emitting devices p.

[0066] In some embodiments, the light-emitting device p is an organic light-emitting diode (OLED) device. Specifically, as shown in FIG3 , the light-emitting device layer 3 includes an anode layer 31 , a hole injection layer 32 , a hole transport layer 33 , a light-emitting layer 34 , an electron transport layer 35 , an electron injection layer 36 , and a cathode layer 37 .

[0067] The anode layer 31 is located on the planar layer 13 and includes multiple discrete anodes. Each anode corresponds to a via h, and the anodes are electrically connected to the drive circuit layer 12 through the corresponding via h. The anode layer 31 is made of a material such as indium tin oxide (ITO). Specifically, a transparent conductive material layer can be formed on the surface of the planar layer 13, and then an etching process can be used to form the anode pattern.

[0068] The openings k in the pixel definition layer 2 correspond one-to-one with the anodes. The pixel definition layer 2 covers the edges of the anodes, and each opening k exposes the corresponding anode. Each anode corresponds to a via h in the planar layer. The drive circuit layer 12 includes multiple drive transistors, and each anode is connected to the corresponding drive transistor through a corresponding via h.

[0069] Hole injection layer 32 is located on the side of the anode facing away from planar layer 13. Hole injection layer 32 is used to provide holes for the OLED device, increasing its stability. Hole injection layer 32 can be made of polymer materials such as poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) (PEDOT:PSS) or polyethylene aniline, or metal oxide materials such as molybdenum trioxide (MoO3) or tungsten trioxide (WO3), without limitation.

[0070] The hole transport layer 33 is located on the side of the hole injection layer 32 away from the anode. The hole transport layer 33 can improve the hole transport ability of the OLED device, which is beneficial to the transport of carriers to the light-emitting layer. At the same time, the hole transport layer 33 also has the function of blocking electrons, which can balance the transport of intercepted carriers and help improve the efficiency of the device. The hole transport layer 33 can be made of tertiary aromatic amine N,N'-diphenyl-N,N'-di(3-methylphenyl)-1,1'-biphenyl-4,4'-diamine (TPD), N,N'-diphenyl-N,N'-(1-naphthyl)-1,1'-biphenyl-4,4'-diamine (NPB), 4,4'-di(9-carbazole)biphenyl (CBP), or isoindole materials, etc., which are not limited here.

[0071] The light-emitting layer 34 is located on the side of the hole transport layer 33 facing away from the hole injection layer 32. In the OLED device, the light-emitting layer 34 is made of an organic light-emitting material. OLED display panels require three OLED devices that emit three primary colors of light, so the materials used for the light-emitting layers in different OLED devices are also different.

[0072] The electron transport layer 35 is located on the side of the light-emitting layer 34 away from the hole transport layer 33. The electron transport layer 35 is used to transport electrons, which facilitates the transport of carriers to the light-emitting layer and improves the efficiency of the device. The electron transport layer 35 can be made of materials such as 8-hydroxyquinoline aluminum (Alq3), 2-(4-biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (PBD), and 1,3,5-tris(1-phenyl-1H-benzimidazol-2-yl)benzene (TPBi), without limitation.

[0073] Electron injection layer 36 is located on the side of electron transport layer 35 facing away from light-emitting layer 34. Electron injection layer 36 is used to provide electrons to the OLED device, thereby increasing device stability. Electron injection layer 36 can be made of materials such as lithium fluoride (LiF), sodium fluoride (NaF), cesium fluoride (CsF), calcium (Ca), and barium (Ba), without limitation.

[0074] The cathode layer 37 is located on the side of the electron injection layer 36 away from the electron transport layer 35. The cathode 37 is usually made of a whole layer and can be made of materials such as metallic silver (Ag), which is not limited here. As shown in Figure 2, the display panel also includes: an encapsulation layer 5 located on the side of the pixel defining layer 2 and the light-emitting device layer 3 away from the flat layer 13. The light-emitting device needs to block water and oxygen to extend its service life. The encapsulation layer covers all light-emitting devices and film layers, which can increase the path for water and oxygen to enter the light-emitting device, thereby playing a role in blocking water and oxygen.

[0075] In the embodiment of the present disclosure, the encapsulation layer 5 can adopt thin film encapsulation (Thin-Film Encapsulation, abbreviated as TFE), which generally includes multiple layers of alternating inorganic layers and organic layers, wherein the layer closest to the light-emitting device and the layer on the outermost side adopt inorganic layers to block water and oxygen; an organic layer is arranged between adjacent inorganic layers to reduce stress.

[0076] Optionally, the outermost surface of the encapsulation layer 5 facing away from the substrate can be set as a flat surface, which is conducive to the formation of other film layers such as the touch function layer on the encapsulation layer 5.

[0077] Optionally, when the encapsulation layer 5 is a thin film layer covering the surface of the light-emitting device layer, the outermost surface of the encapsulation layer 5 facing away from the base substrate may have the same pattern as the light-emitting device layer and the pixel defining layer, which is not limited here.

[0078] In the disclosed embodiment, as shown in Figure 1, the pixel-defining layer 2 includes a plurality of first retaining walls 21 and a plurality of second retaining walls 22. The plurality of first retaining walls 21 extend along a first direction x and are arranged along a second direction y; the plurality of second retaining walls 22 extend along the second direction y and are arranged along the first direction x. The first direction x and the second direction y intersect. In a specific implementation, the first direction x can be the direction of subpixel rows, and the second direction y can be the direction of subpixel columns; alternatively, the first direction x can be the direction of subpixel columns, and the second direction y can be the direction of subpixel rows.

[0079] To reduce the cost of manufacturing the display panel, the embodiment of the present disclosure sets the height of the first retaining wall 21 to be smaller than that of the second retaining wall 22. The first retaining wall 21 and the second retaining wall 22 are surface treated to make the first retaining wall 21 lyophilic and the second retaining wall 22 lyophobic. This allows the functional layer and the light-emitting layer of the light-emitting device to be manufactured using an inkjet printing process along the second direction.

[0080] Specifically, as shown in FIG2 , the light-emitting devices include: red light-emitting devices pr, green light-emitting devices pg, and blue light-emitting devices pb. The plurality of red light-emitting devices pr are arranged along a second direction y to form a plurality of red light-emitting device columns; the plurality of green light-emitting devices pg are arranged along the second direction y to form a plurality of green light-emitting device columns; the plurality of blue light-emitting devices pb are arranged along the second direction y to form a plurality of blue light-emitting device columns; and the plurality of red light-emitting device columns, the plurality of green light-emitting device columns, and the plurality of blue light-emitting device columns are arranged in a predetermined order along a first direction x.

[0081] In the embodiment of the present disclosure, the hole injection layer 32, the hole transport layer 33 and the light-emitting layer 34 of the light-emitting device can be produced by a linear inkjet printing process, and the electron transport layer 35, the electron injection layer 36 and the cathode layer 37 can be produced by a full-surface evaporation process, thereby greatly reducing costs.

[0082] When making the hole injection layer 32, the hole transport layer 33 and the light-emitting layer 34, ink of the corresponding material can be inkjet printed on each opening k and each first retaining wall 21 along the second direction y. Since the height of the first retaining wall 21 is smaller than the height of the second retaining wall 22, and the first retaining wall 21 is lyophilic and the second retaining wall 22 is lyophobic, the ink can only cover the surface of the first retaining wall 21 during inkjet printing so that the ink on the same side is connected into a whole, and will not cross the second retaining wall 22 to cause color bleeding problems.

[0083] When forming the electron transport layer 35, the electron injection layer 36, and the cathode layer 37, a full-surface evaporation method can be used. The electron transport layer 35, the electron injection layer 36, and the cathode layer 37 are sequentially and fully covered on the film layer inside the opening k, the film layer on the surface of the first retaining wall 21, and the surface of the second retaining wall 22. The production process does not require a high-cost fine mask, thereby simplifying the process and reducing production costs.

[0084] FIG3 is a schematic diagram of a top view of a display panel in the related art.

[0085] As shown in FIG3 , in related art, the via hole h connected to the anode of the light-emitting device is typically provided below the first retaining wall 21. Because the via hole h needs to be provided below the first retaining wall 21, the first retaining wall 21 is typically relatively wide, limiting the area of ​​the opening k. This results in a low aperture ratio of the sub-pixel and easily causes problems such as ink overflow.

[0086] In the disclosed embodiment, as shown in Figure 2, via h is positioned below the second retaining wall 22, with the orthographic projection of via h onto the substrate located within the orthographic projection of the second retaining wall 22 onto the substrate. The thickness of the second retaining wall 22 is greater than that of the first retaining wall 21, so positioning via h below the second retaining wall 22 provides better coverage for via h. Furthermore, positioning via h below the second retaining wall 22 appropriately increases the width of opening k in the second direction y, thereby increasing the sub-pixel's opening area and improving the sub-pixel's brightness.

[0087] Optionally, as shown in FIG1 , the via h may be disposed at the intersection of each first retaining wall 21 and each second retaining wall 22 so that the orthographic projection of the via h on the substrate is located within the orthographic projection of the substrate at the intersection of the first retaining wall 21 and the second retaining wall 22 .

[0088] FIG4 is a schematic diagram of the outgoing light of an OLED device in the related art.

[0089] As shown in Figure 4, a display panel typically includes red OLED devices pr, green OLED devices pg, and blue OLED devices pb arranged in an array. Due to the inherent characteristics of the OLED device's light-emitting mechanism, the angle of light emitted by the OLED device is random. This causes large-angle light emitted by the OLED device to reach adjacent OLED devices, resulting in cross-color and low light extraction efficiency directly above them.

[0090] In view of this, in the embodiment of the present disclosure, a dielectric layer 4 is provided in the display panel to allow light to be totally reflected at the interface between the encapsulation layer and the dielectric layer, thereby improving the light extraction efficiency directly above the light emitting device.

[0091] 5 is a second schematic top view of the display panel according to an embodiment of the present disclosure; FIG6 is a schematic cross-sectional view of the display panel along the II' direction in FIG5; and FIG7 is a schematic cross-sectional view of another display panel according to an embodiment of the present disclosure.

[0092] As shown in FIG5 and FIG6 , in the embodiment of the present disclosure, the display panel further includes a dielectric layer 4. The dielectric layer 4 is located on a side of the pixel defining layer 2 away from the planar layer 13.

[0093] In the embodiment of the present disclosure, the dielectric layer 4 includes a plurality of dielectric units 41 . By selecting a material with a suitable refractive index to manufacture the dielectric units 41 , the dielectric units 41 can be made to have a function of total reflection of incident light.

[0094] The encapsulation layer 5 is typically quite thick, and light emitted from the light-emitting device first passes through the encapsulation layer 5 before entering the dielectric unit 41. To satisfy the requirement for total internal reflection, the refractive index of the encapsulation layer 5 must be greater than that of the dielectric layer 4, creating a condition where light is incident from a denser medium into a less dense medium. In practical applications, the refractive index of TFE is approximately 1.8. Therefore, in the disclosed embodiment, the refractive index of the dielectric layer 4 is less than 1.8. The greater the difference in refractive index between the dielectric layer 4 and the encapsulation layer 5, the smaller the critical angle for total internal reflection. In specific implementations, the appropriate dielectric layer material can be selected based on the angle of light emitted from the light-emitting device toward the edge.

[0095] In the embodiment of the present disclosure, the dielectric layer 4 can be made of acrylic material. Acrylic material is usually added with materials such as photosensitive groups, catalytic groups, and surfactants, which are beneficial to improving the optical performance of the dielectric layer 4.

[0096] In some embodiments, as shown in Figure 6, the dielectric layer 4 can be set on the surface of the pixel defining layer 2, and the cathode layer 37 in the light-emitting device covers the dielectric layer during production. Since the functional film layer of the light-emitting device is usually thin, usually at the nanometer level, the optical path generated by the functional film layer can be ignored. When the refractive index of the encapsulation layer is greater than the refractive index of the dielectric layer 4, the dielectric layer 4 can fully reflect the incident light.

[0097] In some embodiments, as shown in FIG7 , the dielectric layer 4 may also be disposed on the cathode layer 37 of the light-emitting device, thereby preventing the functional layer of the light-emitting device from being cut by the dielectric layer 4 during manufacture, and allowing the encapsulation layer 5 to be in direct contact with the dielectric layer 4 so that total reflection occurs at the interface between the encapsulation layer 5 and the dielectric layer 4.

[0098] FIG8 is one of schematic diagrams of the outgoing light of the light emitting device provided in an embodiment of the present disclosure.

[0099] As shown in FIG8 , after a plurality of dielectric units 41 are provided on the pixel defining layer 2 , the large-angle light emitted toward the edge of the light-emitting device p is totally reflected when it enters the dielectric unit 41 , so that the light is converged back again, thereby avoiding the generation of cross-color and increasing the light extraction efficiency directly above the light-emitting device p, thereby improving the luminous performance of the device.

[0100] As shown in FIG4 , the dielectric units 41 in the dielectric layer 4 are arranged along the four edges of the opening k, so that the light emitted from the light emitting device p toward the four edges can be reflected back by the dielectric units 41 , thereby improving the light extraction efficiency directly above the light emitting device.

[0101] The dielectric units 41 are usually spaced at a set distance to reduce the filling rate of the dielectric unit 41. This allows the refractive index to continuously change when light enters the dielectric layer 4, thereby causing the incident angle of the light to change to a certain extent, which is conducive to the total reflection of the incident light.

[0102] In a specific implementation, the dielectric unit 41 is typically micron-sized and is appropriately sized based on the resolution of the display panel. For example, the distance between two adjacent light-emitting devices in a current display panel is approximately 15 μm to 50 μm. Therefore, the width of the dielectric unit 41 parallel to the substrate can be 4 μm to 10 μm. The disclosed embodiments do not limit the specific value of the width of the dielectric unit 41. The distance between adjacent dielectric units 41 is set to be less than the width of the dielectric unit 41. For example, the distance between adjacent dielectric units 41 is set to be 1 μm to 3 μm. The disclosed embodiments do not limit the specific value of the spacing between dielectric units 41.

[0103] In a specific implementation, the dielectric units 41 can be configured as at least one of a cylinder, a cone, or a hemisphere. Taking Figures 6 and 7 as examples, the dielectric units 41 can be configured as cylinders, which can be cylindrical or prism-shaped, without limitation. Each dielectric unit 41 is spaced a predetermined distance apart and evenly distributed around the edges of the opening k. Alternatively, the dielectric units 41 can be configured as cones, pyramids, or frustums or truncated pyramids.

[0104] FIG9 is a second schematic diagram of the outgoing light of the light-emitting device provided in an embodiment of the present disclosure; FIG10 is a third schematic diagram of the outgoing light of the light-emitting device provided in an embodiment of the present disclosure.

[0105] Alternatively, as shown in Figure 9, dielectric element 41 can be configured as a hemisphere, where the height of dielectric element 41 is the radius of the hemisphere, and the width of dielectric element 41 is the diameter of the hemisphere. By configuring dielectric element 41 as a hemisphere, the effect of total internal reflection of incident light by dielectric element 41 can be optimized by taking advantage of the changing angle of incidence of light at different locations on the hemisphere's surface. Simulation experiments with dielectric elements 41 of different shapes indicate that configuring dielectric element 41 as a hemisphere achieves optimal results.

[0106] Alternatively, as shown in FIG10 , the dielectric unit 41 may be configured as a special-shaped columnar structure, with the width of the dielectric unit 41 decreasing first and then increasing in the direction away from the pixel defining layer 2 (i.e., the vertically upward direction in FIG10 ), i.e., the width of the dielectric unit 41 at both ends is greater than the width in the middle. In this way, when light strikes the surface of the dielectric unit 41, it tends to be reflected along the sidewalls of the dielectric unit 41, ultimately converging the light emitted by the light-emitting device p directly upward, thereby improving the light extraction efficiency directly above the light-emitting device.

[0107] The embodiment of the present disclosure requires a dielectric unit 41 to be provided at the edge of each opening k on the pixel defining layer. To avoid affecting the via h during the fabrication of the dielectric unit 41 and to avoid insufficient stress at the via h, the embodiment of the present disclosure places the via h below the second retaining wall 22.

[0108] Optionally, the dielectric unit 41 does not need to be provided at the intersection of the first retaining wall 21 and the second retaining wall 22 , so providing the via h at this location can minimize the impact of the dielectric unit 41 on the via h and the anode.

[0109] In the disclosed embodiment, the width of the orthographic projection of the via h on the base substrate is greater than the width of the orthographic projection of the dielectric unit 41 on the base substrate. The smaller width of the dielectric unit 41 allows for the placement of dielectric units 41 along the edges of the opening k, thereby focusing light. Since the dielectric unit 41 is relatively small and does not occupy a large space, the width of the first retaining wall 21 can be appropriately reduced, thereby increasing the width of the opening k in the second direction y. This increases the width of the anode in the second direction y and increases the opening area of ​​the sub-pixel. Figure 11 is a schematic diagram of the cross-sectional structure of the display panel along the X-X' direction in Figure 5; Figure 12 is a schematic diagram of the cross-sectional structure of the display panel along the Y-Y' direction in Figure 5.

[0110] As shown in Figures 11 and 12, when fabricating the pixel-defining layer, the first retaining wall 21 and the second retaining wall 22 have different heights, but can have the same or different widths. In the disclosed embodiment, the width of the first retaining wall 21 is greater than the width of the second retaining wall 22, and the height of the first retaining wall 21 is less than the height of the second retaining wall 22. The first retaining wall 21 is lyophilic, while the second retaining wall 22 is lyophobic. Providing the second retaining wall 22 with a thicker thickness and a narrower width helps prevent the ink of the luminescent layer from flowing over the second retaining wall 22 and into adjacent openings during inkjet printing. Providing the first retaining wall 21 with a smaller thickness and a wider width helps ensure that the ink of the hole injection layer, hole transport layer, and luminescent layer spreads along the second direction y during inkjet printing, achieving a relatively uniform thickness.

[0111] In the disclosed embodiment, the dielectric units located on the first retaining wall 21 are referred to as first dielectric units 411, and the dielectric units located on the second retaining wall 22 are referred to as second dielectric units 412. As shown in FIG4 , the dielectric units are arranged at the edge of the opening k. For each opening (a sub-pixel), a row of second dielectric units 412 is arranged on each of the second retaining walls 22 on both sides of the first direction x, and a row of first dielectric units 411 is arranged on each of the first retaining walls 21 on both sides of the second direction y. Thus, two rows of first dielectric units 411 are provided on the same first retaining wall 21, and two rows of second dielectric units 412 are provided on the same second retaining wall 22. Because the width of the first retaining wall 21 is greater than the width of the second retaining wall 22, the spacing w1 between the two rows of first dielectric units 411 arranged at the edges of two adjacent openings on the same first retaining wall 21 is greater than the spacing w2 between the two rows of second dielectric units 412 arranged at the edges of two adjacent openings on the same second retaining wall 22. The interval w1 between the two rows of first dielectric units 411 on the first retaining wall 21 may be greater than the width of the first dielectric units 411 ; the interval w2 between the two rows of second dielectric units 412 on the second retaining wall 22 may be less than the width of the second dielectric units 412 .

[0112] In a specific implementation, the width of the first retaining wall 21 is 35 μm to 50 μm, and the width of the second retaining wall 22 is approximately 15 μm to 20 μm. The width of the dielectric unit 41 is typically 4 μm to 10 μm, so the spacing between the two rows of first dielectric units 411 on the first retaining wall 21 can be increased to reduce the manufacturing difficulty.

[0113] As shown in Figure 2, along the first direction x, the light-emitting devices on either side of each second retaining wall 22 are of different colors; along the second direction y, the light-emitting devices on either side of each first retaining wall 21 are of the same color. Because cross-coloring between sub-pixels primarily occurs between light-emitting devices of different colors, in this disclosed embodiment, the spacing between two adjacent first dielectric units 411 located at the same opening edge is greater than the spacing between two adjacent second dielectric units 412. Setting the density of the first dielectric units 411 to be less than that of the second dielectric units 412 results in a relatively sparse arrangement of the first dielectric units 411 and a relatively dense arrangement of the second dielectric units 412. This increases the total internal reflection of the incident light by the second dielectric units 412, thus preventing cross-coloring. Reducing the density of the first dielectric units 411 can also reduce manufacturing complexity.

[0114] Because the heights of the first retaining wall 21 and the second retaining wall 22 are different, the heights of the first and second retaining walls 411, 412 can be set to be consistent when manufacturing the dielectric unit 41. For example, the heights of the first and second dielectric units 411, 412 can both be set to 2 μm to 5 μm. The consistent heights of the first and second dielectric units 411, 412 maintain the height difference between the first and second retaining walls, thereby preventing ink from flowing over the second retaining wall during inkjet printing and causing color bleeding.

[0115] Alternatively, the height of the first dielectric unit 411 can be increased so that the surfaces of the first dielectric unit 411 and the second dielectric unit 412 facing away from the pixel defining layer are flush. It should be noted that the so-called flushness in the embodiment of the present disclosure means that the upper surfaces of the first dielectric unit 411 and the second dielectric unit 412 are substantially in the same plane. During manufacturing, the height difference between the first retaining wall 21 and the second retaining wall 22 is approximately 0.2μm to 1.2μm, so the height of the second dielectric unit 412 can be 2μm to 5μm. In order to compensate for the height difference between the first retaining wall and the second retaining wall, the height of the first dielectric unit 411 can be 2.2μm to 6.2μm. The flushness of the upper surfaces of the first dielectric unit 411 and the second dielectric unit 412 can ensure that the light emitted from the light-emitting device to the four edges is fully reflected, achieving a consistent total reflection effect.

[0116] Based on the same inventive concept, embodiments of the present disclosure further provide a display device comprising any of the aforementioned display panels. The display device may be an OLED display screen, an OLED monitor, an OLED television, or other display device, or may be a mobile device such as a mobile phone, a tablet computer, or a smart photo album. Because the principles underlying the problems solved by the display device are similar to those of the aforementioned display panels, the implementation of the display device may refer to the implementation of the aforementioned display panels, and any repetitions will not be repeated.

[0117] Another aspect of the embodiments of the present disclosure provides a method for manufacturing a display panel. FIG13 is one of the flow charts of the method for manufacturing a display panel provided in the embodiments of the present disclosure; FIG14 is a second flow chart of the method for manufacturing a display panel provided in the embodiments of the present disclosure.

[0118] As shown in FIG13 , the method for manufacturing a display panel provided in an embodiment of the present disclosure includes:

[0119] S10, forming a driving circuit layer on the base substrate;

[0120] S20, forming a flat layer on a side of the driving circuit layer facing away from the base substrate;

[0121] S30, forming an anode layer of the light-emitting device layer on the flat layer;

[0122] S40, forming a pixel defining layer on the planar layer;

[0123] S50, forming a dielectric layer on a side of the pixel defining layer away from the planar layer;

[0124] S60, forming a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer and a cathode layer of a light emitting device layer in sequence on a side of the anode and the pixel defining layer away from the planar layer;

[0125] S70 , forming an encapsulation layer on a side of the light-emitting device layer facing away from the planar layer.

[0126] As shown in FIG14 , the method for manufacturing a display panel provided in an embodiment of the present disclosure includes:

[0127] S10, forming a driving circuit layer on the base substrate;

[0128] S20, forming a flat layer on a side of the driving circuit layer facing away from the base substrate;

[0129] S30, forming an anode layer of the light-emitting device layer on the flat layer;

[0130] S40, forming a pixel defining layer on the planar layer;

[0131] S50, forming a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer and a cathode layer of a light emitting device layer in sequence on a side of the anode and the pixel defining layer away from the planar layer;

[0132] S60, forming a dielectric layer on a side of the cathode layer facing away from the pixel defining layer;

[0133] S70 , forming an encapsulation layer on a side of the light-emitting device layer facing away from the planar layer.

[0134] Among them, the light-emitting device is an OLED device, the anode layer includes a plurality of mutually separated anodes, the anode defines the position of the light-emitting device, and the pixel definition layer includes a plurality of openings for exposing the anode, and one opening corresponds to one anode. An anode and the hole injection layer, hole transport layer, light-emitting layer, electron transport layer, electron injection layer and cathode layer corresponding to the position of the anode constitute a light-emitting device. The dielectric layer includes a plurality of dielectric units, and the dielectric unit is used to fully reflect the incident light. The large-angle light emitted to the edge of the light-emitting device is totally reflected when it is incident on the dielectric unit, so that the light is re-converged to avoid the generation of cross-color, while increasing the light extraction efficiency directly above the light-emitting device and improving the device's luminescence performance.

[0135] Specifically, the manufacturing methods of the drive circuit layer and the planar layer can be found in the related art manufacturing process of the array substrate in the OLED display panel, and will not be described in detail here. The planar layer is formed with a plurality of vias that expose the drive circuit layer. These vias are used to connect to the anode of the light-emitting device to drive the light-emitting device through the drive circuit.

[0136] First, the anode pattern is formed on the surface of the flat layer. Specifically, a transparent conductive material layer can be formed on the flat layer, and then an etching process is used to form the anode pattern. The anode layer can be made of materials such as indium tin oxide (ITO).

[0137] A pixel definition layer pattern is then formed on the flat layer. The pixel definition layer in the disclosed embodiment is composed of a first retaining wall of smaller thickness and a second retaining wall of greater thickness. In some embodiments, a full layer of material for the first retaining wall can be formed, and then etched to form multiple first retaining wall patterns; then a full layer of material for the second retaining wall can be formed, and then etched to form multiple second retaining wall patterns, thereby forming a double-layer retaining wall structure. In some embodiments, a full layer of material for the pixel definition layer can also be formed, and then a halftone mask exposure technique can be used to form first and second retaining walls of varying heights.

[0138] The pixel-defining layer can be made of polyimide or polymethyl methacrylate, with a lyophobic component added to the material. This allows the first retaining wall to become lyophilic and the second retaining wall to become lyophobic after exposure and development. The first and second retaining walls surround the edge of the anode, with the via covered by the second retaining wall. The first and second retaining walls form multiple openings, each exposing an anode.

[0139] Then, a dielectric layer pattern is formed on the pixel definition layer. The dielectric layer can be made of acrylic material, wherein the dielectric unit pattern in the dielectric layer can be formed by any one of the processes of photoresist hot melt method, chemical vapor deposition method or inkjet printing method.

[0140] The hole injection layer is then inkjet-printed along the extension direction of the second retaining wall, so that the ink of the hole injection layer is formed on the surface of each opening and the first retaining wall without exceeding the second retaining wall. The hole injection layer can be made of polymer materials such as poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) (PEDOT:PSS) and polyethylene aniline, or metal oxide materials such as molybdenum trioxide (MoO3) and tungsten trioxide (WO3), without limitation.

[0141] The hole transport layer is then inkjet printed on the surface of the hole injection layer. Similarly, the ink of the hole transport layer will only be on the surface of the previously formed hole injection layer and will not exceed the second barrier wall. The hole transport layer can be made of tertiary aromatic amines N,N'-diphenyl-N,N'-di(3-methylphenyl)-1,1'-biphenyl-4,4'-diamine (TPD), N,N'-diphenyl-N,N'-(1-naphthyl)-1,1'-biphenyl-4,4'-diamine (NPB), 4,4'-bis(9-carbazole)biphenyl (CBP), or isoindole materials, etc., without limitation here.

[0142] The light-emitting layers are then sequentially inkjet-printed on the surface of the hole transport layer. The red light-emitting device array is inkjet-printed with ink for emitting red light; the green light-emitting device array is inkjet-printed with ink for emitting green light; and the blue light-emitting device array is inkjet-printed with ink for emitting blue light. The ink in each light-emitting layer does not extend beyond the second barrier, thus preventing color bleed-through.

[0143] An electron transport layer is then vapor-deposited over each light-emitting layer and the second barrier wall. The electron transport layer can be made of materials such as 8-hydroxyquinoline aluminum (Alq3), 2-(4-biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (PBD), and 1,3,5-tris(1-phenyl-1H-benzimidazol-2-yl)benzene (TPBi), though these materials are not limited here.

[0144] Then, an electron injection layer is deposited on the surface of the electron transport layer. The electron injection layer can be made of materials such as lithium fluoride (LiF), sodium fluoride (NaF), cesium fluoride (CsF), calcium (Ca), barium (Ba), etc., which are not limited here.

[0145] Then, a cathode layer is deposited on the entire surface of the electron injection layer. The cathode layer can be made of metal silver (Ag) and other materials, which are not limited here.

[0146] Finally, an encapsulation layer is evaporated on the cathode layer, and the encapsulation layer is used to encapsulate and protect the light-emitting device.

[0147] Because the thicknesses of layers such as the hole injection layer, hole transport layer, light-emitting layer, electron transport layer, and electron injection layer are on the nanometer scale, the optical path length of light entering these layers is negligible. Therefore, total internal reflection of the dielectric elements in the dielectric layer can be considered to occur at the interface between the encapsulation layer and the dielectric elements. Therefore, the refractive index of the dielectric layer must be lower than that of the encapsulation layer, creating a condition where light is incident from a denser medium into a less dense medium. In practical applications, the refractive index of the encapsulation layer is approximately 1.8, so the refractive index of dielectric layer 4 must be lower than 1.8.

[0148] In some embodiments, after the pixel definition layer is formed, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, and a cathode layer can be formed first, and then a dielectric layer can be formed on the surface of the cathode layer facing away from the pixel definition layer. The processes and materials used to form the functional layers and light-emitting layers of the light-emitting device can be found in the above embodiments and are not further described here.

[0149] The dielectric layer can be made of acrylic material, wherein the pattern of the dielectric unit in the dielectric layer can be formed by any one of a photoresist hot melt method, a chemical vapor deposition method or an inkjet printing method.

[0150] Placing the dielectric layer on the cathode layer can prevent the functional layer of the light-emitting device from being cut by the dielectric layer during fabrication, and can also allow the encapsulation layer to directly contact the dielectric layer, so that total reflection occurs at the interface between the encapsulation layer and the dielectric layer.

[0151] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0152] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A display panel, comprising: substrate; A driving circuit layer is located on the base substrate; a planar layer, located on a side of the driving circuit layer facing away from the base substrate; The planar layer includes a plurality of via holes; a pixel defining layer, located on the flat surface; The pixel defining layer includes: a plurality of first retaining walls and a plurality of second retaining walls, wherein the plurality of first retaining walls extend along a first direction and are arranged along a second direction, and the plurality of second retaining walls extend along the second direction and are arranged along the first direction; the first direction and the second direction intersect; and the plurality of first retaining walls and the plurality of second retaining walls form a plurality of openings; a light-emitting device layer, located on a side of the pixel defining layer away from the planar layer; the light-emitting device layer includes a plurality of light-emitting devices, with one light-emitting device correspondingly disposed in each of the openings; one of the via holes corresponds to one of the light-emitting devices, and the light-emitting device is electrically connected to the driving circuit layer through the corresponding via hole; The height of the first retaining wall is smaller than the height of the second retaining wall, and the orthographic projection of the via hole on the base substrate is located within the orthographic projection of the second retaining wall on the base substrate.

2. The display panel according to claim 1, wherein: The orthographic projection of the via hole on the base substrate is located within the orthographic projection of the base substrate at an intersection of the first retaining wall and the second retaining wall.

3. The display panel according to claim 1 or 2, wherein: The width of the first retaining wall in the second direction is greater than the width of the second retaining wall in the first direction.

4. The display panel according to any one of claims 1 to 3, further comprising: a dielectric layer, located on a side of the pixel defining layer facing away from the planar layer; an encapsulation layer, located on a side of the pixel defining layer and the light-emitting device layer facing away from the planar layer; Wherein, the refractive index of the packaging layer is greater than the refractive index of the dielectric layer.

5. The display panel according to claim 4, wherein: The dielectric layer includes a plurality of dielectric units, and a size of an orthographic projection of the via hole on the base substrate is larger than a size of an orthographic projection of the dielectric unit on the base substrate.

6. The display panel according to claim 5, wherein: The plurality of dielectric units are respectively arranged along four edges of the opening.

7. The display panel according to claim 6, wherein: There is a set distance between adjacent medium units; the set distance is smaller than the width of the medium unit.

8. The display panel according to any one of claims 5 to 7, wherein: The dielectric unit located on the side of the first retaining wall away from the flat layer is a first dielectric unit, and the dielectric unit located on the side of the second retaining wall away from the flat layer is a second dielectric unit; The width of the first medium unit is equal to the width of the second medium unit.

9. The display panel according to claim 8, wherein: The distance between two rows of the first dielectric units arranged at two adjacent edges of the opening on the same first retaining wall is greater than the width of the first dielectric unit; The distance between two rows of the second dielectric units arranged at two adjacent edges of the opening on the same second blocking wall is smaller than the width of the second dielectric unit.

10. The display panel according to claim 8 or 9, wherein: The distance between adjacent first dielectric units located at the same edge of the opening is greater than the distance between adjacent second dielectric units.

11. The display panel according to any one of claims 8 to 10, wherein: The first medium unit and the second medium unit have the same height.

12. The display panel according to any one of claims 8 to 10, wherein: The height of the first dielectric unit is greater than that of the second dielectric unit; and a surface of the first dielectric unit facing away from the first retaining wall is flush with a surface of the second dielectric unit facing away from the second retaining wall.

13. The display panel according to any one of claims 5 to 12, wherein: The dielectric unit is one of a cylinder, a cone or a hemisphere.

14. The display panel according to any one of claims 5 to 12, wherein: The width of the dielectric unit first decreases and then increases in a direction away from the pixel defining layer.

15. A display device comprising the display panel according to any one of claims 1 to 14.

16. A method for manufacturing a display panel, comprising: forming a driving circuit layer on the base substrate; forming a flat layer on a side of the driving circuit layer facing away from the base substrate; The planar layer includes a plurality of via holes; forming an anode layer of a light-emitting device layer on the flat layer; the anode layer comprises a plurality of mutually separated anodes; forming a pixel defining layer on the planar layer; The pixel defining layer includes: a plurality of first retaining walls and a plurality of second retaining walls, wherein the plurality of first retaining walls extend along a first direction and are arranged along a second direction, and the plurality of second retaining walls extend along the second direction and are arranged along the first direction; the first direction and the second direction intersect; the plurality of first retaining walls and the plurality of second retaining walls form a plurality of openings, wherein one opening corresponds to one anode; forming a dielectric layer on a side of the pixel defining layer away from the planar layer; forming a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer and a cathode layer of a light emitting device layer in sequence on a side of the anode and the pixel defining layer away from the planar layer; or forming a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer and a cathode layer of a light emitting device layer in sequence on a side of the anode and the pixel defining layer away from the planar layer; and forming a dielectric layer on a side of the anode layer away from the pixel defining layer; forming an encapsulation layer on a side of the light-emitting device layer facing away from the planar layer; The height of the first retaining wall is smaller than that of the second retaining wall, the orthographic projection of the via hole on the base substrate is located within the orthographic projection of the second retaining wall on the base substrate, and the refractive index of the packaging layer is greater than that of the dielectric layer.

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