Signal transmission circuit and motor controller

Abstract

The invention provides a signal transmission circuit and a motor controller. The signal transmission circuit comprises a micro-control module, a gate driving module, a control channel, a first multiplexing channel and a second multiplexing channel, the control channel and the two multiplexing channels are respectively arranged between the micro-control module and the gate driving module; the gate driving module comprises a transmission function switching unit; when the control signal is at a first level, the first multiplexing channel transmits a clock signal to the transmission function switching unit; the second multiplexing channel is used for transmitting a data signal between the micro-control module and the gate driving module; and when the control signal is at the second level, the first multiplexing channel and the second multiplexing channel respectively transmit the pulse width modulation signal and output the pulse width modulation signal through the transmission function switching unit. According to the invention, two channels for transmitting the pulse broadband modulation signals are multiplexed, so that the channels are also used for transmitting each signal in the SPI protocol, the total number of transmission lines is reduced, and the circuit integration level is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of signal transmission, in particular to a signal transmission circuit and a motor controller. BACKGROUND

[0002] The gate driver plays a crucial intermediary role between the master microcontroller (MCU) and the transistor, and its core responsibility is to manage the switching operation of the transistor according to the complementary pulse width modulation (PWM) signals sent by the MCU, that is, to control the conduction and turn-off of the transistor gate.

[0003] At the same time, in order to ensure the electrical isolation between the high-voltage side and the low-voltage side of the gate driver, the working state of the transistor is monitored in real time through serial peripheral interface (SPI) communication to prevent the transistor from being damaged, and the registers of the Gate Driver can be configured and read by the MCU. In this way, the MCU can not only obtain the state information of the Gate Driver in real time, but also further fine-tune the behavior of the Gate Driver.

[0004] Therefore, there are at least two categories of transmission channels between the gate driver and the microcontroller, one is for transmitting complementary pulse width modulation signals, and the other is for monitoring the working state of the transistor in real time through SPI communication. However, the total number of existing setting channels is large, which is not conducive to providing the integration of the gate driver and the microcontroller.

[0005] It should be noted that the above introduction to the technical background is only to facilitate a clear and complete description of the technical solutions of the present application, and to facilitate the understanding of those skilled in the art. The above technical solutions cannot be considered as known to those skilled in the art merely because they are described in the background section of the present application. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a signal transmission circuit and a motor controller, which can solve the problem of the large total number of setting channels between the existing gate driver and the microcontroller in the prior art, which is not conducive to providing the integration of the gate driver and the microcontroller.

[0007] To achieve the above-mentioned purposes and other related purposes, the present application provides a signal transmission circuit, comprising: a micro-control module, a gate drive module, a control channel, a first multiplexing channel and a second multiplexing channel.

[0008] The control channel and the two multiplexing channels are respectively arranged between the micro-control module and the gate drive module.

[0009] The gate drive module comprises a transmission function switching unit; the micro-control module sends the control signal to the transmission function switching unit through the control channel; the transmission function switching unit is used to switch the functions of the first multiplexing channel and the second multiplexing channel.

[0010] When the control signal is at a first level, the first multiplexing channel is used to receive the clock signal output by the micro-control module and transmit it to the transmission function switching unit, and the second multiplexing channel is used to transmit the data signal between the micro-control module and the gate drive module.

[0011] When the control signal is at a second level, the first multiplexing channel and the second multiplexing channel are respectively used to receive the pulse width modulation signal output by the micro-control module and output it through the transmission function switching unit.

[0012] Optionally, the first input end of the first AND gate receives the control signal, the second input end is connected to the first multiplexing channel, and the output end outputs the corresponding pulse width modulation signal.

[0013] The first input end of the second AND gate receives the control signal, the second input end is connected to the second multiplexing channel, and the output end outputs the corresponding pulse width modulation signal.

[0014] Optionally, the gate drive module further comprises a serial protocol processing unit, a register unit and a logic unit.

[0015] The first end of the serial protocol processing unit receives the control signal, the second end is connected to the first end of the register unit, and the register unit sends a first register instruction based on the level state of the control signal.

[0016] The second end of the register unit is connected to the control end of the logic unit, and the output of the logic unit is regulated based on the first register instruction.

[0017] The first input end and the second input end of the logic unit are both connected to the transmission function switching unit, used to receive the pulse width modulation signal and output the gate control signal based on the first register instruction.

[0018] Optionally, the third end of the serial protocol processing unit is connected to the first multiplexing channel, and the fourth end is connected to the second multiplexing channel; the serial protocol processing unit also performs response processing on the clock signal and the data signal based on the level state of the control signal, and controls the register unit to send a second register instruction.

[0019] Optionally, the signal transmission circuit further comprises n pulse transmission channels; n is an even number greater than or equal to 2; the logic unit comprises n+2 input ends; wherein the third input end to the n+2 input end are arranged one by one corresponding to each pulse transmission channel.

[0020] Each pulse transmission channel is used for receiving the pulse width modulation signal output by the micro control module and transmitting to the logic unit.

[0021] Optionally, when the control signal is the second level, any one of the pulse transmission channels is arranged as a feedback channel.

[0022] The feedback channel is used for outputting the polling signal from the micro control module to the gate drive module when the micro control module is powered on before the gate drive module, and feeding back the power-on reset signal of the gate drive module after the gate drive module is powered on to the micro control module.

[0023] Optionally, the micro control module further comprises a timer unit; the timer unit is used for generating each pulse width modulation signal.

[0024] Optionally, the micro control module further comprises a communication transmission control unit; the communication transmission control unit is used for generating the control signal.

[0025] To achieve the above object and other related objects, the present application provides a motor controller, comprising: a motor system and the signal transmission circuit.

[0026] The motor system is connected to the output end of the gate drive module, and adjusts the torque and speed based on the gate control signal output by the gate drive module.

[0027] Optionally, the motor controller further comprises a back electromotive force detector; the back electromotive force detector is connected to the motor system, and is used for detecting the back electromotive force in the motor system and outputting to the micro control module.

[0028] Optionally, when the micro control module comprises a timer unit, the micro control module further comprises an analog-to-digital conversion unit.

[0029] The analog-to-digital conversion unit is connected to the output end of the back electromotive force detector, and is used for analog-to-digital conversion of the back electromotive force and output to the timer unit to adjust the pulse width modulation signal.

[0030] As described above, the signal transmission circuit and the motor controller of the present application have the following beneficial effects:

[0031] The application multiplexes two transmission pulse broadband modulation signal channels, and uses them to transmit signals in SPI protocol, reduces the total number of transmission lines between the gate drive module and the micro control module, and improves the circuit integration. In addition, the signal transmission circuit only needs one control signal to switch the transmission function switching unit, realizes the function switching of the first multiplexing channel and the second multiplexing channel, and ensures the normal working premise of the circuit, simple structure and low power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 A structure schematic diagram of a data exchange circuit is shown.

[0033] Figure 2 A frame schematic diagram of a signal transmission circuit of the application is shown.

[0034] Figure 3 A structure schematic diagram of a signal transmission circuit of the application is shown.

[0035] Figure 4 A structure schematic diagram of a motor controller of the application is shown.

[0036] Element number explanation

[0037] 1 data exchange circuit

[0038] 11 microcontroller

[0039] 12 gate driver

[0040] 2 signal transmission circuit

[0041] 21 micro control module

[0042] 211 communication transmission control unit

[0043] 212 timer unit

[0044] 213 analog-to-digital conversion unit

[0045] 214 overcurrent protection unit

[0046] 22 gate drive module

[0047] 221 transmission function switching unit

[0048] 2211 first AND gate

[0049] 2212 second AND gate

[0050] 222 serial protocol processing unit

[0051] 223 register unit

[0052] 224 logic units

[0053] 23 Control Channel

[0054] 24 First Multiplexing Channel

[0055] 25 Second Multiplexing Channel

[0056] 26 pulse transmission channels

[0057] 3. Motor controller

[0058] 31 Motor System

[0059] 32 Back EMF Detector Detailed Implementation

[0060] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0061] Please see Figures 1-4 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0062] Comparative Example

[0063] like Figure 1 As shown, this comparative example provides a data exchange circuit 1, including a microcontroller 11, a gate driver 12, and six pulse width modulation (PWM) channels (such as...). Figure 1 Part B) and 4 input / output (IO) channels (e.g. Figure 1 Part A of the microcontroller architecture includes six PWM channels and four I / O channels positioned between the microcontroller 11 and the gate driver 12. The six PWM channels output wideband modulated pulse data from the microcontroller 11 to the gate driver 12. Simultaneously, the four I / O channels implement a serial communication protocol between the microcontroller 11 and the gate driver 12. The four I / O channels are used to transmit the clock signal (SCLK), chip select signal (CS), master-to-slave input (MOSI) data signal, and master-to-slave output (MISO) data signal, respectively.

[0064] Therefore, the microcontroller 11 and the gate driver 12 often need a total of 10 or more transmission lines for corresponding data exchange. In order to further improve the integration and optimize the area of the device, the number of transmission lines needs to be reduced. In some comparative examples, the data unidirectional transmission of the master device output from device input data signal (MOSI) and the master device input from device output data signal (MISO) is changed to an SDIO channel that can be directly bidirectional transmission, that is, part A realizes the SPI protocol through 3 IO channels (including CS channel, SCLK channel and SDIO channel).

[0065] However, even in such a setting, the 10 transmission lines for data exchange can only be optimized to 9 transmission lines, and it is difficult to further reduce the number of transmission lines.

[0066] Embodiments

[0067] As shown in Figure 2 and Figure 3 In order to further optimize the number of transmission lines, the embodiment provides a signal transmission circuit 2, which comprises a micro control module 21, a gate drive module 22, a control channel 23, a first multiplexing channel 24 and a second multiplexing channel 25, wherein the control channel 23 and the two multiplexing channels are respectively arranged between the micro control module 21 and the gate drive module 22.

[0068] As shown in Figure 2 and Figure 3 The gate drive module 22 comprises a transmission function switching unit 221; wherein the micro control module 21 sends a control signal CS and transmits it to the transmission function switching unit 221 through the control channel 23; the transmission function switching unit 221 is used to switch the functions of the first multiplexing channel 24 and the second multiplexing channel 25. When the control signal CS is at a first level, the first multiplexing channel 24 is used to receive the clock signal SCK output by the micro control module 21 and transmit it to the transmission function switching unit 221, and the second multiplexing channel 25 is used to transmit the data signal SDIO between the micro control module 21 and the gate drive module 22; when the control signal CS is at a second level, the first multiplexing channel 24 and the second multiplexing channel 25 are respectively used to receive the pulse width modulation signals (HIN1 signal, LIN1 signal) output by the micro control module 21 and output through the transmission function switching unit 221; wherein the first level and the second level are a group of mutually inverse levels.

[0069] As an example, as shown in Figure 3As shown in the figure, the transmission function switching unit 221 includes a first AND gate 2211 and a second AND gate 2212; the first input end of the first AND gate 2211 and the first input end of the second AND gate 2212 both receive the control signal CS; the second input end of the first AND gate 2211 is connected to the first multiplexing channel 24, and the output end outputs the corresponding pulse width modulation signal. In this embodiment, when the control signal CS is at the first level, the first AND gate 2211 is closed to output, and when the control signal CS is at the second level, the first AND gate 2211 is opened to output the corresponding pulse width modulation signal. The second input end of the second AND gate 2212 is connected to the second multiplexing channel 25, and the output end outputs the corresponding pulse width modulation signal. In this embodiment, when the control signal CS is at the first level, the second AND gate 2212 is closed to output, and when the control signal CS is at the second level, the second AND gate 2212 is opened to output the corresponding pulse width modulation signal. In this embodiment, the first level of the control signal CS is set to low, and the second level is set to high.

[0070] In this embodiment, the logic operation relationship of the two AND gates is controlled based on the control signal CS, so that when the control signal CS is at the second level, the two AND gates respectively turn on the multiplexing channels corresponding to the second input ends of the two AND gates, at this time, the multiplexing channels are used as pulse width modulation signal transmission channels; and when the control signal CS is at the first level, the two AND gates cannot output the data of the corresponding multiplexing channels, at this time, the multiplexing channels are used as serial protocol transmission channels. In this embodiment, the functions of the channels are distinguished by the control signal CS and the two AND gates, so that the functions of the channels are different under different level conditions.

[0071] It should be noted that the specific setting of the transmission function switching unit 221 is not limited to this embodiment, and the level state of the control signal CS is also not limited to this embodiment. As long as the setting of the two multiplexing channel function switching can be realized based on the control signal CS, it is within the protection scope of this embodiment.

[0072] It should be further noted that the specific position of the transmission function switching unit 221 is not limited to this embodiment. For example, in another embodiment, the transmission function switching unit 221 is arranged outside the gate drive module 22, that is, the control channel 23, the first multiplexing channel 24, the second multiplexing channel 25 and the transmission function switching unit 221 are all arranged between the micro control module 21 and the gate drive module 22. In fact, as long as the multiplexing channel function switching can be realized by the transmission function switching unit 221, and the number of channels between the micro control module 21 and the gate drive module 22 is ultimately reduced, it is within the protection scope of this embodiment.

[0073] As an example, as shown in the figure, the signal transmission circuit 2 further includes n pulse transmission channels 26; n is an even number greater than or equal to 2. Figure 3 As an example, as shown in the figure, the signal transmission circuit 2 further includes n pulse transmission channels 26; n is an even number greater than or equal to 2.

[0074] In the embodiment, the gate drive module 22 is a three-phase gate driver, and in addition to the first multiplexing channel 24 and the second multiplexing channel 25, four pulse transmission channels 26 are further provided, which transmit a total of six pulse width modulation signals (corresponding to three groups of first level input signals HIN1-HIN3 and three groups of second level input signals LIN1-LIN3, respectively). At this time, each pulse transmission channel 26 is used to receive the pulse width modulation signal output by the micro control module 21 and transmit it to the subsequent circuit. In the embodiment, the subsequent circuit is provided with a logic unit 224, and the pulse width modulation signal is finally output to the logic unit 224.

[0075] It should be noted that the number of pulse transmission channels 26 is set based on the number of transistors to be driven by the gate drive module 22. Driving two transistors (such as flexible printed circuit board driving), driving four transistors (H-bridge motor system), driving eight transistors (such as four-phase stepping motor system driving), or driving more transistors can be set as needed, as long as the number of pulse transmission channels 26 is greater than or equal to the sum of the first multiplexing channel 24 and the second multiplexing channel 25, which can ensure signal transmission, and is not limited to the embodiment.

[0076] In the embodiment, when the control signal CS is at the second level, any one of the pulse transmission channels 26 is set as a feedback channel, which is used to output the polling signal sent by the micro control module 21 to the gate drive module 22 when the micro control module 21 is powered on before the gate drive module 22, and to feed back the power-on reset signal of the gate drive module 22 to the micro control module 21 after the gate drive module 22 is powered on. After ensuring that the micro control module 21 and the gate drive module 22 are both powered on, the micro control module 21 sends the pulse modulation signal, the clock signal and the data signal to the gate drive module 22.

[0077] As shown in Figure 2 and Figure 3 The gate drive module 22 further includes a serial protocol processing unit 222, a register unit 223, and a logic unit 224. The first end of the serial protocol processing unit 222 receives the control signal CS, and the second end is connected to the first end of the register unit 223, which controls the register unit 223 to send the first register instruction based on the level state of the control signal CS. The second end of the register unit 223 is connected to the control end of the logic unit 224, which controls the output of the logic unit 224 based on the first register instruction. The first input end and the second input end of the logic unit 224 are both connected to the transmission function switching unit 221, which is used to receive the pulse width modulation signal and output the gate control signal based on the first register instruction. The first register instruction is used to control the logic unit 224 to open or close the output.

[0078] Specifically, the third end of the serial protocol processing unit 222 is connected to the first multiplexing channel 24, and the fourth end is connected to the second multiplexing channel 25. The serial protocol processing unit 222 also performs response processing on the clock signal SCK and the data signal SDIO based on the level state of the control signal CS, and controls the register unit 223 to issue a second register instruction. The second register instruction is used to regulate the parameter state of the logic unit 224.

[0079] In this embodiment, when the control signal CS is set to the first level, the serial protocol processing unit 222 controls the register unit 223 to output a first control instruction based on the control signal CS, and turns off the output of the logic unit 224 (at this time, the signal of each pulse transmission channel 26 is input to the logic unit 224 but not output). At the same time, when the control signal CS is set to the first level, the serial protocol processing unit 222 also performs response processing on the received clock signal SCK and data signal SDIO based on the control signal CS, such as performing handshake, data buffering, and error detection in the serial protocol, and regulating the register unit to output a second control instruction based on the received clock signal SCK and data signal SDIO, and configuring the parameters in the logic unit 224, such as regulating the bandwidth time of the gate control signal to control the switching frequency of each switch tube in the subsequent circuit. In addition, the parameters in the gate drive module 22 can also be regulated based on the register unit 223, which is not limited to this embodiment.

[0080] In this embodiment, when the control signal CS is set to the second level, the serial protocol processing unit 222 controls the register unit 223 to output a first control instruction based on the control signal CS, and turns on the output of the logic unit 224. Each pulse modulation signal is regulated by the logic unit 224 to obtain a gate control signal and output to the subsequent circuit. At the same time, when the control signal CS is set to the second level, the serial protocol processing unit 222 does not perform response processing on the received clock signal SCK and data signal SDIO based on the level state of the control signal CS.

[0081] Specifically, the logic unit 224 includes n+2 input ends; wherein the third input end to the n+2 input end is set one-to-one with each pulse transmission channel 26; each pulse transmission channel 224 is used to receive the pulse width modulation signal output by the micro control module 21 and transmit to the corresponding logic unit 224.

[0082] In this embodiment, when the control signal CS is at the second level, the serial protocol processing unit 222 disables the communication control function and does not process the waveforms transmitted by the first multiplexed channel 24 and the second multiplexed channel 25. Therefore, each multiplexed channel and each pulse transmission channel 26 in the gate drive module 22 are used to transmit pulse modulation signals. When the control signal CS is at the first level, the serial protocol processing unit 222 enables the communication control function, identifies the waveforms transmitted by the first multiplexed channel 24 and the second multiplexed channel 25, and issues corresponding register instructions based on the transmitted signals to control and ensure the working state of the logic unit 224. In this embodiment, in addition to the first multiplexed channel 24 and the second multiplexed channel 25, four pulse transmission channels 26 are also provided. When the control signal CS is at the second level, these channels will still be transmitted to the logic unit 224. Therefore, in this embodiment, the register instructions set by the register unit 223 include at least a pause instruction (the first register instruction) to control the logic unit 224 to output gate control signals to subsequent circuits.

[0083] It should be noted that, in addition to regulating the output signal of the gate drive module 22 through registered instructions in conjunction with the control signal CS, additional combinational logic circuits can be set inside the gate drive module 22 to ensure the consistency of the overall circuit function. In fact, the specific setting method is not limited to this embodiment.

[0084] like Figure 2 and Figure 3 As shown, the microcontroller module 21 also includes a communication transmission control unit 211; the communication transmission control unit 211 is used to generate control signals CS.

[0085] Specifically, in this embodiment, the communication transmission control unit 211, as a unit in the microcontroller module 21 that processes the serial communication protocol, is also used to issue clock signal SCK and data signal SDIO.

[0086] like Figure 2 and Figure 3 As shown, the microcontroller module 21 also includes a timer unit 212; the timer unit 212 is used to generate pulse width modulation signals.

[0087] Specifically, in this embodiment, the gate driving module 22 is used for three-phase driving, so the timer unit 212 needs to generate 6 pulse width modulation signals, including three sets of first level input signals HIN1-3 and three sets of second level input signals LIN1-3.

[0088] It should be noted that the signal transmission circuit 2 provided in this embodiment multiplexes at least two channels, performs two functions, and ensures that the two functions do not interfere with each other, thus optimizing the device area and improving the device integration. It can also reduce the number of pins when packaging the circuit in the future.

[0089] like Figure 4 As shown, this embodiment also provides a motor controller 3, including: a motor system 31 and the signal transmission circuit 2 described above.

[0090] Specifically, the motor system 31 is connected to the output terminal of the gate drive module 22, and adjusts the torque and speed based on the gate control signal CS output by the gate drive module 22. In this embodiment, the motor system includes multiple transistors, and the rotation of the motor is controlled by regulating the on and off states of each transistor based on the gate control signal.

[0091] As an example, the motor system 31 also includes a back EMF detector 32; the back EMF detector 32 is connected to the motor system 31 and is used to detect the back EMF in the motor system 31 and output it to the microcontroller module 21.

[0092] In this embodiment, the position is detected by back electromotive force, and the zero-crossing point of the back electromotive force is used as an indicator of the rotor position to achieve precise control of the motor's commutation operation, so that the motor rotates continuously in a fixed direction, thereby ensuring that the motor reaches the maximum output torque and reducing torque pulsation.

[0093] In this embodiment, when the microcontroller module 21 includes a timer unit 212, the microcontroller module 21 also includes an analog-to-digital converter unit 213; the analog-to-digital converter unit 213 is connected to the output terminal of the back EMF detector 32 and is used to convert the back EMF into an analog-to-digital value and output it to the timer unit 212 to adjust each pulse width modulation signal.

[0094] As an example, when the microcontroller module 21 includes a timer unit 212, the microcontroller module 21 also includes an overcurrent protection unit 214; the overcurrent protection unit 214 is connected to the output terminal of the back EMF detector 32 and is used to output a shutdown signal to the timer unit 212 when the back EMF exceeds a preset threshold, so that the motor controller 3 is turned off.

[0095] It should be noted that the specific structure of the motor system 31 is not limited to this embodiment. Any setting that can rotate the motor based on the signal transmission circuit to perform the motor function is within the protection scope of this embodiment.

[0096] It should be further explained that the motor controller 3 set based on the signal transmission circuit 2 in this embodiment can further reduce the complexity of the circuit connection, improve the integration of the motor controller 3, and ensure the lightweight development of the motor controller 3.

[0097] In summary, this invention provides a signal transmission circuit and a motor controller. The signal transmission circuit includes a microcontroller module, a gate drive module, a control channel, a first multiplexed channel, and a second multiplexed channel. The control channel and the two multiplexed channels are respectively disposed between the microcontroller module and the gate drive module. The gate drive module includes a transmission function switching unit. When the control signal is at a first level, the first multiplexed channel transmits a clock signal to the transmission function switching unit; the second multiplexed channel transmits data signals between the microcontroller module and the gate drive module. When the control signal is at a second level, both the first and second multiplexed channels transmit pulse width modulation signals and are output through the transmission function switching unit. This invention multiplexes two channels that transmit pulse width modulation signals, allowing them to also transmit signals in the SPI protocol, reducing the total number of transmission lines and improving circuit integration. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0098] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A signal transmission circuit, characterized by comprising: The signal transmission circuit comprises at least a micro-control module, a gate drive module, a control channel, a first multiplexing channel and a second multiplexing channel, wherein the control channel and the two multiplexing channels are respectively arranged between the micro-control module and the gate drive module; The gate drive module comprises a transmission function switching unit, the micro-control module sends a control signal to the transmission function switching unit through the control channel, and the transmission function switching unit is used for switching the functions of the first multiplexing channel and the second multiplexing channel; When the control signal is at a first level, the first multiplexing channel is used for receiving a clock signal output by the micro-control module and transmitting the clock signal to the transmission function switching unit, and the second multiplexing channel is used for transmitting a data signal between the micro-control module and the gate drive module; When the control signal is at a second level, the first multiplexing channel and the second multiplexing channel are respectively used for receiving a pulse width modulation signal output by the micro-control module and outputting the pulse width modulation signal through the transmission function switching unit.

2. The signal transmission circuit according to claim 1, characterized by: The transmission function switching unit comprises a first AND gate and a second AND gate; The first input end of the first AND gate receives the control signal, the second input end of the first AND gate is connected to the first multiplexing channel, and the output end of the first AND gate outputs a corresponding pulse width modulation signal; The first input end of the second AND gate receives the control signal, the second input end of the second AND gate is connected to the second multiplexing channel, and the output end of the second AND gate outputs a corresponding pulse width modulation signal.

3. The signal transmission circuit of claim 1, wherein: The gate drive module further comprises a serial protocol processing unit, a register unit and a logic unit; The first end of the serial protocol processing unit receives the control signal, the second end of the serial protocol processing unit is connected to the first end of the register unit, and the register unit sends a first register instruction based on the level state of the control signal; The second end of the register unit is connected to the control end of the logic unit, and the logic unit outputs based on the first register instruction; The first input end and the second input end of the logic unit are both connected to the transmission function switching unit, and are used for receiving a pulse width modulation signal and outputting a gate control signal based on the first register instruction.

4. The signal transmission circuit of claim 3, wherein: The third end of the serial protocol processing unit is connected to the first multiplexing channel, and the fourth end of the serial protocol processing unit is connected to the second multiplexing channel; the serial protocol processing unit further performs response processing on the clock signal and the data signal based on the level state of the control signal, and controls the register unit to send a second register instruction.

5. The signal transmission circuit of claim 3, wherein: The signal transmission circuit further comprises n pulse transmission channels; n is an even number greater than or equal to 2; the logic unit comprises n+2 input ends; wherein the third input end to the n+2 input end are arranged one by one corresponding to each pulse transmission channel; Each pulse transmission channel is used for receiving a pulse width modulation signal output by the micro-control module and transmitting the pulse width modulation signal to the logic unit.

6. The signal transmission circuit of claim 5, wherein: When the control signal is at the second level, any one of the pulse transmission channels is set as a feedback channel. The feedback channel is used to output the polling signal from the micro control module to the gate drive module when the micro control module is powered on prior to the gate drive module, and to feed back the power-on reset signal from the gate drive module to the micro control module after the gate drive module is powered on.

7. The signal transmission circuit according to any one of claims 1 to 6, characterized by: The micro control module further comprises a timer unit; the timer unit is used to generate each pulse width modulation signal.

8. The signal transmission circuit according to any one of claims 1 to 6, characterized by: The micro control module further comprises a communication transmission control unit; the communication transmission control unit is used to generate the control signal.

9. A motor controller characterized by: The motor controller comprises a motor system and the signal transmission circuit as claimed in any one of claims 1-8; The motor system is connected to the output end of the gate drive module, and adjusts the torque and speed of the motor based on the gate control signal output by the gate drive module.

10. The motor controller of claim 9, wherein: The motor controller further comprises a back electromotive force detector; The back electromotive force detector is connected to the motor system, and is used to detect the back electromotive force in the motor system and output to the micro control module.

11. The motor controller of claim 10, wherein: When the micro control module comprises a timer unit, the micro control module further comprises an analog-to-digital conversion unit; The analog-to-digital conversion unit is connected to the output end of the back electromotive force detector, and is used to output the back electromotive force after analog-to-digital conversion to the timer unit to adjust each pulse width modulation signal.

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