Compensated power supply circuit, method, system, and electronic device for chiplet inter-chiplet interconnect interface

Abstract

The application discloses a compensation power supply circuit, method and system for a Chiplet inter-chip interconnection interface, and electronic equipment, and relates to the technical field of semiconductor integrated circuits. The circuit comprises an LDO power supply circuit for providing power supply to the drivers of multiple channels; and a distributed local compensation circuit corresponding to the drivers of the multiple channels. Each local compensation circuit comprises a first compensation loop for generating a pre-compensation current pulse in response to the jump of a data signal from a first logic level to a second logic level, and supplementing the charge of the power supply node of the driver; and a second compensation loop for detecting the change trend of the power supply of the target driver to generate a feedback adjustment signal, so as to dynamically adjust the amplitude of the pre-compensation current pulse, provide transient current during dynamic operation, and suppress the voltage ripple of the power supply node, thereby effectively improving the power stability in high-density data transmission, relieving the power supply pressure of the LDO, reducing the power consumption and area required by the LDO, and improving the signal quality.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a compensation power supply circuit, method, system, and electronic device for chiplet interconnect interfaces. Background Technology

[0002] With the development of integrated circuit technology, chiplet technology has attracted widespread attention due to its ability to achieve heterogeneous integration, improve design flexibility, and reduce costs. Interconnection between chiplets is typically achieved through high-speed SerDes (serializer / deserializer) interfaces. The drivers in these interfaces generate significant transient currents during data transmission, leading to substantial voltage ripple at their power supply nodes (VDDQ), which affects signal integrity and system stability.

[0003] Please refer to Figure 1 Traditional power supply schemes typically use a single global LDO (low dropout linear regulator) to power all drivers. However, this approach has the following drawbacks:

[0004] 1. LDOs have limited bandwidth and slew rate, making them unable to quickly respond to the transient current demands generated by the driver, resulting in a significant drop in supply voltage during data transitions.

[0005] 2. Severe IRDrop Issue: Because LDOs need to supply current to all drivers, their output current is relatively large, leading to a severe voltage drop (IRDrop) problem caused by parasitic resistance of traces on the Power Delivery Network (PDN), especially in long-distance or high-density interconnects. According to Ohm's law, even if the LDO can generate a stable power supply, the large supply current and the different trace lengths in different channels will result in a non-negligible voltage drop that varies from channel to channel.

[0006] 3. Large on-chip capacitor requirements: In order to suppress voltage ripple, large on-chip decoupling capacitors are usually required near each driver, which occupies valuable chip area.

[0007] To address the aforementioned issues, several distributed power supply solutions have been proposed, such as placing local voltage regulators or switched capacitor circuits near the driver. However, these solutions are often complex in structure and costly, or still cannot perfectly resolve the impacts of process, voltage, and temperature (PVT) variations. Therefore, there is an urgent need for a new power supply circuit that can achieve more stable and uniform driver power supply in high-density, high-speed chiplet interconnect scenarios with less area and power consumption. Summary of the Invention

[0008] The purpose of this invention is to provide a distributed dual-loop compensated power supply circuit, method, system, and electronic device for Chiplet inter-chip interconnect interfaces. While retaining the traditional LDO for global basic power supply, an intelligent compensation unit is deployed locally on the driver of each data channel. Through two compensation loops, the system is responsible for accurately predicting and compensating for transient large currents caused by data transitions, and adaptively adjusting for slow voltage fluctuations caused by process, voltage, temperature changes, and load differences. This provides stable and fast power supply to suppress voltage ripple during data transmission, while reducing the current output requirements of the global LDO, thereby improving the IRDrop problem of the power supply network.

[0009] This invention provides a compensation power supply circuit for a chipplet inter-chip interconnect interface, comprising:

[0010] The LDO power supply circuit is used to provide power to the drivers of multiple channels;

[0011] Distributed local compensation circuits are configured corresponding to the drivers of multiple channels. Each local compensation circuit includes:

[0012] The first compensation circuit is configured to generate a pre-compensation current pulse in response to a transition of the transmitted data signal of the corresponding channel from a first logic level to a second logic level, so as to inject supplementary charge directly into the power supply node of the target driver during the transition.

[0013] The second compensation circuit is configured to detect the changing trend of the target driver power supply and generate a feedback adjustment signal to dynamically adjust the amplitude of the pre-compensation current pulse of the first compensation circuit.

[0014] The LDO power supply circuit is used to provide static operating current. The first compensation circuit and the second compensation circuit work together to provide transient current and suppress voltage ripple at the power supply node during dynamic operation, thereby maintaining the stability of the power supply voltage.

[0015] Preferably, the first compensation circuit includes a pulse generation circuit and a switching transistor;

[0016] The input terminal of the pulse generation circuit is coupled to the transmit data signal of the driver of the corresponding channel, and is used to output a voltage pulse when a logic level transition is detected.

[0017] The gate of the switching transistor is connected to the output terminal of the pulse generation circuit to receive the voltage pulse, and the source of the switching transistor is connected to the current source I. c The drain of the switching transistor is connected to the power supply node VDDQ of the target driver DRV;

[0018] Wherein, the voltage pulse controls the switching transistor to turn on to form the pre-compensated current pulse, and / or, the pulse generation circuit is configured to output a voltage pulse with adjustable pulse width so that the duration of the pre-compensated current pulse can adapt to the transient current requirements under different process, voltage and temperature conditions.

[0019] Preferably, the second compensation circuit includes a high-pass filter circuit, a negative feedback amplifier, and a regulating transistor;

[0020] The input terminal of the high-pass filter circuit is connected to the power supply node of the target driver to detect the changing trend of the power supply and filter out the DC component.

[0021] The non-inverting input of the negative feedback amplifier is coupled to a common-mode reference voltage Vcm, and the inverting input of the negative feedback amplifier is coupled to the output of the high-pass filter circuit, for generating the feedback adjustment signal based on the changing trend;

[0022] The gate of the regulating transistor is coupled to the output of the negative feedback amplifier to receive the regulating signal Vsc, the source of the regulating transistor is coupled to the power supply node provided by the LDO power supply circuit, and the drain of the regulating transistor is coupled to the input of the current source to adjust the amplitude of the pre-compensation current pulse.

[0023] Preferably, the high-pass filter circuit includes a capacitor and a resistor connected in series between the power supply node and the common-mode reference voltage Vcm.

[0024] Preferably, the switching transistor is an NMOS transistor; the regulating transistor is a PMOS transistor.

[0025] Preferably, the LDO power supply circuit includes:

[0026] A low-dropout linear regulator (LDO) provides a stable supply voltage VDDQ at its output.

[0027] A power supply network is provided between the output of the LDO and the drivers of the multiple channels for distributing the power supply voltage VDDQ to each channel;

[0028] Each of the plurality of channels includes a serializer SER and a driver DRV, wherein the power supply node of the driver DRV is coupled to the power supply network to receive the power supply voltage VDDQ.

[0029] Preferably, the second compensation circuit is configured to dynamically adjust the conduction state of the regulating transistor through the feedback adjustment signal, thereby adjusting the amplitude of the pre-compensation current pulse to adapt to the load current differences of different drivers.

[0030] The present invention also provides a compensated power supply method for a chipplet inter-chip interconnect interface, comprising:

[0031] The LDO power supply circuit provides a stable static power supply voltage to the drivers of multiple channels.

[0032] In each channel, in response to the transition of the corresponding channel transmitted data signal from the first logic level to the second logic level, a pre-compensation current pulse is generated through the first compensation circuit and directly injected into the power supply node of the channel driver to compensate for the transient charge demand during the transition.

[0033] The second compensation circuit detects the low-frequency voltage change trend of the power supply node, generates a feedback adjustment signal, and dynamically adjusts the amplitude of the pre-compensation current pulse according to the adjustment signal to suppress voltage ripple and adapt to process, voltage, temperature changes and load differences of different drivers.

[0034] The present invention also provides a Chiplet interconnect interface compensation power supply system, including the compensation power supply circuit as described in the embodiments, and the compensation power supply method as described in the embodiments.

[0035] The present invention also provides an electronic device including a Chiplet interconnect interface compensated power supply system as described in the embodiments.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] 1. Provides a more stable power supply: By setting a fast-response compensation circuit locally on the driver, transient current can be replenished in time, effectively suppressing voltage ripple during data transitions. Even with a significant reduction in on-chip capacitance, it can provide a more stable power supply than traditional single LDO power supply solutions, thereby improving eye diagram quality.

[0038] 2. Reduce LDO design complexity and size: Since most transient current is provided by the local compensation circuit, the LDO only needs to provide the static operating current. Therefore, its current output capability requirement is greatly reduced, and it can be used in a very small size, which reduces the design complexity and chip area of ​​the LDO.

[0039] 3. Improve the IRDrop problem: Since the LDO output current is relatively small, the voltage drop (IRDrop) problem caused by the parasitic resistance of the traces on the power supply network will be greatly improved, thus enhancing the power supply quality.

[0040] 4. High adaptability: Through the pulse width adjustable fast loop and the feedback-based slow loop, this solution can adapt to different process, voltage, temperature (PVT) conditions, as well as the personalized load requirements of different drivers, and has high robustness. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of a traditional single LDO power supply layout in the background art of this invention;

[0042] Figure 2 This is a schematic diagram of the layout of the compensation power supply circuit for the Chiplet inter-chip interconnect interface in an embodiment of the present invention. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] In high-speed chiplet interconnect circuits, power supply is a critical factor affecting signal quality, especially the driver power supply, which directly impacts the quality of the signal eye diagram. Drivers need to drive off-chip channels with significant parasitic resistance, capacitance, and inductance; therefore, their output stage transistors (such as MOSFETs) are typically designed to be large, requiring substantial transient current. If the driver's power supply (VDDQ) is unstable, exhibiting noise, voltage drop, or ripple, these disturbances will directly couple to the transmitted data signal, leading to a reduction in the eye height and eye width of the receiver's eye diagram, severely affecting interconnect reliability. Therefore, the stability requirements for the driver power supply network are far higher than those for the internal logic circuitry.

[0045] like Figure 1In the traditional single LDO power supply scheme shown, a single low-dropout linear regulator (LDO) needs to supply current to the drivers (DRVs) and serializers (SERs) of all channels. However, the drivers have extremely high data rates, requiring a large current pulse to be supplied in a very short time each time data transitions from logic "0" to "1". This places extremely high demands on the bandwidth and transient response capability of the LDO, typically forcing designers to use high-power, high-bandwidth LDOs supplemented with a large number of on-chip decoupling capacitors. Simultaneously, due to the physical distance between each channel driver and the LDO, the metal traces on the power supply path have a significant parasitic resistance. According to Ohm's law (ΔV=I×R), even if the LDO output voltage is stable, the large dynamic current flowing through traces of different lengths will produce different IR voltage drops, resulting in a significant decrease in the actual supply voltage (VDDQ) of the remote driver and an increase in ripple. This unevenness and instability in power supply has become a bottleneck limiting the performance improvement of high-density, high-speed chiplet interconnects.

[0046] To address the problems encountered in the traditional single LDO power supply scheme, this invention provides a compensated power supply circuit for the Chiplet inter-chip interconnect interface, namely a distributed dual-loop compensated power supply scheme. (See also...) Figure 2 As shown, it includes:

[0047] The LDO power supply circuit is used to provide power to the drivers of multiple channels;

[0048] Distributed local compensation circuits are configured corresponding to the drivers of multiple channels. Each local compensation circuit includes:

[0049] The first compensation circuit is configured to generate a pre-compensation current pulse in response to a transition of the transmitted data signal of the corresponding channel from a first logic level to a second logic level, so as to inject supplementary charge directly into the power supply node of the target driver during the transition.

[0050] The second compensation circuit is configured to detect the changing trend of the target driver power supply and generate a feedback adjustment signal to dynamically adjust the amplitude of the pre-compensation current pulse of the first compensation circuit.

[0051] The LDO power supply circuit provides quiescent operating current. The first compensation circuit and the second compensation circuit work together to provide transient current and suppress voltage ripple at the power supply node during dynamic operation, thereby maintaining the stability of the power supply voltage. This embodiment can be understood as follows: while retaining a simplified central LDO for global quiescent power supply, a smart compensation unit is locally deployed for the driver of each data channel. This unit includes two cooperating compensation loops, one fast and one slow, to accurately address transient high current demands and slow voltage fluctuations, respectively, thus freeing the LDO from high dynamic performance requirements.

[0052] Specifically, the LDO power supply circuit includes: a low-dropout linear regulator (LDO) whose output provides a stable supply voltage VDDQ; a power supply network, disposed between the output of the LDO and the drivers of the plurality of channels, for distributing the supply voltage VDDQ to each channel; wherein each of the plurality of channels includes a serializer (SER) and a driver (DRV), and the power supply node of the driver (DRV) is coupled to the power supply network to receive the supply voltage VDDQ. Figure 2 As shown, the LDO receives an input voltage (such as VDD) and outputs a stable supply voltage VDDQ. This VDDQ is distributed to multiple parallel data channels via a power supply network (e.g., a PDN consisting of metal traces). Each data channel includes a serializer (SER) and a driver (DRV). The driver's power supply node is directly connected to the power supply network to receive VDDQ. Since it only needs to provide quiescent current, its output transistor can be designed to be very small, which greatly reduces its power consumption and area.

[0053] Distributed local compensation circuit: At the power supply node (labeled VDDQ_Local) of each driver (DRV), a local compensation unit is integrated in a distributed manner. Each unit operates independently and is responsible for maintaining the stability of its corresponding driver power supply node. Each local compensation unit consists of a first compensation loop (fast loop) and a second compensation loop (slow loop).

[0054] The first compensation loop (fast loop) includes a pulse generation circuit and a switching transistor. The input of the pulse generation circuit is coupled to the transmit data signal of the driver of the corresponding channel, and is used to output a voltage pulse when a logic level transition is detected. The gate of the switching transistor is connected to the output of the pulse generation circuit to receive the voltage pulse. The source of the switching transistor is connected to the current source Ic, and the drain of the switching transistor is connected to the power supply node VDDQ of the target driver DRV. The voltage pulse controls the switching transistor to turn on to form the pre-compensation current pulse. For example, the switching transistor is an NMOS transistor.

[0055] When the driver's transmit data signal transitions from 0 to 1, the pulse generation circuit immediately generates a narrow voltage pulse. This pulse causes the NMOS switching transistor to turn on momentarily, allowing the current from the current source Ic to flow through the switching transistor briefly and be directly injected into the driver's power supply node VDDQ. This injected pre-compensation current pulse effectively provides additional charge for the driver to charge the channel load capacitor at the moment of transition, thereby significantly suppressing the voltage drop (undershoot) of VDDQ caused by sudden current demand.

[0056] To enhance the adaptability of the circuit under different process angles, operating voltages, and temperatures (PVT), the pulse generation circuit is configured to output voltage pulses with adjustable pulse widths, so that the duration of the pre-compensation current pulse can adapt to the transient current demand under different process, voltage, and temperature conditions, thereby adjusting the duration of the pre-compensation current to match the differences in transient current demand caused by PVT variations.

[0057] The second compensation loop (slow loop) includes a high-pass filter circuit, a negative feedback amplifier, and a regulating transistor. The input of the high-pass filter circuit is connected to the power supply node of the target driver to detect the changing trend of the power supply and filter out the DC component. The non-inverting input of the negative feedback amplifier is coupled to a common-mode reference voltage Vcm, and the inverting input is coupled to the output of the high-pass filter circuit to generate the feedback regulation signal based on the changing trend. The gate of the regulating transistor is coupled to the output of the negative feedback amplifier to receive the regulation signal Vsc, the source of the regulating transistor is coupled to the power supply node provided by the LDO power supply circuit, and the drain of the regulating transistor is coupled to the input of the current source to adjust the amplitude of the pre-compensation current pulse. The goal of the second compensation loop (slow loop) is to stabilize the slow fluctuation of VDDQ and dynamically calibrate the amplitude of the fast loop compensation current to cope with PVT changes and load differences between different drivers. For example, the regulating transistor is a PMOS transistor, and the high-pass filter circuit includes a capacitor and a resistor connected in series between the power supply node and the common-mode reference voltage Vcm.

[0058] While the fast loop provides transient current, the slow loop handles fine-tuning. The high-pass filter continuously monitors the VDDQ node and filters out its DC component, transmitting only the voltage ripple trend to the negative feedback amplifier. The amplifier compares this change with a common-mode reference voltage Vcm and generates a feedback adjustment signal Vsc. This signal Vsc is sent to the gate of the PMOS transistor, dynamically adjusting its on-resistance. Since the PMOS transistor, current source Ic, and NMOS switch are connected in series in the compensation current path from VDDQ to ground, adjusting the PMOS transistor's conduction state directly controls the maximum current amplitude that this path can handle (i.e., the amplitude of the pre-compensation current pulse). For example, when environmental changes cause an increase in driver current demand, or when VDDQ shows a decreasing trend, the amplifier output Vsc decreases, deepening the PMOS transistor's conduction and allowing a larger compensation current Ic to flow, thereby boosting and stabilizing the VDDQ voltage near the target value. Since the transistor is connected in series with the current source Ic, the change in its on-resistance directly affects the magnitude of the current flowing through Ic, thereby dynamically adjusting the amplitude of the pre-compensation current pulse. This feedback mechanism ensures that the compensation current is neither too large (leading to overshoot) nor too small (leading to insufficient suppression), perfectly matching the actual load requirements of the driver and adapting to changes in PVT.

[0059] The core principle of this embodiment is as follows: Based on the original LDO power supply, the distributed dual-loop compensation power supply scheme adds a local PMOS compensation circuit at the driver of each channel, thus making it distributed. Each local compensation circuit has two loops: a fast loop detects the data transmission transition from 0 to 1 and drives an NMOS transistor through a circuit that generates a voltage pulse. When the data transitions from 0 to 1, the NMOS transistor briefly conducts, allowing current Ic to flow. Since the fast loop provides different pulse widths of supply current under different PVT states, and different drivers require different currents, a slow loop is needed for adjustment. The slow loop detects changes in VDDQ, filters the DC component of VDDQ through a high-pass filter circuit to stabilize the amplifier's input common-mode voltage to VCM, and then amplifies the changes in VDDQ using an amplifier connected as a negative feedback circuit, generating a control voltage Vsc. Vsc is used to adjust the gate voltage of the PMOS transistor above the local compensation circuit, thereby adjusting the magnitude of Ic. In this circuit, the LDO's current output transistor needs to be very small, and only the LDO needs to provide the DC voltage in the circuit's initial state. The voltage stability in the operating state is ensured by a local compensation circuit. This power supply scheme can provide a more stable power supply than the traditional single LDO power supply scheme while reducing the size of the on-chip capacitors in each channel. Moreover, since the required LDO output current is small, the voltage drop problem caused by the parasitic resistance of the traces will also be greatly improved.

[0060] The distributed dual-loop compensation circuit proposed above can provide a stable, low-ripple VDDQ under different process-voltage-temperature (PVT) conditions, thereby improving eye diagram quality; it also reduces the load capacitance and local decoupling capacitance of the LDO, improving the integration of the transmitter; and it reduces the output current of the LDO, greatly improving the IR voltage drop problem.

[0061] In this embodiment, through the coordinated operation of the LDO power supply circuit and the distributed local compensation circuit (fast loop and slow loop), precise and efficient management of the power supply of the Chiplet interconnect interface is achieved. Its workflow can be divided into a static working stage and a dynamic transition stage.

[0062] During the static operation phase, the system experiences no data transitions and remains in standby or low-speed operation. The LDO stably outputs VDDQ, providing static bias current to all serializers (SER), drivers (DRV), and amplifiers and current sources in the local compensation unit. At this time, since there are no data transitions, the NMOS transistors in the fast loop remain off, the compensation current Ic is almost zero, and the system power consumption is extremely low.

[0063] During the dynamic transition phase, when data transmission begins and a logical transition from 0 to 1 occurs, the system enters dynamic compensation mode, where the fast and slow loops work together.

[0064] Fast response (fast loop dominant): The data transition edge is detected by the local pulse generation circuit, which immediately outputs a voltage pulse. This pulse turns on the NMOS transistor instantaneously, and the preset compensation current Ic quickly flows from the supply voltage VDDQ provided by the LDO and is directly injected into the power supply node VDDQ of the driver. This process realizes the localization and instantaneous replenishment of transient charge, which greatly alleviates the transient supply pressure on the LDO.

[0065] Slow calibration (slow loop coordination): While the fast loop provides transient current, and subsequently, the slow loop continuously monitors the voltage level of the driver power supply node VDDQ. Its core function is "calibration" rather than "transient response." Regardless of whether there is a current jump, as long as VDDQ deviates from the ideal value due to PVT changes or load differences, the negative feedback amplifier will adjust Vsc to change the conduction state of the PMOS transistor, thereby dynamically setting the optimal amplitude reference for Ic. This ensures precise preparation for each compensation, both now and in the future, guaranteeing that the compensation strength always matches the real-time requirements.

[0066] Based on the same inventive concept, embodiments of the present invention provide a compensation power supply method for a Chiplet inter-chip interconnect interface, comprising:

[0067] Step S1: A stable static supply voltage is provided to the drivers of multiple channels through the LDO power supply circuit. During this stage, the LDO provides static bias current to the serializers (SER), drivers (DRV), amplifiers, current sources, etc. in the local compensation unit of all channels, ensuring that the system is in standby or low-speed operation. At this time, since there is no data transition, the switching transistors of the compensation circuit are turned off, no compensation current is generated, and the system power consumption is extremely low.

[0068] Step S2: In each channel, in response to the transition of the corresponding channel transmitted data signal from the first logic level to the second logic level, a pre-compensation current pulse is generated through the first compensation circuit and directly injected into the power supply node of the channel driver to compensate for the transient charge demand during the transition.

[0069] Step S21: Transition Detection: The local pulse generation circuit continuously monitors the transmitted data signal of the corresponding channel. When a transition edge from logic low level to logic high level is detected, the subsequent steps are immediately triggered.

[0070] Step S22: Pulse generation and switching control: The pulse generation circuit outputs a voltage pulse with a preset width, which is applied to the gate of the switching transistor such as an NMOS transistor in the first compensation circuit, causing it to turn on momentarily.

[0071] Step S23: Current Injection: After the switching transistor is turned on, a transient current path is formed from the supply voltage VDDQ through the current source Ic, the switching transistor, and the driver power supply node VDDQ. The preset compensation current Ic is directly injected as a pre-compensation current pulse to realize the localization and immediate replenishment of transient charge, thereby suppressing the instantaneous voltage drop of VDDQ.

[0072] Step S3: The low-frequency voltage change trend of the power supply node is detected by the second compensation circuit, a feedback adjustment signal is generated, and the amplitude of the pre-compensation current pulse is dynamically adjusted according to the adjustment signal to suppress voltage ripple and adapt to process, voltage, temperature changes and load differences of different drivers.

[0073] Step S31: Trend detection: The voltage of the driver power supply node VDDQ is continuously detected by the high-pass filter circuit in the second compensation circuit, and its DC component is filtered out, extracting only the low-frequency ripple and slow drift signal caused by PVT changes or load differences.

[0074] Step S32: Feedback Signal Generation: The extracted trend signal is input to a negative feedback amplifier and compared with a stable common-mode reference voltage VCM. The amplifier generates a feedback adjustment signal Vsc based on the difference between the two. For example, when VDDQ shows a decreasing trend, Vsc decreases accordingly.

[0075] Step S33: Current Amplitude Adjustment: The feedback adjustment signal Vsc is applied to the gate of the adjustment transistor, such as a PMOS transistor, in the second compensation circuit to dynamically adjust its on-resistance. Since the adjustment transistor is connected in series with the current source Ic in the compensation current path, adjusting its on-state can dynamically adjust the magnitude of the current flowing through the current source Ic, thus setting the amplitude reference of the pre-compensation current pulse.

[0076] Step S34: Closed-loop stabilization: This adjustment process is continuous and closed-loop. It ensures that the compensation current amplitude is always set at the optimal value regardless of whether there are data jumps, thus preparing precisely for the next transient compensation and keeping the VDDQ voltage stable near the target value for a long time.

[0077] By iteratively executing the above steps, this method achieves precise, dynamic, and adaptive management of power supply to the Chiplet interconnect interface, effectively solving problems such as slow transient response, severe IRDrop, and poor PVT adaptability in traditional solutions.

[0078] Based on the same inventive concept, this invention also provides a Chiplet interconnect interface compensation power supply system, including the compensation power supply circuit as described in the embodiment, and the compensation power supply method as described in the embodiment. The principle of solving the problem in the embodiment is the same as that in the circuit embodiment, and will not be repeated here.

[0079] This invention also provides an electronic device, including the Chiplet interconnect interface compensated power supply system as described in this invention.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A compensation power supply circuit for a chiplet interconnect interface, characterized in that, include: The LDO power supply circuit includes: a low dropout linear regulator (LDO) whose output provides a stable supply voltage VDDQ; and a power supply network disposed between the output of the LDO and the drivers of multiple channels, distributing the supply voltage VDDQ to each channel to provide power to the drivers of the multiple channels; wherein each of the multiple channels includes a serializer (SER) and a driver (DRV), and the power supply node of the driver (DRV) is coupled to the power supply network to receive the supply voltage VDDQ. Distributed local compensation circuits are configured corresponding to the drivers of multiple channels. Each local compensation circuit includes: The first compensation circuit, including a pulse generation circuit and a switching transistor, is configured to generate a pre-compensation current pulse in response to a transition of the transmitted data signal of the corresponding channel from a first logic level to a second logic level, so as to inject supplementary charge directly into the power supply node of the target driver during the transition. The second compensation circuit includes a high-pass filter circuit, a negative feedback amplifier, and an adjustment transistor, configured to detect the changing trend of the target driver power supply and generate a feedback adjustment signal to dynamically adjust the amplitude of the pre-compensation current pulse of the first compensation circuit. The LDO power supply circuit is used to provide static operating current. The first compensation circuit and the second compensation circuit work together to provide transient current and suppress voltage ripple at the power supply node during dynamic operation, thereby maintaining the stability of the power supply voltage.

2. The compensation power supply circuit for the Chiplet inter-chip interconnect interface as described in claim 1, characterized in that, The input terminal of the pulse generation circuit is coupled to the transmit data signal of the driver of the corresponding channel, and is used to output a voltage pulse when a logic level transition is detected. The gate of the switching transistor is connected to the output terminal of the pulse generation circuit to receive the voltage pulse, and the source of the switching transistor is connected to the current source I. c The drain of the switching transistor is connected to the power supply node VDDQ of the target driver DRV; Wherein, the voltage pulse controls the switching transistor to turn on to form the pre-compensated current pulse, and / or, the pulse generation circuit is configured to output a voltage pulse with adjustable pulse width so that the duration of the pre-compensated current pulse can adapt to the transient current requirements under different process, voltage and temperature conditions.

3. The compensation power supply circuit for the Chiplet inter-chip interconnect interface as described in claim 1, characterized in that, The input terminal of the high-pass filter circuit is connected to the power supply node of the target driver to detect the changing trend of the power supply and filter out the DC component. The non-inverting input of the negative feedback amplifier is coupled to a common-mode reference voltage Vcm, and the inverting input of the negative feedback amplifier is coupled to the output of the high-pass filter circuit, for generating the feedback adjustment signal based on the changing trend; The gate of the regulating transistor is coupled to the output of the negative feedback amplifier to receive the regulating signal Vsc, the source of the regulating transistor is coupled to the power supply node provided by the LDO power supply circuit, and the drain of the regulating transistor is coupled to the current source I. c The input terminal is used to adjust the amplitude of the pre-compensated current pulse.

4. The compensation power supply circuit for the Chiplet inter-chip interconnect interface as described in claim 3, characterized in that, The high-pass filter circuit includes a capacitor and a resistor connected in series between the power supply node and the common-mode reference voltage Vcm.

5. The compensation power supply circuit for the Chiplet inter-chip interconnect interface as described in claim 2, characterized in that, The switching transistor is an NMOS transistor.

6. The compensation power supply circuit for the Chiplet inter-chip interconnect interface as described in claim 3, characterized in that, The regulating transistor is a PMOS transistor.

7. The compensation power supply circuit for the Chiplet inter-chip interconnect interface as described in claim 3, characterized in that, The second compensation circuit is configured to dynamically adjust the conduction state of the regulating transistor through the feedback adjustment signal, thereby adjusting the amplitude of the pre-compensation current pulse to adapt to the load current differences of different drivers.

8. A method for compensating power supply for a chiplet interconnect interface, characterized in that, The compensation power supply circuit for the Chiplet inter-chip interconnect interface as described in any one of claims 1 to 7 comprises: The LDO power supply circuit provides a stable static power supply voltage to the drivers of multiple channels. In each channel, in response to the transition of the corresponding channel transmitted data signal from the first logic level to the second logic level, a pre-compensation current pulse is generated through the first compensation circuit and directly injected into the power supply node of the channel driver to compensate for the transient charge demand during the transition. The second compensation circuit detects the low-frequency voltage change trend of the power supply node, generates a feedback adjustment signal, and dynamically adjusts the amplitude of the pre-compensation current pulse according to the adjustment signal to suppress voltage ripple and adapt to process, voltage, temperature changes and load differences of different drivers.

9. A Chiplet interconnect interface compensated power supply system, characterized in that, It includes the compensation power supply circuit as described in any one of claims 1-7, and the compensation power supply method as described in claim 8.

10. An electronic device, characterized in that, Includes the Chiplet interconnect interface compensated power supply system as described in claim 9.

Images