Package substrate and method of manufacturing the same

Abstract

The present disclosure relates to the technical field of semiconductor manufacturing, and particularly relates to a packaging substrate and a preparation method thereof. The packaging substrate comprises a substrate and two isolated rings; the substrate comprises a bonding surface and a bottom surface; the two isolated rings extend along the direction perpendicular to the substrate and penetrate the bonding surface and the bottom surface, and define a movable cavity in the middle of the bonding surface with a top surface lower than the bonding surface, and a movable cavity ring surrounding the two isolated rings; the bonding surface around the movable cavity ring comprises a bonding ring; between the top of any isolated ring and the bonding surface surrounding the isolated ring, an anti-overflow isolation groove ring is provided for isolation; the bonding surface around the anti-overflow isolation groove ring comprises a solder pad; adjacent anti-overflow isolation groove rings are connected through the movable cavity in the middle. At least one packaging substrate with excellent electrical isolation performance and good thermal matching can be provided, and the signal crosstalk caused by excessive parasitic capacitance can be avoided while realizing the vertical interconnection of multiple independent signals.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a packaging substrate and a method for preparing the same. Background Technology

[0002] In the manufacturing and packaging of Micro Electro-Mechanical Systems (MEMS) devices, wafer-level packaging technology is one of the key technologies for achieving device miniaturization, high performance, high reliability, and low-cost mass production. Vertical interconnection of electrical signals is the core link to achieve three-dimensional integration and high-density packaging, while through-silicon via (TSV) technology is the mainstream technical path for achieving vertical electrical lead-out.

[0003] However, traditional TSV technology faces many challenges in terms of multi-channel electrical signal isolation, process complexity, thermal mismatch control, and packaging hermeticity. It is prone to interface cracking or insulation layer failure, thereby reducing packaging yield and device reliability. Summary of the Invention

[0004] According to various embodiments of this disclosure, a packaging substrate and its preparation method are provided, which can at least provide a packaging substrate with excellent electrical isolation performance and good thermal matching, so as to realize the vertical interconnection and output of multiple independent signals while avoiding signal crosstalk caused by excessive parasitic capacitance.

[0005] According to some embodiments, a first aspect of this disclosure provides a packaging substrate including a substrate and two mutually isolated isolation rings; the substrate includes a bonding surface and a bottom surface facing away from each other; the two isolation rings extend along a direction perpendicular to the substrate and penetrate the bonding surface and the bottom surface, defining a central movable cavity on the bonding surface with its top surface lower than the bonding surface, and a movable cavity ring surrounding the two isolation rings; a bonding ring is included on the bonding surface surrounding the movable cavity ring; in the two isolation rings, the top of either isolation ring is isolated from the bonding surface it surrounds via an anti-overflow isolation groove ring; the bonding surface surrounded by the anti-overflow isolation groove ring includes a pad; adjacent anti-overflow isolation groove rings communicate via the central movable cavity.

[0006] In the above embodiments, the packaging substrate defines a movable cavity in the middle of the substrate bonding surface with its top surface lower than the bonding surface via an isolation ring extending perpendicular to the substrate and penetrating the substrate bonding surface and bottom surface, and a movable cavity ring surrounding the two isolation rings. The top of either isolation ring is isolated from the bonding surface it surrounds via an anti-overflow isolation groove ring, providing an isolation and containment space for the subsequently molten bonding metal, preventing subsequent bonding metal overflow and protrusion that could reduce the reliability of the electrical connection. The vertically penetrating isolation ring effectively reduces thermal stress mismatch between the substrate and the isolation ring, and also effectively avoids electrical insulation problems, improving electrical isolation performance while reducing parasitic capacitance. The bonding surface surrounding the anti-overflow isolation ring includes pads, and the bonding surface around the movable cavity ring includes a bonding ring. This allows for vertical interconnection and lead-out of multiple independent signals while avoiding signal crosstalk caused by excessive parasitic capacitance. Compared to horizontal lead-out schemes, it reduces the length of interconnect signal lines and has broad application prospects in the field of 3D integration. Adjacent anti-overflow isolation rings are connected via a central movable cavity, which can circumferentially surround the two isolation rings, facilitating vacuum packaging.

[0007] According to some embodiments, the movable cavity ring, the anti-overflow isolation groove ring, and the central movable cavity are prepared simultaneously in the same process steps, which reduces the number of photomasks and process steps used in preparing the movable cavity ring, the anti-overflow isolation groove ring, and the central movable cavity, thereby reducing the complexity and cost of the preparation process.

[0008] According to some embodiments, the bonding ring and the pad are fabricated simultaneously in the same process steps, reducing the number of photomasks and process steps required to fabricate the bonding ring and the pad, thereby reducing the complexity and cost of the fabrication process.

[0009] According to some embodiments, the bonding ring and the bonding surface are eutectic bonded, and the pads are eutectic bonded to the bonding surface, which is beneficial for achieving vacuum packaging. During the eutectic bonding process, the metal can flow back into the anti-overflow isolation groove ring groove, and be isolated by the isolation ring to avoid the generation of current leakage channels and metal contamination.

[0010] According to some embodiments, the packaging substrate further includes a getter layer located on the bottom surface of the central movable cavity and the bottom surface of the movable cavity ring. The getter layer is activated during the eutectic bonding process to achieve vacuum packaging.

[0011] According to some embodiments, the orthographic projection of the pad on the bonding surface surrounded by the isolation ring is located within the bonding surface surrounded by the isolation ring. The isolation ring is used to electrically isolate the pad surrounded by the isolation ring from the outside world, avoiding the problem of poor electrical insulation, improving the electrical isolation performance, and reducing parasitic capacitance.

[0012] According to some embodiments, the resistivity of the substrate is 0.001 Ω·cm to 1 Ω·cm, which facilitates the reduction of the resistivity of the vertical interconnect structure.

[0013] According to some embodiments, a second aspect of this application provides a method for preparing a packaging substrate, comprising:

[0014] Provide substrate;

[0015] Multiple annular trenches are formed on the front side of the substrate, spaced apart along a first direction parallel to the top surface of the substrate; the annular trenches are used to define an isolation ring;

[0016] The dielectric material layer is filled into multiple annular trenches at the target temperature. After cooling and solidification, the front and back sides of the substrate are thinned to expose the top and bottom surfaces of the dielectric material layer. The remaining front side of the substrate forms the bonding surface of the substrate, and the remaining back side of the substrate forms the bottom surface of the substrate. The remaining dielectric material layer forms multiple isolation rings.

[0017] After forming a conductive layer on the bonding surface, a first patterned photoresist layer covering the conductive layer is formed. The conductive layer includes pads and bonding rings.

[0018] Based on the first patterned photoresist layer, the substrate is etched to obtain a cavity ring and an isolation ring. The cavity ring includes an anti-overflow isolation groove ring, a central movable cavity, and a movable cavity ring surrounding multiple isolation rings. In two isolation rings separated by the central movable cavity along a first direction, the top of any isolation ring is isolated from its surrounding bonding surface by the anti-overflow isolation groove ring. The bonding pad is located on the bonding surface surrounded by the anti-overflow isolation groove ring. Adjacent anti-overflow isolation groove rings are connected through the central movable cavity, and the bonding ring is located on the bonding surface surrounding the movable cavity ring.

[0019] According to some embodiments, the first patterned photoresist layer includes a first pattern for defining an anti-overflow isolation groove ring, and a second pattern for defining a central movable cavity and a movable cavity ring; the first pattern exposes the top surface of the isolation ring;

[0020] The substrate is etched based on the first patterned photoresist layer, and a cavity ring and an isolation ring are obtained simultaneously, including:

[0021] Using the first patterned photoresist layer as a mask, the substrate is etched to a preset depth, thereby obtaining a cavity ring and an isolation ring at the preset depth.

[0022] According to some embodiments, a dielectric material layer is filled within a plurality of annular trenches at a target temperature, including:

[0023] The front side of the substrate is bonded to a borophosphate glass sheet to obtain a bonded sheet;

[0024] The bonded sheet is heat-treated in a tube furnace at a target temperature of 850℃-1000℃, so that the molten borophosphate glass sheet fills multiple annular grooves.

[0025] According to some embodiments, the method for preparing the packaging substrate further includes:

[0026] After forming the cavity ring and the isolation ring, a second patterned photoresist layer is formed covering the cavity ring, the isolation ring and the conductive layer. The second patterned photoresist layer includes an opening pattern for defining the getter layer.

[0027] Form a getter material layer that at least fills the opening pattern;

[0028] Remove the getter material layer outside the second patterned photoresist layer and the opening pattern, and the remaining getter material layer is used to form the getter layer.

[0029] According to some embodiments, the method for preparing the packaging substrate further includes:

[0030] Provides a MEMS device layer;

[0031] The MEMS device layer and the conductive layer are eutectic bonded under preset process conditions. During the eutectic bonding process, the getter layer is activated to provide vacuum-tight packaging conditions for the MEMS device layer.

[0032] The packaging substrate and its preparation method in the above embodiments have at least the following unexpected technical effects:

[0033] Using a target temperature of, for example, 850℃-1000℃, molten dielectric material layers are reflowed and filled into multiple annular trenches. After cooling and solidification, the front and back sides of the substrate are thinned to expose the top and bottom surfaces of the dielectric material layer. The remaining front side of the substrate forms the bonding surface of the substrate, and the remaining back side forms the bottom surface of the substrate. The remaining dielectric material layer forms multiple isolation rings. Compared with the deposition process, this method is easier to implement, can effectively reduce the linewidth of the isolation rings, avoid the problem of poor electrical insulation, and reduce parasitic capacitance. The smaller linewidth isolation rings can effectively reduce the thermal stress mismatch between the substrate and the isolation rings. In the same process steps, a cavity ring and an isolation ring are fabricated simultaneously. In one of the two isolation rings, the top of the isolation ring is isolated from the bonding surface it surrounds via an anti-overflow isolation groove ring. This provides an isolation and containment space for the subsequent molten bonding metal, preventing overflow and protrusion that could reduce the reliability of the electrical connection. It also avoids increasing the number of photomasks and process steps due to the isolation ring. The vertically penetrating isolation ring effectively reduces thermal stress mismatch between the substrate and the isolation ring, and also effectively avoids electrical insulation problems, improving electrical isolation performance while reducing parasitic capacitance. The bonding surface surrounded by the anti-overflow isolation groove ring includes pads, and the bonding surface around the movable cavity ring includes a bonding ring. This enables vertical interconnection of multiple independent signals while avoiding signal crosstalk caused by excessive parasitic capacitance. Compared to horizontal lead-out schemes, it reduces the length of interconnect signal lines and has broad application prospects in the field of 3D integration. Adjacent anti-overflow isolation rings are connected via a central movable cavity. The movable cavity ring can circumferentially surround the two isolation rings, facilitating vacuum sealing. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic flowchart of a method for preparing a packaging substrate provided in some embodiments;

[0036] Figure 2 This is a schematic diagram of the longitudinal cross-sectional structure of the substrate provided in step S10 of a packaging substrate fabrication method provided in some embodiments;

[0037] Figure 3 This is a schematic diagram of the longitudinal section of the structure obtained after forming the first hard mask layer in step S20 of a packaging substrate fabrication method provided in some embodiments;

[0038] Figure 4 This is a schematic diagram of the longitudinal section of the structure obtained after forming the first patterned photoresist layer in step S20 of a packaging substrate preparation method provided in some embodiments;

[0039] Figure 5 This is a schematic diagram of the longitudinal section of the structure obtained after forming the first patterned hard mask layer in step S20 of a packaging substrate fabrication method provided in some embodiments;

[0040] Figure 6 This is a schematic diagram of the longitudinal section of the structure obtained after forming an annular trench in step S20 of a packaging substrate fabrication method provided in some embodiments;

[0041] Figure 7 This is a schematic diagram of the longitudinal section of the structure obtained after forming a dielectric material layer in step S30 of a packaging substrate preparation method provided in some embodiments;

[0042] Figure 8 This is a schematic diagram of the longitudinal section of the structure obtained after treating the dielectric material layer with a target temperature in step S30 of a packaging substrate preparation method provided in some embodiments;

[0043] Figure 9 This is a schematic diagram of the longitudinal section of the structure obtained after forming an isolation ring in step S30 of a packaging substrate preparation method provided in some embodiments;

[0044] Figure 10 This is a schematic diagram of the longitudinal section of the structure obtained after forming the second patterned photoresist layer in step S40 of a packaging substrate preparation method provided in some embodiments;

[0045] Figure 11 This is a schematic diagram of the longitudinal section of the structure obtained after forming a conductive layer in step S40 of a packaging substrate preparation method provided in some embodiments;

[0046] Figure 12 This is a schematic diagram of the longitudinal section of the structure obtained after forming the cavity ring and the isolation ring in step S50 of a packaging substrate preparation method provided in some embodiments;

[0047] Figure 13 This is a top view of the structure obtained after forming a cavity ring and an isolation ring in step S50 of a packaging substrate preparation method provided in some embodiments;

[0048] Figure 14 This is a top view schematic diagram of the structure obtained after forming a getter layer in a packaging substrate preparation method provided in some embodiments.

[0049] Explanation of reference numerals in the attached figures:

[0050] 10. Substrate; 11. First hard mask layer; PR1. First patterned photoresist layer; Y1. First patterned hard mask layer; H1. Annular trench; 12. Dielectric material layer; 13. Isolation ring; PR2. Second patterned photoresist layer; 14. Bonding ring; 15. Pad; 161. Central movable cavity; 162. Movable cavity ring; 17. Anti-overflow isolation trench ring; 18. Silicon pillar; 19. Getter layer. Detailed Implementation

[0051] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0053] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0054] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0055] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0056] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for the anticipation of variations in the shown shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the invention.

[0057] Traditional technologies typically employ deposited dielectric materials such as polycrystalline silicon and silicon dioxide to fill the conductive channel (TSV) for electrical isolation. For example, filling polycrystalline silicon using low-pressure chemical vapor deposition (LPCVD) can create conductive channels, but it suffers from drawbacks such as high process temperatures, slow deposition rates, and limited aspect ratios. Furthermore, voids or cracks are easily formed during the filling process, affecting isolation reliability. In addition, when using silicon dioxide as the insulating layer, the significant difference in thermal expansion coefficients between silicon and silicon dioxide can introduce substantial interfacial stress during temperature cycling, leading to interfacial cracking or insulating layer failure, thereby reducing package yield and long-term reliability.

[0058] On the other hand, to meet the vacuum environment requirements of MEMS devices (such as gyroscopes, accelerometers, and RF switches), wafer-level hermetically sealed packaging has become essential. Traditional metal eutectic bonding is an effective means of achieving vacuum packaging, but during the bonding process, the molten eutectic metal is prone to lateral overflow, which may cause short circuits or contaminate movable structures, seriously affecting device yield and performance. Simultaneously, to achieve a long-term stable vacuum environment inside the package, it is necessary to integrate high-performance getters and ensure their effective activation during the packaging process, which places higher demands on the compatibility of the packaging structure and process.

[0059] Furthermore, traditional vertical interconnect solutions often rely on complex and costly TSV insulation processes. These processes are not only cumbersome, but also prone to crosstalk due to excessive parasitic capacitance when implementing multiple independent signal outputs, thus affecting the performance of high-frequency or high-precision MEMS devices. Therefore, there is an urgent need to develop a vertical interconnect solution that is simple to manufacture, has excellent electrical isolation performance, good thermal matching, and is suitable for wafer-level hermetically sealed packaging.

[0060] Based on this, this application aims to provide a packaging substrate and its preparation method, which can at least provide a packaging substrate with excellent electrical isolation performance and good thermal matching, so as to realize the vertical interconnection and output of multiple independent signals while avoiding signal crosstalk caused by excessive parasitic capacitance.

[0061] Please refer to Figure 1 In some embodiments, a method for preparing a packaging substrate is provided, comprising:

[0062] Step S10: Provide a substrate;

[0063] Step S20: A plurality of annular trenches are formed on the front side of the substrate, spaced apart along a first direction parallel to the top surface of the substrate; the annular trenches are used to define an isolation ring;

[0064] Step S30: Fill the dielectric material layer in multiple annular trenches at the target temperature. After cooling and solidification, thin the front and back sides of the substrate until the top and bottom surfaces of the dielectric material layer are exposed. The remaining front side of the substrate forms the bonding surface of the substrate, and the remaining back side of the substrate forms the bottom surface of the substrate. The remaining dielectric material layer forms multiple isolation rings.

[0065] Step S40: After forming a conductive layer on the bonding surface, a first patterned photoresist layer covering the conductive layer is formed. The conductive layer includes pads and bonding rings.

[0066] Step S50: Etch the substrate based on the first patterned photoresist layer to simultaneously obtain a cavity ring and an isolation ring. The cavity ring includes an anti-overflow isolation groove ring, a central movable cavity, and a movable cavity ring surrounding multiple isolation rings. In two isolation rings separated by the central movable cavity along a first direction, the top of any isolation ring is isolated from its surrounding bonding surface by the anti-overflow isolation groove ring. The bonding pad is located on the bonding surface surrounded by the anti-overflow isolation groove ring. Adjacent anti-overflow isolation groove rings are connected through the central movable cavity, and the bonding ring is located on the bonding surface surrounding the movable cavity ring.

[0067] Please refer to Figure 2 In some embodiments, in step S10, an N-type crystal with a crystal orientation of... <100> The substrate 10, after double-sided polishing, can be made of silicon. The resistivity of the substrate 10 can be 0.002 Ω·cm to 0.004 Ω·cm. For example, the resistivity of the substrate 10 can be 0.002 Ω·cm, 0.003 Ω·cm, or 0.004 Ω·cm, etc. The thickness of the substrate 10 can be 380 µm to 400 µm. For example, the thickness of the substrate 10 can be 380 µm, 390 µm, or 400 µm, etc. The substrate 10 can be organically cleaned using acetone or ethanol, then rinsed with deionized water and dried with a nitrogen gun to remove contaminants such as dirt, grease, and dust from the surface of the substrate 10.

[0068] Please continue to refer to this. Figure 2 In some embodiments, the resistivity of the substrate 10 is 0.001 Ω·cm to 1 Ω·cm. For example, the resistivity of the substrate 10 can be 0.001 Ω·cm, 0.005 Ω·cm, 0.009 Ω·cm, 0.01 Ω·cm, 0.05 Ω·cm, 0.1 Ω·cm, 0.5 Ω·cm, or 1 Ω·cm, which facilitates reducing the resistivity of vertical interconnect structures such as silicon pillars.

[0069] Please refer to Figure 3 In some embodiments, in step S20, the cleaned substrate 10 can be placed in a magnetron sputtering apparatus to sputter a first hard mask layer 11 with a thickness of 95nm-105nm. The thickness of the first hard mask layer 11 can be 95nm, 100nm, or 105nm, etc. The material of the first hard mask layer 11 can be Al.

[0070] Please refer to Figure 4In some embodiments, in step S20, photoresist is spin-coated onto the top surface of the first hard mask layer 11 and photolithography is performed to obtain a first patterned photoresist layer PR1. The first patterned photoresist layer PR1 includes an opening pattern for defining an annular trench H1. The linewidth of the pattern of the first patterned photoresist layer PR1 can be 19.5µm-20.5µm. For example, the linewidth of the pattern of the first patterned photoresist layer PR1 can be 19.5µm, 20µm, or 20.5µm, etc. The thickness of the first patterned photoresist layer PR1 is 1.95µm-2.05µm. For example, the thickness of the first patterned photoresist layer PR1 can be 1.95µm, 2.00µm, or 2.05µm, etc.

[0071] Please refer to Figure 5 In some embodiments, in step S20, the first patterned photoresist layer PR1 is used as a mask, and the first hard mask layer 11 is dry etched to obtain the first patterned hard mask layer Y1.

[0072] Please refer to Figure 6 In some embodiments, in step S20, using the first patterned photoresist layer PR1 and the first patterned hard mask layer Y1 as masks, the substrate 10 is dry etched to a depth of 250µm~300µm to obtain an annular trench H1. The annular trench H1 is used to define silicon pillars within the substrate 10. Figure 6 (Not shown).

[0073] Please refer to Figure 7 In some embodiments, after obtaining the annular trench H1, the first patterned photoresist layer PR1 can be removed using an oxygen plasma dry process, or the first patterned photoresist layer PR1 and the first patterned hard mask layer Y1 can be removed simultaneously using a wet etching process. The depth of the annular trench H1 can be 250µm, 260µm, 270µm, 280µm, 290µm, or 300µm, etc. In step S30, the substrate 10 and a dielectric material layer 12 with a thickness of 290µm-310µm are anoly bonded to obtain a bonded sheet. The thickness of the dielectric material layer 12 can be 290µm, 300µm, or 310µm, etc. The material of the dielectric material layer 12 can be a borosilicate glass sheet. The borosilicate glass sheet can be used for subsequent glass reflow processes.

[0074] Please refer to Figure 8In some embodiments, in step S30, the bonding wafer is reflowed in a high-temperature tube furnace. The target reflow temperature needs to be higher than the softening melting point of the borophosphate glass sheet to ensure that the softened glass melts and fills the etched annular trench H1 under atmospheric pressure. The target temperature range can be 850℃-1000℃, and the target temperature for the hot reflow treatment can be 850℃, 900℃, 950℃, or 1000℃, etc. After the annular trench H1 is filled with molten glass, it is gradually cooled to room temperature, and the backfilled glass re-solidifies to form a silicon-glass composite substrate.

[0075] Please refer to Figure 9 In some embodiments, in step S30, the silicon-glass composite substrate is thinned by double-sided grinding until a top-surfaced isolation ring 13 and silicon pillar 18 are obtained. The remaining dielectric material layer 12 is used to form the isolation ring 13, and the remaining substrate is used to form the silicon pillar 18. A chemical mechanical polishing process can be used to make the top surface of the isolation ring 13 flush with the top surface of the silicon pillar 18, and the bottom surface of the isolation ring 13 flush with the bottom surface of the silicon pillar 18.

[0076] Please refer to Figure 10 In some embodiments, in step S40, photoresist is spin-coated onto the bonding surface of the remaining substrate 10 and photolithography is performed to obtain a second patterned photoresist layer PR2. The thickness of the second patterned photoresist layer PR2 can be 3.95µm-4.05µm. For example, 3.95µm, 4µm, or 4.05µm. The second patterned photoresist layer PR2 includes opening patterns for defining bonding rings and pads.

[0077] Please refer to Figure 11 In some embodiments, in step S40, the... Figure 10 The obtained structure is sputtered with a conductive layer in a magnetron sputtering apparatus. The conductive layer may include Ti, Pt, Au, or a combination thereof, for example, a composite metal layer of Ti, Pt, and Au. For example, Ti, Pt, and Au layers can be sequentially sputtered onto the second patterned photoresist layer PR2 along the direction away from the substrate. The thickness of the Ti layer is 40 nm, the thickness of the Pt layer is 60 nm, and the thickness of the Au layer is 300 nm. The Ti layer can act as an adhesion layer, the Pt layer as a diffusion barrier layer, and the Au layer as a reaction layer. The Au layer can react with silicon in the substrate to be bonded to form an Au-Si eutectic bonding bonding metal layer. The second patterned photoresist layer PR2 and the conductive layer outside the opening pattern can be stripped using chemical reagents. Part of the stripped conductive layer is attached to the top surface of the silicon pillar 18 to form the pad 15, and another part is attached to the chip packaging frame, located around the pad 15, to form the bonding ring 14.

[0078] Please refer to Figure 12In some embodiments, in step S40, after forming a conductive layer on the bonding surface, a first patterned photoresist layer (not shown) covering the conductive layer is formed. The first patterned photoresist layer includes a first pattern for defining an anti-overflow isolation groove ring 17 and a second pattern for defining a central movable cavity 161 and a movable cavity ring 162. The first pattern exposes the top surface of the isolation ring 13.

[0079] Please continue to refer to this. Figure 12 In some embodiments, step S50 involves etching the substrate 10 based on the first patterned photoresist layer to simultaneously obtain a cavity ring and an isolation ring 13, including:

[0080] Step S51: Using the first patterned photoresist layer as a mask, etch the substrate 10 to a preset depth, and simultaneously obtain a cavity ring and an isolation ring 13 at the preset depth.

[0081] For example, the preset depth can be 8µm-10µm, and the depth of the cavity ring and isolation ring 13 can be 8µm, 9µm, or 10µm, etc. The cavity ring includes an anti-overflow isolation groove ring 17, a central movable cavity 161, and a movable cavity ring 162 surrounding multiple isolation rings 13; in two isolation rings 13 spaced apart by the central movable cavity 161 along a first direction, the top of any isolation ring 13 is isolated from its surrounding bonding surface by the anti-overflow isolation groove ring 17; the pad 15 is located on the bonding surface surrounded by the anti-overflow isolation groove ring 17; adjacent anti-overflow isolation groove rings 17 are connected through the central movable cavity 161, and the bonding ring 14 is located on the outer bonding surface of the movable cavity ring 162. A top view of the anti-overflow isolation groove ring 17, silicon pillar 18, and pad 15 on the top surface of the substrate is shown below. Figure 13 As shown.

[0082] Please refer to Figure 14 In some embodiments, after forming the cavity ring and the isolation ring 13, the method further includes:

[0083] Step S61: Form a second patterned photoresist layer covering the cavity ring, the isolation ring 13 and the conductive layer. The second patterned photoresist layer includes an opening pattern for defining the getter layer 19.

[0084] Step S62: Form a getter material layer that at least fills the opening pattern;

[0085] Step S63: Remove the getter material layer outside the second patterned photoresist layer and the opening pattern. The remaining getter material layer is used to form getter layer 19.

[0086] In some embodiments, after forming the getter layer 19, the method further includes:

[0087] Step S71: Provide the MEMS device layer;

[0088] Step S72: Eutectic bonding of the MEMS device layer and the conductive layer under preset process conditions, wherein, during eutectic bonding, the getter layer 19 is activated to provide vacuum-tight packaging conditions for the MEMS device layer.

[0089] In some embodiments, in step S72, the eutectic reaction conditions are 380℃-420℃, maintained for more than 30 minutes. During the bonding process, the getter layer 19 can be activated simultaneously to provide vacuum-tight encapsulation for the MEMS device. The eutectic reaction temperature can be 380℃, 400℃, or 420℃, etc.

[0090] Please refer to Figures 12-14 In some embodiments, a packaging substrate is provided, including a substrate 10 and two mutually isolated isolation rings 13; the substrate 10 includes a bonding surface and a bottom surface facing away from each other; the two isolation rings 13 extend along a direction perpendicular to the substrate 10 and penetrate the bonding surface and the bottom surface, defining a central movable cavity 161 on the bonding surface with its top surface lower than the bonding surface, and a movable cavity ring 162 surrounding the two isolation rings 13; the bonding surface surrounding the movable cavity ring 162 includes a bonding ring 14; the top of either isolation ring 13 is isolated from the bonding surface it surrounds via an anti-overflow isolation groove ring 17; the bonding surface surrounded by the anti-overflow isolation groove ring 17 includes a pad 15; adjacent anti-overflow isolation groove rings 17 are connected via the central movable cavity 161.

[0091] Please continue to refer to this. Figures 12-14 In some embodiments, an isolation ring 13 extending along the direction perpendicular to the substrate 10 and penetrating the bonding surface and bottom surface of the substrate 10 defines a movable cavity 161 in the middle of the bonding surface of the substrate 10 with its top surface lower than the bonding surface, and a movable cavity ring 162 surrounding the two isolation rings 13. In this embodiment, the top of either isolation ring 13 is isolated from the bonding surface it surrounds via an anti-overflow isolation groove ring 17, so that the top of the isolation ring 13 is isolated from the adjacent bonding surface via the anti-overflow isolation groove ring 17, providing an isolation and containment space for the subsequent molten bonding metal, and preventing the subsequent bonding metal from overflowing and protruding, thus reducing the reliability of the electrical connection. The isolation ring 13 that vertically penetrates the substrate 10 can effectively reduce the thermal stress mismatch between the substrate 10 and the isolation ring 13, and can also effectively avoid the problem of poor electrical insulation, improving the electrical isolation performance while reducing parasitic capacitance. The bonding surface surrounded by the anti-overflow isolation ring 17 includes pads 15, and the bonding surface surrounding the movable cavity ring 162 includes a bonding ring 14. This allows for the vertical interconnection and extraction of multiple independent signals while avoiding signal crosstalk caused by excessive parasitic capacitance. Compared to the horizontal extraction scheme, it reduces the length of the interconnection signal lines and has broad application prospects in the field of 3D integration. Adjacent anti-overflow isolation rings 17 are connected via the central movable cavity 161. The movable cavity ring 162 can circumferentially surround the two isolation rings 13, facilitating vacuum packaging.

[0092] Please continue to refer to this. Figures 12-13 In some embodiments, the movable cavity ring 162, the anti-overflow isolation groove ring 17, and the central movable cavity 161 are prepared simultaneously in the same process steps, which reduces the number of photomasks and process steps used in preparing the movable cavity ring 162, the anti-overflow isolation groove ring 17, and the central movable cavity 161, thereby reducing the complexity and cost of the preparation process.

[0093] Please continue to refer to this. Figures 12-13 In some embodiments, the bonding ring 14 and the pad 15 are prepared simultaneously in the same process steps, which reduces the number of photomasks and process steps required to prepare the bonding ring 14 and the pad 15, thereby reducing the complexity and cost of the preparation process.

[0094] Please continue to refer to this. Figures 12-13 In some embodiments, the bonding ring 14 is eutectic bonded to the bonding surface, and the pad 15 is eutectic bonded to the bonding surface, which is beneficial for achieving vacuum packaging. During the eutectic bonding process, the metal can flow back into the groove of the anti-overflow isolation groove ring 17 and be isolated by the isolation ring 13 to avoid the generation of current leakage channels and metal contamination.

[0095] Please continue to refer to this. Figures 12-13 The orthographic projection of the pad 15 onto the bonding surface surrounded by the isolation ring 13 is located within the bonding surface surrounded by the isolation ring 13. The isolation ring 13 is used to electrically isolate the pad 15 it surrounds from the outside world, avoiding the problem of poor electrical insulation, improving the electrical isolation performance, and reducing parasitic capacitance.

[0096] Please continue to refer to this. Figures 12-13 Substrate 10 is N-type and its crystal orientation is <100> This facilitates the subsequent eutectic bonding of the packaging substrate with MEMS devices, enabling wafer-level hermetic packaging.

[0097] Please continue to refer to this. Figures 12-14 In some embodiments, the encapsulation substrate further includes a getter layer 19, which is located on the bottom surface of the central movable cavity 161 and the bottom surface of the movable cavity ring 162. The getter layer 19 is activated during the eutectic bonding process to achieve vacuum encapsulation.

[0098] In some embodiments, the getter in the getter layer 19 includes at least one of Ti-Zr-V alloy getter, Zr-V-Fe alloy getter, and Au-Ti composite metal getter.

[0099] Please refer to Figures 12-14 The packaging substrate and its preparation method in the above embodiments have at least the following unexpected technical effects:

[0100] Using a target temperature of, for example, 850℃-1000℃, molten dielectric material layer 12 is reflowed and filled into multiple annular trenches H1. After cooling and solidification, the front and back sides of the substrate 10 are thinned to expose the top and bottom surfaces of the dielectric material layer 12. The remaining front side of the substrate 10 forms the bonding surface of the substrate 10, and the remaining back side of the substrate 10 forms the bottom surface of the substrate 10. The remaining dielectric material layer 12 forms multiple isolation rings 13. Compared with the deposition process, this method is less difficult to implement and can effectively reduce the linewidth of the isolation rings 13, thus avoiding the problem of poor electrical insulation and reducing parasitic capacitance. The smaller linewidth isolation rings 13 can effectively reduce the thermal stress mismatch between the substrate 10 and the isolation rings 13. In the same process steps, a cavity ring and an isolation ring 13 are fabricated simultaneously. The top of either isolation ring 13 is isolated from its surrounding bonding surface by an anti-overflow isolation groove ring 17. This isolation provides an isolation and containment space for the subsequent molten bonding metal, preventing subsequent bonding metal overflow and protrusion that could reduce the reliability of the electrical connection. It also avoids increasing the number of photomasks and process steps due to the isolation ring 13. The isolation ring 13, which vertically penetrates the substrate 10, effectively reduces thermal stress mismatch between the substrate 10 and the isolation ring 13, and also effectively avoids problems with poor electrical insulation, improving electrical isolation performance while reducing parasitic capacitance. The bonding surface surrounded by the anti-overflow isolation ring 17 includes pads 15, and the bonding surface surrounding the movable cavity ring 162 includes a bonding ring 14. This allows for the vertical interconnection and extraction of multiple independent signals while avoiding signal crosstalk caused by excessive parasitic capacitance. Compared to the horizontal extraction scheme, it reduces the length of the interconnection signal lines and has broad application prospects in the field of 3D integration. Adjacent anti-overflow isolation rings 17 are connected via the central movable cavity 161. The movable cavity ring 162 can circumferentially surround the two isolation rings 13, facilitating vacuum packaging.

[0101] Although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the exact order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed, and they can be executed in other sequences. Moreover, although Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution of these sub-steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0102] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0103] The embodiments described above are merely illustrative of several implementation methods of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these modifications and improvements all fall within the scope of protection of this disclosure.

Claims

1. A packaging substrate, characterized in that, It includes a getter layer, a substrate, and two mutually isolating annular isolation rings; The substrate includes a bonding surface and a bottom surface that are opposite to each other; The two annular isolation rings extend along the direction perpendicular to the substrate and penetrate the bonding surface and the bottom surface, with the top surfaces of the two annular isolation rings flush with the bonding surface; the two annular isolation rings are prepared by processing borophosphate glass sheets using a glass reflow process; A movable cavity is defined on the bonding surface with its top surface lower than the bonding surface, and a movable cavity ring surrounds the two annular isolation rings; the bonding surface around the movable cavity ring includes a bonding ring. In the two annular isolation rings, the top of either isolation ring is isolated from the bonding surface it surrounds via an anti-overflow isolation groove ring; the bonding surface surrounded by the anti-overflow isolation groove ring includes a pad; adjacent anti-overflow isolation groove rings are connected via the central movable cavity; the movable cavity ring, the anti-overflow isolation groove ring, and the central movable cavity are simultaneously prepared by etching to a predetermined depth in the same process step; The getter layer is located on the bottom surface of the central movable cavity and the bottom surface of the movable cavity ring. The getter layer is activated during the eutectic bonding process to achieve vacuum encapsulation.

2. The packaging substrate according to claim 1, characterized in that, The bonding ring and the pad are prepared simultaneously in the same process steps.

3. The packaging substrate according to claim 1, characterized in that, The bonding ring is eutectic bonded to the bonding surface, and the pad is eutectic bonded to the bonding surface.

4. The packaging substrate according to claim 1, characterized in that, The orthographic projection of the pad onto the bonding surface surrounded by the isolation ring is located within the bonding surface surrounded by the isolation ring.

5. The packaging substrate according to any one of claims 1-4, characterized in that, The resistivity of the substrate is 0.001Ω·cm-1Ω·cm.

6. A method for preparing a packaging substrate, characterized in that, include: Provide substrate; A plurality of annular trenches are formed on the front side of the substrate, spaced apart along a first direction parallel to the top surface of the substrate; The annular groove is used to define the annular isolation ring; A borophosphate glass sheet is processed using a target temperature and glass reflow process. A dielectric material layer is filled into the plurality of annular trenches. After cooling and solidification, both the front and back sides of the substrate are thinned to expose the top and bottom surfaces of the dielectric material layer. The remaining front side of the substrate forms the bonding surface of the substrate, and the remaining back side of the substrate forms the bottom surface of the substrate. The remaining dielectric material layer forms a plurality of annular isolation rings. The top surfaces of the plurality of annular isolation rings are flush with the bonding surface. After forming a conductive layer on the bonding surface, a first patterned photoresist layer is formed covering the conductive layer, the conductive layer including pads and bonding rings; Based on the first patterned photoresist layer, the substrate is etched to a predetermined depth to simultaneously obtain a cavity ring and an isolation ring. The cavity ring includes an anti-overflow isolation groove ring, a central movable cavity, and a movable cavity ring surrounding the plurality of annular isolation rings. In two isolation rings spaced apart along the first direction via the central movable cavity, the top of any isolation ring is isolated from its surrounding bonding surface via the anti-overflow isolation groove ring. The bonding pad is located on the bonding surface surrounded by the anti-overflow isolation groove ring. Adjacent anti-overflow isolation groove rings are connected via the central movable cavity, and the bonding ring is located on the outer bonding surface of the movable cavity ring. A getter layer is formed, which is located on the bottom surface of the central movable cavity and the bottom surface of the movable cavity ring. The getter layer is activated during the eutectic bonding process to achieve vacuum encapsulation.

7. The method for preparing a packaging substrate according to claim 6, characterized in that, The first patterned photoresist layer includes a first pattern for defining the anti-overflow isolation groove ring, and a second pattern for defining the central movable cavity and the movable cavity ring; The first pattern exposes the top surface of the isolation ring; The substrate is etched based on the first patterned photoresist layer to simultaneously obtain a cavity ring and an isolation ring, including: Using the first patterned photoresist layer as a mask, the substrate is etched to a predetermined depth, thereby obtaining a cavity ring and an isolation ring at the predetermined depth.

8. The method for preparing a packaging substrate according to claim 6, characterized in that, The process of filling the plurality of annular trenches with a dielectric material layer at a target temperature includes: The front side of the substrate is bonded to a borophosphate glass sheet to obtain a bonded sheet; The bonded sheet is heat-treated in a tube furnace at the target temperature, such that the molten borophosphate glass sheet fills multiple annular grooves, and the target temperature is 850℃-1000℃.

9. The method for preparing a packaging substrate according to claim 6, characterized in that, Also includes: After forming the cavity ring and the isolation ring, a second patterned photoresist layer is formed covering the cavity ring, the isolation ring and the conductive layer. The second patterned photoresist layer includes an opening pattern for defining the getter layer. Form a getter material layer that at least fills the opening pattern; The second patterned photoresist layer and the getter material layer, excluding the opening pattern, are removed, and the remaining getter material layer is used to form the getter layer.

10. The method for preparing a packaging substrate according to claim 9, characterized in that, Also includes: Provides a MEMS device layer; The MEMS device layer and the conductive layer are eutectic bonded under preset process conditions, wherein the getter layer is activated during the eutectic bonding process to provide vacuum-tight packaging conditions for the MEMS device layer.

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