A design method of wideband asymmetric quasi-balanced DPA with extended backoff range

Abstract

The application relates to a design method of a wideband asymmetric quasi-balanced DPA with an enlarged backoff range, which comprises the following steps: establishing the architecture of the wideband asymmetric quasi-balanced DPA, establishing the equivalent circuit model of the wideband asymmetric quasi-balanced DPA, and obtaining the mathematical relationship between voltage and current; adopting a linear current model as an excitation signal to determine the load impedance, output power and drain efficiency under different normalized input levels; setting the load impedance of the main power amplifier and the auxiliary power amplifier to be equal when the output power is saturated, and obtaining the adjustable proportional coefficient of the loaded load; setting the voltage of the main power amplifier to be equal after the voltage saturation, and obtaining the relationship between the current ratio of the auxiliary power amplifier and the normalized input starting level; obtaining the relationship between the output power backoff ratio and the normalized input starting level; and optimizing the isolation port load of the output coupler and the direct current bias combination of the main power amplifier and the auxiliary power amplifier in the target working frequency band to meet the efficiency requirement under the set output power backoff ratio.

Description

Technical Field

[0001] This invention relates to the field of power amplifier technology, and in particular to a design method for a broadband asymmetric quasi-balanced DPA with extended back-off range. Background Technology

[0002] New-generation wireless communication systems commonly employ wideband and high-spectral-efficiency digital modulation techniques to improve data transmission rates. However, these complex digital modulation techniques significantly increase the peak-to-average power ratio (PAPR) of the transmitted signal. This necessitates that power amplifiers (PAs) maintain sufficiently high efficiency while transmitting PAPR signals within their output power back-off range. Furthermore, to enable power amplifiers to support multi-mode, multi-band wireless communication systems, they must operate over a wide bandwidth. Therefore, achieving high-efficiency power amplifiers with wide bandwidth and a large back-off range has become a key focus of current research and development.

[0003] Currently, Doherty power amplifiers (DPAs) and emerging load-modulated balanced power amplifiers (LMBAs) have made a series of positive advances in improving efficiency, extending back-off range, and increasing operating bandwidth. For example, a dual-band broadband DPA is proposed in Reference 1 (L.-H. Zhou, XY Zhou, and WS Chan, “Compact dual-passband Doherty power amplifier based on stub-loaded stepped-impedance transformer,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 71, no. 1, pp. 99-109, Jan. 2024.), but its back-off range can only reach 6 dB. To further increase the backoff range and support more operating frequency bands, reference 2 (Z. Zhang, V. Fusco, Z. Cheng, W. Wang, C. Gu, and N. Buchanan, “Design of a quadband Doherty power amplifier with large power back-off range,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 68, no. 9, pp. 3598-3610, Sep. 2021.) proposes a high-efficiency DPA that supports four frequency bands and has a backoff range of 9 dB. Although this PA has a backoff range of up to 9 dB, its operating bandwidth still cannot continuously cover a bandwidth exceeding one octave. To address this, reference 3 (S. Liu et al., “Analysis and design of ultrawideband generalized asymmetrical Doherty power amplifier using hybrid voltage–current configuration,” IEEE Trans. Microw. Theory Techn., EarlyAccess, 2025.) proposes that an asymmetric ultrawideband high-efficiency DPA operating in the 0.7–2.1 GHz range can be achieved by using a hybrid voltage–current configuration. Although its relative bandwidth is increased to 100%, the backoff range is still only 7 dB.Furthermore, with the emergence of load-modulated balanced amplifiers (LMBA), wideband pseudo-Dougherty LMBA (PD-LMBA), sequential LMBA (SLMBA), three-stage high-efficiency LMBA (3-stage LMBA), asymmetric coupled LMBA, and ultra-wideband PD-LMBA based on signal flow analysis, their backoff range has generally reached 10 dB, and their operating bandwidth can reach up to 10 times the frequency. However, these structures have complex circuits and large circuit sizes, requiring at least three power amplifier chips, resulting in higher costs. It is necessary to further simplify the structure.

[0004] Furthermore, reference 4 (H. Lyu and K. Chen, “Analysis and design of reconfigurable multiband mismatch-resilient quasi-balanced Doherty poweramplifier for massive MIMO systems,” IEEE Trans. Microw. Theory Techn., vol.70, no. 10, pp. 4410-4421, Oct. 2022.) proposes a single-frequency and multi-band reconfigurable quasi-balanced DPA (QBDPA) based on a 3dB quadrature coupler. This DPA achieves a DPA efficiency curve and reaches a bandwidth comparable to a typical PD-LMBA, but its backoff range is only 6 dB, and its bandwidth does not exceed one octave. Therefore, there is an urgent need to propose a power amplifier with both wide bandwidth and large backoff range to solve the aforementioned problems. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a design method for a broadband asymmetric quasi-balanced DPA with an expanded backoff range.

[0006] To achieve the above-mentioned objectives, this invention provides a design method for a broadband asymmetric quasi-balanced DPA with expanded backoff range, comprising the following steps:

[0007] S1. Establish the architecture of a broadband asymmetric quasi-balanced DPA, wherein the broadband asymmetric quasi-balanced DPA includes: an input coupler, a main power amplifier, an auxiliary power amplifier, a first output hybrid impedance transformation network, a second output hybrid impedance transformation network, and an output coupler;

[0008] S2. Establish an equivalent circuit model of a broadband asymmetric quasi-balanced DPA using an ideal current source and an output coupler, and obtain the mathematical relationship between voltage and current in the equivalent circuit model.

[0009] S3. Using a linear current model as the excitation signal for the main power amplifier and auxiliary power amplifier, the excitation signal is determined at different normalized input levels. The load impedance, output power, and drain efficiency under these conditions;

[0010] S4. Set the load impedance of the main power amplifier and auxiliary power amplifier to remain equal when the output power is at saturation, and obtain the adjustable proportional coefficient of the load loaded at the output port of the output coupler. ;

[0011] Set the main power amplifier to normalized input level With the normalized input level of the auxiliary power amplifier enabled When the voltages are equal When the voltages are equal, the current ratio of the auxiliary and main power amplifiers is obtained. With normalized input level The relationship between them;

[0012] The saturated output power and input level of the broadband asymmetric quasi-balanced DPA are set to the normalized input level. The ratio of the output power at different times is the output power back-off ratio. The output power back-off ratio and the normalized input level are then obtained. The relationship between them;

[0013] S5. Use ADS tools for simulation verification to optimize the isolation port load of the output coupler and the DC bias combination of the main power amplifier and auxiliary power amplifier in the target operating frequency band to meet the efficiency requirements under the set output power back-off ratio.

[0014] According to one aspect of the present invention, in step S1, in the step of establishing a broadband asymmetric quasi-balanced DPA architecture, the input coupler is an input orthogonal 3dB coupler with a characteristic impedance of 50Ω, and the isolation port of the input coupler is connected to a 50Ω load.

[0015] The output coupler has a characteristic impedance. The output quadrature coupler, and the back-end matching circuit of the output coupler has The output coupler has an impedance transformation capability from a load to a 50Ω load. The isolation port of the output coupler is equipped with a variable load, which includes: a short-circuit load, an open-circuit load, and a reactive element load.

[0016] The main power amplifier and the auxiliary power amplifier have the same power amplifier chip and the same input matching circuit;

[0017] The first output hybrid impedance transformation network is used to connect the main power amplifier and the output coupler, complete the fundamental impedance transformation and realize the second harmonic impedance control, so that the main power amplifier works in continuous mode.

[0018] The second output hybrid impedance transformation network is used to connect the auxiliary power amplifier and the output coupler, complete the fundamental impedance transformation and realize the second harmonic impedance control, so that the auxiliary power amplifier works in continuous mode.

[0019] According to one aspect of the present invention, in step S2, in the step of establishing an equivalent circuit model of a broadband asymmetric quasi-balanced DPA using an ideal current source and an output coupler, when the variable load is a short-circuit load, the equivalent circuit model is a series AQBDPA model, and when the variable load is an open-circuit load, the equivalent circuit model is a parallel AQBDPA model.

[0020] In the series AQBDPA model, as the input level increases, the series AQBDPA model moves from the low power region to the high power region. In the low power region, the main power amplifier is turned on and the auxiliary power amplifier is turned off. In the high power region, both the main power amplifier and the auxiliary power amplifier are turned on.

[0021] In the parallel AQBDPA model, as the input level increases, the parallel AQBDPA model moves from the low-power region to the high-power region. In the low-power region, the main power amplifier is turned on and the auxiliary power amplifier is turned off. In the high-power region, both the main power amplifier and the auxiliary power amplifier are turned on.

[0022] According to one aspect of the present invention, in step S2, in the step of establishing an equivalent circuit model of a broadband asymmetric quasi-balanced DPA using an ideal current source and an output coupler, and obtaining the mathematical relationship between voltage and current in the equivalent circuit model, for the series AQBDPA model, the mathematical relationship between voltage and current is expressed as follows:

[0023]

[0024] in, This represents the voltage level of the auxiliary power amplifier in the series AQBDPA model. This represents the voltage level of the main power amplifier in the series AQBDPA model. This represents the voltage level at the output port of the output coupler in the series AQBDPA model. This represents the current level of the auxiliary power amplifier in the series AQBDPA model. This represents the current level of the main power amplifier in the series AQBDPA model. This represents the isolation port current level of the output coupler in the series AQBDPA model. This represents the current level at the output port of the output coupler in the series AQBDPA model. This represents the characteristic impedance of the output coupler. This represents the transmission coefficient of the output coupler. This represents the coupling coefficient of the output coupler. Represents the imaginary unit;

[0025] For the parallel AQBDPA model, the mathematical relationship between voltage and current is expressed as follows:

[0026]

[0027] in, This represents the voltage level of the main power amplifier in the parallel AQBDPA model. This represents the voltage level of the auxiliary power amplifier in the parallel AQBDPA model. This represents the voltage level at the isolation port of the output coupler in the parallel AQBDPA model. This represents the voltage level at the output port of the output coupler in the parallel AQBDPA model. This represents the current level of the main power amplifier in the parallel AQBDPA model. This represents the current level of the auxiliary power amplifier in the parallel AQBDPA model. This represents the current level at the output port of the output coupler in the parallel AQBDPA model.

[0028] According to one aspect of the present invention, in step S3, a linear current model is used as the excitation signal for the main power amplifier and the auxiliary power amplifier to determine the input signals at different normalized input levels. The steps for determining load impedance, output power, and drain efficiency include:

[0029] S31. Using a linear current model as the excitation signal for the main power amplifier and auxiliary power amplifier in the series AQBDPA model and the parallel AQBDPA model, the main power amplifier current is established. and auxiliary power amplifier current Respectively with normalized input level The relationship is defined, and the current ratio between the auxiliary power amplifier and the main power amplifier is defined when the maximum input level is reached. ;

[0030] S32. For the low-power region of the equivalent circuit model, obtain the normalized input level in the low-power region. The corresponding load impedance, output power, and drain efficiency;

[0031] S33. For the high-power region of the equivalent circuit model, obtain the normalized input level in the high-power region. The corresponding load impedance, output power, and drain efficiency.

[0032] According to one aspect of the present invention, in step S31, the main power amplifier current is established. and auxiliary power amplifier current Respectively with normalized input level The relationship is defined, and the current ratio between the auxiliary power amplifier and the main power amplifier is defined when the maximum input level is reached. In the steps, the main power amplifier current With normalized input level The relational expression is as follows:

[0033]

[0034] in, This represents the current of the main power amplifier at its maximum input level.

[0035] Auxiliary power amplifier current With normalized input level The relational expression is as follows:

[0036]

[0037] in, This represents the current of the auxiliary power amplifier at its maximum input level. This indicates the normalized input level for enabling the auxiliary power amplifier;

[0038] Defined auxiliary and main power amplifier current ratio Represented as:

[0039] .

[0040] According to one aspect of the present invention, in step S32, for the low-power region of the equivalent circuit model, the normalized input level under the low-power region is obtained. In the steps related to load impedance, output power, and drain efficiency, if the equivalent circuit model is a series AQBDPA model, then the load impedance of the main power amplifier in the low-power region is expressed as:

[0041]

[0042] in, This represents the load impedance of the main power amplifier in the low-power region of the series AQBDPA model;

[0043] The output power of the series AQBDPA model is expressed as:

[0044]

[0045] in, This represents the output power of the series AQBDPA model in the low-power region;

[0046] The drain efficiency of the series AQBDPA model is expressed as:

[0047]

[0048] in, This represents the drain efficiency of the series AQBDPA model in the low-power region. This represents the drain supply voltage of the main power amplifier;

[0049] If the equivalent circuit model is a parallel AQBDPA model, then the load impedance of the main power amplifier in the low-power region is expressed as:

[0050]

[0051] in, This represents the load impedance of the main power amplifier in the low-power region of the parallel AQBDPA model;

[0052] The output power of the parallel AQBDPA model is expressed as:

[0053]

[0054] in, This represents the output power of the parallel AQBDPA model in the low-power region;

[0055] The drain efficiency of the parallel AQBDPA model is expressed as:

[0056]

[0057] in, This represents the drain efficiency of the parallel AQBDPA model in the low-power region. This indicates the drain supply voltage of the main power amplifier;

[0058] In step S33, for the high-power region of the equivalent circuit model, the normalized input level under the high-power region is obtained. In the steps related to load impedance, output power, and drain efficiency, if the equivalent circuit model is a series AQBDPA model, then the load impedance of the main power amplifier in the high-power region is expressed as:

[0059]

[0060] in, This represents the load impedance of the main power amplifier in the high-power region of the series AQBDPA model;

[0061] The load impedance of the auxiliary power amplifier in the high-power region is expressed as:

[0062]

[0063] in, This represents the load impedance of the auxiliary power amplifier in the high-power region of the series AQBDPA model;

[0064] The output power of the series AQBDPA model is expressed as:

[0065]

[0066] in, This represents the output power of the series AQBDPA model in the high-power region;

[0067] The drain efficiency of the series AQBDPA model is expressed as:

[0068]

[0069] in, This represents the drain efficiency of the series AQBDPA model in the high-power region. This represents the drain supply voltage of the main power amplifier. This indicates the drain supply voltage of the auxiliary power amplifier;

[0070] If the equivalent circuit model is a parallel AQBDPA model, then the load impedance of the main power amplifier in the high-power region is expressed as:

[0071]

[0072] in, This represents the load impedance of the main power amplifier in the high-power region of the parallel AQBDPA model;

[0073] The load impedance of the auxiliary power amplifier in the high-power region is expressed as:

[0074]

[0075] in, This represents the load impedance of the auxiliary power amplifier in the high-power region of the parallel AQBDPA model;

[0076] The output power of the parallel AQBDPA model is expressed as:

[0077]

[0078] in, This represents the output power of the parallel AQBDPA model in the high-power region;

[0079] The drain efficiency of the parallel AQBDPA model is expressed as:

[0080]

[0081] in, This represents the drain efficiency of the parallel AQBDPA model in the high-power region. This represents the drain supply voltage of the main power amplifier. This indicates the drain supply voltage of the auxiliary power amplifier.

[0082] According to one aspect of the invention, in step S4, the adjustable proportional coefficient of the load loaded at the output port of the output coupler is obtained. In the steps, if the equivalent circuit model is a series AQBDPA model, then the adjustable scaling factor... Represented as:

[0083]

[0084] in, This indicates the adjustable scaling factor of the series AQBDPA model, and the subscript SE is the identifier of the series AQBDPA model;

[0085] If the equivalent circuit model is a parallel AQBDPA model, then the adjustable scaling factor... Represented as:

[0086]

[0087] in, This indicates the adjustable scaling factor of the parallel AQBDPA model; the subscript PL is the identifier of the parallel AQBDPA model.

[0088] In step S4, the auxiliary and main power amplifier current ratio is obtained. With normalized input level In the steps relating the auxiliary and main power amplifier current ratios With normalized input level The relationship between them is represented as follows:

[0089] ;

[0090] In step S4, the output power back-off ratio and the normalized input level are obtained. In the steps relating the output power back-off ratio to the normalized input level The relationship between them is represented as follows:

[0091]

[0092] in, Indicates the output power back-off ratio. This represents the output power of a broadband asymmetric quasi-balanced DPA at saturation. This indicates that the broadband asymmetric quasi-balanced DPA operates at a normalized input level. With the normalized input level of the auxiliary power amplifier enabled Output power when they are equal.

[0093] According to one aspect of the present invention, step S5, which involves using ADS tools to perform simulation verification and optimize the isolation port load of the output coupler and the DC bias combination of the main power amplifier and the auxiliary power amplifier in the target operating frequency band to meet the efficiency requirements under the set output power back-off ratio, includes:

[0094] S51. Set the characteristic impedance of the output coupler Transmission coefficient And establish an equivalent circuit model of broadband asymmetric quasi-balanced DPA in the ADS tool;

[0095] S52. Set the range of the output power back-off ratio, and draw the output power back-off ratio at different normalized input levels based on the constructed equivalent circuit model. The curves showing the changes in load impedance, drain efficiency, voltage, and current are obtained, and the output power back-off ratio is determined based on the drain efficiency and preset design requirements. Target;

[0096] S53. Obtain the adjustable proportional coefficient The value of is determined, and the characteristic impedance of the output coupler is determined. Orthogonal 3dB coupler;

[0097] S54. Set the target operating frequency band and saturation output power, based on The goal is to select multiple frequency points within the target operating frequency band, use the ADS tool to perform load traction simulation on the current surface of the power amplifier chip, and output the load traction simulation results.

[0098] S55. Construct the first output hybrid impedance transformation network, the second output hybrid impedance transformation network, and the output coupler into an orthogonal 3 dB coupler for impedance transformation, and set its characteristic impedance ratio to be... The characteristic impedance was determined based on the load traction simulation results. and characteristic impedance The value of , where, This represents the characteristic impedance of the power amplifier chip viewed from the current surface of the constructed impedance-transformation orthogonal 3 dB coupler; and, based on the characteristic impedance... and characteristic impedance The value determines the structure of the first output hybrid impedance transformation network, the second output hybrid impedance transformation network, the input matching circuit, and the back-end matching circuit;

[0099] S56. Select multiple operating frequencies based on the target operating frequency band, and determine the load and optimal efficiency DC bias combination for each operating frequency using the ADS tool, ensuring that the set... The drain efficiency within the target backoff range meets the design requirements;

[0100] S57. Based on the determined load at each operating frequency, a load connection circuit is constructed to form a variable load arranged at the isolation port of the output coupler.

[0101] According to one aspect of the present invention, in step S55, the first output hybrid impedance transformation network includes: a device parasitic parameter model of the main power amplifier and a first external matching circuit; wherein, the first external matching circuit is a microstrip circuit;

[0102] The second output hybrid impedance transformation network includes: a device parasitic parameter model of the auxiliary power amplifier and a second external matching circuit; wherein, the second external matching circuit is a microstrip circuit;

[0103] The input matching circuit is a microstrip circuit;

[0104] The back-end matching circuit is a microstrip circuit;

[0105] In step S57, the constructed load connection circuit is a multi-channel RF switch circuit, and each switching channel on the multi-channel RF switch circuit has a load, thereby realizing the switching function of variable load.

[0106] According to one aspect of the present invention, the main power amplifier and auxiliary power amplifier in a broadband asymmetric quasi-balanced DPA (AQBDPA) are configured with different drain supply voltages. The main power amplifier can enter a high-efficiency state with voltage saturation at a lower output power, further improving the back-off range of the AQBDPA. Second harmonic control is performed in the output matching circuits of the two sub-amplifiers, and the two sub-amplifiers operate in continuous mode, which is beneficial to improving the operating bandwidth and the efficiency of the back-off range. By reconfiguring different reactive components at the isolation port of the output quadrature coupler and providing adaptive bias for the two sub-amplifiers, the bandwidth of the AQBDPA can exceed one octave.

[0107] According to one aspect of the present invention, this approach differs from the traditional QBDPA. The main power amplifier and the auxiliary power amplifier are configured with different drain supply voltages. When the main power amplifier is in saturation, its output power is less than that of the auxiliary power amplifier, but the sum of their powers remains the same as that of the traditional QBDPA. Therefore, the main power amplifier can enter a high-efficiency state with voltage saturation at a lower output power, further expanding the back-off range.

[0108] According to one aspect of the present invention, this approach achieves second harmonic control in output matching and incorporates the device parasitic parameter model of the power amplifier chip into the output matching circuit for collaborative design. The circuit structure is simple, and the main power amplifier and auxiliary power amplifier operate in continuous mode, which is beneficial for simultaneously improving efficiency and bandwidth.

[0109] According to one aspect of the present invention, when the broadband asymmetric quasi-balanced DPA configured in this scheme operates at different operating frequencies, different loads are reconfigured at the isolation port of the output coupler, and the optimal DC bias combination for the two power amplifiers is provided, with a bandwidth exceeding one octave.

[0110] According to one embodiment of the present invention, compared to a typical LMBA, this embodiment achieves a comparable level of backoff range and efficiency performance. It features a simple circuit structure, small size, requires only two power amplifier chips, and is low in cost. The proposed broadband asymmetric quasi-balanced DPA (AQBDPA) has a bandwidth exceeding one harmonic and a backoff range extended to 10 dB, meeting the application requirements of 5G communication.

[0111] According to one aspect of the present invention, the proposed AQBDPA can further expand the backoff range under asymmetric conditions, and the output coupler can adopt an orthogonal 3dB coupler. Furthermore, the adjustable proportional coefficients of the series-parallel AQBDPAs can simultaneously be set to 1. Therefore, by employing an orthogonal 3dB coupler, it is advantageous to select commercially available broadband orthogonal 3dB couplers exceeding one harmonic in practical designs, significantly reducing the size.

[0112] According to one aspect of the present invention, the adjustable proportional coefficients of the series-parallel AQBDPA can simultaneously take the value of 1, thereby achieving optimal efficiency at different operating frequencies by constructing the optimal DC bias (selecting between series and parallel forms) and reconfiguring different loads at the isolation port of the output coupler, which is beneficial for achieving bandwidth exceeding one harmonic. Attached Figure Description

[0113] Figure 1 A flowchart illustrating the design steps of the broadband asymmetric quasi-balanced DPA with expanded backoff range according to the present invention.

[0114] Figure 2 This is an architectural diagram of the broadband asymmetric quasi-balanced DPA of the present invention;

[0115] Figure 3 This is the equivalent circuit diagram of the series AQBDPA model in the equivalent circuit model of the present invention, wherein, Figure 3 (a) shows the equivalent circuit diagram of the series AQBDPA model in the low-power region. Figure 3 (b) shows the equivalent circuit diagram of the series AQBDPA model in the high-power region;

[0116] Figure 4 This is the equivalent circuit diagram of the parallel AQBDPA model in the equivalent circuit model of the present invention, wherein, Figure 4 (a) shows the equivalent circuit diagram of the parallel AQBDPA model in the low-power region. Figure 4(b) shows the equivalent circuit diagram of the parallel AQBDPA model in the high-power region;

[0117] Figure 5 These are characteristic diagrams of the series AQBDPA model and the parallel AQBDPA model with different output power back-off ratios (OBO) in this invention. Figure 5 (a) shows the curves representing the change in drain efficiency versus normalized input level. Figure 5 (b) shows the curves of load impedance versus normalized input level. Figure 5 (c) shows the curve of current versus normalized input level. Figure 5 (d) shows the curves of voltage versus normalized input level;

[0118] Figure 6 This is a graph showing the relationship between λ and m in the series AQBDPA model and the parallel AQBDPA model of the present invention;

[0119] Figure 7 This is an orthogonal 3 dB coupler for impedance transformation in an embodiment of the present invention;

[0120] Figure 8 The diagram shows the structure and performance of the output hybrid impedance transformation network in an embodiment of the present invention. Figure 8 (a) shows the circuit diagram of the output hybrid impedance transformation network. Figure 8 (b) shows the S-parameter plot of the simulation. Figure 8 (c) shows the impedance trajectories of the fundamental and second harmonic waves on the current surface;

[0121] Figure 9 This is a diagram illustrating the structure and performance of the input matching circuit in an embodiment of the present invention. Figure 9 (a) shows the circuit diagram of the input matching circuit. Figure 9 (b) shows the S-parameter plot of the simulation;

[0122] Figure 10 The diagram shows the simulated current and voltage variations with output power at 0.8 GHz, 1.4 GHz, and 1.7 GHz in an embodiment of the present invention. Figure 10 (a) shows the simulated relationship between drain current and output power. Figure 10 (b) shows the relationship between the simulated drain voltage and the output power;

[0123] Figure 11 The broadband asymmetric quasi-balanced DPA (AQBDPA) designed in the embodiments of the present invention exhibits typical DPA efficiency characteristics at multiple frequencies within the 0.8-1.8 GHz operating frequency band, where... Figure 11(a) shows the simulated drain efficiency and gain as a function of output power. Figure 11 (b) A physical diagram showing a broadband asymmetric quasi-equilibrium DPA (AQBDPA);

[0124] Figure 12 In an embodiment of the present invention, signals with different power levels are input using a single-carrier continuous wave. Figure 11 (b) shows the results of testing the actual object, where... Figure 12 (a) shows the relationship between the tested drain efficiency and gain as a function of output power. Figure 12 (b) shows the relationship between simulated and tested saturated output power, gain, and drain efficiency as a function of frequency. Detailed Implementation

[0125] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0126] Combination Figure 1 and Figure 2 As shown, according to one embodiment of the present invention, a design method for a broadband asymmetric quasi-balanced DPA with expanded backoff range includes the following steps:

[0127] S1. Establish the architecture of a broadband asymmetric quasi-balanced DPA, wherein the broadband asymmetric quasi-balanced DPA includes: an input coupler, a main power amplifier, an auxiliary power amplifier, a first output hybrid impedance transformation network, a second output hybrid impedance transformation network, and an output coupler;

[0128] S2. Establish an equivalent circuit model of a broadband asymmetric quasi-balanced DPA using an ideal current source and an output coupler, and obtain the mathematical relationship between voltage and current in the equivalent circuit model.

[0129] S3. Using a linear current model as the excitation signal for the main power amplifier and auxiliary power amplifier, the excitation signal is determined at different normalized input levels. The load impedance, output power, and drain efficiency under these conditions;

[0130] S4. Set the load impedance of the main power amplifier and auxiliary power amplifier to remain equal when the output power is at saturation, and obtain the adjustable proportional coefficient of the load loaded at the output port of the output coupler. ;

[0131] Set the main power amplifier to normalized input level With the normalized input level of the auxiliary power amplifier enabled When the voltages are equal When the voltages are equal, the current ratio of the auxiliary and main power amplifiers is obtained. With normalized input level The relationship between them;

[0132] The saturated output power and input level of the broadband asymmetric quasi-balanced DPA are set to the normalized input level. The ratio of the output power at different times is the output power back-off ratio. The output power back-off ratio and the normalized input level are then obtained. The relationship between them;

[0133] S5. Use ADS tools for simulation verification to optimize the isolation port load of the output coupler and the DC bias combination of the main power amplifier and auxiliary power amplifier in the target operating frequency band to meet the efficiency requirements under the set output power back-off ratio.

[0134] like Figure 2 As shown, according to one embodiment of the present invention, in step S1, in the step of establishing a broadband asymmetric quasi-balanced DPA architecture, the input coupler is connected to the main power amplifier BA1 and the auxiliary power amplifier BA2 respectively. The main power amplifier BA1 is connected to the output coupler through a first output hybrid impedance transformation network BA3, and the auxiliary power amplifier BA2 is connected to the output coupler through a second output hybrid impedance transformation network BA4. Further, the input coupler is an input orthogonal 3dB coupler with a characteristic impedance of 50Ω, and the isolation port of the input coupler is connected to a 50Ω load; the output coupler has a characteristic impedance of... The output quadrature coupler, and the back-end matching circuit of the output coupler has The impedance transformation capability from a load to a 50Ω load is provided to meet the requirements of the target operating frequency band, and the isolation port of the output coupler is equipped with a variable load, which includes: a short-circuit load, an open-circuit load, and a reactive component load. In this embodiment, the variable load is also configured with a multi-channel RF switching circuit, wherein each switching channel of the multi-channel RF switching circuit has one load, realizing the switching function of the variable load. In this embodiment, the main power amplifier and the auxiliary power amplifier have the same power amplifier chip and the same input matching circuit.

[0135] In this embodiment, a first output hybrid impedance transformation network is used to connect the main power amplifier and the output coupler, completing the fundamental impedance transformation and implementing second harmonic impedance control, enabling the main power amplifier to operate in continuous mode. The first output hybrid impedance transformation network includes a device parasitic parameter model of the main power amplifier and a first external matching circuit. A second output hybrid impedance transformation network is used to connect the auxiliary power amplifier and the output coupler, completing the fundamental impedance transformation and implementing second harmonic impedance control, enabling the auxiliary power amplifier to operate in continuous mode. The second output hybrid impedance transformation network includes a device parasitic parameter model of the auxiliary power amplifier and a second external matching circuit. In this embodiment, the main power amplifier and auxiliary power amplifier are configured with the optimal DC bias combination for different frequency bands within the target operating band.

[0136] Combination Figure 3 and Figure 4As shown, according to one embodiment of the present invention, in step S2, in the step of establishing the equivalent circuit model of broadband asymmetric quasi-balanced DPA using an ideal current source and an output coupler, when the variable load is a short-circuit load, the equivalent circuit model is a series AQBDPA model; when the variable load is an open-circuit load, the equivalent circuit model is a parallel AQBDPA model. Specifically, see... Figure 3 A normalized reactance is applied to the isolation port of the output coupler. , and when When there is a short-circuit load, the equivalent circuit model is a series AQBDPA model. As the input level increases, the series AQBDPA model moves from the low-power region (only the main power amplifier is on and the auxiliary power amplifier is off) to the high-power region (both the main power amplifier and the auxiliary power amplifier are on at the same time). This allows us to construct the mathematical relationship between voltage and current in the equivalent circuit model.

[0137] First, obtain the ideal output coupler. A matrix, and is represented as:

[0138] (1)

[0139] in, Represents the imaginary unit. This represents the transmission coefficient of the output coupler. This represents the coupling coefficient of the output coupler; therefore, when the output coupler has no losses, we can obtain:

[0140] (2)

[0141] in, This represents the transmission coefficient of the output coupler. This represents the coupling coefficient of the output coupler.

[0142] Secondly, the characteristic impedance of the output coupler is set to... Then the output coupler The parameter matrix is ​​derived as follows:

[0143] (3)

[0144] in, This represents the transmission coefficient of the output coupler. This represents the coupling coefficient of the output coupler.

[0145] Finally, based on the short-circuit load applied to the isolation port of the output coupler by the series AQBDPA, and the load applied to the output port... The load boundary conditions, combined with the output coupler The parameter matrix generates the voltage and current relationships at the four ports of the output coupler, and is expressed as follows:

[0146] (4)

[0147] in, This represents the voltage level of the auxiliary power amplifier in the series AQBDPA model. This represents the voltage level of the main power amplifier in the series AQBDPA model. This represents the voltage level at the output port of the output coupler in the series AQBDPA model. This represents the current level of the auxiliary power amplifier in the series AQBDPA model. This represents the current level of the main power amplifier in the series AQBDPA model. This represents the isolation port current level of the output coupler in the series AQBDPA model. This represents the current level at the output port of the output coupler in the series AQBDPA model. This represents the characteristic impedance of the output coupler. This represents the transmission coefficient of the output coupler. This represents the coupling coefficient of the output coupler. It represents the imaginary unit.

[0148] See Figure 4 As shown, a normalized reactance is further applied to the isolation port of the output coupler. ,when When there is an open-circuit load, the equivalent circuit model is a parallel AQBDPA model. Therefore, as the input level increases, the parallel AQBDPA model transitions from a low-power region (only the main power amplifier is on, the auxiliary power amplifier is off) to a high-power region (both the main power amplifier and the auxiliary power amplifier are on simultaneously). This allows us to construct the mathematical relationship between voltage and current in the equivalent circuit model. Specifically, based on the parallel AQBDPA model, an open-circuit load is applied to the isolation port of the output coupler, and a load is applied to the output port... The load boundary conditions, combined with the aforementioned output coupler The parameter matrix can then generate the voltage and current relationships at the four ports of the output coupler, expressed as follows:

[0149] (5)

[0150] in, This represents the voltage level of the main power amplifier in the parallel AQBDPA model. This represents the voltage level of the auxiliary power amplifier in the parallel AQBDPA model. This represents the voltage level at the isolation port of the output coupler in the parallel AQBDPA model. This represents the voltage level at the output port of the output coupler in the parallel AQBDPA model. This represents the current level of the main power amplifier in the parallel AQBDPA model. This represents the current level of the auxiliary power amplifier in the parallel AQBDPA model. This represents the current level at the output port of the output coupler in the parallel AQBDPA model.

[0151] According to one embodiment of the present invention, in step S3, a linear current model is used as the excitation signal for the main power amplifier and the auxiliary power amplifier to determine the excitation signal at different normalized input levels. The steps for determining load impedance, output power, and drain efficiency include:

[0152] S31. Using a linear current model as the excitation signal for the main power amplifier and auxiliary power amplifier in the series AQBDPA model and the parallel AQBDPA model, the main power amplifier current is established. and auxiliary power amplifier current Respectively with normalized input level The relationship is defined, and the current ratio between the auxiliary power amplifier and the main power amplifier is defined when the maximum input level is reached. ;

[0153] S32. For the low-power region of the equivalent circuit model, obtain the normalized input level in the low-power region. The corresponding load impedance, output power, and drain efficiency;

[0154] S33. For the high-power region of the equivalent circuit model, obtain the normalized input level in the high-power region. The corresponding load impedance, output power, and drain efficiency.

[0155] According to one embodiment of the present invention, in step S31, the main power amplifier current is established. and auxiliary power amplifier current Respectively with normalized input level The relationship is defined, and the current ratio between the auxiliary power amplifier and the main power amplifier is defined when the maximum input level is reached. In the following steps, the load modulation behavior can be mathematically described based on the constructed relational formula. Therefore, a linear current model is used to analyze the main power amplifier BA1 and the auxiliary power amplifier BA2, and their currents are related to the normalized input level. The relationships are represented as follows:

[0156] Main power amplifier current With normalized input level The relational expression is as follows:

[0157] (6)

[0158] in, This represents the current of the main power amplifier at its maximum input level.

[0159] Auxiliary power amplifier current With normalized input level The relational expression is as follows:

[0160] (7)

[0161] in, This represents the current of the auxiliary power amplifier at its maximum input level. This indicates the normalized input level for enabling the auxiliary power amplifier;

[0162] Defined auxiliary and main power amplifier current ratio Represented as:

[0163] (8)

[0164] in, This represents the current of the auxiliary power amplifier at its maximum input level. This indicates the current of the main power amplifier at its maximum input level.

[0165] According to one embodiment of the present invention, in step S32, for the low-power region of the equivalent circuit model, the normalized input level under the low-power region is obtained. In the steps corresponding to load impedance, output power, and drain efficiency, in the low power region (i.e. When ), the impedance on the auxiliary power amplifier It is infinitely large because the auxiliary power amplifier is off in the low-power region. Furthermore, the load impedances on the main power amplifier in the series AQBDPA model and the parallel AQBDPA model can be further derived from equations (4) and (5), and are respectively:

[0166] If the equivalent circuit model is a series AQBDPA model, then the load impedance of the main power amplifier in the low-power region is expressed as:

[0167] (9)

[0168] in, This represents the load impedance of the main power amplifier in the low-power region of the series AQBDPA model;

[0169] If the equivalent circuit model is a parallel AQBDPA model, then the load impedance of the main power amplifier in the low-power region is expressed as:

[0170] (10)

[0171] in, This represents the load impedance of the main power amplifier in the low-power region of the parallel AQBDPA model.

[0172] Based on the aforementioned steps, by further combining equations (6) and (7), the output power and drain efficiency of the series AQBDPA model and the parallel AQBDPA model in the low-power region can be derived respectively, and are as follows:

[0173] The output power of the series AQBDPA model is expressed as:

[0174] (11)

[0175] in, This represents the output power of the series AQBDPA model in the low-power region;

[0176] The output power of the parallel AQBDPA model is expressed as:

[0177] (12)

[0178] in, This represents the output power of the parallel AQBDPA model in the low-power region;

[0179] The drain efficiency of the series AQBDPA model is expressed as:

[0180] (13)

[0181] in, This represents the drain efficiency of the series AQBDPA model in the low-power region. This represents the drain supply voltage of the main power amplifier;

[0182] The drain efficiency of the parallel AQBDPA model is expressed as:

[0183] (14)

[0184] in, This represents the drain efficiency of the parallel AQBDPA model in the low-power region. This indicates the drain supply voltage of the main power amplifier.

[0185] According to one embodiment of the present invention, in step S33, for the high-power region of the equivalent circuit model, the normalized input level under the high-power region is obtained. In the steps related to load impedance, output power, and drain efficiency, as the input level increases, the equivalent circuit model enters the high-power region (i.e., After the auxiliary power amplifier is turned on, the main power amplifier and the auxiliary power amplifier perform load modulation on each other. The load impedance in the high power region can be derived by equations (4) and (5), respectively:

[0186] If the equivalent circuit model is a series AQBDPA model, then the load impedance of the main power amplifier in the high-power region is expressed as:

[0187] (15)

[0188] in, This represents the load impedance of the main power amplifier in the high-power region of the series AQBDPA model;

[0189] The load impedance of the auxiliary power amplifier in the high-power region is expressed as:

[0190] (16)

[0191] in, This represents the load impedance of the auxiliary power amplifier in the high-power region of the series AQBDPA model;

[0192] If the equivalent circuit model is a parallel AQBDPA model, then the load impedance of the main power amplifier in the high-power region is expressed as:

[0193] (17)

[0194] in, This represents the load impedance of the main power amplifier in the high-power region of the parallel AQBDPA model;

[0195] The load impedance of the auxiliary power amplifier in the high-power region is expressed as:

[0196] (18)

[0197] in, This represents the load impedance of the auxiliary power amplifier in the high-power region of the parallel AQBDPA model.

[0198] Based on the aforementioned steps, by further combining equations (6) and (7), the output power and drain efficiency of the series AQBDPA model and the parallel AQBDPA model in the high-power region can be derived respectively, and are as follows:

[0199] The output power of the series AQBDPA model is expressed as:

[0200] (19)

[0201] in, This represents the output power of the series AQBDPA model in the high-power region;

[0202] The output power of the parallel AQBDPA model is expressed as:

[0203] (20)

[0204] in, This represents the output power of the parallel AQBDPA model in the high-power region;

[0205] The drain efficiency of the series AQBDPA model is expressed as:

[0206] (twenty one)

[0207] in, This represents the drain efficiency of the series AQBDPA model in the high-power region. This represents the drain supply voltage of the main power amplifier. This indicates the drain supply voltage of the auxiliary power amplifier;

[0208] The drain efficiency of the parallel AQBDPA model is expressed as:

[0209] (twenty two)

[0210] in, This represents the drain efficiency of the parallel AQBDPA model in the high-power region. This represents the drain supply voltage of the main power amplifier. This indicates the drain supply voltage of the auxiliary power amplifier.

[0211] According to one embodiment of the present invention, in step S4, the adjustable proportional coefficient of the load loaded at the output port of the output coupler is obtained. In the steps, based on the obtained adjustable scaling factor It can accurately establish adjustable proportional coefficients. With transmission coefficient Coupling coefficient Auxiliary and main power amplifier current ratio The mathematical relationship between them. Specifically, when the input level is at its maximum, that is... At this time, the load impedances of the main power amplifier and the auxiliary power amplifier are set to remain equal when the power output is at saturation. ,in, The load impedance when the main power amplifier is at saturated output power. To determine the load impedance when the power amplifier is at saturated output power, the corresponding adjustable proportional coefficients are further derived from equations (15), (16), (17), and (18). Specifically, it is expressed as:

[0212] If the equivalent circuit model is a series AQBDPA model, then the adjustable scaling factor... Represented as:

[0213] (twenty three)

[0214] in, This indicates the adjustable scaling factor of the series AQBDPA model, and the subscript SE is the identifier of the series AQBDPA model;

[0215] If the equivalent circuit model is a parallel AQBDPA model, then the adjustable scaling factor... Represented as:

[0216] (twenty four)

[0217] in, This indicates the adjustable scaling factor of the parallel AQBDPA model; the subscript PL is the identifier of the parallel AQBDPA model.

[0218] According to one embodiment of the present invention, in step S4, the auxiliary-to-main power amplifier current ratio is obtained. With normalized input level In the steps of the relationship, since the main function is placed in It begins to enter voltage saturation, which means the main power amplifier... Voltage at time and The voltages at the same time are equal, that is ,in, The voltage when the main power amplifier is in saturation state. Main power supply The voltage at that time is used to derive the auxiliary and main power amplifier current ratios for the series AQBDPA model and the parallel AQBDPA model by combining equations (6), (7), (9), (10), (15), and (17). With normalized input level The relationship between them is the same, specifically expressed as:

[0219] (25).

[0220] like Figure 1 As shown, according to one embodiment of the present invention, in step S4, the output power back-off ratio and the normalized input level are obtained. In the steps relating the relationship, the output power of the broadband asymmetric quasi-balanced DPA at saturation is... and Output power The ratio is defined as the output power back-off ratio (OBO). Then, according to equations (11), (12), (19), and (20), the output power back-off ratio and the normalized input level can be derived. The relationship between them is expressed as:

[0221] (26)

[0222] in, Indicates the output power back-off ratio. This represents the output power of a broadband asymmetric quasi-balanced DPA at saturation. This indicates that the broadband asymmetric quasi-balanced DPA operates at a normalized input level. With the normalized input level of the auxiliary power amplifier enabled Output power when they are equal.

[0223] According to one embodiment of the present invention, step S5, which involves using ADS tools to perform simulation verification and optimize the isolation port load of the output coupler and the DC bias combination of the main power amplifier and the auxiliary power amplifier in the target operating frequency band to meet the efficiency requirements under the set output power back-off ratio, includes:

[0224] S51. Set the characteristic impedance of the output coupler Transmission coefficient An equivalent circuit model of a broadband asymmetric quasi-balanced DPA is established in the ADS tool; in this embodiment, the following is set: , Therefore, an equivalent circuit model of a broadband asymmetric quasi-balanced DPA can be established in the ADS tool for simulation. The established equivalent circuit model includes a series AQBDPA model and a parallel AQBDPA model.

[0225] S52. Set the range of the output power back-off ratio, and draw the output power back-off ratio at different normalized input levels based on the constructed equivalent circuit model. The curves showing the changes in load impedance, drain efficiency, voltage, and current are obtained, and the output power back-off ratio is determined based on the drain efficiency and preset design requirements. Objective: In this embodiment, the output power back-off ratio is set to a range of OBO = 6 / 8 / 10 / 12 dB. Therefore, based on the simulation process, the equivalent circuit model can be plotted at different normalized input levels. The curves showing the changes in load impedance, drain efficiency, voltage, and current are as follows: Figure 5 As shown. Figure 5 This indicates the drain efficiency, load impedance, current, and voltage of the series AQBDPA model and the parallel AQBDPA model in relation to the normalized input level. The relationship between the changes is the same, and it confirms that the theoretical essence of the broadband asymmetric quasi-equilibrium DPA proposed in this scheme is an extension of the traditional QBDPA theory.

[0226] Further evidence Figure 5 Based on the drain efficiency characteristics of (a) and the preset design requirements, the set output power back-off ratio can be determined. The goal. Specifically, from... Figure 5 (a) It can be seen that when the normalized input level of the auxiliary power amplifier is turned on... The output power back-off ratio changes from 6 dB to 12 dB as it changes from 0.5012 to 0.2512, indicating that the broadband asymmetric quasi-balanced DPA in this scheme can further expand the back-off range compared to the traditional QBDPA. Figure 5 (b) Shows that when the output power back-off ratio is 10 dB, the load impedance of the main power amplifier modulates from 2.15 dB to 0.68 dB in the back-off range. From Figure 5 (c) and 5(d) show that when the input is at its maximum level, the current ratio and voltage ratio between the auxiliary power amplifier and the main power amplifier increase with the increase of the output power back-off ratio. For example, when the output power back-off ratio is 12dB, the current ratio and voltage ratio are both 1.73, while the current ratio and voltage ratio of the traditional QBDPA are only 1.

[0227] S53. Obtain the adjustable proportional coefficient The value of is determined, and the characteristic impedance of the output coupler is determined. The orthogonal 3dB coupler; in this embodiment, by combining equations (2), (23), (24), (25) and (26), the adjustable scaling factor in the series AQBDPA model and the parallel AQBDPA model is plotted. (Right now and ) and transmission coefficient The relationship between them, such as Figure 6 As shown. When the output power back-off ratio = 6 / 8 / 10 / 12 dB and the transmission coefficient... Values At the same time, the adjustable scaling factor in the series AQBDPA model and the parallel AQBDPA model The value range is within a small interval of 0.87 to 1.15; because Furthermore, in order to achieve broadband applications, the adjustable scaling factor is required. A value of 1 indicates that the back-end matching circuit should achieve... The broadband impedance transformation to 50Ω also indicates that choosing the characteristic impedance of the output coupler is... An orthogonal 3 dB coupler is feasible.

[0228] S54. Set the target operating frequency band and saturation output power, based on The objective is to select multiple frequency points within the target operating frequency band and use the ADS tool to perform load-pull simulation on the current surface of the power amplifier chip, outputting the load-pull simulation results. In this embodiment, the power amplifier chips required for the main power amplifier BA1 and auxiliary power amplifier BA2 are selected, and the typical output power of the two power amplifier chips should meet the target saturated output power requirement. According to the OBO target, multiple frequency points are selected within the target operating frequency band, and the fundamental impedance load-pull simulation with second harmonic control is performed on the current surface of the power amplifier chip using the ADS tool. First, the power amplifier chip is biased in deep AB class, and a drain supply voltage lower than the typical value is provided. This drain voltage is continuously adjusted to the optimal value to ensure that the saturated output power simulated at multiple frequency points is greater than half of the target saturated output power of the broadband asymmetric quasi-balanced DPA, and the corresponding load impedances are all distributed within the same small real impedance range (i.e., the corresponding load impedances can all take the same real impedance value). Z SAT Multiple frequency points maintain high efficiency at OBO output power, and the corresponding load impedances are all distributed within the same large real impedance range (i.e., the corresponding load impedances can all take the same real impedance value). Z OBO Then, the power amplifier chip is biased to Class C, and the gate bias and drain supply voltage (which are greater than typical values) are adjusted to their optimal values ​​to ensure that the saturated output power simulated at multiple frequency points is greater than half of the target saturated output power of the broadband asymmetric quasi-balanced DPA, and that the corresponding load impedances are all distributed within the same small real impedance range (i.e., the corresponding load impedances can all take the same real impedance value). Z SAT Meanwhile, the gate voltage and drain supply voltage of the main power amplifier and auxiliary power amplifier were initially determined.

[0229] S55. Construct the first output hybrid impedance transformation network, the second output hybrid impedance transformation network, and the output coupler into an orthogonal 3 dB coupler for impedance transformation, and set its characteristic impedance ratio to be... The characteristic impedance was determined based on the load traction simulation results. and characteristic impedance The value of , where, The characteristic impedance is represented by the current plane of the power amplifier chip viewed from the constructed impedance-transformation orthogonal 3 dB coupler; and the structures of the first output hybrid impedance transformation network, the second output hybrid impedance transformation network, the input matching circuit, and the back-end matching circuit are determined based on the impedance transformation ratio; in this embodiment, the characteristic impedance is realized within the operating frequency band. To characteristic impedance The fundamental impedance transformation and the control of the second harmonic impedance to the edge of the Smith chart are the performance requirements that the first and second output hybrid impedance transformation networks must meet. In this embodiment, based on the simulation model established in steps S51 to S52, the determined... Simulations are performed under the target conditions to obtain the desired results. The target output power is the load impedance of the main power amplifier and the common load impedance of the main power amplifier and auxiliary power amplifier at saturated output power, based on the selected... After denormalizing the value with respect to the load impedance, ensure that the following conditions are met. When the target output power is reached, the load impedance of the main power amplifier is the real impedance obtained in step S54. Z OBO When the output is at saturation, the common load impedance of the main power amplifier and the auxiliary power amplifier is the real impedance obtained in step S54. Z SAT Additionally, based on choice Value, ensuring the characteristic impedance is The output quadrature 3dB coupler is easy to implement, and the characteristic impedance is easy to achieve within the operating frequency band. To characteristic impedance Fundamental impedance transformation and second harmonic control. If the requirements are not met, the characteristic impedance should be reselected. and characteristic impedance The value is maintained until the requirement is met.

[0230] Furthermore, based on the target operating frequency band, a first output hybrid impedance transformation network and a second output hybrid impedance transformation network are designed. The first and second output hybrid impedance transformation networks are identical, and both are constructed from the device parasitic parameter model of the power amplifier chip and an external matching circuit, achieving operation within the target operating frequency band. arrive The impedance transformation is as follows: Specifically, the first output hybrid impedance transformation network includes: the device parasitic parameter model of the main power amplifier and the first external matching circuit; wherein, the first external matching circuit is a microstrip circuit; the second output hybrid impedance transformation network includes: the device parasitic parameter model of the auxiliary power amplifier and the second external matching circuit; wherein, the second external matching circuit is a microstrip circuit; based on the consistency of their structures, the first external matching circuit and the second external matching circuit are identical.

[0231] Furthermore, ensure the actual impedance during the design. The return loss at the terminal should be less than -20dB within the operating frequency band. Second harmonic impedance control should be performed in the external matching circuit to ensure that the second harmonic impedance within the operating frequency band is distributed as close as possible to the edge of the Smith chart. Then, a low-loss high-frequency circuit board should be selected, and the external matching circuit should be transformed into a microstrip circuit. The impedance transformation and second harmonic impedance control performance of the output hybrid impedance transformation network within the target operating frequency band should be verified by electromagnetic layout simulation. If the requirements are not met, the external matching circuit should be redesigned until the requirements are met.

[0232] Furthermore, based on the target operating frequency band and the obtained external matching circuit, the input matching circuits for the main power amplifier and the auxiliary power amplifier are designed, with the input matching circuits for the main power amplifier and the auxiliary power amplifier remaining identical. Specifically, the sub-amplifier (whose output and input matching circuits are identical for both the main and auxiliary power amplifiers, allowing any sub-amplifier to be configured as the DC bias of the main power amplifier for input matching circuit design) is set to the main power amplifier gate voltage and drain supply voltage obtained in step S54, and the load impedance of the external matching circuit is set to... The designed input matching circuit ensures that the entire sub-amplifier is stable and well matched within the target operating frequency band, and maximizes the in-band gain and flatness of the sub-amplifier. The input matching circuit is then converted into a microstrip circuit. The high-frequency circuit board is the same as the low-loss high-frequency circuit board in step S55. The performance is verified by electromagnetic layout simulation. If the requirements are not met, the input matching circuit is redesigned until the requirements are met.

[0233] Furthermore, based on the target operating frequency band, a back-end matching circuit is designed and converted into a microstrip circuit. The high-frequency circuit substrate is the same as the low-loss high-frequency circuit substrate in step S55. Electromagnetic layout simulation verifies that it is implemented within the target operating frequency band. Impedance transformation up to 50Ω.

[0234] S56. Select multiple operating frequencies based on the target operating frequency band, and determine the load (i.e., the load on the isolation terminal of the output coupler) and the optimal efficiency DC bias combination for each operating frequency using the ADS tool, ensuring that the set... The drain efficiency within the target backoff interval meets the design requirements. In this embodiment, the circuit layout of the overall broadband asymmetric quasi-balanced DPA is established in the ADS tool. Based on multiple selected operating frequencies, the drain efficiency and gain of the broadband asymmetric quasi-balanced DPA as a function of output power are simulated through electromagnetic layout. The optimal isolation port load and the optimal efficiency DC bias combination are selected for each operating frequency to ensure that the drain efficiency meets the design requirements within the set OBO backoff interval.

[0235] S57. Based on the determined load at each operating frequency, a load connection circuit is constructed to form a variable load arranged at the isolation port of the output coupler. In this embodiment, the constructed load connection circuit is a multi-channel RF switch circuit, and each switching channel on the multi-channel RF switch circuit has one load (such as an optimal reactive element or an open / short-circuit load) to achieve the switching function of the variable load. Based on this, the final structure of the broadband asymmetric quasi-balanced DPA can be determined based on steps S56 and S57. Then, in practical applications, at different operating frequencies within the target operating frequency band, the broadband asymmetric quasi-balanced DPA is configured with the optimal DC bias combination for the corresponding operating frequency, and the multi-channel RF switch is switched to the RF channel with the optimal load to achieve the target performance.

[0236] To further illustrate this plan, further examples will be provided.

[0237] Example

[0238] To verify the proposed theory and design method, two MACOM 10W CG2H40010F power amplifier chips were used to design a broadband asymmetric quasi-balanced DPA operating in the 0.8-1.8 GHz range. The target OBO was set at 10 dB, the saturated output power was 20W (43 dBm), and the efficiency was greater than 40% when outputting 2W (33 dBm) power with a 10 dB backoff.

[0239] The circuit board material used is the F4BM-220 dielectric substrate manufactured by Taizhou Wangling Company. The dielectric constant of this substrate is... and loss tangent In addition, to reduce the size of the power amplifier, the input coupler is a broadband orthogonal 3 dB coupler HC1500W03 with a characteristic impedance of 50Ω provided by Shenzhen Yantong Co., Ltd. The output coupler is an output orthogonal 3 dB coupler. When the OBO target is 10 dB, the adjustable scaling factor in the series AQBDPA model and the parallel AQBDPA model can be obtained from equations (23) and (24). They are respectively and That is Therefore, the adjustable proportional coefficient The final value is 1.

[0240] according to Figure 2Design two main power amplifiers BA1 and auxiliary power amplifier BA2, and design their output mixed impedance transformation networks (i.e., the first output mixed impedance transformation network and the second output mixed impedance transformation network). The main power amplifier BA1 and auxiliary power amplifier BA2 use the same power amplifier chip, and the external matching circuits of the main power amplifier BA1 and auxiliary power amplifier BA2 are designed with the same circuit form. Load-pull simulations were performed on the current surface of the CG2H40010F transistor at three frequency points: 0.8 GHz, 1.3 GHz, and 1.8 GHz, under second harmonic impedance control. The simulation results show that when the gate bias is -2.7 V, the drain supply voltage is 20 V, and the load impedance is 107.5 Ω, the power-added efficiency (PAE) is greater than 63% at an output power greater than 33 dBm. When the load impedance is 34 Ω, the PAE is greater than 78.6% at an output power slightly greater than 40 dBm. When the gate bias is -4.5 V, the drain supply voltage is 36 V, and the load impedance is 34 Ω, the PAE is greater than 55.5% at an output power greater than 41 dBm. From equations (9), (10), (15), (16), (17), and (18), it can be seen that when OBO = 10 dB, the denormalized load impedance of the main power amplifier under the OBO output power is 2.15 dB. The denormalized load impedance of the main power amplifier and auxiliary power amplifier at saturated output is 0.68Ω. ,choose = The 50Ω characteristic impedance meets the above requirements, therefore, the output coupler can still be the HC1500W03 broadband orthogonal 3 dB coupler with a characteristic impedance of 50Ω provided by Shenzhen Yantong Co., Ltd., and the back-end matching circuit can be omitted. The two output hybrid impedance transformation networks and the actual output coupler constitute an impedance transformation orthogonal 3 dB coupler, as shown below. Figure 7 As shown, the impedance transformation ratio is =1.

[0241] Within the 0.8-1.8 GHz range, the output hybrid impedance transformation network performs a 50Ω to 50Ω impedance transformation, incorporating the device parasitic parameter model of the power amplifier chip and external matching circuitry. The specific circuit design is as follows... Figure 8 As shown in (a), by Figure 8 (b) It can be seen that the backlash loss S11 is less than 20 dB in the 1-1.8 GHz range and less than 13 dB in the 0.8-1.8 GHz range, indicating good in-band impedance transformation. Figure 8 (c) The impedance of 2–3.6 GHz is controlled at the edge of the Smith chart, confirming that the main and auxiliary power amplifiers operate in continuous class mode for most of the operating frequency band.

[0242] The input matching circuits for the main power amplifier and the auxiliary power amplifier are identical. A parallel resistor and capacitor stabilization circuit is designed within the input matching circuit, and a resistor is connected in series in the gate bias circuit to ensure the stability of the two sub-amplifiers within the operating frequency band. The entire input matching circuit is designed to achieve good matching within the operating frequency band, improving the small-signal gain within the band. The designed input matching circuit is as follows: Figure 9 As shown in (a). Since the main power amplifier operates in deep Class AB, with the grid piezoelectric voltage set to -2.7 V, the drain supply voltage set to 20 V, and the load of the output hybrid impedance transformation network set to 50 Ω, the simulated S-parameters are as follows: Figure 9 As shown in (b), the S21 curve shows that the in-band gain is around 16 dB, and the S11 curve has relatively good matching in the high-frequency part of the operating frequency band, which is conducive to maintaining the flatness of the gain.

[0243] For different frequencies within the target operating frequency band, appropriate loads were configured at the isolation ports of the output quadrature 3dB coupler, and large-signal simulations were performed at multiple frequencies. The gate voltage of the main power amplifier was initially set to -2.7 V and the drain voltage to 20 V, while the gate voltage of the auxiliary power amplifier was set to -4.5 V and the drain voltage to 36 V. Due to the phase and amplitude imbalance issues in the actual output coupler, appropriate DC bias combinations were selected for the main and auxiliary power amplifiers at different frequency bands to achieve optimal efficiency. Figure 10 Simulated current and voltage variations with output power at 0.8 GHz, 1.4 GHz, and 1.7 GHz are presented. Figure 10 (a) It can be observed that when the output power is less than 33 dBm, only the current of the main power amplifier increases with the increase of the output power, while the current of the auxiliary power amplifier is close to 0. When it is greater than 33 dBm, after the auxiliary power amplifier is started, the current of the auxiliary power amplifier increases rapidly with the increase of the output power. When the saturated output power of 43 dBm is reached, the current of the auxiliary power amplifier is significantly greater than the current of the main power amplifier. Figure 10 (b) shows that when the output power is greater than 33 dBm, the voltage of the main power amplifier approaches saturation. Figure 11 (a) shows that the drain efficiency curves of the designed broadband asymmetric quasi-balanced DPA at multiple frequencies in the 0.8-1.8 GHz operating band have typical DPA efficiency characteristics, with a significant improvement in efficiency within a 10 dB backoff range.

[0244] Using single-carrier continuous wave input signals of different power to... Figure 11 The physical test in (b) was performed similarly to that of a conventional QBDPA, by manually changing the load on the output quadrature 3 dB coupler isolation port to verify performance. Figure 12 The test results in (a) are consistent with Figure 11 The simulation results in (a) are similar, from Figure 12(b) It can be seen that the saturation power in the entire operating frequency band is 42.1-44.2 dBm, the gain at saturation is 7.1-9.2 dB, and the drain efficiency at 10 dB back-off output power and saturation output power is 42.1%-56.2% and 50.7%-70.4%, respectively.

[0245] The designed broadband asymmetric quasi-balanced DPA is compared with existing advanced DPAs and LMBAs, as shown in Table 1. Compared with Comparative Examples 1, 2, and 4, the broadband asymmetric quasi-balanced DPA designed in this scheme achieves an OBO of 10dB; the target operating bandwidth is also significantly larger than Comparative Examples 3 and 4; especially compared with the LMBA in Comparative Example 3, under the premise of the same OBO, it is not only more efficient, but also requires only 2 power amplifier chips, and the circuit is simpler. In addition, compared with all the listed power amplifiers, the designed AQBDPA has a smaller size, which is more advantageous in practical applications.

[0246] Table 1 Performance Comparison of This Solution with Existing Advanced DPA and LMBA

[0247]

[0248] The above description is merely one embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A design method for a broadband asymmetric quasi-balanced DPA with expanded backoff range, characterized in that, Includes the following steps: S1. Establish the architecture of a broadband asymmetric quasi-balanced DPA, wherein the broadband asymmetric quasi-balanced DPA includes: an input coupler, a main power amplifier, an auxiliary power amplifier, a first output hybrid impedance transformation network, a second output hybrid impedance transformation network, and an output coupler; S2. Establish an equivalent circuit model of a broadband asymmetric quasi-balanced DPA using an ideal current source and an output coupler, and obtain the mathematical relationship between voltage and current in the equivalent circuit model. S3. Using a linear current model as the excitation signal for the main power amplifier and auxiliary power amplifier, the excitation signal is determined at different normalized input levels. The load impedance, output power, and drain efficiency under these conditions; S4. Set the load impedance of the main power amplifier and auxiliary power amplifier to remain equal when the output power is at saturation, and obtain the adjustable proportional coefficient of the load loaded at the output port of the output coupler. ; Set the main power amplifier to normalized input level With the normalized input level of the auxiliary power amplifier enabled Voltages when they are equal When the voltages are equal, the auxiliary and main power amplifier current ratios are obtained. With normalized input level The relationship between them; The saturated output power and input level of the broadband asymmetric quasi-balanced DPA are set to the normalized input level. The ratio of the output power at different times is the output power back-off ratio. The output power back-off ratio and the normalized input level are then obtained. The relationship between them; S5. Use ADS tools for simulation verification to optimize the isolation port load of the output coupler and the DC bias combination of the main power amplifier and auxiliary power amplifier in the target operating frequency band to meet the efficiency requirements under the set output power back-off ratio.

2. The design method for broadband asymmetric quasi-balanced DPA with expanded backoff range according to claim 1, characterized in that, In step S1, the step of establishing a broadband asymmetric quasi-balanced DPA architecture, the input coupler is an input orthogonal 3dB coupler with a characteristic impedance of 50Ω, and the isolation port of the input coupler is connected to a 50Ω load. The output coupler has a characteristic impedance. The output quadrature coupler, and the back-end matching circuit of the output coupler has The output coupler has an impedance transformation capability from a load to a 50Ω load. The isolation port of the output coupler is equipped with a variable load, which includes: a short-circuit load, an open-circuit load, and a reactive element load. The main power amplifier and the auxiliary power amplifier have the same power amplifier chip and the same input matching circuit; The first output hybrid impedance transformation network is used to connect the main power amplifier and the output coupler, complete the fundamental impedance transformation and realize the second harmonic impedance control, so that the main power amplifier works in continuous mode. The second output hybrid impedance transformation network is used to connect the auxiliary power amplifier and the output coupler, complete the fundamental impedance transformation and realize the second harmonic impedance control, so that the auxiliary power amplifier works in continuous mode.

3. The design method for broadband asymmetric quasi-balanced DPA with expanded backoff range according to claim 2, characterized in that, In step S2, when establishing the equivalent circuit model of broadband asymmetric quasi-balanced DPA using an ideal current source and output coupler, the equivalent circuit model is a series AQBDPA model when the variable load is a short-circuit load, and a parallel AQBDPA model when the variable load is an open-circuit load. In the series AQBDPA model, as the input level increases, the series AQBDPA model moves from the low power region to the high power region. In the low power region, the main power amplifier is turned on and the auxiliary power amplifier is turned off. In the high power region, both the main power amplifier and the auxiliary power amplifier are turned on. In the parallel AQBDPA model, as the input level increases, the parallel AQBDPA model moves from the low-power region to the high-power region. In the low-power region, the main power amplifier is turned on and the auxiliary power amplifier is turned off. In the high-power region, both the main power amplifier and the auxiliary power amplifier are turned on.

4. The design method for broadband asymmetric quasi-balanced DPA with expanded backoff range according to claim 3, characterized in that, In step S2, where an equivalent circuit model of a broadband asymmetric quasi-balanced DPA is established using an ideal current source and an output coupler, and the mathematical relationship between voltage and current in the equivalent circuit model is obtained, the mathematical relationship between voltage and current for the series AQBDPA model is expressed as follows: in, This represents the voltage level of the auxiliary power amplifier in the series AQBDPA model. This represents the voltage level of the main power amplifier in the series AQBDPA model. This represents the voltage level at the output port of the output coupler in the series AQBDPA model. This represents the current level of the auxiliary power amplifier in the series AQBDPA model. This represents the current level of the main power amplifier in the series AQBDPA model. This represents the isolation port current level of the output coupler in the series AQBDPA model. This represents the current level at the output port of the output coupler in the series AQBDPA model. This represents the characteristic impedance of the output coupler. This represents the transmission coefficient of the output coupler. This represents the coupling coefficient of the output coupler. Represents the imaginary unit; For the parallel AQBDPA model, the mathematical relationship between voltage and current is expressed as follows: in, This represents the voltage level of the main power amplifier in the parallel AQBDPA model. This represents the voltage level of the auxiliary power amplifier in the parallel AQBDPA model. This represents the voltage level at the isolation port of the output coupler in the parallel AQBDPA model. This represents the voltage level at the output port of the output coupler in the parallel AQBDPA model. This represents the current level of the main power amplifier in the parallel AQBDPA model. This represents the current level of the auxiliary power amplifier in the parallel AQBDPA model. This represents the current level at the output port of the output coupler in the parallel AQBDPA model.

5. The design method for broadband asymmetric quasi-balanced DPA with expanded backoff range according to claim 4, characterized in that, In step S3, a linear current model is used as the excitation signal for the main power amplifier and the auxiliary power amplifier to determine the excitation signal at different normalized input levels. The steps for determining load impedance, output power, and drain efficiency include: S31. Using a linear current model as the excitation signal for the main power amplifier and auxiliary power amplifier in the series AQBDPA model and the parallel AQBDPA model, the main power amplifier current is established. and auxiliary power amplifier current Respectively with normalized input level The relationship is defined, and the current ratio between the auxiliary power amplifier and the main power amplifier is defined when the maximum input level is reached. ; S32. For the low-power region of the equivalent circuit model, obtain the normalized input level in the low-power region. The corresponding load impedance, output power, and drain efficiency; S33. For the high-power region of the equivalent circuit model, obtain the normalized input level in the high-power region. The corresponding load impedance, output power, and drain efficiency.

6. The design method for broadband asymmetric quasi-balanced DPA with expanded backoff range according to claim 5, characterized in that, In step S31, the main power amplifier current is established. and auxiliary power amplifier current Respectively with normalized input level The relationship is defined, and the current ratio between the auxiliary power amplifier and the main power amplifier is defined when the maximum input level is reached. In the steps, the main power amplifier current With normalized input level The relational expression is as follows: in, This represents the current of the main power amplifier at its maximum input level. Auxiliary power amplifier current With normalized input level The relational expression is as follows: in, This represents the current of the auxiliary power amplifier at its maximum input level. This indicates the normalized input level for enabling the auxiliary power amplifier; Defined auxiliary and main power amplifier current ratio Represented as: 。 7. The design method for broadband asymmetric quasi-balanced DPA with expanded backoff range according to claim 6, characterized in that, In step S32, for the low-power region of the equivalent circuit model, the normalized input level under the low-power region is obtained. In the steps related to load impedance, output power, and drain efficiency, if the equivalent circuit model is a series AQBDPA model, then the load impedance of the main power amplifier in the low-power region is expressed as: in, This represents the load impedance of the main power amplifier in the low-power region of the series AQBDPA model; The output power of the series AQBDPA model is expressed as: in, This represents the output power of the series AQBDPA model in the low-power region; The drain efficiency of the tandem AQBDPA model is expressed as: in, This represents the drain efficiency of the series AQBDPA model in the low-power region. This represents the drain supply voltage of the main power amplifier; If the equivalent circuit model is a parallel AQBDPA model, then the load impedance of the main power amplifier in the low-power region is expressed as: in, This represents the load impedance of the main power amplifier in the low-power region of the parallel AQBDPA model; The output power of the parallel AQBDPA model is expressed as: in, This represents the output power of the parallel AQBDPA model in the low-power region; The drain efficiency of the parallel AQBDPA model is expressed as: in, This represents the drain efficiency of the parallel AQBDPA model in the low-power region. This indicates the drain supply voltage of the main power amplifier; In step S33, for the high-power region of the equivalent circuit model, the normalized input level under the high-power region is obtained. In the steps related to load impedance, output power, and drain efficiency, if the equivalent circuit model is a series AQBDPA model, then the load impedance of the main power amplifier in the high-power region is expressed as: in, This represents the load impedance of the main power amplifier in the high-power region of the series AQBDPA model; The load impedance of the auxiliary power amplifier in the high-power region is expressed as: in, This represents the load impedance of the auxiliary power amplifier in the high-power region of the series AQBDPA model; The output power of the series AQBDPA model is expressed as: in, This represents the output power of the series AQBDPA model in the high-power region; The drain efficiency of the tandem AQBDPA model is expressed as: in, This represents the drain efficiency of the series AQBDPA model in the high-power region. This represents the drain supply voltage of the main power amplifier. This indicates the drain supply voltage of the auxiliary power amplifier; If the equivalent circuit model is a parallel AQBDPA model, then the load impedance of the main power amplifier in the high-power region is expressed as: in, This represents the load impedance of the main power amplifier in the high-power region of the parallel AQBDPA model; The load impedance of the auxiliary power amplifier in the high-power region is expressed as: in, This represents the load impedance of the auxiliary power amplifier in the high-power region of the parallel AQBDPA model; The output power of the parallel AQBDPA model is expressed as: in, This represents the output power of the parallel AQBDPA model in the high-power region; The drain efficiency of the parallel AQBDPA model is expressed as: in, This represents the drain efficiency of the parallel AQBDPA model in the high-power region. This represents the drain supply voltage of the main power amplifier. This indicates the drain supply voltage of the auxiliary power amplifier.

8. The design method for broadband asymmetric quasi-balanced DPA with expanded backoff range according to claim 7, characterized in that, In step S4, the adjustable proportional coefficient of the load loaded at the output port of the output coupler is obtained. In the steps, if the equivalent circuit model is a series AQBDPA model, then the adjustable scaling factor... Represented as: in, This indicates the adjustable scaling factor of the series AQBDPA model, and the subscript SE is the identifier of the series AQBDPA model; If the equivalent circuit model is a parallel AQBDPA model, then the adjustable scaling factor... Represented as: in, This indicates the adjustable scaling factor of the parallel AQBDPA model; the subscript PL is the identifier of the parallel AQBDPA model. In step S4, the auxiliary and main power amplifier current ratio is obtained. With normalized input level In the steps relating the auxiliary and main power amplifier current ratios With normalized input level The relationship between them is represented as follows: ； In step S4, the output power back-off ratio and the normalized input level are obtained. In the steps relating the output power back-off ratio to the normalized input level The relationship between them is represented as follows: in, Indicates the output power back-off ratio. This represents the output power of a broadband asymmetric quasi-balanced DPA at saturation. This indicates that the broadband asymmetric quasi-balanced DPA operates at a normalized input level. With the normalized input level of the auxiliary power amplifier enabled Output power when they are equal.

9. The design method for broadband asymmetric quasi-balanced DPA with expanded backoff range according to claim 8, characterized in that, Step S5, which involves using ADS tools for simulation verification and optimizing the isolation port load of the output coupler and the DC bias combination of the main and auxiliary power amplifiers in the target operating frequency band to meet the efficiency requirements under the set output power back-off ratio, includes: S51. Set the characteristic impedance of the output coupler Transmission coefficient And establish an equivalent circuit model of broadband asymmetric quasi-balanced DPA in the ADS tool; S52. Set the range of the output power back-off ratio, and draw the output power back-off ratio at different normalized input levels based on the constructed equivalent circuit model. The curves showing the changes in load impedance, drain efficiency, voltage, and current are obtained, and the output power back-off ratio is determined based on the drain efficiency and preset design requirements. Target; S53. Obtain the adjustable proportional coefficient The value of is determined, and the characteristic impedance of the output coupler is determined. Orthogonal 3dB coupler; S54. Set the target operating frequency band and saturation output power, based on The goal is to select multiple frequency points within the target operating frequency band, use the ADS tool to perform load traction simulation on the current surface of the power amplifier chip, and output the load traction simulation results. S55. Construct the first output hybrid impedance transformation network, the second output hybrid impedance transformation network, and the output coupler into an orthogonal 3 dB coupler for impedance transformation, and set its characteristic impedance ratio to be... The characteristic impedance was determined based on the load traction simulation results. and characteristic impedance The value of , where, This represents the characteristic impedance of the power amplifier chip viewed from the current surface of the constructed impedance-transformation orthogonal 3 dB coupler; and, based on the characteristic impedance... and characteristic impedance The value determines the structure of the first output hybrid impedance transformation network, the second output hybrid impedance transformation network, the input matching circuit, and the back-end matching circuit; S56. Select multiple operating frequencies based on the target operating frequency band, and determine the load and optimal efficiency DC bias combination for each operating frequency using the ADS tool, ensuring that the set... The drain efficiency within the target backoff range meets the design requirements; S57. Based on the determined load at each operating frequency, a load connection circuit is constructed to form a variable load arranged at the isolation port of the output coupler.

10. The design method for broadband asymmetric quasi-balanced DPA with expanded backoff range according to claim 9, characterized in that, In step S55, the first output hybrid impedance transformation network includes: a device parasitic parameter model of the main power amplifier and a first external matching circuit; wherein, the first external matching circuit is a microstrip circuit; The second output hybrid impedance transformation network includes: a device parasitic parameter model of the auxiliary power amplifier and a second external matching circuit; wherein, the second external matching circuit is a microstrip circuit; The input matching circuit is a microstrip circuit; The back-end matching circuit is a microstrip circuit; In step S57, the constructed load connection circuit is a multi-channel RF switch circuit, and each switching channel on the multi-channel RF switch circuit has a load, thereby realizing the switching function of variable load.

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