Dual-mode communication chip

Abstract

The application discloses a dual-mode communication chip and belongs to the technical field of communication. The dual-mode communication chip comprises an HPLC signal sending end and an HPLC signal receiving end; the HPLC signal sending end is configured as an encoding module, is used for encoding load data, and obtains encoded load data; a first storage module is used for storing the encoded load data; a channel interleaving module is used for performing interleaving processing on bit data read from the first storage module; a first bit cache queue is used for sequentially writing bit data from the channel interleaving module in a first bit number and sequentially reading out the bit data in a second bit number according to the writing order; and a bit mapping module is used for mapping bit data from the first bit cache queue to each subcarrier in the second bit number. The application realizes efficient matching of the rate of data processing under a high-order modulation mode and data transmission without subcarrier across physical blocks.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, and in particular relates to a dual-mode communication chip. Background Technology

[0002] In dual-mode communication systems that combine high-speed power line communication (HPLC) and high-speed radio frequency (HRF), multi-carrier modulation technology is typically used as the physical layer foundation.

[0003] Against this backdrop, in order to further improve spectrum efficiency, optimized modulation schemes have been introduced into dual-mode communication systems, such as using a higher-order 64-Quadrature Amplitude Modulation (64QAM) mode.

[0004] However, the subcarriers introduced by higher-order modulation modes have the characteristic of carrying high data volume. When combined with processing modules that process data based on fixed bit number or fixed beat, problems such as inconsistent data beat and rate mismatch are likely to occur. This can lead to waiting, blocking or reduced throughput during data processing, thereby affecting the overall transmission efficiency of the system. Summary of the Invention

[0005] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a dual-mode communication chip to achieve efficient matching of data processing rates under high-order modulation modes.

[0006] In a first aspect, the present invention provides a dual-mode communication chip, comprising an HPLC signal transmitter and an HPLC signal receiver; the HPLC signal transmitter is configured as follows:

[0007] The encoding module is used to encode the load data to obtain the encoded load data;

[0008] The first storage module is used to store the encoded payload data;

[0009] The channel interleaving module is used to interleave the bit data read from the first storage module;

[0010] The first bit buffer queue is used to write bit data from the channel interleaving module sequentially with a first number of bits, and to read it out sequentially in the writing order with a second number of bits; the second number of bits is greater than the first number of bits.

[0011] The bit mapping module is used to map bit data from the first bit buffer queue to each subcarrier with a second number of bits.

[0012] According to one embodiment of the present invention, the maximum number of cached bits in the first bit cache queue is an integer multiple of the number of second bits.

[0013] According to one embodiment of the present invention, the signal transmitting end is configured with two channel interleaving modules, and the first storage module is a dual-port storage module.

[0014] According to one embodiment of the present invention, the HPLC signal receiver is configured as follows:

[0015] The demapping module is used to demapping the bit data in each subcarrier, wherein the number of bits obtained after demapping any subcarrier is the second number of bits.

[0016] The second bit buffer queue is used to write bit data from the demapping module sequentially in the second bit number, and read out bit data according to the first preset rule;

[0017] The second storage module is used to store the bit data read from the second bit cache queue, and read out the bit data with the first number of bits when the stored bit data matches the bit data of the physical block;

[0018] The deinterleaving module is used to deinterleave the bit data read from the second storage module with a first number of bits, and read out the deinterleaved bit data with a first number of bits; the second number of bits is greater than the first number of bits.

[0019] The decoding module is used to decode the deinterleaved bit data with a first number of bits.

[0020] According to one embodiment of the present invention, the first preset rule is configured to read bit data sequentially from the second bit cache queue module in the order of writing, with a second number of bits; if the remaining writable bits of the physical block are less than the second number of bits, a number of bits data corresponding to the remaining writable bits are read.

[0021] According to one embodiment of the present invention, the storage row width of the second storage module is configured to be an integer multiple of the least common multiple of the first number of bits and the second number of bits.

[0022] According to one embodiment of the present invention, the HPLC signal receiver is configured as follows:

[0023] The demapping module is used to demapping the bit data from each subcarrier, wherein the number of bits obtained after demapping any subcarrier is the second number of bits.

[0024] The second bit buffer queue is used to write bit data from the demapping module sequentially in the second bit number, and to read out bit data according to the second preset rule;

[0025] Two parallel deinterleaving modules, wherein either deinterleaving module is used to deinterleave the bit data read from the second bit buffer queue with a first number of bits, and read out the deinterleaved bit data with the first bit data;

[0026] The second storage module is used to store the bit data read from the two parallel deinterleaving modules and to read out the bit data in the first bit count.

[0027] The decoding module is used to decode the bit data read from the second storage module using the first bit data.

[0028] According to one embodiment of the present invention, the second preset rule is configured to read bit data sequentially from the second bit cache queue in the order of writing, with a third number of bits; wherein the third number of bits is twice the first number of bits, so that two parallel deinterleaving modules respectively perform deinterleaving processing on the bit data read from the second bit cache queue with the first number of bits; when the remaining writable bits of the physical block are less than the third number of bits, a number of bits data corresponding to the remaining writable bits are read out, and according to the correspondence between the remaining writable bits and the first number of bits, the number of bits data corresponding to the remaining writable bits are allocated to one or two deinterleaving modules for deinterleaving processing.

[0029] According to one embodiment of the present invention, the second storage module includes multiple storage rows, and the second storage module is configured to write bit data read from two parallel deinterleaving modules into the same storage row of the second storage module.

[0030] According to one embodiment of the present invention, the second storage module is a dual-port storage module.

[0031] The above-described one or more technical solutions in the embodiments of the present invention have at least one of the following technical effects:

[0032] The payload data is encoded by the encoding module, providing reliable forward error correction protection for subsequent data transmission and making the data robust in complex channel environments. Afterwards, the first storage module, which stores the encoded payload data, buffers and temporarily stores the encoded data, providing a stable data source for subsequent data processing. Then, the channel interleaving module interleaves the bit data read from the first storage module, effectively dispersing burst channel errors into random errors, thereby improving the system's anti-interference and error correction capabilities. Finally, the bit data from the channel interleaving module is sequentially written into the first bit buffer queue in the order of the first bit number, and then... The two-bit number reads out the bit data in the order it was written, realizing rate buffering and decoupling between the fixed-rate interleaving output and the bit mapping request with different rates. This allows the interleaving module to work continuously at full load, effectively avoiding data backlog and overall throughput bottlenecks caused by rate mismatch. Finally, the bit mapping module maps the bit data from the first bit buffer queue to each subcarrier, completing adaptive bit data filling. This not only maximizes the utilization of spectrum resources, but also effectively solves the problem of subcarrier data crossing physical block boundaries caused by the mismatch between the number of bits required by the factor carrier and the fixed number of bits of the processing module, simplifying the data scheduling logic.

[0033] In summary, without significantly increasing hardware complexity and chip area overhead, this invention effectively solves the problems of data transmission rate mismatch and cross-physical block transmission faced by HPLC systems during high-order modulation, significantly improves data modulation efficiency and overall throughput, and ensures highly reliable and low-latency data transmission.

[0034] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0035] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0036] Figure 1 This is a schematic diagram of the channel interleaver provided in some embodiments of the present invention;

[0037] Figure 2 This is a schematic diagram of the structure of the HPLC signal transmitting end provided in some embodiments of the present invention;

[0038] Figure 3 This is a schematic diagram of the data processing flow of the HPLC signal transmitter provided in some embodiments of the present invention;

[0039] Figure 4This is a schematic diagram of the structure of the HPLC signal receiving end provided in some embodiments of the present invention;

[0040] Figure 5 This is a schematic diagram of the HPLC signal receiving end data processing flow provided in some embodiments of the present invention;

[0041] Figure 6 This is a schematic diagram of the HPLC signal receiving end provided in some other embodiments of the present invention;

[0042] Figure 7 This is a schematic diagram of the HPLC signal receiving terminal data processing flow provided in some other embodiments of the present invention. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0044] The terms "first," "second," etc., used in the specification and claims of this invention are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0045] In dual-mode communication systems, the application of high-order modulation modes mainly covers the following two typical scenarios: First, a unified high-order modulation mode, in which all subcarriers in the entire communication frequency band adopt the same high-order modulation method during transmission (e.g., all using 64QAM); Second, a bit-loaded mode, which allows the system to dynamically allocate different modulation orders to subcarriers according to channel conditions, such as binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), 16-quadrature amplitude modulation (16QAM), and 64QAM, etc.

[0046] Among them, 64QAM, as a representative high-order modulation mode that can significantly improve the spectral efficiency of a single subcarrier, has a significant bit rate mismatch problem due to its characteristic of carrying 6 bits per symbol, which is generally based on 4-bit signal processing units (such as interleavers and memories) in existing communication chips. This non-integer multiple rate relationship is the core reason for inconsistent data clock speeds, throughput bottlenecks, and difficulties in cross-physical block transmission. Therefore, this invention uses 64QAM as a typical application scenario for detailed description. Of course, it is not limited to this. The core of this invention is to provide a general, hardware-based rate-adaptive architecture that can be applied to communication modulation scenarios with fixed clock speeds and data demand mismatches.

[0047] To address the data clock inconsistency problem introduced by the 64QAM modulation mode, one approach is to optimize the modulation algorithm itself so that the final bit allocation result can be adapted as much as possible to the downstream data processing unit operating at a fixed rate.

[0048] However, the optimization effect of such algorithms is limited by the dynamic changes in channel conditions, making it difficult to fundamentally solve the structural mismatch between modulation requirements and fixed rates. This leads to data buffering, waiting, and even forces data to cross physical block (PB) boundaries for access. To address these issues, more complex real-time scheduling and control logic is often required, which in turn increases the system's implementation complexity and uncertainty, making it difficult to balance reliability and efficiency.

[0049] Therefore, with the widespread adoption of 64QAM modulation, how to effectively solve the bit rate matching problem without sacrificing its high spectral efficiency advantage, and how to ensure good data transmission performance while avoiding complex software scheduling, remains an urgent problem to be solved.

[0050] Furthermore, to enhance multipath interference resistance and improve spectrum utilization efficiency, dual-mode communication systems typically employ Orthogonal Frequency Division Multiplexing (OFDM) technology as the core of the physical layer. OFDM effectively addresses the challenges of frequency-selective channels by dividing a broadband signal into multiple mutually orthogonal subcarriers for parallel transmission. Moreover, when the subcarriers use 64QAM modulation, the number of bits that can be carried in a single transmission is increased compared to traditional low-order modulation, thereby significantly improving the theoretical peak rate of the system.

[0051] For example, a subcarrier that requires 6 bits of padding cannot be matched with a data processing module that processes 4 bits per cycle. This rate mismatch, exacerbated by the increase in modulation order, causes the bit data to be unable to be aligned continuously during processing, leading to blocking and waiting, and may cause the subcarrier data to cross the physical block boundary, thereby affecting the overall throughput and data transmission efficiency of the system.

[0052] In dual-mode communication systems, although HPLC and HRF differ fundamentally in their transmission media and operating frequency bands, they typically share OFDM as the core modulation and multiple access technology framework at the physical layer. This means that whether it's an HPLC subcarrier based on power line transmission or an HRF subcarrier based on space wireless transmission, the basic processing flow from bit stream generation to final modulation mapping is highly isomorphic in both mathematical principles and hardware implementation structure. Given that the power line channel environment faced by HPLC places more stringent and typical demands on the robustness of signal processing, this invention uses an HPLC system as the illustrative scenario for specific implementation.

[0053] It should be noted that the embodiments of the present invention are not limited to HPLC systems. In practical applications, the embodiments of the present invention can be adapted to the HRF system according to the subcarrier parameters, modulation and coding strategies, etc.

[0054] The transmission and processing of OFDM signals typically requires rearranging and mapping the encoded bit sequence to enhance the system's anti-interference capability in complex power line channel environments and provide a basic data organization for subsequent modulation processing. This rearrangement process is generally achieved through channel interleaving, and the interleaved bit data further participates in bit mapping to complete subcarrier modulation. Therefore, to facilitate understanding of the organization of bit data in the channel interleaving stage of existing systems and its impact on subsequent modulation processing, a typical channel interleaver structure and its read / write method are described below with reference to the accompanying drawings.

[0055] Figure 1 This is a schematic diagram of the channel interleaver provided in some embodiments of the present invention. For example... Figure 1 As shown, the channel interleaver is a storage matrix with a fixed structure. Numbers 1 to 28 within the matrix represent the storage location indices of the bits. Bit data is written sequentially along the column direction indicated by the write arrows, with four bits written at a time. For example, positions 1, 2, 3, and 4 in the diagram represent a set of bits written sequentially. Subsequently, the channel interleaver reads data sequentially along the row direction indicated by the read arrows, also reading four bits at a time. For example, positions 1, 8, 15, and 22 in the diagram constitute a set of data read row by row.

[0056] It should be noted that in complex channel environments with impulse noise, narrowband interference, and frequency-selective fading, data transmission is highly susceptible to continuous burst errors during transmission. If these erroneous bits occur in a concentrated manner, they will exceed the error correction capability of the channel coding, leading to data loss. The purpose of channel interleaving is to combat such burst errors. By rearranging the order of the encoded bit sequence, the erroneous bits that were originally continuous in the time or frequency domain are dispersed to different coding blocks or time positions after deinterleaving. This transforms concentrated burst errors into discrete random errors, thereby improving the error correction success rate of subsequent channel decoding. It is one of the key technologies to ensure high-reliability transmission even in harsh channel environments.

[0057] After channel interleaving is completed, the bit mapping module fills the processed bit data onto each subcarrier for subsequent modulation and transmission. In a dual-mode system, the subcarriers typically employ a uniform and fixed modulation scheme, such as BPSK, QPSK, or 16QAM, with each subcarrier capable of carrying 1 bit, 2 bits, or 4 bits, respectively. Since the channel interleaver typically reads out 4 bits at a time, which is an integer multiple of the fixed number of bits required by the subcarrier (1 bit, 2 bits, 4 bits), the bit data stream can be processed continuously and in a matched manner, preventing subcarrier data from crossing physical block boundaries.

[0058] However, in the 64QAM modulation mode, each subcarrier can carry 6 bits. The original channel interleaver, which was fixed to read and write in 4-bit units, caused a rate mismatch with the variable bit mapping requirements of the back end.

[0059] In addition, when the total number of bits in a physical block is not an integer multiple of the number of subcarrier bits (such as 6 bits), the data required by a single subcarrier may come from two different physical blocks, which creates a "cross-physical block" data transmission problem. This not only disrupts the continuous processing flow based on physical blocks, but also causes complex scheduling problems in actual hardware implementation.

[0060] In view of this, embodiments of the present invention provide a dual-mode communication chip, which aims to solve the problems of rate mismatch and subcarrier transmission across physical blocks in high-order modulation modes. By introducing a configurable bit buffer queue, it achieves efficient adaptation between fixed-rate bit data processing and bit demand, thereby improving the throughput and reliability of the data processing link and realizing data transmission without subcarriers crossing physical blocks.

[0061] The dual-mode communication chip provided in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0062] The dual-mode communication chip provided in this embodiment of the invention includes an HPLC signal transmitter and an HPLC signal receiver. The HPLC signal transmitter and the HPLC signal receiver correspond to each other and work together in the overall communication link. The bit organization and modulation method adopted by the transmitter and the demodulation and recovery process of the receiver are logically consistent and compatible.

[0063] The HPLC signal transmitter is used to generate and transmit the modulated carrier signal from the payload data, while the HPLC signal receiver is used to demodulate the received signal and recover the data.

[0064] The HPLC signal transmitter and receiver can be electronic devices, such as power line communication terminals, concentrators, smart meters, communication module embedded devices, or communication test terminals. Alternatively, the electronic devices can be devices with computing capabilities or intelligent robots to perform the signal acquisition, processing, and synchronization steps in the embodiments of the present invention.

[0065] To facilitate the explanation of the signal processing mechanism involved in the embodiments of the present invention, the following will first use the processing process of the HPLC signal transmitter as an example.

[0066] Figure 2 This is a schematic diagram of the HPLC signal transmitting end provided in some embodiments of the present invention. For example... Figure 2 As shown, the HPLC signal transmitter 200 includes an encoding module 201, a first storage module 202, a channel interleaving module 203, a first bit buffer queue 204, and a bit mapping module 205.

[0067] The encoding module 201 is used to encode the payload data to obtain encoded payload data. Its main function is to improve the reliability of data transmission in harsh channels by adding redundant bits. For example, the encoding process includes, but is not limited to, using turbo codes, low-density parity-check codes, etc.

[0068] The first storage module 202 is used to store the encoded payload data. It plays the role of data buffering and rate matching in the signal processing chain, so that the subsequent data processing modules can obtain a continuous and stable bit data stream.

[0069] The channel interleaving module 203 is used to interleave the bit data read from the first storage module. Its main function is to disperse the consecutive erroneous bits that may be caused by channel burst errors in the time domain or frequency domain, thereby converting burst errors into random errors and improving the error correction capability of subsequent channel decoding.

[0070] The first bit buffer queue 204 is used to write bit data from the channel interleaving module sequentially with a first bit number, and read it out sequentially in the writing order with a second bit number, wherein the second bit number is greater than the first bit number.

[0071] For example, the first number of bits could be 4 bits, and the second number of bits could be 6 bits.

[0072] The bit mapping module 205 is used to map bit data from the first bit buffer queue to each subcarrier with a second number of bits.

[0073] It should be noted that writing in the order of writing means that each data unit from the channel interleaving module is stored sequentially in the physical storage space of the first bit buffer queue according to the time sequence in which it was processed. This ensures that the data generated earlier occupies a higher storage position, thus maintaining the temporal order of the data stream at the physical level. Reading in the order of writing means that when reading data, the first bit buffer queue starts from the earliest written data unit among all currently stored data and reads continuously in strict accordance with the writing order.

[0074] The first bit buffer queue with the pipelined access mechanism with strict write and read timing can effectively avoid data out of order during storage, so that the logical order of the signal can still be intact after a series of processes such as interleaving, buffering, and mapping.

[0075] Furthermore, the bit buffer queue in this embodiment of the invention is fundamentally different from the general-purpose memory used for random access and the random access memory (RAM) used for regular data access in the system. This is because general-purpose memory provides a universal storage space where addresses can be arbitrarily assigned and data can be accessed randomly and repeatedly; its access order depends entirely on complex external address management logic, making management complex. In contrast, the bit buffer queue strictly follows the timing of data writing for non-skipped sequential reading. This characteristic makes it suitable for processing continuous data streams from the channel interleaving module to the bit mapping module.

[0076] In hardware circuit implementation, bit buffer queues differ significantly from RAM and other memory types. Specifically, bit buffer queues do not directly access arbitrary specified locations via external address lines. Instead, they do not provide external read / write address lines; data position advancement is entirely achieved through automatic incrementing of internal read / write pointers, offering advantages such as a simple interface and convenient control. The hardware circuit consists of numerous independent functional modules interconnected via specific control and data signals. When there are differences in data processing speeds between interconnected modules (i.e., clock mismatch), the faster module must wait for the slower module. This waiting mechanism essentially achieves data flow synchronization and smoothing through buffering, and bit buffer queues effectively address this type of data caching requirement.

[0077] In this embodiment of the invention, the first bit buffer queue is configured to write in fixed units of a preset number of bits (e.g., 4 bits) for the channel interleaving module, and read out in units adapted to the target number of bits required by the subcarrier (e.g., 6 bits). This operating mode makes it act as both a "bit data rate adapter" and a "bit data length shaper," thereby solving the mismatch between the fixed processing cycle and bit requirements with a simple architecture and avoiding the additional overhead caused by using a complex parallel storage architecture.

[0078] Figure 3 This is a schematic diagram of the data processing flow of the HPLC signal transmitter provided in some embodiments of the present invention. For example... Figure 3 As shown, the first storage module first stores the payload data encoded by the encoding module. Then, the channel interleaving module reads the bit data from the first storage module and performs interleaving. By rearranging the bits, potential burst errors in the channel are dispersed in the time or frequency domain, transforming them into random errors, thereby improving the system's anti-interference capability and the final decoding error correction success rate. The interleaved bit data is written to the first bit buffer queue with a first number of bits, and the first bit buffer queue then reads the bit data sequentially in the order it was written, with a larger second number of bits. Finally, the bit mapping module receives the bit data from the buffer queue and maps it to the corresponding OFDM subcarrier, thus completing the conversion and transmission from the bit stream to the modulated signal.

[0079] In some implementations, the first bit buffer queue may, for example, continuously receive bit data from the upstream channel interleaving module and store it in itself in units of a fixed first number of bits (e.g., 4 bits), and then read out the bit data it has buffered in sequence in units of a larger second number of bits (e.g., 6 bits) according to the bit data writing order.

[0080] It should be noted that the maximum number of cached bits in the first bit cache queue is one of its key parameters, which directly affects the efficiency and continuity of data buffering.

[0081] In other implementations, the maximum number of cached bits in the first bit cache queue is an integer multiple of the second number of bits. The core principle is that the maximum number of cached bits in the first bit cache queue is determined based on the second number of bits required by the bit mapping module downstream of the first bit cache queue in 64QAM mode.

[0082] Taking a second bit count of 6 bits as an example, the maximum number of cached bits for the first bit cache queue can be set to, for example, 12 bits, 18 bits, or 24 bits.

[0083] By configuring the maximum capacity of the first bit buffer queue to be an integer multiple of the second bit number, the internal data processing of the first bit buffer queue can reach its optimal state when continuously outputting data in fixed bit numbers. This is because when the maximum number of cached bits in the first bit buffer queue is an integer multiple of the second bit number read, the storage space of the first bit buffer queue can be filled exactly by an integer number of complete read data blocks (each block being the second bit number). For example, a depth of 12 bits can store exactly 2 complete second bit number data blocks, and 18 bits can store 3. This means that regardless of the operating state of the first bit buffer queue, the data stored inside it is always logically composed of several complete second bit number data units, thus avoiding incomplete or cross-boundary bit data at storage boundaries. This minimizes fragmented data or invalid waiting cycles caused by a mismatch between the buffer capacity and the number of read bits, making the process of reading data from the first bit buffer queue more continuous and efficient.

[0084] In applications requiring high system throughput, the data stream provided by a single channel interleaving module at its inherent rate may be insufficient to meet the data processing rate of the transmission link. In some implementations, two parallel channel interleaving modules can be used to improve the parallel processing capability of the channel interleaving stage.

[0085] However, simply adding parallel channel interleaving modules introduces new technical problems. If two parallel channel interleaving modules still share a single-port first storage module for data reading, they will not be able to access data concurrently within the same clock cycle. They must share the storage port through time-division multiplexing or complex scheduling mechanisms, which introduces additional waiting latency.

[0086] To address the aforementioned issues, in some embodiments, when the signal transmitting end is configured with two channel interleaving modules, the first storage module is configured as a dual-port storage module.

[0087] Among them, a dual-port storage module refers to a storage module with two independent read / write ports, which are respectively connected to two channel interleaving modules.

[0088] Specifically, the bit data to be interleaved, stored in the first storage module, is divided into two parts or scheduled according to interleaving rules and allocated to two channel interleaving modules. The two channel interleaving modules are driven by the same clock signal, read their respective bit data from the first storage module in parallel through their independent ports, and perform channel interleaving processing independently and synchronously. Afterward, the outputs of the two channel interleaving modules are merged and written to the downstream first bit buffer queue at twice the aggregation rate of a single module.

[0089] In the above embodiments, by configuring a dual-channel interleaving module, the data output rate of the channel interleaving stage can be increased, providing a higher rate of bit data supply to the first bit buffer queue. In conjunction with the use of a dual-port first storage module, the two channel interleaving modules can access the bit data in the storage module in parallel without conflict or waiting, avoiding performance loss caused by storage access conflicts.

[0090] According to the dual-mode communication chip provided in the embodiments of the present invention, the payload data is encoded by the encoding module, providing reliable forward error correction protection for subsequent data transmission, making the data robust in complex channel environments. Subsequently, the first storage module, which stores the encoded payload data, can buffer and temporarily store the encoded data, providing a stable data source for subsequent data processing. Then, the bit data read from the first storage module is interleaved using the channel interleaving module, effectively dispersing burst channel errors into random errors, thereby improving the system's anti-interference and error correction capabilities. Finally, the bit data from the channel interleaving module is written to the first number of bits. The first bit buffer queue is used to read out bit data with the second number of bits, realizing rate buffering and decoupling between fixed-rate interleaving output and bit mapping requests with different rates. This allows the interleaving module to work continuously at full load, effectively avoiding data backlog and overall throughput bottlenecks caused by rate mismatch. Finally, the bit mapping module maps the bit data from the first bit buffer queue to each subcarrier, completing adaptive bit data filling. This not only maximizes the utilization of spectrum resources but also effectively solves the problem of subcarrier data crossing physical block boundaries caused by the mismatch between the number of bits required by the factor carrier and the fixed number of bits of the processing module, simplifying the data scheduling logic.

[0091] After describing the HPLC signal transmitter, the HPLC signal receiver will now be described. It should be noted that the HPLC signal receiver and the HPLC signal transmitter are functionally complementary; their purpose is to recover and reconstruct the transmitted signal to obtain data content consistent with the original bit sequence from the transmitter. Figure 4 This is a schematic diagram of the HPLC signal receiving end provided in some embodiments of the present invention. For example... Figure 4As shown, the HPLC signal receiver 400 includes a demapping module 401, a second bit buffer queue 402, a second storage module 403, a deinterleaving module 404, and a decoding module 405.

[0092] The demapping module 401 is used to demapping the bit data in each subcarrier, wherein the number of bits obtained after demapping any subcarrier is the second number of bits.

[0093] The second bit buffer queue 402 is used to write bit data from the demapping module sequentially in the second bit number and read out bit data according to the first preset rule.

[0094] The second storage module 403 is used to store the bit data read from the second bit cache queue, and reads out the bit data in the first number of bits when the stored bit data matches the bit data of the physical block. The second storage module 403 typically processes data in units of physical blocks, and triggers subsequent data processing operations after a physical block of bit data is filled.

[0095] The deinterleaving module 404 is used to deinterleave the bit data read from the second storage module with a first number of bits, and to read out the deinterleaved bit data with the first number of bits. Specifically, the deinterleaving module 404 can perform a reverse interleaving operation, i.e., a deinterleaving operation, on the bit data read from the second storage module, which is the opposite of the channel interleaving process at the transmitting end.

[0096] The second bit count is greater than the first bit count.

[0097] The decoding module 405 is used to decode the deinterleaved bit data with the first number of bits. Its goal is to use the redundancy introduced during encoding to correct bit errors in the transmission process and finally recover the original payload data of the sending end.

[0098] For example, the decoding module could be a Turbo decoder.

[0099] Figure 5 This is a schematic diagram of the HPLC signal receiving end data processing flow provided in some embodiments of the present invention. For example... Figure 5As shown, the demapping module first demodulates the modulation symbols carried by each subcarrier to recover the bit data corresponding to each subcarrier. The obtained bit data is sequentially written into the second bit buffer queue, which then reads out the bit data according to a first preset rule. Subsequently, the bit data is written into the second storage module. When the number of bits stored in the second storage module accumulates to the size of a complete physical block, subsequent operations are triggered, and the bit data is read out in units of a fixed first number of bits. Next, the deinterleaving module performs deinterleaving processing on the read bit data with the first number of bits to restore the original bit order. Finally, the decoding module also performs channel decoding on the deinterleaved data with the first number of bits, using coding redundancy to correct bit errors introduced during transmission, thereby ultimately recovering the original payload data from the HPLC signal transmitter.

[0100] Furthermore, at the HPLC signal receiver, the second bit buffer queue is primarily used to write the demapped output bit data into the second storage module. The second storage module typically processes data in physical blocks for subsequent processing by the deinterleaving and decoding modules. If writing is done in units of the second bit count, when filling the end of a physical block, there might be insufficient remaining space for a complete write unit. Forcing a write in this situation would disrupt the physical block boundaries, leading to data misalignment. Waiting to fill the next complete physical block before writing would create stored data fragmentation, introduce latency, disrupt data flow continuity, and increase storage management complexity.

[0101] Based on this, in some embodiments, the first preset rule is configured to read bit data sequentially from the second bit cache queue module in the order of writing, with the second bit number; if the remaining writable bits of the physical block are less than the second bit number, the number of bit data corresponding to the remaining writable bits is read out.

[0102] Specifically, the second storage module calculates the remaining writable bits of the current physical block in real time by recording the number of bits already written to it and comparing this number with the known total number of bits in the physical block. Taking a second bit count of 6 bits as an example, when the remaining writable bits are greater than or equal to 6 bits, the second bit buffer queue performs a 6-bit read operation and writes this 6-bit data to the second storage module. When the remaining writable bits are less than 6 bits (e.g., only 4 bits or 2 bits remain), the second bit buffer queue performs a read operation matching the remaining bit count, thus filling the current physical block completely.

[0103] The second storage module, as the key link between the second bit cache queue and the deinterleaving module, has a crucial basic access width for its storage units, i.e., the storage row width. If the first or second number of bits is not aligned, it can easily lead to inefficient access and logical complexity during actual read / write operations. Specifically, when writing bits to the second storage module in units of the second number of bits, the bits may cross multiple storage row boundaries; when the subsequent deinterleaving module reads bits in units of the first number of bits, it may need to perform cross-row accesses to piece together a complete read unit. This misaligned access pattern not only increases the number of cycles per access operation and reduces effective bandwidth, but also forces the second storage module to design complex address generation and data masking logic, significantly increasing hardware implementation difficulty and timing risks.

[0104] Therefore, in some implementations, the storage row width of the second storage module is configured as an integer multiple of the least common multiple of the first number of bits and the second number of bits.

[0105] For example, when the first number of bits is 4 bits and the second number of bits is 6 bits, the least common multiple (LCM) of 4 and 6 is 12. Therefore, the storage row width of the second storage module should be an integer multiple of 12, such as 12, 24, or 36. This is because when the storage row width of the second storage module is an integer multiple of the LCM of the first and second number of bits, whether writing continuously with the second number of bits (6 bits) or reading continuously with the first number of bits (4 bits), the boundary of the data block will inevitably align with the boundary of the storage row. This ensures that writing two 6-bit units completely fills one storage row (12 bits) of the second storage module, and reading three 4-bit units also completely reads one storage row of the second storage module.

[0106] By configuring the storage row width of the second storage module to be an integer multiple of the least common multiple of the first number of bits and the second number of bits, cross-row access can be effectively avoided, so that each read and write operation of bit data can be completed within a single storage access cycle, and there is no need to waste bandwidth to fill unused parts. The storage control logic is simple, which greatly simplifies the control logic of the second storage module.

[0107] In the above embodiments, by writing at the boundaries of physical blocks according to the remaining writable bits, each physical block can be completely and continuously filled, avoiding bit data fragmentation or storage across physical blocks. This provides a correct and aligned data foundation for subsequent deinterleaving and decoding operations performed on a physical block basis, avoiding data fragmentation or unused space caused by mismatched storage block boundaries. This allows the data writing process from the second bit cache queue to the second storage module to proceed smoothly and uninterruptedly, without waiting or complex reconfiguration even at physical block boundaries. This effectively ensures the smoothness of data processing at the HPLC signal receiver and maintains high throughput and low latency system performance.

[0108] For application scenarios with stringent requirements for system real-time performance or data processing throughput, in order to overcome the deinterleaving bottleneck that may exist in a single path, we can start from the perspective of adding a deinterleaving module. At the same time, in order to avoid the waiting delay caused by two parallel deinterleaving modules sharing a single-port second storage module, the second storage module is configured as a dual-port storage module to improve the system's data processing speed.

[0109] Figure 6 This is a schematic diagram of the HPLC signal receiving end provided in other embodiments of the present invention. For example... Figure 6 As shown, the HPLC signal receiver 400 includes a demapping module 401, a second bit buffer queue 402, two parallel deinterleaving modules 404, a second storage module 403, and a decoding module 405.

[0110] The demapping module 401 and the decoding module 405 have been described in the foregoing embodiments and will not be repeated here.

[0111] The second bit buffer queue 402 is used to write bit data from the demapping module sequentially in the second bit number and read out bit data according to the second preset rule.

[0112] Two parallel deinterleaving modules 404, wherein either deinterleaving module is used to deinterleave the bit data read from the second bit buffer queue with a first number of bits, and read out the deinterleaved bit data with the first number of bits.

[0113] The second storage module 403 is used to store bit data read from two parallel deinterleaving modules and read out bit data in the first number of bits. In some embodiments, the second storage module is a dual-port storage module, one of the dual ports is connected to one of the deinterleaving modules, and the other of the dual ports is connected to the other of the deinterleaving modules.

[0114] Figure 7 This is a schematic diagram of the HPLC signal receiving end data processing flow provided in other embodiments of the present invention. For example... Figure 7 As shown, firstly, the demapping module demodulates the modulation symbols carried by each subcarrier, recovering the bit data corresponding to each subcarrier. The obtained bit data is written sequentially into the second bit buffer queue. Next, the second bit buffer queue reads out the buffered bit data and allocates it according to the second preset rule processed by the parallel deinterleaving module. Subsequently, the allocated bit data is sent in parallel to two parallel deinterleaving modules; each deinterleaving module performs deinterleaving processing on its received bit data at a fixed first bit count as the processing cycle, restoring the original order of that part of the bits and outputting it at the first bit count. The second storage module stores the bit data output by the two parallel deinterleaving modules. After this, the storage module reads out the aggregated bit data in units of the first bit count. Finally, the decoding module, also at the first bit count as the cycle, performs channel decoding on the deinterleaved bit data read from the second storage module, thereby ultimately and accurately recovering the original payload data from the transmitting end.

[0115] The dual-port storage module provides physically independent write channels for the two deinterleaving modules, allowing them to write the processed data to the second storage module within the same clock cycle after processing. This avoids the port contention and serialization latency present when using single-port storage, effectively translating the theoretical bandwidth increase from parallel deinterleaving into increased throughput. It also simplifies control logic and timing complexity, improving the reliability and predictability of the chip design.

[0116] It should be noted that in the data processing flow of the HPLC signal receiver in the single deinterleaving module, the data processing order is: demapping module, second bit buffer queue, second storage module, deinterleaving module, and decoding module. The second storage module is placed before the deinterleaving module, and its main function is to first buffer and align the variable-length bit data, so that it can be read by the deinterleaving module in the form of physical blocks.

[0117] In the data processing flow of the HPLC signal receiver with two parallel deinterleaving modules, the data processing order is: demapping module, second bit buffer queue, two parallel deinterleaving modules, second storage module, and decoding module. This is because, to efficiently achieve parallel operation of the two deinterleaving modules, the bit data needs to be allocated for processing first. If the bit data is first stored in the storage module and then read from it in parallel by the two deinterleaving modules, it will cause complex shared memory access conflicts and synchronization problems. Therefore, the second bit buffer queue schedules and allocates the bit data to the parallel deinterleaving modules in real time. After the bit data is processed in parallel, the second storage module merges the parallel results in an orderly manner. This adjustment in the bit data processing order is key to supporting the efficiency of parallel deinterleaving processing and can effectively avoid the complex logic in traditional dual-port storage parallel architectures.

[0118] In HPLC signal receivers employing two parallel deinterleaving modules, improper allocation rules, such as simple alternating allocation without considering the integrity of the physical block, can lead to unbalanced loads between the two deinterleaving modules or disrupt the sequential relationship of bit data after interleaving encoding, thus affecting the correctness of subsequent merging and decoding. Especially when processing the end of a physical block, the amount of data remaining to be allocated may be less than that required for a single conventional parallel allocation. If a fixed number of bits is still allocated in this case, it will not only cause hardware resource idleness but may also disrupt the data order due to incomplete data or improper allocation, even preventing the physical block from ending correctly, increasing the system's scheduling complexity and error risk.

[0119] Based on this, in some embodiments, the second preset rule is configured to read bit data from the second bit cache queue with a third number of bits; wherein the third number of bits is twice the first number of bits, so that two parallel deinterleaving modules respectively perform deinterleaving processing on the bit data read from the second bit cache queue with the first number of bits; when the remaining writable bits of the physical block are less than the third number of bits, a number of bits corresponding to the remaining writable bits are read out, and according to the correspondence between the remaining writable bits and the first number of bits, the number of bits corresponding to the remaining writable bits are allocated to a deinterleaving module for deinterleaving processing.

[0120] The third bit count refers to the number of bits prepared for parallel allocation after a single read operation from the second bit buffer queue, and the third bit count is twice the first bit count.

[0121] For example, when the first number of bits is 4 bits, the third number of bits is 8 bits, thereby enabling two parallel deinterleaving modules to deinterleave the bit data read from the second bit buffer queue with 4 bits each.

[0122] Specifically, the HPLC signal receiver calculates the remaining writable bits of the current physical block in real time. When the remaining writable bits of the physical block are greater than or equal to the third number of bits, the third number of bits of data is read from the second bit buffer queue. Subsequently, the third number of bits of data is split into two data packets of the first number of bits, and sent to two parallel deinterleaving modules respectively.

[0123] When the remaining writable bits of a physical block are less than the third number of bits, it means that the remaining writable bits of the current physical block are insufficient for the two parallel deinterleaving modules to perform deinterleaving processing with the first number of bits.

[0124] In some implementations, when the remaining writable bits of a physical block are less than the third number of bits, and when the remaining writable bits of a physical block are less than the first number of bits, the remaining writable bits are read out all at once and distributed to either of the two parallel deinterleaving modules for deinterleaving processing.

[0125] For example, when the third bit is 8 bits and the first bit is 4 bits, the remaining writable bits of the physical block are 2 bits. Then, the 2 bits of data are read out and allocated to either of the two parallel deinterleaving modules for deinterleaving processing.

[0126] In other implementations, when the remaining writable bits of a physical block are less than the third number of bits, and when the remaining writable bits of a physical block are greater than the first number of bits, the remaining writable bits are read out all at once. These bits are then allocated into the first number of bits and the number of bits representing the difference between the remaining writable bits and the first number of bits. These bits are then distributed to two parallel deinterleaving modules. One of the two parallel deinterleaving modules performs the deinterleaving of the first number of bits, while the other deinterleaving module performs the deinterleaving of the number of bits representing the difference between the remaining writable bits and the first number of bits.

[0127] For example, when the third bit is 8 bits and the first bit is 4 bits, the remaining writable bits of the physical block are 6 bits. Then, the 6 bits of bit data are read out and allocated into 4 bits and 2 bits. One of the two parallel deinterleaving modules performs the 4-bit deinterleaving process, and the other deinterleaving module performs the 2-bit deinterleaving process.

[0128] In some other implementations, when the remaining writable bits of a physical block are less than the third number of bits, and when the remaining writable bits of a physical block are greater than the first number of bits, the remaining writable bits are read out all at once. If the remaining writable bits are even, the remaining writable bits are divided into two groups of bits and assigned to two parallel deinterleaving modules for deinterleaving processing.

[0129] For example, when the third bit is 8 bits and the first bit is 4 bits, the remaining writable bits of the physical block are 6 bits. Then, the 6 bits of bit data are read out and divided into two groups of 3 bits each. The two parallel deinterleaving modules then deinterleave the data in 3 bits each.

[0130] In the above embodiments, by reading and evenly distributing data in units of twice the first number of bits, the hardware processing capabilities of the two deinterleaving modules are maximized, effectively improving the data processing throughput and the system's deinterleaving performance under high load. Simultaneously, by introducing an adaptive physical block boundary handling mechanism, each physical block can be processed completely and logically correctly. Through precise allocation based on the remaining bits, problems such as data loss, out-of-order data, or physical blocks failing to terminate properly are effectively avoided.

[0131] In an architecture employing two parallel deinterleaving modules, the data output from both modules ultimately needs to be aggregated in a second storage module for the decoding module to read. If the output data from the two modules are written to different rows or non-contiguous address spaces within the storage module, when the subsequent decoding module needs to read a complete, contiguous logical data block (e.g., a physical block), it may be forced to perform multiple discrete storage row accesses to piece the data together. Therefore, in some embodiments, the second storage module is configured to write the bit data read by the two parallel deinterleaving modules into the same storage row within the second storage module.

[0132] Specifically, when the two deinterleaving modules complete the deinterleaving process and are ready to output bit data, the second storage module coordinates the two deinterleaving modules to write the bit data output by each of the two deinterleaving modules, in units of the first number of bits, into different consecutive fields of the same physical storage row within the same or adjacent clock cycles.

[0133] In the above embodiments, by writing the parallel deinterleaved bit data into the same storage row, the decoding module can obtain the maximum amount of continuous valid data with the fewest storage accesses during subsequent readings, effectively reducing data reading latency and dynamic power consumption, and improving system throughput.

[0134] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0135] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of the present invention is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0136] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the related technology, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0137] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

[0138] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0139] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A dual-mode communication chip, characterized in that, It includes an HPLC signal transmitter and an HPLC signal receiver; the HPLC signal transmitter is configured as follows: The encoding module is used to encode the load data to obtain the encoded load data; The first storage module is used to store the encoded payload data; The channel interleaving module is used to interleave the bit data read from the first storage module; The first bit buffer queue is used to write bit data from the channel interleaving module sequentially with a first bit number and read it out sequentially in the writing order with a second bit number; the second bit number is adapted to the target bit number required by the subcarrier, and the second bit number is greater than the first bit number; wherein, the maximum buffer bit number of the first bit buffer queue is an integer multiple of the second bit number, so that the storage space of the first bit buffer queue can store bit data of an integer number of complete data blocks; A bit mapping module is used to map bit data from the first bit buffer queue to each subcarrier with a second number of bits; The HPLC signal receiver is configured as follows: The demapping module is used to demapping the bit data in each subcarrier, wherein the number of bits obtained after demapping any subcarrier is the second number of bits. The second bit cache queue is used to write bit data from the demapping module sequentially with the second bit number, and read out bit data according to the first preset rule; the first preset rule is configured to read bit data sequentially from the second bit cache queue module in the writing order with the second bit number; if the remaining writable bits of the physical block are less than the second bit number, read out a number of bit data corresponding to the remaining writable bits. The second storage module is used to store the bit data read from the second bit cache queue, and read out the bit data with a first number of bits when the stored bit data matches the bit data of the physical block; The deinterleaving module is used to deinterleave the bit data read from the second storage module with a first number of bits, and read the deinterleaved bit data with a first number of bits. The decoding module is used to decode the deinterleaved bit data with a first number of bits.

2. The dual-mode communication chip according to claim 1, characterized in that, The signal transmitting end is configured with two channel interleaving modules, and the first storage module is a dual-port storage module.

3. The dual-mode communication chip according to claim 1, characterized in that, The storage row width of the second storage module is configured to be an integer multiple of the least common multiple of the first number of bits and the second number of bits.

4. The dual-mode communication chip according to claim 1, characterized in that, The HPLC signal receiver is configured as follows: The demapping module is used to perform demapping processing on bit data from each subcarrier, wherein the number of bits obtained after demapping any subcarrier is the second number of bits; The second bit buffer queue is used to write bit data from the demapping module sequentially with the second number of bits, and to read out bit data according to the second preset rule; Two parallel deinterleaving modules, wherein each deinterleaving module is used to deinterleave the bit data read from the second bit buffer queue with a first number of bits, and read out the deinterleaved bit data with the first number of bits; The second storage module is used to store the bit data read from the two parallel deinterleaving modules and read out the bit data in the first number of bits. The decoding module is used to decode the bit data read from the second storage module using the first bit data.

5. The dual-mode communication chip according to claim 4, characterized in that, The second preset rule is configured as follows: Bit data is read sequentially from the second bit buffer queue in the order of writing, with a third number of bits; wherein the third number of bits is twice the first number of bits, so that two parallel deinterleaving modules respectively perform deinterleaving processing on the bit data read from the second bit buffer queue with the first number of bits; If the number of remaining writable bits in a physical block is less than the third number of bits, read out the number of bits corresponding to the number of remaining writable bits, and allocate the number of bits corresponding to the number of remaining writable bits to a deinterleaving module for deinterleaving processing according to the correspondence between the number of remaining writable bits and the first number of bits.

6. The dual-mode communication chip according to claim 4 or 5, characterized in that, The second storage module includes multiple storage rows, and the second storage module is configured to write the bit data read by the two parallel deinterleaving modules into the same storage row of the second storage module.

7. The dual-mode communication chip according to claim 6, characterized in that, The second storage module is a dual-port storage module.

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