A data processing method and device for a front-end electronics module

Abstract

The application discloses a data processing method and device for a front-end electronics module, which comprises the following steps: collecting waveform data from a detector according to channels, merging data of 8 adjacent channels into a group, and storing the group into a first-level FIFO memory; compressing the collected data, compressing the data according to the characteristics of pulse signals, and storing compressed data of 64 adjacent channels into a second-level FIFO memory; dividing a DDR into 16 independent caches, and performing partition cache management; dynamically transferring data between different cache regions according to the storage conditions of the 16 cache regions of the DDR; transferring data between multiple front-end electronics modules through a GT port according to the storage conditions of the multiple front-end electronics modules; and uploading data to a back-end data acquisition system through a high-speed link. The method reduces the waveform data rate and reduces the transmission pressure through segmented compression, layered caching, intra-module balancing and inter-module balancing.

Description

Technical Field

[0001] This invention relates to the field of data storage and high-speed data transmission technology, and in particular to a data processing method and apparatus for front-end electronics modules. Background Technology

[0002] In large-scale physics experiments, the Ring Imaging Cherenkov (RICH) detector is a crucial option for particle identification. For example, the STCF RICH PID has as many as 690,000 readout channels. However, typically, the number of Cherenkov photons generated per physical event is less than 10. This means that for a given physical event, the number of channels hit by the prototype RICH is approximately 1 / 100 of the total readout channels. If a full readout approach is adopted, the massive amount of redundant data, storage, and analysis will pose significant challenges to the electronic systems, both for data transmission and storage. Without intervention, the maximum readout data rate could reach several Tbps, which would be a huge challenge for the data acquisition system.

[0003] In such cases, zero-compression is typically used to reduce the pressure on backend data processing. The principle of zero-compression is that, given a threshold Vth, signals exceeding the threshold are read out, while signals below the threshold are not. This discards a large amount of invalid data while minimizing the loss of valid data, which is acceptable for most data acquisition systems. However, for engineering applications, such as the LHCb SciFiTracker upgrade project, a scintillation fiber tracker consisting of approximately 590,000 SiPM channels would generate approximately 47.2 Tb / s of raw data without zero-compression. This is difficult to transmit and process directly due to the power consumption, structure, and link bandwidth constraints of the experimental system. Therefore, this system introduces a clustering-based zero-compression algorithm in the front-end electronics FPGA to transmit only the location information of valid hit clusters. Based on detector physical simulation and test beam data evaluation, this method can control the output data rate to within 8 Tb / s, achieving more than 6 times data compression. However, the readout data rate after zero data compression is still as high as several Tbps, which still puts great pressure on data transmission and data storage. Therefore, further research is needed on waveform data compression and data caching technologies.

[0004] In view of this, the present invention is hereby proposed. Summary of the Invention

[0005] The purpose of this invention is to provide a data processing method and apparatus for front-end electronics modules to solve the aforementioned technical problems in the prior art. The method of this invention reduces the waveform data rate and decreases the transmission pressure from front-end electronics to back-end electronics through segmented compression, hierarchical caching, intra-module equalization, and inter-module equalization, while ensuring that the amplitude and time measurement accuracy after compression meets the requirements of physical detection.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] A data processing method for a front-end electronics module, the method comprising:

[0008] Step 1: Acquire waveform data from the detector by channel, merge the data from 8 adjacent channels into a group, and store it in the first-level first-in-first-out FIFO memory for initial buffering;

[0009] Step 2: Compress the acquired data by segmenting it according to the characteristics of the pulse signal and then loading the compressed data of adjacent 64 channels into the second-level FIFO memory.

[0010] Step 3: Divide the Double Data Rate Synchronous Dynamic Random Access Memory (DDR memory) into 16 independent cache areas, and store the data from the 16 Level 2 FIFO memories into the corresponding cache areas for partitioned cache management.

[0011] Step 4: Based on the storage status of the 16 cache regions of the DDR memory, dynamically transfer data between different cache regions to perform the first level of data balancing;

[0012] Step 5: Based on the storage situation between different front-end electronics modules, data is transferred between multiple front-end electronics modules through a high-speed serial transceiver GT to perform a second level of data balancing;

[0013] Step 6: Perform unified encapsulation on the balanced data and upload it to the backend data acquisition system via a high-speed link.

[0014] A data processing apparatus for a front-end electronics module, the apparatus comprising:

[0015] The multi-channel waveform acquisition and grouping buffer unit is used to acquire waveform data from the detector by channel, merge the data of 8 adjacent channels into a group, and store it in the first-level FIFO memory for initial buffering.

[0016] The segmented compression unit is used to compress the acquired data. It performs compression processing on segments according to the characteristics of the pulse signal and loads the compressed data of adjacent 64 channels into the second-level FIFO memory.

[0017] The partitioned cache management unit is used to divide the DDR memory into 16 independent caches and store the data of the 16 secondary FIFO memory into the corresponding cache areas for partitioned cache management.

[0018] The first-level balancing unit is used to dynamically transfer data between different cache regions based on the storage status of the 16 cache regions of the DDR memory, thus performing the first level of data balancing.

[0019] The second-level equalization unit is used to transfer data between multiple front-end electronics modules through a high-speed serial transceiver GT according to the storage situation between different front-end electronics modules, and to perform second-level data equalization.

[0020] The data upload unit is used to perform unified encapsulation on the balanced data and upload it to the backend data acquisition system via a high-speed link.

[0021] Compared with existing technologies, the method and apparatus provided by this invention can reduce waveform data rate, reduce transmission pressure from front-end electronics to back-end electronics, and ensure that the amplitude and time measurement accuracy after compression meets the requirements of physical detection; achieve dynamic balancing among multiple storage units on a single board to avoid local buffer overflow; and achieve global data balancing among multiple modules to improve overall storage and bandwidth utilization. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A flowchart illustrating a data processing method for a front-end electronics module is provided for embodiments of the present invention.

[0024] Figure 2 This is a comparison diagram of data before and after compression in an embodiment of the present invention;

[0025] Figure 3 This is a simulation diagram of the data compression effect in an embodiment of the present invention;

[0026] Figure 4 This is a simulation diagram illustrating the data balancing effect of an embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them, and do not constitute a limitation on the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0028] First, the following explanations are provided for the terms that may be used in this article:

[0029] The term "and / or" means that either or both can be achieved simultaneously. For example, X and / or Y means that it includes both "X" or "Y" as well as the three cases of "X and Y".

[0030] The terms "comprising," "including," "containing," "having," or other similar semantic descriptions should be interpreted as non-exclusive inclusion. For example, including a technical feature element (such as raw material, component, ingredient, carrier, dosage form, material, size, part, component, mechanism, device, step, process, method, reaction conditions, processing conditions, parameter, algorithm, signal, data, product or article of manufacture, etc.) should be interpreted as including not only the expressly listed technical feature element, but also other technical feature elements that are not expressly listed and are well-known in the art.

[0031] The term "composed of" excludes any technical features not expressly listed. When used in a claim, it closes the claim to exclude all technical features other than those expressly listed, except for associated conventional impurities. If the term appears only in a clause of a claim, it limits the claim to the elements expressly listed in that clause; elements recited in other clauses are not excluded from the overall claim.

[0032] The technical solution provided by this invention will be described in detail below. Contents not described in detail in the embodiments of this invention are prior art known to those skilled in the art. Where specific conditions are not specified in the embodiments of this invention, they shall be performed according to conventional conditions in the art or conditions recommended by the manufacturer. Reagents or instruments used in the embodiments of this invention whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0033] like Figure 1 The diagram shown is a flowchart illustrating a data processing method for a front-end electronics module provided by an embodiment of the present invention. The method includes:

[0034] Step 1: Acquire waveform data from the detector by channel, merge the data from 8 adjacent channels into a group, and store it in the first-level first-in, first-out (FIFO) memory for initial buffering;

[0035] Step 2: Compress the acquired data by segmenting it according to the characteristics of the pulse signal and then loading the compressed data of adjacent 64 channels into the second-level FIFO memory.

[0036] In this step, the cached waveform data undergoes preliminary processing. Since the detector readout is usually concerned with its charge and time information and also has certain accuracy requirements, lossy compression of the data can be performed to reduce the pressure of data upload while ensuring accuracy requirements.

[0037] The charge information of pulse signals is concentrated near the waveform peak, and the time information is concentrated near the threshold. The remaining information is relatively less important. Therefore, lossy compression can be used in the less important waveform parts, while lossless compression can be used in the high-fidelity areas to reduce the data volume. Based on the proportion of pulse signal amplitude in the 0-1 range, the amplitude range is divided into key and non-key regions. Lossless compression is performed on the key regions, and lossy compression is performed on the non-key regions. Sampling points with a compression result of 0 are discarded. Specifically:

[0038] If the amplitude of the pulse signal is Based on amplitude values ​​of 0.2, 0.4, and 0.8, it is divided into three amplitude ranges: low, medium, and high. , , ;

[0039] Let the value of the sampling point of the pulse signal be... The compressed sampling point value Based on the amplitude range where the sampling point is located, the correspondence before and after compression is as follows:

[0040] ;

[0041] Each waveform sampling point has 10 significant bits. For less important sampling points, i.e. and Lossy compression is performed; at the same time, sampling points with a value of 0 after compression are discarded during transmission, thereby reducing the pressure of data transmission.

[0042] like Figure 2 The image shown is a comparison chart of data compression before and after in an embodiment of the present invention. Figure 2 The dotted solid line represents the waveform before compression, and the long solid line represents the waveform after compression.

[0043] like Figure 3The figure shown is a simulation diagram of the data compression effect of an embodiment of the present invention. The compression rate of most pulse signals can reach below 0.5, the root mean square value of amplitude measurement is 0.06%, and the root mean square value of time jitter measurement is 36.5 ps, which can meet the compression rate and error requirements.

[0044] Step 3: Divide the Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), or DDR memory for short, into 16 independent cache areas, and store the data from the 16 Level 2 FIFO memories into the corresponding cache areas for partitioned cache management.

[0045] In this step, the DDR memory is divided into 16 cache regions of equal capacity, corresponding to the output channels of 16 secondary FIFO memories of 16 application-specific integrated circuits (ASICs).

[0046] The output data of the second-level FIFO memory is written into the corresponding cache areas of the 16 DDR memory.

[0047] Here, since each ASIC in the design contains 64 channels, the DDR memory is divided into 16 equal cache blocks corresponding one-to-one with the ASIC.

[0048] Step 4: Based on the storage status of the 16 cache regions of the DDR memory, dynamically transfer data between different cache regions to perform the first level of data balancing;

[0049] In this step, the 16 independent cache regions are viewed as a loop connected end to end, and data can be transferred between two adjacent storage units.

[0050] When the capacity of a storage cell within the ring is greater than the capacity of two adjacent storage cells, data is dynamically transferred to the adjacent storage cells to maintain an average capacity utilization across all storage cells and achieve local balance of storage space within the single board.

[0051] Step 5: Based on the storage situation between different front-end electronics modules, data is transferred between multiple front-end electronics modules through a high-speed serial transceiver (GT) to perform a second level of data balancing;

[0052] In this step, each front-end electronics module has 4 GT interfaces and can connect to up to 4 other front-end electronics modules in the vicinity.

[0053] If the transmission loss of adjacent front-end electronics modules is k, the storage utilization rate of the front-end electronics module itself is m, and the weighted storage rate of adjacent front-end electronics modules is... Then, the weighted storage rate of the front-end electronics module itself is calculated as follows:

[0054] ;

[0055] When the weighted storage rate of a front-end electronics module minus the weighted storage rate of a surrounding front-end electronics module is greater than the set migration threshold w, data is transmitted to that front-end electronics module, thereby achieving global balanced scheduling in the entire electronics array.

[0056] like Figure 4 The diagram shown is a simulation illustration of the data balancing effect in an embodiment of the present invention. A 4×4 storage array is selected, and the transmission loss is... migration threshold Combined with the first-level data balancing in step 4, global balancing scheduling is completed within 4 iteration cycles, ensuring efficient utilization of storage space and bandwidth resources.

[0057] Step 6: Perform unified encapsulation on the balanced data and upload it to the backend data acquisition system via a high-speed link.

[0058] Based on the above method, embodiments of the present invention also provide a data processing apparatus for a front-end electronics module, the apparatus comprising:

[0059] The multi-channel waveform acquisition and grouping buffer unit is used to acquire waveform data from the detector by channel, merge the data of 8 adjacent channels into a group, and store it in the first-level FIFO memory for initial buffering.

[0060] The segmented compression unit is used to compress the acquired data. It performs compression processing on segments according to the characteristics of the pulse signal and loads the compressed data of adjacent 64 channels into the second-level FIFO memory.

[0061] The partitioned cache management unit is used to divide the DDR memory into 16 independent caches and store the data of the 16 secondary FIFO memory into the corresponding cache areas for partitioned cache management.

[0062] The first-level balancing unit is used to dynamically transfer data between different cache regions based on the storage status of the 16 cache regions of the DDR memory, thus performing the first level of data balancing.

[0063] The second-level balancing unit is used to transfer data between multiple front-end electronics modules through the GT port according to the storage situation between different front-end electronics modules, and to perform second-level data balancing.

[0064] The data upload unit is used to perform unified encapsulation on the balanced data and upload it to the backend data acquisition system via a high-speed link.

[0065] The specific implementation process of each unit in the above device is described in the above method embodiments.

[0066] This invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program in the method described above.

[0067] This invention also provides a computer storage medium storing a plurality of instructions adapted for loading and executing the method by a processor.

[0068] In summary, compared with the prior art, the data processing method and apparatus described in this embodiment of the invention have significant advantages in terms of system integration, bandwidth utilization efficiency, and compression flexibility.

[0069] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to those skilled in the art.

[0070] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of the present invention and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.

Claims

1. A data processing method for a front-end electronics module, characterized in that, The method includes: Step 1: Acquire waveform data from the detector by channel, merge the data from 8 adjacent channels into a group, and store it in the first-level first-in-first-out FIFO memory for initial buffering; Step 2: Compress the acquired data by segmenting it according to the characteristics of the pulse signal and then loading the compressed data of adjacent 64 channels into the second-level FIFO memory. Step 3: Divide the Double Data Rate Synchronous Dynamic Random Access Memory (DDR memory) into 16 independent cache areas, and store the data from the 16 Level 2 FIFO memories into the corresponding cache areas for partitioned cache management. Step 4: Based on the storage status of the 16 cache regions of the DDR memory, dynamically transfer data between different cache regions to perform the first level of data balancing; Step 5: Based on the storage situation between different front-end electronics modules, data is transferred between multiple front-end electronics modules through a high-speed serial transceiver GT to perform a second level of data balancing; Step 6: Perform unified encapsulation on the balanced data and upload it to the backend data acquisition system via a high-speed link.

2. The data processing method for a front-end electronics module according to claim 1, characterized in that, In step 2, the charge information of the pulse signal is focused near the peak of the waveform, and the time information is focused near the threshold. Based on the proportion of the pulse signal amplitude in the range of 0 to 1, the amplitude range is divided into key areas and non-key areas. The key areas are compressed without loss, and the non-key areas are compressed with loss. Sampling points with a compression result of 0 are discarded.

3. The data processing method for a front-end electronics module according to claim 2, characterized in that, In step 2, if the amplitude value of the pulse signal is Based on amplitude values ​​of 0.2, 0.4, and 0.8 times, the amplitude is divided into three ranges: low, medium, and high. , , ; Let the value of the sampling point of the pulse signal be... The compressed sampling point value Based on the amplitude range where the sampling point is located, the correspondence before and after compression is as follows: ； Each waveform sampling point has 10 significant bits. For less important sampling points, i.e. and Lossy compression is performed; at the same time, sampling points with a value of 0 after compression are discarded during transmission.

4. The data processing method for a front-end electronics module according to claim 1, characterized in that, In step 3, the DDR memory is divided into 16 equal-capacity cache regions, corresponding to the output channels of the 16-channel second-level FIFO memory of 16 application-specific integrated circuits (ASICs). The output data of the second-level FIFO memory is written into the corresponding cache areas of the 16 DDR memory.

5. The data processing method for a front-end electronics module according to claim 4, characterized in that, In step 4, the 16 independent cache regions are considered as a loop connected end to end, and data can be transferred between two adjacent storage units; When the capacity of a storage cell within the ring is greater than the capacity of two adjacent storage cells, data is dynamically transferred to the adjacent storage cells to maintain an average capacity utilization across all storage cells and achieve local balance of storage space within the single board.

6. The data processing method for a front-end electronics module according to claim 1, characterized in that, In step 5, each front-end electronics module has 4 GT interfaces and can connect to up to 4 other front-end electronics modules in the vicinity; If the transmission loss of adjacent front-end electronics modules is k, the storage utilization rate of the front-end electronics module itself is m, and the weighted storage rate of adjacent front-end electronics modules is... Then, the weighted storage rate of the front-end electronics module itself is calculated as follows: ； When the weighted storage rate of a front-end electronics module minus the weighted storage rate of a surrounding front-end electronics module is greater than the set migration threshold w, data is transmitted to that front-end electronics module, thereby achieving global balanced scheduling in the entire electronics array.

7. A data processing device for a front-end electronics module, characterized in that, The device includes: The multi-channel waveform acquisition and grouping buffer unit is used to acquire waveform data from the detector by channel, merge the data of 8 adjacent channels into a group, and store it in the first-level FIFO memory for initial buffering. The segmented compression unit is used to compress the acquired data. It performs compression processing on segments according to the characteristics of the pulse signal and loads the compressed data of adjacent 64 channels into the second-level FIFO memory. The partitioned cache management unit is used to divide the DDR memory into 16 independent caches and store the data of the 16 secondary FIFO memory into the corresponding cache areas for partitioned cache management. The first-level balancing unit is used to dynamically transfer data between different cache regions based on the storage status of the 16 cache regions of the DDR memory, thus performing the first level of data balancing. The second-level equalization unit is used to transfer data between multiple front-end electronics modules through a high-speed serial transceiver GT according to the storage situation between different front-end electronics modules, and to perform second-level data equalization. The data upload unit is used to perform unified encapsulation on the balanced data and upload it to the backend data acquisition system via a high-speed link.

8. The data processing apparatus for a front-end electronics module according to claim 7, characterized in that, In the first-level balancing unit, the 16 independent cache areas are treated as a ring connected end to end, and data can be transferred between two adjacent storage units. When the capacity of a storage unit in the ring is more than the capacity of the two adjacent storage units, data is dynamically transferred to the adjacent storage units to keep the capacity of each storage unit evenly used and achieve local balancing of storage space within the board.

9. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 6.

10. A computer storage medium, characterized in that, The computer storage medium stores a plurality of instructions adapted for loading by a processor and executing the method of any one of claims 1 to 6.

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