Single signal line protocol method

Abstract

A single signal line protocol method includes inputting (X1 + M1) pulse waves via a single signal line bus according to a pulse wave definition table, where M1 is less than or equal to 2A1. According to the pulse wave definition table, after the (X1 + M1) pulse waves are input, (Y1 + N1) pulse waves are input through the single signal line bus, N1 is smaller than or equal to 2B1, the (M1 + N1) pulse waves are used for setting a first output voltage, and based on A1 and B1, the first output voltage has at most (2A1 * 2B1) voltage levels. By splitting the first output voltage into two groups, a write-in time of a voltage setting instruction can be reduced.

Description

Technical Field

[0001] This invention relates to a single signal line protocol method, and more particularly to a single signal line protocol method that can reduce the write time of a parameter setting instruction. Background Technology

[0002] Unlike other communication protocols such as I2C (Inter-Integrated Circuit), PCI (Peripheral Component Interconnect), ISA (Industry Standard Architect), or LPC (Low Pin Count), the Single Signal Line (SLINE) protocol transmits parameter data or control signals through a single signal line / bus. Its advantage is a significant reduction in the number of pins, but its disadvantage is slower transmission speed. Generally, SLINE can be used to modulate an output voltage. For example, when each voltage level is 25 millivolts and there are a total of 512 levels, using traditional SLINE might require approximately 512 pulse cycles to write an output voltage once. When the system needs to modulate the output voltage multiple times, the total write time can become excessively long.

[0003] Therefore, a new single-signal-line protocol technology is needed to reduce the write time of a parameter setting instruction. Summary of the Invention

[0004] In view of the aforementioned problems, the object of the present invention is to provide a single-signal-line protocol method that can reduce the write time of a parameter setting instruction.

[0005] This invention provides a single signal line protocol method. When this single signal line protocol method is applied to a voltage setting command, the single signal line protocol method may include: inputting (X1+M1) pulses via a single signal line bus SWB according to a pulse definition table 200, wherein X1 is greater than or equal to 0, M1 is greater than or equal to 1, and M1 is less than or equal to 2. A1 A1 is greater than or equal to 1. According to the pulse definition table 200, after inputting (X1+M1) pulses, (Y1+N1) pulses are input via the single signal line bus SWB, where Y1 is greater than or equal to 0, N1 is greater than or equal to 1, and N1 is less than or equal to 2. B1 B1 is greater than or equal to 1, and the (M1+N1) pulses are used to set a first output voltage. Based on A1 and B1, the first output voltage has at most (2 A1 ×2 B1( ) voltage levels. By splitting the first output voltage into two groups, the write time of a voltage setting command can be reduced. In addition, a single-line signal SWS can be transmitted via the single signal line bus SWB to a power supply circuit that provides the first output voltage.

[0006] The first output voltage will not be written after (X1+M1) pulses are input. The first output voltage will only be written after (Y1+N1) pulses are input. This prevents the first output voltage from being temporarily changed to an incorrect voltage.

[0007] The single-line signal SWS is applied to the single signal line bus SWB. When the single-line signal SWS changes from a low level to a high level, if the duration of the high level is greater than an on time, the single signal line bus SWB is enabled. When the single-line signal SWS changes from a high level to a low level, if the duration of the low level is greater than an off time, the single signal line bus SWB is disabled. The duration of the low level of each pulse is between a first predetermined time and a second predetermined time. The duration of the high level of each pulse is between a third predetermined time and a fourth predetermined time. When the (X1+M1) pulse is input, if the duration of the high level of the single-line signal SWS is between a fifth predetermined time and a sixth predetermined time, the number of input pulses (X1+M1) is stored. When the (Y1+N1) pulse is input, if the high level duration of the single-line signal SWS is between the fifth predetermined time and the sixth predetermined time, then the input pulse number (Y1+N1) is stored.

[0008] Broadly speaking, designers can replace the output voltage with a parameter and split that parameter into two groups, thereby reducing the writing time of the parameter setting command. In other words, this single signal line protocol method may include: inputting (X2+M2) pulses via a single signal line bus SWB1 according to a pulse definition table 201, where X2 is greater than or equal to 0, M2 is greater than or equal to 1, and M2 is less than or equal to 2. A2 A2 is greater than or equal to 1. According to the pulse definition table 201, after inputting (X2+M2) pulses, (Y2+N2) pulses are input via the single signal line bus SWB1, where Y2 is greater than or equal to 0, N2 is greater than or equal to 1, and N2 is less than or equal to 2. B2 B2 is greater than or equal to 1, and the (M2+N2) pulses are used to set a parameter PARA based on A2 and B2. This parameter PARA has at most (2 A2 ×2 B2 (Number of values)

[0009] A single-line signal SWS1 is applied to the single-signal-line bus SWB1. When the single-line signal SWS1 changes from a low level to a high level, if the duration of the high level is greater than the enable time, the single-signal-line bus SWB1 is enabled. When the single-line signal SWS1 changes from a high level to a low level, if the duration of the low level is greater than the disable time, the single-signal-line bus SWB1 is disabled. The duration of the low level of each pulse is between a first predetermined time and a second predetermined time. The duration of the high level of each pulse is between a third predetermined time and a fourth predetermined time. When the (X2+M2) pulse is input, if the duration of the high level of the single-line signal SWS1 is between a fifth predetermined time and a sixth predetermined time, the number of input pulses (X2+M2) is stored. When the (Y2+N2) pulse is input, if the high level duration of the single-line signal SWS1 is between the fifth predetermined time and the sixth predetermined time, the input pulse number (Y2+N2) is stored. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a power supply circuit according to an embodiment of the present invention.

[0011] Figure 2 This is a pulse definition table according to an embodiment of the present invention.

[0012] Figure 3 This is a timing diagram of an embodiment of the present invention.

[0013] Figure 4 This is a first flowchart of an embodiment of the present invention.

[0014] Figure 5 This is a second flowchart of an embodiment of the present invention.

[0015] Figure labeling: 100 - Power supply circuit; SWB - Single signal line bus; AVEE - First output voltage; VSS - Second output voltage; AVDD - Third output voltage; VCORE - Fourth output voltage; 200 - Pulse definition table; MSB - Maximum weighted bits; LSB - Minimum weighted bits; SWS - Single-line signal; Ton - Turn-on time; Toff - Turn-off time; Tpl - Low level duration; Tph - High level duration; Ts - High level hold time; S41, S42, S51, S52 - Steps. Detailed Implementation

[0016] The objects, features, and advantages of the invention will become more apparent from the following description. Preferred embodiments of the invention will now be described in detail with reference to the accompanying drawings.

[0017] Figure 1This is a schematic diagram of a power supply circuit 100 according to an embodiment of the present invention, wherein the power supply circuit 100 communicates with a system using a single signal line protocol. For example, the power supply circuit 100 may be an integrated power supply circuit. The power supply circuit 100 may output a first output voltage AVEE, a second output voltage VSS, a third output voltage AVDD, and a fourth output voltage VCORE according to a single signal line bus SWB. The first output voltage AVEE may be a negative voltage. The second output voltage VSS, the third output voltage AVDD, and the fourth output voltage VCORE may each be a positive voltage.

[0018] Figure 2This is a pulse definition table 200 according to an embodiment of the present invention, wherein the first column represents a pulse definition and the second column represents a functional description corresponding to the pulse definition. The system can transmit a single-line signal SWS to the power supply circuit 100 via a single signal line bus SWB, wherein the single-line signal SWS can have multiple pulses and the power supply circuit 100 is used to provide the first output voltage AVEE. For example, according to the pulse definition table 200, when the pulse number is 3 to 5, the power supply circuit 100 can enter a test mode. When the pulse number is 6 to 37, the power supply circuit 100 can be used to set the maximum significant bit (MSB) of the first output voltage AVEE, wherein the maximum significant bit (MSB) of the first output voltage AVEE can be 00000 to 11111. When the pulse count is 39–54, the power supply circuit 100 can be used to set the minimum significant bit (LSB) of the first output voltage AVEE, where the LSB of the first output voltage AVEE can be 0000–1111. When the pulse count is 56–63, the power supply circuit 100 can be used to set the maximum significant bit (MSB) of the second output voltage VSS, where the MSB of the second output voltage VSS can be 000–111. When the pulse count is 65–80, the power supply circuit 100 can be used to set the minimum significant bit (LSB) of the second output voltage VSS, where the LSB of the second output voltage VSS can be 0000–1111. When the pulse count is 82–89, the power supply circuit 100 can be used to set the maximum significant bit (MSB) of the third output voltage AVDD, where the MSB of the third output voltage AVDD can be 000–111. When the pulse number is 91 to 106, the power supply circuit 100 can be used to set the minimum weighted bit number (LSB) of the third output voltage AVDD, where the LSB of the third output voltage AVDD can be 0000 to 1111. When the pulse number is 173, the power supply circuit 100 can be used to execute a first control command. When the pulse number is 174, the power supply circuit 100 can be used to execute a second control command.

[0019] According to one embodiment of the present invention, the system can first input 6 to 37 pulses via a single signal line bus SWB to set the maximum weight bit number MSB (5 bits) of the first output voltage AVEE. After inputting 6 to 37 pulses, the system can input 39 to 54 pulses via the single signal line bus SWB to set the minimum weight bit number LSB (4 bits) of the first output voltage AVEE. Accordingly, a complete first output voltage AVEE can be formed, wherein the first output voltage AVEE has at most (25... 5 ×244 The system can write an output voltage at 512 voltage levels in a time, requiring a maximum of approximately (37 + 54) pulse cycles. However, using conventional single-signal-line protocol technology, it may take up to approximately 512 pulse cycles to write an output voltage. In other words, using conventional single-signal-line protocol technology, the system may take 5 milliseconds to write an output voltage. When using the single-signal-line protocol technology of this invention, that is, when the output voltage is split into two groups, the system only needs about 1 millisecond to write an output voltage for the same voltage command or setting, thus reducing the write time for a voltage setting command. Furthermore, when using the single-signal-line protocol technology of this invention, the output voltage can also be split into three or more groups, which will not be elaborated further in this invention.

[0020] If the voltage change is large, the first output voltage AVEE will not be written after 6 to 37 pulses are input, thus preventing the first output voltage AVEE from being temporarily changed to an incorrect voltage. Then, after 39 to 54 pulses are input, the first output voltage AVEE will be written. If the voltage change is small, the first output voltage AVEE can be quickly changed by directly inputting 39 to 54 pulses. It should be noted that the above features are not essential features of this invention. Designers can use other means to prevent the first output voltage AVEE from being temporarily changed to an incorrect voltage.

[0021] Figure 3 This is a timing diagram of an embodiment of the present invention, wherein a single-line signal SWS is applied to a single signal line bus SWB. When the single-line signal SWS changes from a low level to a high level, if the duration of the high level is greater than an on time Ton, the single signal line bus SWB can be enabled and perform a power-on operation. When the single-line signal SWS changes from the high level to the low level, if the duration of the low level is greater than an off time Toff, the single signal line bus SWB can be disabled and perform a power-off operation. Furthermore, the duration Tpl of the low level of each pulse can be between a first predetermined time and a second predetermined time. The duration Tph of the high level of each pulse can be between a third predetermined time and a fourth predetermined time. After the pulse is input, if the duration Ts of the high level of the single-line signal SWS is between a fifth predetermined time and a sixth predetermined time, the number of input pulses can be stored.

[0022] Figure 4 This is a first flowchart of an embodiment of the present invention. According to a pulse definition table 200, (X1+M1) pulses are input via a single signal line bus SWB, where X1 is greater than or equal to 0, M1 is greater than or equal to 1, and M1 is less than or equal to 2. A1A1 is greater than or equal to 1 (step S41). According to the pulse definition table 200, after inputting (X1+M1) pulses, (Y1+N1) pulses are input via the single signal line bus SWB, where Y1 is greater than or equal to 0, N1 is greater than or equal to 1, and N1 is less than or equal to 2. B1 B1 is greater than or equal to 1, and the (M1+N1) pulses are used to set a first output voltage AVEE. Based on A1 and B1, the first output voltage AVEE can have at most (2 A1 ×2 B1 ) voltage levels (step S42). According to Figure 2 As can be observed from the pulse definition table 200, X1 equals 5, Y1 equals 38, A1 equals 5, and B1 equals 4. Furthermore, the single signal line protocol method of this invention can also be used to set the second output voltage VSS or the third output voltage AVDD, which will not be elaborated further here. In other words, after inputting the (Y1+N1) pulses, the second output voltage VSS, the third output voltage AVDD, and so on can be set.

[0023] Broadly speaking, designers can replace the output voltage with a parameter and split that parameter into two groups. Figure 5 This is a second flowchart of an embodiment of the present invention. According to a pulse definition table 201, (X2+M2) pulses are input via a single signal line bus SWB1, where X2 is greater than or equal to 0, M2 is greater than or equal to 1, and M2 is less than or equal to 2. A2 A2 is greater than or equal to 1 (step S51). According to the pulse definition table 201, after inputting (X2+M2) pulses, (Y2+N2) pulses are input via the single signal line bus SWB1, where Y2 is greater than or equal to 0, N2 is greater than or equal to 1, and N2 is less than or equal to 2. B2 B2 is greater than or equal to 1, and the (M2+N2) pulses are used to set a parameter PARA based on A2 and B2. This parameter PARA can have at most (2 A2 ×2 B2 (Step S52) . Similarly, when the (X2+M2) pulses are input, the parameter PARA will not be written. The parameter PARA will only be written when the (Y2+N2) pulses are input. The pulse definition table 201 can be similar to the pulse definition table 200. For example, the pulse definition table 201 can replace the output voltage with a parameter. Furthermore, Figure 3The timing diagram can also be applied to the parameter PARA, so this invention will not show another identical timing diagram. In other words, the single-signal-line protocol technique of this invention can be used to reduce the write time of a parameter setting instruction. The parameter PARA can be a first output voltage AVEE, a second output voltage VSS, a third output voltage AVDD, a current limit, or other parameters. Therefore, this invention is not limited to application only to the power supply circuit 100.

[0024] According to one embodiment of the present invention, the single-signal-line protocol method of the present invention can be applied to a power supply circuit, a power management integrated circuit, an organic light-emitting diode, a liquid crystal display, an augmented reality glasses, or a virtual reality glasses. The single-signal-line protocol method of the present invention can be used to reduce the write time of voltage setting commands or parameter setting commands.

[0025] While the invention has been described by way of example with reference to preferred embodiments, it should be understood that the invention is not limited to the embodiments provided herein. Rather, the invention is intended to cover various modifications and similar configurations that will be apparent to those skilled in the art. Therefore, the claims of the invention should be interpreted in the broadest sense to include all such modifications and similar configurations.

[0026] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A single-wire protocol method, comprising: Comprising: According to a pulse definition table, X1+M1 pulses are input via a single signal line bus (X1+M1), where X1 is greater than or equal to 0, M1 is greater than or equal to 1, and M1 is less than or equal to 2 A1 A1 is greater than or equal to 1; and According to the pulse definition table, after inputting the (X1+M1) pulses, (Y1+N1) pulses are inputted through the single signal line bus, where Y1 is greater than or equal to 0, N1 is greater than or equal to 1, and N1 is less than or equal to 2 B1 , B1 is greater than or equal to 1, and the (M1+N1) pulses are used to set a first output voltage, which has at most (2 A1 ×2 B1 ) voltage levels based on A1 and B1.

2. The single signal line protocol method of claim 1, wherein, The first output voltage is a negative voltage.

3. The single signal line protocol method of claim 1, wherein, A single-wire signal is applied to the single signal line bus, when the (X1+M1) pulses are inputted, if a high level of the single-wire signal maintains for a time between a fifth predetermined time and a sixth predetermined time, then the inputted pulse number (X1+M1) is stored.

4. The single signal line protocol method of claim 1, wherein, The first output voltage is not written when the (X1+M1) pulses are inputted.

5. The single signal line protocol method of claim 1, wherein, The first output voltage is written when the (Y1+N1) pulses are inputted.

6. The single signal line protocol method of claim 1, wherein, A single-wire signal is applied to the single signal line bus, when the (X1+M1) pulses are inputted, if a high level of the single-wire signal maintains for a time between a fifth predetermined time and a sixth predetermined time, then the inputted pulse number (X1+M1) is stored.

7. The single signal line protocol method of claim 1, wherein, A single-wire signal is applied to the single signal line bus, when the (Y1+N1) pulses are inputted, if a high level of the single-wire signal maintains for a time between a fifth predetermined time and a sixth predetermined time, then the inputted pulse number (Y1+N1) is stored.

8. The single-wire protocol method of claim 1, wherein, A second output voltage and a third output voltage are set after the (Y1+N1) pulses are inputted.

9. The single signal line protocol method of claim 1, wherein, The single signal line protocol method is applied to a power management integrated circuit.

10. The single-wire protocol method of claim 1, wherein, The single signal line protocol method is applied to an organic light emitting diode.

11. The single-wire protocol method of claim 1, wherein, The single signal line protocol method is applied to a liquid crystal display.

12. The single-wire protocol method of claim 1, wherein, The single signal line protocol method is applied to an augmented reality glasses.

13. The single-wire protocol method of claim 1, wherein, The single signal line protocol method is applied to a virtual reality glasses.

14. The single-wire protocol method of claim 1, wherein, The single signal line protocol method is to reduce a write time of a voltage setting instruction.

15. The single-wire protocol method of claim 1, wherein, Comprising:

16. The single-wire protocol method of claim 1, wherein, The parameter is a first output voltage, a second output voltage or a third output voltage.

17. The single-wire protocol method of claim 1, wherein, The parameter is not written when the (X2+M2) pulses are inputted.

18. The single-wire protocol method of claim 1, wherein, The parameter is written when the (Y2+N2) pulses are inputted.

19. A single-wire protocol method, comprising: A single-wire signal is applied to the single signal line bus, when the single-wire signal changes from a low level to a high level, if a duration of the high level is greater than a turn-on time, then the single signal line bus is enabled and performs a turn-on action. According to a pulse definition table, X2+M2 pulses are input via a single signal line bus (X2+M2), where X2 is greater than or equal to 0, M2 is greater than or equal to 1, and M2 is less than or equal to 2 A2 A2 is greater than or equal to 1; and According to the pulse definition table, after the (X2+M2) pulses are input, (Y2+N2) pulses are input via the single signal line bus, where Y2 is greater than or equal to 0, N2 is greater than or equal to 1, and N2 is less than or equal to 2 B2 , B2 is greater than or equal to 1, and the (M2+N2) pulses are used to set a parameter that has at most (2 A2 ×2 B2 ) values based on A2 and B2.

20. The single-wire protocol method of claim 19, wherein, A single-wire signal is applied to the single signal line bus, when the single-wire signal changes from a high level to a low level, if a duration of the low level is greater than a turn-off time, then the single signal line bus is disabled and performs a turn-off action.

21. The single-wire protocol method of claim 19, wherein, A low level duration of each pulse is between a first predetermined time and a second predetermined time.

22. The single-wire protocol method of claim 19, wherein, A high level duration of each pulse is between a third predetermined time and a fourth predetermined time.

23. The single-wire protocol method of claim 19, wherein, ​ 24. The single-wire protocol method of claim 19, wherein, ​ 25. The single-wire protocol method of claim 19, wherein, ​ 26. The single-wire protocol method of claim 19, wherein, ​ 27. The single-wire protocol method of claim 19, wherein, A single wire signal is applied to the single signal line bus, when the (X2+M2) pulse is inputted, if the maintaining time of the high level of the single wire signal is between a fifth predetermined time and a sixth predetermined time, then the inputted pulse number (X2+M2) is stored.

28. The single-wire protocol method of claim 19, wherein, A single wire signal is applied to the single signal line bus, when the (Y2+N2) pulse is inputted, if the maintaining time of the high level of the single wire signal is between a fifth predetermined time and a sixth predetermined time, then the inputted pulse number (Y2+N2) is stored.

29. The single-wire protocol method of claim 19, wherein, The single signal line protocol method is applied to a power management integrated circuit.

30. The single-wire protocol method of claim 19, wherein, The single signal line protocol method is applied to an organic light emitting diode.

31. The single-wire protocol method of claim 19, wherein, The single signal line protocol method is applied to a liquid crystal display.

32. The single-wire protocol method of claim 19, wherein, The single signal line protocol method is applied to an augmented reality glasses.

33. The single-wire protocol method of claim 19, wherein, The single signal line protocol method is applied to a virtual reality glasses.

34. The single-wire protocol method of claim 19, wherein, The single signal line protocol technology is used to reduce the write time of a parameter setting instruction.

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