Cross-clock domain synchronization circuits, methods, and simulators in an EMU simulation and verification environment.

Abstract

This application provides a cross-clock domain synchronization circuit, method, and simulator in an EMU simulation verification environment to solve the technical problem that cross-clock domain metastable states cannot be simulated in EMU simulation verification environments before chip design. This application adds a metastable state simulation circuit after the trigger synchronization circuit constructed based on a multi-level trigger cascade mode. The metastable state simulation circuit simulates cross-clock domain metastable data output scenarios. The technical solution provided in this application complements the CDC simulation method in the DV design verification environment, effectively identifying potential problems in the design under test under CDC scenarios in the early stages of chip verification, thereby effectively ensuring the correctness of the chip design and accelerating the chip development process.

Description

Technical Field

[0001] This application relates to the field of chip simulation and verification technology, and in particular to a cross-clock domain synchronization circuit, method and simulator in an EMU simulation and verification environment. Background Technology

[0002] Clock Domain Crossing (CDC) is a widely used and essential technique in semiconductor chips. By dividing the chip into different clock domains, chip design can achieve advantages such as reduced power consumption and performance matching. However, because the clock domains of proprietary designs (IP cores) within a chip are often independent, modules communicating with IP cores require CDC processing, making thorough verification of CDC extremely important.

[0003] Chip simulation is typically divided into pre-simulation and post-simulation. Pre-simulation focuses on the correctness of the design's logical functions, verifying whether the chip logic can process signals and perform operations as expected, without considering factors such as latency and parasitic effects in the physical implementation. For example, when designing a microprocessor, it verifies whether the logical functions such as instruction decoding and data processing are accurately implemented. Post-simulation focuses on evaluating the performance of the chip after its actual physical implementation, especially timing performance, ensuring that signals can be correctly transmitted and processed within a specified time in a real working environment, avoiding timing issues such as setup and hold violations.

[0004] Standard Delay Format (SDF) files are crucial for describing circuit timing information. They primarily record the delay information of various logic gates and interconnects within a chip, providing critical data support for timing analysis and verification. Generally, verifying the presence of timing-dependent stability (CDC) issues in a chip design requires post-simulation that includes an SDF file. However, post-simulation with a netlist takes longer to run, the number of test cases cannot be as comprehensive as in pre-simulation, and the discovery of metastability issues caused by CDC relies on probability and time. This often leads to post-simulation potentially missing CDC-related problems or discovering CDC issues too late, impacting the chip project's progress. Therefore, pre-simulation needs to cover CDC-induced metastability issues in chip design. Summary of the Invention

[0005] This application provides a cross-clock domain synchronization circuit, method, and simulator in an EMU simulation verification environment to solve the technical problem that cross-clock domain metastability cannot be simulated in an EMU simulation verification environment before chip design.

[0006] Based on one aspect of the embodiments of this application, this application provides a cross-clock domain synchronization circuit in an EMU simulation verification environment. The circuit is located in a second clock domain and includes: a trigger synchronization circuit and a metastable simulation circuit.

[0007] The trigger synchronization circuit is used to synchronize the data input signal (Data in) in the first clock domain (CLKA) using a trigger cascade mode, and output a synchronized data output signal (CDC Data out).

[0008] Metastable simulation circuits are used to simulate metastable data output scenarios across clock domains in an EMU simulator simulation and verification environment; the metastable simulation circuits include:

[0009] The fourth flip-flop is used to latch the synchronous data output signal (CDC Dataout) of the flip-flop synchronization circuit and output the synchronous data output delay signal (CDC Data out Delay).

[0010] The selector is used, under the control of the random factor generator, to select either the synchronous data output signal (CDC Dataout) or the synchronous data output delay signal (CDC Data out Delay) as the synchronous data analog output signal (CDC Data SIM out) of the cross-clock domain synchronization circuit.

[0011] A random factor generator is used to generate random signals to trigger a selector to select the output signal.

[0012] Furthermore, the random factor generator includes:

[0013] A random number generator is used to generate a multi-bit pseudo-random number and generate a random signal based on the generated random number according to a preset logical operation rule; and to generate a new random number when triggered by an update signal output by the update control unit.

[0014] A counter is used to accumulate counts under the control of a clock signal; and to perform a count reset operation when triggered by a reset signal output by the update control unit.

[0015] The first comparator is used to compare whether the random number output by the random number generator is equal to the count value of the counter. If they are equal, the first control signal is output.

[0016] A logic unit is used to detect whether the synchronous data output signal (CDC Data out) meets the conditions for generating the second control signal, and outputs the second control signal when the conditions are met;

[0017] The update control unit is used to output an update signal after receiving the first control signal and the second control signal. The update signal is used to clear the counter and to make the random number generator generate a new random number.

[0018] Furthermore, the random number generator generates a random factor, i.e. a random signal, based on the generated random number and according to a preset logical operation rule; the preset logical operation rule includes: taking two or more fixed bits from the generated random number and performing a single-bit logical operation to obtain the value as the random factor.

[0019] Furthermore, the cross-clock domain synchronization circuit is a multi-bit-width synchronization circuit, with a corresponding trigger synchronization circuit and metastable simulation circuit for each synchronization data signal, and each channel is equipped with its own independent random factor generator.

[0020] Furthermore, the second control signal is generated when the logic unit detects a falling edge or a rising edge of the synchronous data output signal (CDC Data out).

[0021] Based on another aspect of the embodiments of this application, this application also provides a cross-clock domain synchronization method in an EMU simulation verification environment. The method is applied to implement cross-clock domain simulation in an EMU simulation verification environment, synchronizing data signals from a first clock domain to a second clock domain. The method includes:

[0022] In the second clock domain, a metastable simulation circuit (310) is added after the flip-flop synchronization circuit (320) constructed based on the multi-level flip-flop cascade mode. The metastable simulation circuit simulates the metastable data output scenario across clock domains.

[0023] The metastable analog circuit uses a fourth flip-flop to latch the flip-flop and synchronize the output of the synchronous data output signal (CDC Data out) and output the synchronous data output delay signal (CDC Data out Delay).

[0024] In the metastable analog circuit, a random factor generator is used to generate a random signal to trigger a selector to select either the synchronous data output signal (CDC Data out) or the synchronous data output delay signal (CDC Data outDelay) as the synchronous data analog output signal (CDC Data SIM out).

[0025] Furthermore, a multi-bit pseudo-random number is generated using a random number generator in the random factor generator, and the random signal is generated based on the generated random number according to a preset logical operation rule;

[0026] A counter is used to accumulate counts under the control of a clock signal. When a random number is detected to be equal to the count value of the counter, the first control signal is output.

[0027] The logic unit detects the synchronous data output signal (CDC Data out), and when the conditions for generating the second control signal are met, the second control signal is output.

[0028] After detecting the first control signal and the second control signal, the update control unit outputs an update signal to clear the counter and cause the random number generator to generate a new random number.

[0029] Furthermore, the random signal is obtained by extracting two or more fixed bits from the random numbers generated by the random number generator and performing single-bit logical operations.

[0030] Furthermore, the cross-clock domain synchronization circuit is a multi-bit-width synchronization circuit, with a corresponding trigger synchronization circuit and metastable simulation circuit for each synchronization data signal, and each channel is equipped with its own independent random factor generator.

[0031] Based on the embodiments of this application, this application also provides an EMU emulator, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the steps or module functions of the cross-clock domain synchronization method in the above-described EMU simulation verification environment.

[0032] Beneficial effects: This application adds a metastable simulation circuit after the trigger synchronization circuit constructed based on the multi-level trigger cascade mode. The metastable simulation circuit simulates the metastable data output scenario across clock domains. The technical solution provided by this application complements the CDC simulation method in the DV environment. It can effectively discover the problems that the design under test may cause in the CDC scenario in the early stage of chip verification, thereby effectively ensuring the correctness of the chip design and accelerating the progress of chip development.

[0033] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0034] Figure 1 A schematic diagram of a circuit structure for cross-clock domain verification in a design verification environment;

[0035] Figure 2 This is a timing diagram of the synchronization data signal under metastable conditions in a cross-clock domain scenario according to an embodiment of this application;

[0036] Figure 3 This is a schematic diagram of the structure of a single-bit cross-clock domain synchronization circuit provided in an embodiment of this application;

[0037] Figure 4 This is a schematic diagram of the circuit structure of a random factor generator used in an embodiment of this application;

[0038] Figure 5 A schematic diagram of the signal timing of a cross-clock domain synchronization circuit under the influence of a random factor in one embodiment of this application;

[0039] Figure 6 This is a schematic diagram of the structure of a multi-bit wide cross-clock domain synchronization circuit in one embodiment of this application. Detailed Implementation

[0040] The exemplary embodiments will now be described in detail. When the description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification; they are merely exemplary embodiments of apparatuses and methods consistent with some aspects of this specification.

[0041] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “described,” and “the” as used herein are also intended to include the plural forms unless the context clearly indicates otherwise.

[0042] It should be understood that the terms "first," "second," "third," etc., may be used in this specification to describe various information or structural modules for the purpose of more clearly describing the solution. These terms should not be construed as indicating or implying relative importance or implicitly specifying the number, order, or position of the indicated technical features. Therefore, a feature defined with "first," "second," "third," etc., may explicitly or implicitly include one or more of that feature. In the description of this specification, unless otherwise stated, "a plurality of" means two or more; "if" can be interpreted as "when," "when," or "in response to determination."

[0043] In this specification, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0044] The most basic way to cross clock domains in CDC is to use a synchronizer, which is to use a multi-level register cascaded timing method. However, under asynchronous clocks, the output of the multi-level register cascaded will have an uncertain value due to metastability, which may be 1 or 0.

[0045] Figure 1This diagram illustrates a circuit structure for cross-clock domain verification in a design verification environment. In this Design Verification (DV) example, two clock domains are included: a first clock domain (clock signal CLKA) and a second clock domain (clock signal CLKB). Flip-flops in the first clock domain, driven by clock signal CLKA, output data from the first clock domain to the second clock domain via D flip-flops. Since CLKA and CLKB are asynchronous clock signals, metastability may occur. To address this, a synchronous circuit (also called a synchronization circuit) of two cascaded D flip-flops is used in the second clock domain. The two flip-flops in the synchronous circuit are driven by the CLKB clock signal. In this example, to simulate the physical delays caused by traces and components in a real chip, "delay logic" is added before inputting data from the first clock domain to the second clock domain. This delay logic sets a fixed delay for data transmission, simulating the physical delays caused by traces and components in a real chip.

[0046] However, unlike the DV design verification environment, the EMU (Emulation Model Unit) environment uses simulation equipment to simulate the actual operation of the chip. The simulator is a hardware device that can load the hardware description language (HDL) model of the design, such as Verilog or VHDL code, and execute these models at speeds close to those of a real chip. Because the compiler of an EMU simulation environment (such as the Palladium simulation verification platform) cannot recognize non-synthesizable statements starting with the "#" identifier (statements starting with "#" can be used to specify delays), it cannot simulate physical delays like in a DV design verification environment. Furthermore, asynchronous clocks in the design cannot be implemented within the EMU simulation verification environment. Therefore, there is currently no cross-clock domain verification scheme in the existing technology for EMU simulation verification environments.

[0047] Figure 2 This is a timing diagram illustrating the synchronous data signal under metastability conditions in a cross-clock domain scenario according to an embodiment of this application. The diagram illustrates the timing relationship between the data input signal (Data_in) in the first clock domain (CLKA domain) and the synchronous data output signal (Data_out) in the second clock domain (CLKB domain) under metastability conditions. When CDC metastability occurs, the following pattern exists between the data input signal and the data output signal in the second clock domain when sampled at the rising or falling edge of the clock signal:

[0048] like Figure 2For example, the D flip-flop synchronization circuit samples the data input signal in the first clock domain on the rising edge of CLKB. When the data input signal Data_in (CLKA domain) in the first clock domain is high, if the sampling is correct, the current output data signal Data_out (CLKB domain) in the second clock domain should be high, and the data output signal in the current EMU simulation verification environment should also be high. If the sampling is incorrect, the current data output signal Data_out (CLKB domain) is low, and the actual output is the data output signal in the EMU simulation verification environment under the previous clock cycle. The correct high-level data output signal (Data_out) will be output in the next cycle.

[0049] When the D flip-flop synchronization circuit samples the data input signal (Data_in) in the first clock domain at the falling edge of CLKB (not shown in the figure), if the current data input signal Data_in (CLKAdomain) in the first clock domain is low, and the sampling is correct, the current data output signal Data_out (CLKBdomain) in the second clock domain should also be low, and the data output signal in the current EMU simulation verification environment should also be low. Conversely, if the sampling is incorrect, the current data output signal in the second clock domain will be high, and the actual data output signal in the current EMU simulation verification environment is the data output signal in the previous clock cycle. The correct data output signal will only be output in the next cycle.

[0050] Based on the above analysis, it can be found that when metastability occurs, due to the metastability, the data output signal obtained by the second clock domain sampling may be the original correct value, or the correct value may be in the next clock cycle.

[0051] Based on the above-mentioned patterns, in order to solve the technical problem that cross-clock domain simulation verification cannot be achieved in the EMU simulation verification environment, this invention provides a technical solution for simulating cross-clock domain CDC metastable scenarios in the EMU simulation verification environment. This solution complements the CDC simulation method in the DV environment. Through this solution, problems that the design under test (DUT) may cause in the CDC scenario can be effectively discovered in the early stage of chip verification, which can effectively ensure the correctness of chip design and accelerate the progress of chip development.

[0052] Figure 3 This is a schematic diagram of a single-bit cross-clock domain synchronization circuit provided in an embodiment of this application. The cross-clock domain synchronization circuit 300 provided in this embodiment is applied in an EMU simulation verification environment, located in the second clock domain, and includes a trigger synchronization circuit 320 and a metastable analog circuit 310. It should be noted that, for the sake of simplicity, Figure 3The example only illustrates a single-bit cross-clock domain synchronization circuit. In practical applications, the structure shown in the diagram can be reused and extended by multiplexing the flip-flop synchronization circuit 320 and the metastable analog circuit 310 according to the bit width of the input data.

[0053] In this embodiment, the circuit structure of the first clock domain and the trigger synchronization circuit 320 in the second clock domain can adopt the same circuit structure as in the DV design verification environment. The output signal of the first trigger 301 can still be input to the data input port (D) of the second trigger 322 through delay logic. However, since the non-synthesizable statement used by the delay logic does not work during the compilation process in the EMU simulation verification environment, the delay logic is equivalent to being ineffective. The original output port (Q) of the second trigger 322 is connected to the data input port (D) of the third trigger 323. The original output port (Q) of the third trigger 323 outputs a synchronous data output signal (CDC Data out). The clock ports of the second trigger 322 and the third trigger 323 are connected to the clock signal (CLKB) of the second clock domain.

[0054] The trigger synchronization circuit 320 is configured to synchronize the data input signal (Data in) in the first clock domain (CLKA) using a trigger cascade mode and output a synchronized data output signal (CDC Data out).

[0055] Metastable analog circuit 310 is configured to simulate metastable data output scenarios across clock domains in an EMU simulation verification environment. Metastable analog circuit 310 mainly consists of three parts: a fourth flip-flop 313, a selector 311, and a random factor generator 312. All three parts are located in the second clock domain, and their clock ports are all connected to the clock signal (CLKB) of the second clock domain.

[0056] The fourth flip-flop 313 is configured as the synchronous data output signal (CDCData out) of the latched flip-flop synchronization circuit 320, and the output signal of the fourth flip-flop 313 is the synchronous data output delay signal (CDC Data out Delay); the data signal output from the original output port (Q) of the third flip-flop 323 is connected to the data input port (D) of the fourth flip-flop 313, and the original output port (Q) of the fourth flip-flop 313 is connected to one input terminal of the selector 311.

[0057] Selector 311 is configured, under the control of random factor generator 312, to select either the synchronous data output signal (CDCData out) or the synchronous data output delay signal (CDC Data out Delay) output by the fourth flip-flop 313 as the data output signal (i.e., synchronous data analog output signal (CDC Data SIM out)) of the metastable analog circuit 310. Due to the addition of the fourth flip-flop, the data output signal (CDC Data out Delay) of the original output port (Q) of the fourth flip-flop 313 will have some delay relative to the data output signal (CDC Data out) of the third flip-flop 323. Under the trigger of the random signal generated by the random factor generator, selector 311 selects either the synchronous data output signal (CDC Dataout) without delay or the synchronous data output delay signal (CDC Data out Delay) as the data output signal (i.e., synchronous data analog output signal (CDC Data SIM out)) of the cross-clock domain synchronous circuit 300, thereby realizing the simulation of a cross-clock domain metastable data output scenario.

[0058] The random factor generator 312 is configured to generate a random signal to trigger the selector 311 to select either the synchronous data output signal (CDC Data out, corresponding to the current clock beat, i.e., the data output signal of the current beat) or the synchronous data output delay signal (CDC Data out Delay, corresponding to the data output signal of the next beat) as the output signal.

[0059] based on Figure 2 The conclusion drawn from the timing signal analysis is that when metastability occurs, the signal output by the trigger synchronization circuit 320 in the second clock domain may be the original correct value (i.e., the data output signal of the current clock cycle) or the correct value (the data output signal of the next clock cycle) may be output in the next clock cycle. In this embodiment, the metastable data output scenario across clock domains is simulated in the EMU simulation verification environment by combining the random factor generator 312, the selector 311 and the fourth trigger 313.

[0060] Figure 4 This is a schematic diagram of the circuit structure of a random factor generator used in an embodiment of this application. The basic principle of the random factor generator 312 is to generate a one-bit random signal, i.e., a random factor, under the combined action of the clock signal (CLKB) and the synchronous data output signal (CDCData out) of the flip-flop synchronization circuit 320.

[0061] Random number generator 3121 is configured to generate a multi-bit pseudo-random number and, based on the generated random number, produce a random signal, i.e., a random factor, according to a preset logical operation rule. Triggered by an update signal output from update control unit 3125, the random number generator generates a new random number; changes in the random number cause changes in the random signal. Random number generator 3121 can be implemented using methods such as a linear feedback shift register (LFSR), a nonlinear feedback shift register (NLFSR), or a ring oscillator (RO).

[0062] Counter 3122 is used to accumulate counts under the control of a clock signal; counter 3122 performs a count reset operation when triggered by a reset signal output by update control unit 3125.

[0063] The first comparator 3123 is used to compare whether the random number output by the random number generator 3121 is equal to the count value of the counter 3122. If they are equal, the first control signal is output.

[0064] Logic unit 3124 is used to detect whether the synchronous data output signal (CDC Data out) meets the conditions for generating the second control signal, and outputs the second control signal when the conditions are met; the conditions for generating the second control signal can be the detection of the falling edge or rising edge of the synchronous data output signal (CDC Data out).

[0065] The update control unit 3125 is used to output an update signal after receiving the first control signal and the second control signal. The update signal is used to trigger the counter 3122 to be cleared and to trigger the random number generator 3121 to generate a new random number.

[0066] As can be seen from the structure of the random factor generator 312, the bit width of the random number generator determines the size of the random time window. The smaller the bit width, the smaller the interval between changes in the random factor, i.e., the random signal, which can control the frequency of metastable behavior. The value of the random factor determines whether the selector 311 selects the output data signal of the current clock cycle (CDC Data out) or the data of the next clock cycle (CDC Data out Delay). Within the update time window, if the update enable is not pulled high, the random number will not change.

[0067] The random number generator 3121 can generate random factors, i.e. random signals, based on the generated random numbers according to preset logical operation rules in various ways. For example, the value obtained by performing single-bit logical operations (such as AND, OR, NOT, XOR, etc.) on two or more fixed bits in the generated random numbers can be used as the random factor.

[0068] Figure 5 This application presents a schematic diagram of the timing of a cross-clock domain synchronization circuit under the influence of a random factor in one embodiment. As shown in the example, initially, the random number generator 3121 generates a random number "0x0F". The counter 3122 counts from "0" to "0x0F". The first comparator 3123 determines that the random value and the counter value are equal, and then outputs a first control signal, i.e., a high level. The logic unit 3124 detects the falling edge of the synchronous data output signal (CDC Data out) within the same clock cycle and outputs a second control signal, i.e., a high level. The update control unit 3125 uses an AND gate circuit. When both the first control signal and the second control signal are high, it outputs a high-level update signal, thereby triggering the counter to be cleared and the random number generator to be updated. After the random number is updated, it is "0xBF". The random number generator 3121 uses the XOR value of the 0th bit and the 7th bit of the random number (LFSR[7]^LFSR[0]) as the random factor and outputs it to the selector 311. Since the random factor changes from a high level "1" to a low level "0", the selector 311 selects the current data (CDC Data out) output when the random factor is low. Correspondingly, if the one-bit random signal generated by the random factor generator is high, the selector 311 selects the next data (CDCData out Delay) output.

[0069] Figure 6 This is a schematic diagram of the structure of a multi-bit-width cross-clock domain synchronization circuit in one embodiment of this application. In this example, the cross-clock domain synchronization circuit 300 is a multi-bit-width synchronization circuit. For each channel of synchronization data signal, there is a corresponding trigger synchronization circuit 320 and metastable analog circuit 310. Each channel has its own independent random factor generator 312.

[0070] The triggers used in this application can be selected from D triggers, JK triggers, synchronous SR triggers, etc., depending on the actual application scenario. This application does not make any specific restrictions.

[0071] Based on the cross-clock-domain synchronization circuit 300 in the EMU simulation verification environment provided in the foregoing embodiments, this application embodiment also provides a corresponding method. This method is applied to implement cross-clock-domain simulation in the EMU simulation verification environment, realizing the function of synchronizing data signals from a first clock domain to a second clock domain. The method includes:

[0072] S1. In the second clock domain, a metastable simulation circuit 310 is added after the flip-flop synchronization circuit 320 constructed based on the multi-level flip-flop cascade mode. The metastable simulation circuit simulates the metastable data output scenario across clock domains.

[0073] S2. In the metastable analog circuit 310, the fourth flip-flop 313 latches the flip-flop and the synchronous data output signal (CDC Data out) outputs the synchronous data output delay signal (CDC Data out Delay).

[0074] S3. In the metastable analog circuit 310, a random factor generator 312 is used to generate a random signal to trigger the selector 311 to select either the synchronous data output signal (CDC Data out) or the synchronous data output delay signal (CDC Dataout Delay) as the synchronous data analog output signal (CDC Data SIM out).

[0075] Preferably, a multi-bit pseudo-random number is generated in the random factor generator 312 using a random number generator 3121, and the random signal is generated based on the generated random number according to a preset logical operation rule;

[0076] The counter 3122 is used to accumulate counts under the control of the clock signal. When the random number is detected to be equal to the count value of the counter, the first control signal is output.

[0077] The logic unit 3124 detects the synchronous data output signal (CDC Data out), and when the conditions for generating the second control signal are met, the second control signal is output.

[0078] After detecting the first control signal and the second control signal, the update control unit 3125 outputs an update signal to clear the counter 3122 and to cause the random number generator 3121 to generate a new random number.

[0079] Preferably, the random signal is obtained by extracting two or more fixed bits from the random number generated by the random number generator 3121 and performing single-bit logical operations.

[0080] Preferably, the cross-clock domain synchronization circuit 300 is a multi-bit-width synchronization circuit, with a corresponding trigger synchronization circuit 320 and metastable analog circuit 310 for each synchronization data signal, and each channel is equipped with its own independent random factor generator 312.

[0081] The foregoing has described exemplary embodiments of this specification. It should be understood that in some cases, the modules described in this specification may be divided in a manner different from that in the embodiments, and the described actions or steps may be performed in a different order than that in the embodiments, while still achieving the desired result. Furthermore, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0082] Other embodiments of this specification will readily occur to those skilled in the art upon consideration of the specification and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations that follow the general principles of this specification and include common knowledge or customary techniques in the art not illustrated herein.

[0083] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

Claims

1. A cross-clock domain synchronization circuit in an EMU simulation verification environment, characterized in that, The circuit is located in the second clock domain and includes: a flip-flop synchronization circuit and a metastable analog circuit; A trigger synchronization circuit is used to synchronize the data input signal in the first clock domain using a trigger cascade mode, and output a synchronized data output signal. Metastable simulation circuits are used to simulate metastable data output scenarios across clock domains in an EMU simulator simulation and verification environment; the metastable simulation circuits include: The fourth flip-flop is used to latch the synchronous data output signal of the flip-flop synchronization circuit, and outputs a synchronous data output delay signal. The selector is used, under the control of the random factor generator, to select either the synchronous data output signal or the synchronous data output delay signal as the synchronous data analog output signal of the cross-clock domain synchronization circuit. A random factor generator is used to generate a random signal in conjunction with the clock signal in the second clock domain and the synchronous data output signal of the trigger synchronization circuit to trigger the selector to select the output signal.

2. The circuit according to claim 1, characterized in that, The random factor generator includes: A random number generator is used to generate a multi-bit pseudo-random number and generate a random signal based on the generated random number according to a preset logical operation rule; and to generate a new random number when triggered by an update signal output by the update control unit. The counter is used to accumulate counts under the control of a clock signal; and to perform a count reset operation when triggered by a reset signal output by the update control unit. The first comparator is used to compare whether the random number output by the random number generator is equal to the count value of the counter. If they are equal, the first control signal is output. A logic unit is used to detect whether the synchronous data output signal meets the conditions for generating a second control signal, and outputs the second control signal when the conditions are met; The update control unit is used to output an update signal after receiving the first control signal and the second control signal. The update signal is used to clear the counter and to make the random number generator generate a new random number.

3. The circuit according to claim 2, characterized in that, The random number generator generates a random factor, i.e., a random signal, based on the generated random number and according to a preset logical operation rule; the preset logical operation rule includes: taking two or more fixed bits from the generated random number and performing a single-bit logical operation to obtain the value as the random factor.

4. The circuit according to claim 1, characterized in that, The cross-clock domain synchronization circuit is a multi-bit-width synchronization circuit. For each synchronization data signal, there is a corresponding trigger synchronization circuit and metastable simulation circuit. Each channel is equipped with its own independent random factor generator.

5. The circuit according to claim 2, characterized in that, The second control signal is generated when the logic unit detects a falling edge or a rising edge of the synchronous data output signal.

6. A method for cross-clock domain synchronization in an EMU simulation verification environment, characterized in that, The method is applied to implement cross-clock domain simulation in an EMU simulation verification environment, synchronizing data signals from a first clock domain to a second clock domain. The method includes: In the second clock domain, a metastable simulation circuit is added after the flip-flop synchronization circuit constructed based on the multi-level flip-flop cascade mode. The metastable simulation circuit simulates the metastable data output scenario across clock domains. The metastable analog circuit uses a fourth flip-flop to latch the synchronous data output signal of the synchronous circuit, and outputs a synchronous data output delay signal. In the metastable analog circuit, a random factor generator is used to generate a random signal under the combined action of the clock signal in the second clock domain and the synchronous data output signal of the trigger synchronization circuit. This triggers a selector to select either the synchronous data output signal or the synchronous data output delay signal as the synchronous data analog output signal.

7. The method according to claim 6, characterized in that, A multi-bit pseudo-random number is generated using a random number generator in the random factor generator, and the random signal is generated based on the generated random number according to a preset logical operation rule; A counter is used to accumulate counts under the control of a clock signal. When a random number is detected to be equal to the count value of the counter, the first control signal is output. The logic unit detects the synchronous data output signal, and when the condition for generating the second control signal is met, the second control signal is output. After detecting the first control signal and the second control signal, the update control unit outputs an update signal to clear the counter and cause the random number generator to generate a new random number.

8. The method according to claim 7, characterized in that, The random signal is obtained by extracting two or more fixed bits from the random numbers generated by the random number generator and performing single-bit logical operations.

9. The method according to claim 7, characterized in that, The cross-clock domain synchronization circuit is composed of the aforementioned trigger synchronization circuit and metastable analog circuit; The cross-clock domain synchronization circuit is a multi-bit-width synchronization circuit. For each synchronization data signal, there is a corresponding trigger synchronization circuit and metastable simulation circuit. Each channel is equipped with its own independent random factor generator.

10. An EMU emulator, characterized in that, The EMU emulator includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the steps or module functions of the method as described in any one of claims 6 to 9.

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