Pixel array, display panel and panel driving method

Abstract

The application belongs to the technical field of display driving, and particularly relates to a pixel array, a display panel and a panel driving method, which comprise N rows of pixel rows and M columns of data lines, the nth row of pixel rows comprises a scanning line and an auxiliary driving line; a logic control unit is configured to: in response to a compensation control signal output by a compensation control end, output an auxiliary driving signal to the auxiliary driving line when the nth row of scanning signals and the nth+1 row of scanning signals are both effective levels; M pixel circuits, each pixel circuit is connected with a corresponding scanning line, data line, auxiliary driving line and pixel electrode, the pixel circuit is configured to: in response to the nth row of scanning signals, establish a first charging path from the data line to the pixel electrode; in response to the auxiliary driving signal, establish a second charging path from the data line to the pixel electrode. Through the design of the first charging path and the second charging path, the pixel charging rate in a low-temperature environment is effectively improved.

Description

Technical Field

[0001] This application belongs to the field of display driver technology, specifically relating to a pixel array, a display panel, and a panel driving method. Background Technology

[0002] In liquid crystal displays, gate integrated driving technology integrates the gate driving circuit directly onto the array substrate, replacing the original external driving chip and effectively reducing costs.

[0003] In low-temperature environments, due to the temperature dependence of transistors, their threshold voltage will drift negatively as the temperature decreases, the peak voltage of the gate output signal will decrease, and it will be unable to reach the turn-on voltage of the pixel transistor, resulting in insufficient turn-on and a decrease in the pixel capacitor charging rate.

[0004] Therefore, how to improve the pixel charging rate in low-temperature environments is a problem that this application urgently needs to solve. Summary of the Invention

[0005] This application provides a pixel array, a display panel, and a panel driving method to improve pixel charging rate in low-temperature environments.

[0006] In a first aspect, this application provides a pixel array comprising N rows of pixels and M columns of data lines, wherein the nth row of pixels includes:

[0007] Scan lines;

[0008] Auxiliary drive line;

[0009] The logic control unit has its input terminals connected to the nth scan line, the (n+1)th scan line, and the compensation control terminal, respectively, and its output terminal connected to the auxiliary drive line. The logic control unit is configured to: in response to the compensation control signal output by the compensation control terminal, when both the nth scan signal and the (n+1)th scan signal are at an active level, output an auxiliary drive signal to the auxiliary drive line.

[0010] There are M pixel circuits, each connected to a corresponding scan line, data line, auxiliary drive line and pixel electrode. The pixel circuits are configured to: establish a first charging path from the data line to the pixel electrode in response to the nth row scan signal; and establish a second charging path from the data line to the pixel electrode in response to the auxiliary drive signal.

[0011] Optionally, the pixel circuit includes:

[0012] The pixel transistor has a control terminal connected to the nth scan line, a first terminal connected to the data line, and a second terminal connected to the pixel electrode.

[0013] The auxiliary transistor has its control terminal connected to the auxiliary drive line, its first terminal connected to the data line, and its second terminal connected to the pixel electrode.

[0014] Optionally, the logic control unit includes:

[0015] The first transistor has its control terminal connected to the nth row of scan lines, and its first terminal is connected to the first compensation control terminal.

[0016] The second transistor has its control terminal connected to the nth row of the scan line, its first terminal connected to the second compensation control terminal, and its second terminal connected to the auxiliary drive line.

[0017] The third transistor has its control terminal connected to the (n+1)th scan line, its first terminal connected to the second terminal of the first transistor, and its second terminal connected to the second terminal of the second transistor.

[0018] The fourth transistor has its control terminal connected to the (n+1)th scan line, its first terminal connected to the first terminal of the second transistor, and its second terminal connected to the second terminal of the third transistor.

[0019] The first and third transistors are both N-type transistors, while the second and fourth transistors are both P-type transistors.

[0020] Optionally, the logic control unit includes:

[0021] The fifth transistor has its control terminal connected to the nth scan line, and its first terminal connected to the power supply terminal.

[0022] The sixth transistor has its control terminal connected to the nth row of the scan line, and its first terminal is connected to the second terminal of the fifth transistor.

[0023] The seventh transistor has its control terminal connected to the (n+1)th scan line, its first terminal connected to the first terminal of the fifth transistor, and its second terminal connected to the first terminal of the sixth transistor.

[0024] The eighth transistor has its control terminal connected to the (n+1)th scan line, its first terminal connected to the second terminal of the sixth transistor, and its second terminal grounded.

[0025] The control terminal of the ninth transistor is connected to the first terminal of the sixth transistor, and the first terminal of the ninth transistor is connected to the first compensation control terminal.

[0026] The tenth transistor has its control terminal connected to the control terminal of the ninth transistor, its first terminal connected to the second compensation control terminal, and its second terminal connected to the second terminal of the ninth transistor.

[0027] Among them, the fifth, seventh and ninth transistors are all P-type transistors, while the sixth, eighth and tenth transistors are all N-type transistors.

[0028] In a second aspect, this application provides a display panel, which includes the pixel array described in the first aspect of the invention;

[0029] The temperature detection circuit is configured to detect the current temperature of the display panel and generate a compensation trigger signal when the current temperature is lower than the preset temperature.

[0030] The timing controller, connected to the temperature detection circuit, is configured to output a compensation enable signal based on the compensation trigger signal;

[0031] The power management chip, connected to the timing controller and the logic control unit of the pixel array, is configured to generate a corresponding compensation control signal based on the compensation enable signal, so that the logic control unit responds to the compensation control signal and establishes a second charging path for the pixel circuit.

[0032] Optionally, the temperature detection circuit includes:

[0033] The temperature detection module is configured to detect the current ambient temperature and convert the current ambient temperature into a current detection voltage;

[0034] The voltage comparison module, connected to the output of the temperature detection module, is configured to output a compensation trigger signal when the current detected voltage is less than the reference voltage corresponding to the preset temperature.

[0035] Optionally, the temperature detection module includes:

[0036] Thermistor, with its first terminal connected to the power supply terminal;

[0037] The first resistor has its first end connected to the second end of the thermistor, and the second end of the first resistor is grounded.

[0038] The amplifier's first input terminal is connected to the second terminal of the thermistor.

[0039] The second resistor has its first end connected to the power supply terminal and its second end connected to the second input terminal of the amplifier.

[0040] The third resistor has its first end connected to the second end of the second resistor, and the second end of the third resistor is grounded.

[0041] The fourth resistor has its first end connected to the second end of the second resistor, and its second end is connected to the output of the amplifier.

[0042] Optionally, the voltage comparison module includes:

[0043] The comparator's first input is connected to the output of the temperature detection module, and the comparator's output is connected to the timing controller.

[0044] The fifth resistor has its first end connected to the second input terminal of the comparator, and its second end connected to the output terminal of the comparator.

[0045] The sixth resistor has its first terminal connected to the second input terminal of the comparator and its second terminal connected to the reference voltage terminal.

[0046] Thirdly, this application provides a panel driving method applied to the display panel described in the second aspect of the invention. The panel driving method includes:

[0047] Get the current temperature of the display panel;

[0048] When the current temperature is lower than the preset temperature, a compensation control signal is generated;

[0049] A compensation charging path is established for the pixel electrode based on the compensation control signal.

[0050] Optionally, each row of pixels in the display panel includes a scan line, an auxiliary drive line, a logic control unit, and a pixel circuit; a compensation charging path is established for the pixel circuit according to the compensation control signal, including:

[0051] The logic control unit responds to the compensation control signal and outputs an auxiliary drive signal to the auxiliary drive line when both the current row scan signal and the next row scan signal are at an active level.

[0052] The pixel circuit responds to the current row scan signal to establish a first charging path from the data line to the pixel electrode; and responds to the auxiliary drive signal to establish a second charging path from the data line to the pixel electrode.

[0053] The second charging path is a compensation charging path.

[0054] This application designs an auxiliary drive line through adjacent scan lines to control the charging circuit corresponding to the pixel circuit. The pixel electrode can be charged through the auxiliary drive line, improving the charging rate of the pixel capacitor. Through the logic control unit, combined with the scan signals of adjacent scan lines, a corresponding auxiliary drive signal is generated, reducing the phenomenon of insufficient opening caused by threshold voltage changes. Through the auxiliary drive signal, the pixel circuit is driven to establish two charging circuits. When the threshold voltage drifts, one of the two charging circuits can be used to double the charging current to charge the pixel capacitor, improving the pixel charging rate. Attached Figure Description

[0055] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0056] Figure 1 The diagram shown is a schematic representation of a pixel array provided in an embodiment of this application. Figure 1 ;

[0057] Figure 2 The diagram shown is a schematic of the circuit structure of a pixel array provided in an embodiment of this application. Figure 2 ;

[0058] Figure 3 The diagram shown is a schematic of the circuit structure of a pixel array provided in an embodiment of this application. Figure 3 ;

[0059] Figure 4 A schematic diagram of a pixel array circuit structure provided in an embodiment of this application. Figure 4 ;

[0060] Figure 5 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0061] Figure 6 This application provides a schematic diagram of a temperature detection circuit structure for a display panel.

[0062] Figure 7 A flowchart illustrating a panel driving method provided in this application embodiment. Figure 1 ;

[0063] Figure 8 A flowchart illustrating a panel driving method provided in this application embodiment. Figure 2 ;

[0064] Figure 9This is a schematic diagram of a charging process provided in an embodiment of this application.

[0065] Explanation of reference numerals in the attached figures:

[0066] 100, Pixel array; 110, Scan line; Gn, nth row scan line; Gn+1, (n+1)th row scan line; 120, Auxiliary drive line; 130, Logic control unit; 140, Pixel circuit; 150, Data line; 160, Compensation control terminal; VC, Pixel electrode; VCOM, Common electrode; C, Pixel capacitor;

[0067] T1A, pixel transistor; T2A, auxiliary transistor; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; 161, first compensation control terminal; 162, second compensation control terminal; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor;

[0068] 500, Display panel; 510, Temperature detection circuit; 520, Timing controller; 530, Power management chip; 540, Printed circuit board; 511, Temperature detection module; 512, Voltage comparison module; NTC, Thermistor; R1, First resistor; R2, Second resistor; R3, Third resistor; R4, Fourth resistor; EN-VDD, Power supply terminal; OPA, Amplifier; CMP, Comparator; R5, Fifth resistor; R6, Sixth resistor; EN-VREF, Reference voltage terminal; Gn+2, Scan line n+2; t1, Pre-charge process; t2, Actual charging process. Detailed Implementation

[0069] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0070] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0071] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0072] With the continuous development of display technology, gate integrated driving technology has become the mainstream application method for modern LCD panels due to its advantages such as integration and structural optimization. Gate integrated driving technology directly integrates the external gate driving circuit onto the array substrate, realizing the gate progressive scan driving function with the panel's own process, replacing the external driving chip, reducing costs, simplifying the panel structure, and enabling narrow bezel design.

[0073] In practical applications, gate-integrated drive technology faces the serious challenge of not being able to operate in low-temperature environments. Due to the temperature dependence of transistors, the threshold voltage of transistors will drift negatively as the temperature decreases. Consequently, the rising edge transition and peak voltage of the corresponding gate output signal decrease, making it impossible to reach the high level required for the pixel transistor to be fully turned on.

[0074] Poor gate signal quality will directly lead to insufficient activation of pixel transistors, increasing on-resistance. Since the horizontal scan time is limited, insufficient transistor activation prevents data signals from fully charging the pixel capacitor through the increased resistance of the transistors, resulting in a decreased pixel charging rate and consequently affecting display quality.

[0075] Therefore, how to fully activate the transistors and improve the pixel charging rate in low-temperature environments, thereby enhancing the display effect, is a problem that this application urgently needs to solve.

[0076] Based on this, this application provides a pixel array, a display panel, and a panel driving method, which can be used in the field of display driving technology and aims to solve the above-mentioned technical problems.

[0077] In a first aspect, this application provides a pixel array, specifically including the following embodiments:

[0078] Figure 1 The diagram shown is a schematic representation of a pixel array provided in an embodiment of this application. Figure 1 ,like Figure 1As shown, pixel array 100 includes N rows of pixels and M columns of data lines. For ease of explanation, only a few adjacent scan lines and a few columns of data lines are shown in the figure. Taking the nth row of pixel array 100 (a horizontal row of pixels) as an example, the nth row of pixel array 100 includes: scan lines 110, auxiliary drive lines 120, logic control unit 130, and pixel circuits 140. Simultaneously, pixel array 100 also includes multiple data lines 150, compensation control terminal 160, and pixel electrode VC.

[0079] Scan line 110 includes the nth scan line Gn and the (n+1)th scan line Gn+1.

[0080] The nth scan line Gn is connected to the input terminal of the logic control unit 130, and the (n+1)th scan line Gn+1 is also connected to the input terminal of the logic control unit 130. The input terminal of the logic control unit 130 is also connected to the compensation control terminal 160. The output terminal of the logic control unit 130 is connected to the auxiliary drive line 120.

[0081] It should be noted that the auxiliary drive line 120 is not the same as the scan line 110. The auxiliary drive line 120 can only output the auxiliary drive signal when the scan signals of the two adjacent scan lines 110 are both indicated as valid.

[0082] An active level refers to a high-level scan signal; an inactive level refers to a low-level scan signal.

[0083] Since the display panel uses a row scanning method, when the logic control unit 130 receives the compensation control signal from the compensation control terminal 160, it will output an auxiliary drive signal to the auxiliary drive line 120 only when both the nth row scan line Gn and the (n+1)th row scan line Gn+1 are at an active level, so that the pixel circuit 140 can establish a corresponding charging path.

[0084] The pixel circuit 140 is connected to the nth scan line Gn, the auxiliary drive line 120, and the data line 150. The output terminal of the pixel circuit 140 is connected to the pixel electrode VC to form a charging path.

[0085] The pixel circuit 140 is configured to, in response to the scan signal output by the nth scan line Gn, establish a first charging circuit between the data line 150 and the pixel electrode VC to perform real charging of the pixel electrode VC; and in response to the auxiliary driving signal of the auxiliary driving line 120, establish a second charging circuit between the data line 150 and the pixel electrode VC to perform auxiliary charging of the pixel electrode VC.

[0086] In display panels, to prevent insufficient charging time, a pre-charging process is typically added before actual charging. This involves the scan signal being active and the data signal from data line 150 being released to charge the pixel electrode VC. The second charging circuit in this application performs pre-charging (auxiliary charging) on ​​the pixel electrode VC.

[0087] The pixel electrode VC and the common electrode VCOM are opposite to each other and together form a pixel capacitor C, which is used to change the deflection state of the liquid crystal molecules after the pixel is charged. Figure 1 In the diagram, solid dots represent connections, and empty dots represent disconnections; this will be used in the following text as well. Each pixel row includes a logic control unit 130 and M pixel circuits 140. In the diagram, Gn represents the nth row of scan line 110, and synchronously, Gn+1 is the (n+1)th row of scan line 110. In the diagram, D1 refers to the first column of data line 150, D2 is the second column, and DM is the Mth column of data line 150.

[0088] This application designs an auxiliary drive line through adjacent scan lines to control the charging circuit corresponding to the pixel circuit. The pixel electrode can be charged through the auxiliary drive line, improving the charging rate of the pixel capacitor. Through the logic control unit, combined with the scan signals of adjacent scan lines, a corresponding auxiliary drive signal is generated, reducing the phenomenon of insufficient opening caused by threshold voltage changes. Through the auxiliary drive signal, the pixel circuit is driven to establish two charging circuits. When the threshold voltage drifts, one of the two charging circuits can be used to double the charging current to charge the pixel capacitor, improving the pixel charging rate.

[0089] In another embodiment, Figure 2 The diagram shown is a schematic of the circuit structure of a pixel array provided in an embodiment of this application. Figure 2 , Figure 2 Is Figure 1 Based on the embodiments, the pixel circuit will be described in detail, such as Figure 2 The diagram shows a schematic of the structure of two adjacent pixel rows, but only the nth pixel row is used as an example for illustration. The pixel circuit 140 includes a pixel transistor T1A and an auxiliary transistor T2A.

[0090] The control terminal of pixel transistor T1A is connected to the nth scan line Gn, the first terminal of pixel transistor T1A is connected to the data line 150, and the second terminal of pixel transistor T1A is connected to the pixel electrode VC.

[0091] When the scan signal of the nth scan line Gn is at an effective level, the pixel transistor T1A is turned on, establishing the first charging circuit. This allows the data signal output from the data line 150 to be transmitted to the pixel electrode VC through the pixel transistor T1A, thereby realizing the charging of the pixel capacitor C corresponding to the pixel electrode VC.

[0092] The control terminal of the auxiliary transistor T2A is connected to the auxiliary drive line 120, the first terminal of the auxiliary transistor T2A is connected to the data line 150, and the second terminal of the auxiliary transistor T2A is connected to the pixel electrode VC.

[0093] Under the control of the auxiliary driving signal output by the auxiliary driving line 120, the auxiliary transistor T2A is turned on, establishing a second charging circuit. This allows the data signal output by the data line 150 to be transmitted to the pixel electrode VC through the auxiliary transistor T2A, thereby achieving auxiliary charging of the pixel capacitor corresponding to the pixel electrode VC.

[0094] This embodiment, through the design of auxiliary transistors and auxiliary driving lines, utilizes the auxiliary driving lines established by two adjacent scan lines to drive the auxiliary transistors to build a second charging circuit, thereby achieving pre-charging of the pixel capacitor. This provides a charging process that differs from that of pixel transistors and can improve the charging rate of the pixel capacitor.

[0095] In another embodiment, Figure 3 The diagram shown is a schematic of the circuit structure of a pixel array provided in an embodiment of this application. Figure 3 ,like Figure 3 As shown, the structural relationship between two adjacent rows of pixels is illustrated. In this embodiment, only the first column of the nth row of pixels is used as an example. The logic control unit 130 includes: a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. Since... Figure 3 The pixel circuit 140 in this embodiment is the same as the pixel circuit 140 in the previous embodiment. The connection method between the scan line 110 and the data line 150 remains unchanged. Even if the solid or empty dots of the pixel circuit 140 are not shown one by one in the figure, the pixel circuit 140 has the same connection method. Figure 3 Only the connection method of the logic control unit 130 is shown in the text.

[0096] The control terminal of the first transistor T1 is connected to the nth scan line Gn, and the first terminal of the first transistor T1 is connected to the first compensation control terminal 161.

[0097] Under the control of the scan signal output by the nth scan line Gn, the first transistor T1 is turned on, and the first compensation control signal output from the first compensation control terminal 161 will be transmitted to the second terminal of the first transistor T1 through the first transistor T1.

[0098] The control terminal of the second transistor T2 is connected to the nth scan line Gn, the first terminal of the second transistor T2 is connected to the second compensation control terminal 162, and the second terminal of the second transistor T2 is connected to the auxiliary drive line 120.

[0099] When the second transistor T2 is turned on under the control of the scan signal output from the nth scan line Gn, the second compensation control signal output from the second compensation control terminal 162 can pass through the second transistor T2.

[0100] It should be noted that the first transistor T1 and the second transistor T2 have opposite conduction characteristics, that is, opposite turn-on voltages. The first transistor T1 is an N-type transistor, and the second transistor T2 is a P-type transistor.

[0101] The control terminal of the third transistor T3 is connected to the (n+1)th scan line Gn+1. The first terminal of the third transistor T3 is connected to the second terminal of the first transistor T1. The second terminal of the third transistor T3 is connected to the auxiliary drive line 120. The second terminal of the third transistor T3 is also connected to the second terminal of the second transistor T2.

[0102] Under the control of the scan signal output from the (n+1)th scan line Gn+1, the third transistor T3 is turned on, so that when the first transistor T1 is turned on, the input first compensation control signal is transmitted to the auxiliary drive line 120 through the third transistor T3.

[0103] The control terminal of the fourth transistor T4 is connected to the (n+1)th scan line Gn+1. The first terminal of the fourth transistor T4 is connected to the second compensation control terminal 162. The second terminal of the fourth transistor T4 is connected to the auxiliary drive line 120. The second terminal of the fourth transistor T4 is also connected to the second terminal of the third transistor T3. The second terminal of the fourth transistor T4 is also connected to the second terminal of the second transistor T2.

[0104] Under the control of the scan signal output from the (n+1)th scan line, the fourth transistor T4 is turned on, so that the second compensation control signal output from the second compensation control terminal 162 is transmitted to the auxiliary drive line.

[0105] It should be noted that the third transistor T3 and the fourth transistor T4 have opposite conduction characteristics, that is, opposite turn-on voltages. The third transistor T3 is an N-type transistor, and the fourth transistor T4 is a P-type transistor.

[0106] The first compensation control signal output from the first compensation control terminal 161 and the second compensation control signal output from the second compensation control terminal 162 are not the same. The first compensation control signal refers to the gate high voltage (VGH) signal, and the second compensation control signal refers to the gate low voltage (VGL) signal.

[0107] In this embodiment, by using a combination of multiple N-type transistors and multiple P-type transistors, an auxiliary drive signal can only be output when both the nth and (n+1)th scan lines are at an active level. This allows the auxiliary transistors to be turned on by the auxiliary drive signal, establishing a second charging path and enabling auxiliary charging of the pixel capacitor.

[0108] In another embodiment, Figure 4 A schematic diagram of a pixel array circuit structure provided in an embodiment of this application. Figure 4 This embodiment is in Figure 1 and Figure 2 Based on the existing embodiments, a new logic control unit 130 is provided. The specific structure of the logic control unit 130 in this embodiment is as follows: Figure 3 The specific structure of the logic control unit 130 in the illustrated embodiments is not the same.

[0109] because Figure 4 The pixel circuit 140 in this embodiment is the same as the pixel circuit 140 in the previous embodiment. The connection method between the scan line 110 and the data line 150 remains unchanged. Even if the solid or empty dots of the pixel circuit 140 are not shown one by one in the figure, the pixel circuit 140 has the same connection method, only differing in that... Figure 4 The connection method of the Lieutenant General Logic Control Unit 130 is shown.

[0110] Because pull-up resistors (large-size resistors) are difficult to manufacture in the display panel industry, they result in slow rise times, occupy a large area, and are detrimental to narrow-bezel panel manufacturing processes. Therefore, this embodiment... Figure 3 The embodiments shown are based on upgrades.

[0111] like Figure 4 As shown, the logic control unit 130 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10.

[0112] The control terminal of the fifth transistor T5 is connected to the nth scan line Gn, and the first terminal of the fifth transistor T5 is connected to the power supply terminal. Under the control of the scan signal output from the nth scan line Gn, the fifth transistor T5 can be turned on.

[0113] The control terminal of the sixth transistor T6 is connected to the nth row of scan line Gn, and the first terminal of the sixth transistor T6 is connected to the second terminal of the fifth transistor T5. Under the control of the scan signal output by the nth row of scan line Gn, the sixth transistor T6 can be turned on.

[0114] Among them, the fifth transistor T5 and the sixth transistor T6 have opposite conduction characteristics, that is, opposite turn-on voltages. The fifth transistor T5 is a P-type transistor; the sixth transistor T6 is an N-type transistor.

[0115] The control terminal of the seventh transistor T7 is connected to the (n+1)th scan line Gn+1. The first terminal of the seventh transistor T7 is connected to the power supply terminal and is also connected to the fifth transistor T5. The second terminal of the seventh transistor T7 is connected to the first terminal of the sixth transistor T6 and is also connected to the second terminal of the fifth transistor T5.

[0116] The seventh transistor T7 is turned on or off under the control of the scan signal output from the (n+1)th scan line Gn+1.

[0117] The control terminal of the eighth transistor T8 is turned on or off under the control of the scan signal output from the (n+1)th scan line Gn+1. The first terminal of the eighth transistor T8 is connected to the second terminal of the sixth transistor T6, and the second terminal of the eighth transistor T8 is connected to the reference ground.

[0118] Among them, the seventh transistor T7 is a P-type transistor, and the eighth transistor T8 is an N-type transistor.

[0119] The control terminal of the ninth transistor T9 is connected to the first terminal of the sixth transistor T6 (the second terminal of the seventh transistor T7), the first terminal of the ninth transistor T9 is connected to the first compensation control terminal 161, and the second terminal of the ninth transistor T9 is connected to the auxiliary drive line 120.

[0120] The control terminal of the tenth transistor T10 is connected to the first terminal of the sixth transistor T6 (the second terminal of the seventh transistor T7). The first terminal of the tenth transistor T10 is connected to the second compensation control terminal 162. The second terminal of the tenth transistor T10 is connected to the second terminal of the ninth transistor T9. That is, the second terminal of the tenth transistor T10 is also connected to the auxiliary drive line 120.

[0121] The voltage output at the first compensation control terminal 161 is a gate high level; the voltage output at the second compensation control terminal 162 is a gate low level.

[0122] Among them, the ninth transistor T9 is a P-type transistor, and the tenth transistor T10 is an N-type transistor.

[0123] This embodiment uses a variety of different transistors to form pull-up and pull-down networks, thereby upgrading and reducing power consumption; and effectively improving the difficulty of implementing pull-up resistors in the display field.

[0124] This application also provides a display panel. Figure 5This is a schematic diagram of the structure of a display panel provided in an embodiment of this application, such as... Figure 5 As shown, the display panel 500 includes a pixel array 100, a temperature detection circuit 510, a timing controller 520, and a power management chip 530.

[0125] The temperature detection circuit 510 is connected to the timing controller 520. The temperature detection circuit 510 is used to detect the display panel temperature or ambient temperature under the current environment. When the display panel temperature or ambient temperature is lower than the preset temperature, a compensation trigger signal is generated and sent to the timing controller 520.

[0126] The actual design location of the temperature detection circuit 510 within the display panel 500 is not fixed. It can be placed on the printed circuit board (PCBA) corresponding to the timing controller 520, or it can be placed inside the panel. Placing it on the PCBA board is more convenient and neater, but when assembled into the whole device, it will interfere with the back panel LEDs, thus affecting temperature detection. Therefore, placing it inside the panel is more reasonable. Thus, the specific design location of the temperature detection circuit 510 is determined according to the user's actual needs, requiring only that it accurately transmits the compensation trigger signal to the timing controller 520.

[0127] It is important to note that Figure 5 The temperature detection circuit 510 shown is located inside the panel and is only an example; it does not represent that there is only one possible location for it. Figure 5 The image only shows the pixel array of two adjacent rows, and does not mean that the pixel array only includes these two rows of pixels.

[0128] The timing controller 520 is connected to the temperature detection circuit 510 and also to the power management chip 530. When the timing controller 520 receives the compensation trigger signal sent by the temperature detection circuit 510, it generates a compensation enable signal and sends it to the power management chip 530.

[0129] The power management chip 530 includes a first compensation control terminal 161 and a second compensation control terminal 162.

[0130] The first compensation control terminal 161 is connected to the pixel array 100, and the first compensation control terminal 161 provides the pixel array 100 with a gate high level VGH; the second compensation control terminal 162 is also connected to the pixel array 100, and the second compensation control terminal 162 provides the pixel array 100 with a gate low level VGL.

[0131] The power management chip 530 is connected to the timing controller 520. When it receives the compensation enable signal transmitted by the timing controller 520, it outputs the voltage corresponding to the compensation enable signal.

[0132] The compensation enable signal includes a first compensation enable signal and a second compensation enable signal. The first compensation enable signal is used to indicate that the power management chip 530 outputs a high gate level VGH, and the second compensation enable signal is used to indicate that the power management chip 530 outputs a low gate level VGL.

[0133] In addition, the display panel 500 also includes a printed circuit board 540, on which a timing controller 520 and a power management chip 530 are disposed. The printed circuit board 540 may also be provided with a temperature detection circuit 510.

[0134] The pixel array 100 includes multiple rows of scan lines 110, multiple rows of auxiliary drive lines 120, and multiple columns of data lines 150. Each column of data lines 150 and each row of scan lines 110 is generated by a corresponding source driver chip and gate driver circuit, and is controlled by a timing controller 520. Figure 5 It was not shown in the document.

[0135] This application provides a display panel with a temperature detection circuit, which can detect the ambient temperature or panel temperature in real time. In low-temperature environments, it can accurately output whether compensation is required, thereby improving the switching performance of the transistors in the pixel array and improving the pixel charging rate in low-temperature environments. Furthermore, the temperature detection circuit can be set inside the panel or on the printed circuit board according to user requirements, adding flexibility.

[0136] In another embodiment, Figure 6 This application provides a schematic diagram of a temperature detection circuit structure for a display panel, as shown in the embodiment. Figure 6 As shown, the temperature detection circuit 510 includes a temperature detection module 511 and a voltage comparison module 512.

[0137] The temperature detection module 511 is used to detect the ambient temperature or panel temperature and convert the detected ambient temperature or panel temperature into the current detected voltage, so that the voltage comparison module 512 can compare and process it.

[0138] The voltage comparison module 512 is connected to the output terminal of the temperature detection module 511; the voltage comparison module 512 is used to output a corresponding compensation trigger signal when the current detected voltage is less than the reference voltage corresponding to the preset temperature.

[0139] The compensation trigger signal is the output signal that drives the timing controller 520 to output the corresponding compensation enable signal when the current detected voltage is lower than the reference voltage corresponding to the preset temperature.

[0140] Upon receiving a compensation trigger signal, the timing controller 520 outputs a corresponding first compensation enable signal (high level), driving the power management chip 530 to output VGH.

[0141] When no compensation trigger signal is received, the timing controller 520 outputs a corresponding second compensation enable signal (low level), which drives the power management chip 530 to output VGL.

[0142] This embodiment divides the temperature detection circuit into two functional modules. The two functional modules perform temperature detection and comparison processing respectively, which effectively improves the accuracy and reliability of the temperature detection results. This provides a more accurate compensation trigger signal for the timing controller, which is beneficial for compensation control in low-temperature environments and improves the working performance of the panel.

[0143] In another embodiment, reference Figure 6 The temperature detection module 511 includes a thermistor NTC, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.

[0144] NTC thermistors are negative temperature coefficient thermistors, meaning their resistance changes with temperature, allowing them to detect voltage changes.

[0145] The first terminal of the thermistor NTC is connected to the power supply terminal EN-VDD.

[0146] The first terminal of the first resistor R1 is connected to the second terminal of the thermistor NTC, and the second terminal of the first resistor R1 is grounded.

[0147] The first end of the second resistor R2 is connected to the power supply terminal EN-VDD, the second end of the second resistor R2 is connected to the second end of the third resistor R3, and the second end of the third resistor R3 is grounded.

[0148] The first end of the fourth resistor R4 is connected to the second end of the second resistor R2.

[0149] The amplifier OPA includes a first input terminal, a second input terminal, and a power input terminal. The positive power input terminal is connected to the power supply terminal EN-VDD, and the negative power input terminal is grounded. The first input terminal of the amplifier OPA is connected to the second terminal of the thermistor NTC (the first terminal of the first resistor R1). The second input terminal of the amplifier OPA is connected to the second terminal of the second resistor R2 (i.e., the first terminal of the third resistor R3 or the first terminal of the fourth resistor R4).

[0150] Since the resistance of the thermistor NTC decreases exponentially with increasing temperature, in this embodiment, the thermistor NTC and a high-precision fixed resistor (first resistor R1) are connected in series and connected to the reference voltage.

[0151] Furthermore, if the voltage value between the thermistor NTC and the first resistor R1 is directly measured, there will be a small voltage change and a DC bias problem. Therefore, an amplifier OPA is added to the temperature detection module 511 as a first-stage operational amplifier to amplify the voltage change, thereby improving the temperature resolution and detection accuracy of the temperature detection module 511. As a result, the amplifier OPA outputs the detection voltage.

[0152] The detected voltage is within the set operating temperature range and has an approximately linear relationship with the temperature, effectively utilizing the operational amplifier's resolution.

[0153] It should be noted that the other resistor settings of the temperature detection module 511 are not fixed, and users can adjust them according to the actual application conditions and status.

[0154] This embodiment utilizes the characteristics of thermistors, combined with high-precision fixed resistance and operational amplifiers, to amplify small voltage changes, thereby improving the detection accuracy and temperature resolution of temperature detection.

[0155] In another embodiment, reference Figure 6 The voltage comparison module 512 includes a fifth resistor R5, a sixth resistor R6, and a comparator CMP.

[0156] The comparator CMP includes a first input terminal and a second input terminal, two power supply input terminals, and an output terminal. The positive power supply input terminal is connected to the power supply terminal EN-VDD, and the negative power supply input terminal is grounded. The first input terminal of the comparator CMP is connected to the output terminal of the temperature detection module 511 (the output terminal of the amplifier OPA). The output terminal of the comparator CMP is connected to the timing controller 520, outputting a compensation trigger signal.

[0157] The comparator CMP is a hysteresis comparator.

[0158] The first terminal of the fifth resistor R5 is connected to the second input terminal of the comparator CMP, and the second terminal of the fifth resistor R5 is connected to the output terminal of the comparator CMP.

[0159] The first terminal of the sixth resistor R6 is connected to the second input terminal of the comparator CMP (the first terminal of the fifth resistor R5), and the second terminal of the sixth resistor R6 is connected to the reference voltage terminal EN-VREF.

[0160] The comparator CMP converts the detected voltage into a defined digital level for subsequent processing. The comparator CMP compares this digital level with a reference voltage corresponding to a preset temperature. When the temperature continues to drop, causing the detected voltage to fall to a minimum threshold, the comparator CMP outputs a compensation trigger signal, causing the timing controller 520 to issue a corresponding first compensation control signal.

[0161] When the temperature rises, causing the detection voltage to increase, and compensation is no longer needed, the comparator CMP does not output a compensation trigger signal, but drives the timing controller 520 to issue a corresponding second compensation control signal to close the compensation charging path.

[0162] This embodiment uses a comparator and multiple resistors to form a two-stage operational amplifier, which continuously monitors the detection voltage output by the temperature detection module and responds promptly to improve the pixel charging rate. By designing a hysteresis comparator, the noise output jitter that may be caused by ordinary comparators is reduced, minimizing the impact of jitter.

[0163] This application also provides a panel driving method. Figure 7 A flowchart illustrating a panel driving method provided in this application embodiment. Figure 1 The panel driving method is a panel driving method provided based on the above-described display panel embodiments, such as... Figure 7 As shown, it specifically includes:

[0164] S701, Get the current temperature of the display panel.

[0165] Specifically, the temperature detection module 511 acquires the current temperature of the display panel in real time.

[0166] Current temperature includes the current ambient temperature or the panel temperature.

[0167] The thermistor (NTC) changes its resistance with temperature, thus providing the current temperature and the corresponding detection voltage.

[0168] S702. When the current temperature is lower than the preset temperature, a compensation control signal is generated.

[0169] Specifically, the voltage comparison module 512 compares the detected voltage corresponding to the current temperature with the reference voltage corresponding to the preset temperature.

[0170] When the current temperature is lower than the preset temperature, the voltage comparison module 512 outputs a compensation trigger signal to the timing controller 520.

[0171] After receiving the compensation trigger signal, the timing controller 520 outputs the first compensation enable signal.

[0172] Similarly, when the current temperature is higher than the preset temperature, the voltage comparison module 512 outputs a low level, causing the timing controller 520 to output a second compensation enable signal.

[0173] S703. Based on the compensation control signal, establish a compensation charging path for the pixel electrode.

[0174] Specifically, according to the first compensation enable signal output by the timing controller 520, the power management chip 530 outputs a corresponding gate high level VGH. Multiple transistors of the pixel array 100 are input to the auxiliary drive line 120 according to the gate high level VGH, thereby controlling the conduction of the auxiliary transistor T2A, establishing a compensation charging path, and performing auxiliary charging on the pixel electrode VC.

[0175] When the second compensation enable signal is output by the timing controller 520, no compensation charging path is established.

[0176] This embodiment provides a new panel driving method through the display panel corresponding to the temperature detection circuit and the pixel array, which effectively improves the phenomenon of insufficient pixel charging rate under low temperature conditions; it can automatically detect the real-time temperature under low temperature conditions to establish a supplementary charging circuit, double the charging current, and charge the pixel capacitor.

[0177] In another embodiment, each pixel row of the display panel includes a scan line 110, an auxiliary drive line 120, a logic control unit 130, a pixel circuit 140, and a data line 150.

[0178] To facilitate the explanation of this embodiment, the method will be described using only the nth row of pixels as an example. Figure 8 A flowchart illustrating a panel driving method provided in this application embodiment. Figure 2 This embodiment is in Figure 1 The illustrated embodiment Figure 5 Display panel embodiments, and Figure 7 Based on the implementation examples of the panel driving method, the specific steps of the panel driving method are explained.

[0179] It should be noted that during the pixel charging process of the array substrate row driving circuit (Gate On Array, GOA), in order to prevent insufficient charging time, a pre-charging process is usually added before the actual charging. That is, the scan signal output by the scan line 110 controls the transistor to turn on and release the data signal of the data line 150 in advance to charge the pixel capacitor.

[0180] Figure 9 A schematic diagram of a charging process is provided for an embodiment of this application, such as... Figure 9 The diagram shows only the scan signals of three adjacent scan lines 110 and the auxiliary drive signals on the auxiliary drive line 120.

[0181] Figure 9 From top to bottom, they are represented as the nth scan line Gn, the (n+1)th scan line Gn+1, the (n+2)th scan line Gn+2, and the auxiliary drive line 120. Figure 9The diagram includes two vertical dashed lines. The first dashed line indicates that when both the nth scan line Gn and the (n+1)th scan line Gn+1 are at a high level, the auxiliary drive signal of the auxiliary drive line 120 becomes high, establishing a second charging path for auxiliary charging, i.e., pre-charging. The second dashed line indicates that when the nth scan line Gn drops to a low level, the auxiliary drive signal of the auxiliary drive line 120 becomes low, and auxiliary charging ceases.

[0182] Figure 9 The first bidirectional arrow within the waveform represents the pre-charging process t1, and the second bidirectional arrow represents the actual charging process t2. Therefore... Figure 9 It is known that the auxiliary drive signal of the auxiliary drive line 120 is only output by the two adjacent scan lines 110, and the auxiliary drive signal is only output when both adjacent scan lines 110 are at an effective level, thereby establishing a second charging path.

[0183] Based on this, this embodiment provides a new panel driving method, specifically including:

[0184] S801, Get the current temperature of the display panel.

[0185] S802. When the current temperature is lower than the preset temperature, a compensation control signal is generated.

[0186] S801 and S802 operate on the same principle as S701 and S702, and will not be elaborated upon here.

[0187] S803, the logic control unit responds to the compensation control signal and outputs an auxiliary drive signal to the auxiliary drive line when both the current row scan signal and the next row scan signal are at an active level.

[0188] Specifically, in response to the compensation control signal at this time, the logic control unit 130 turns on the input terminal corresponding to the auxiliary drive line 120.

[0189] When the scan signal output from the nth scan line Gn is at an effective level, and the scan signal output from the (n+1)th scan line Gn+1 is also at an effective level, a high-level auxiliary drive signal will be output to the auxiliary drive line 120.

[0190] The scanning signals of the nth scan line Gn and the (n+1)th scan line Gn+1 have a one-to-one correspondence with the auxiliary drive signals above the auxiliary drive line 120, as shown in Table 1 below.

[0191] Table 1 is a table showing the correspondence between logical relation states.

[0192]

[0193] As shown in Table 1 and Figure 9As shown, the auxiliary drive signal on the auxiliary drive line 120 is jointly output by the two adjacent scan lines 110. The high-level auxiliary drive signal is only output when the scan signals output by the two adjacent scan lines 110 are both at an effective level.

[0194] S804: The pixel circuit responds to the current row scan signal to establish a first charging path from the data line to the pixel electrode; and responds to the auxiliary drive signal to establish a second charging path from the data line to the pixel electrode.

[0195] Specifically, in response to the current row scan signal, the pixel circuit 140 establishes a first charging path from the data line 150 to the pixel electrode. The first charging path includes the pixel transistor T1A, which corresponds to the actual charging path.

[0196] In response to an auxiliary drive signal, pixel circuit 140 establishes a second charging path from the data line to the pixel electrode. The second charging path includes an auxiliary transistor T2A, corresponding to the pre-charging path.

[0197] To facilitate the explanation of this application, two specific embodiments are introduced herein, respectively... Figure 3 Corresponding embodiments and Figure 4 The corresponding implementation examples are described below.

[0198] First scenario: Assuming the temperature detection circuit 510 detects that the temperature is lower than the preset temperature, the timing controller 520 outputs the first compensation enable signal.

[0199] refer to Figure 3 If the logic control unit 130 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4, then the specific driving method includes:

[0200] When the scan signals output from the nth scan line Gn and the (n+1)th scan line Gn+1 are both at valid levels, the first transistor T1 and the third transistor T3 are turned on, while the second transistor T2 and the fourth transistor T4 are turned off. The first terminal of the first transistor T1 receives the gate high level VGH input from the first compensation control terminal 161, and through the first transistor T1 and the third transistor T3, outputs a high-level auxiliary drive signal.

[0201] The auxiliary drive signal turns on the auxiliary transistor T2A, establishing a second charging path and transmitting the data signal from the data line 150 to the pixel electrode VC in advance, thus providing auxiliary charging for the pixel electrode VC.

[0202] Then, the scanning signal output by the nth scan line Gn turns on the pixel transistor T1A, establishes the first charging path, and transmits the data signal output by the data line 150 to the pixel electrode VC to actually charge the pixel capacitor.

[0203] refer to Figure 4 If the logic control unit 130 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10, then the specific driving method includes:

[0204] When the scan signals output from the nth scan line Gn and the (n+1)th scan line Gn+1 are both at valid levels, the fifth transistor T5 and the seventh transistor T7 are turned off, while the sixth transistor T6 and the eighth transistor T8 are turned on.

[0205] The high voltage at the first terminal of the corresponding fifth transistor T5 and the seventh transistor T7 is cut off, and the low voltage at the second terminal of the sixth transistor T6 and the eighth transistor T8 is transmitted to the control terminal of the ninth transistor T9.

[0206] When the ninth transistor T9 is turned on and the tenth transistor T10 is turned off, the first compensation control terminal 161 connected to the first terminal of the ninth transistor T9 inputs a high level VGH, which is transmitted to the auxiliary drive line 120 as an auxiliary drive signal.

[0207] The auxiliary drive signal turns on the auxiliary transistor T2A connected to the auxiliary drive line 120, establishing a second charging path, so that the data signal output from the data line 150 is transmitted to the pixel electrode VC to perform auxiliary charging of the pixel electrode.

[0208] Then, the scanning signal output by the nth scan line Gn turns on the pixel transistor T1A, establishes the first charging path, and transmits the data signal output by the data line 150 to the pixel electrode VC to actually charge the pixel electrode VC.

[0209] The second scenario: Assuming that the temperature detection circuit 510 detects that the temperature is higher than the preset temperature, the timing controller 520 outputs the second compensation enable signal, that is, the second compensation control terminal 162 outputs the gate low level VGL.

[0210] The second compensation enable signal indicates that there is no need to establish a second charging path; charging can be achieved solely through the first charging path.

[0211] refer to Figure 3 When the scan line Gn in the nth row is not at an effective level, the first transistor T1 is turned off and the second transistor T2 is turned on. Then, the output VGL of the second transistor T2 and the connected second compensation control terminal 162 will be transmitted to the auxiliary drive line 120 as an auxiliary drive signal, and the auxiliary transistor T2A will be turned off, thus shutting down the auxiliary charging process.

[0212] And / or, when the scan line Gn+1 in the (n+1)th row is not at an effective level, the third transistor T3 is turned off and the fourth transistor T4 is turned on. Then, the VGL output by the third transistor T3 and the connected second compensation control terminal 162 will be transmitted to the auxiliary drive line 120 as an auxiliary drive signal, and the auxiliary transistor T2A will be turned off, thus shutting down the auxiliary charging process.

[0213] refer to Figure 4 When the nth scan line Gn is not at an active level, the fifth transistor T5 is turned on and the sixth transistor T6 is turned off. The high-level voltage VDD output from the power supply terminal EN-VDD by the fifth transistor T5 will be transmitted to the control terminals of the ninth transistor T9 and the tenth transistor T10. When the ninth transistor T9 is turned off and the tenth transistor T10 is turned on, the VGL input from the first terminal of the tenth transistor T10 and the connected second compensation control terminal 162 will be transmitted as an auxiliary drive signal to the auxiliary drive line 120. The auxiliary transistor T2A will then be turned off, shutting down the auxiliary charging process.

[0214] And / or, when the (n+1)th scan line Gn+1 is not at an active level, the seventh transistor T7 is turned on and the eighth transistor T8 is turned off. Then, the high-level voltage VDD output by the seventh transistor T7 and the power supply terminal EN-VDD will be transmitted to the control terminals of the ninth transistor T9 and the tenth transistor T10. When the ninth transistor T9 is turned off and the tenth transistor T10 is turned on, the VGL input from the first terminal of the tenth transistor T10 and the connected second compensation control terminal 162 will be transmitted as an auxiliary drive signal to the auxiliary drive line 120. The auxiliary transistor T2A will be turned off, shutting down the auxiliary charging process.

[0215] This embodiment improves the working state of the display panel under low temperature conditions by detecting the temperature of the temperature detection circuit and using the general pre-charging principle. During the pixel charging process, it provides a charging path independent of the original pixel transistor to achieve auxiliary charging of the pixel capacitor and reduce the phenomenon of insufficient opening caused by low temperature negative drift, which leads to a decrease in pixel charging rate.

[0216] Furthermore, the terms "first," "second," "third," "fourth," "fifth," "sixth," "seventh," "eighth," "ninth," and "tenth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature specified with "first," "second," "third," "fourth," "fifth," "sixth," "seventh," "eighth," "ninth," and "tenth" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0217] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0218] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A pixel array, characterized in that, The pixel array comprises N rows of pixels and M columns of data lines, wherein the nth row of pixels includes: Scan lines; Auxiliary drive line; A logic control unit, wherein the input terminals of the logic control unit are respectively connected to the nth scan line, the (n+1)th scan line and the compensation control terminal, and the output terminal of the logic control unit is connected to the auxiliary drive line. The logic control unit is configured to: in response to the compensation control signal output by the compensation control terminal, when both the nth scan signal and the (n+1)th scan signal are at an active level, output an auxiliary drive signal to the auxiliary drive line. M pixel circuits, each pixel circuit being connected to the corresponding scan line, data line, auxiliary drive line, and pixel electrode, and the pixel circuits being configured to: in response to the nth row scan signal, establish a first charging path from the data line to the pixel electrode; and in response to the auxiliary drive signal, establish a second charging path from the data line to the pixel electrode.

2. The pixel array according to claim 1, characterized in that, The pixel circuit includes: A pixel transistor, wherein the control terminal of the pixel transistor is connected to the nth row of scan lines, the first terminal of the pixel transistor is connected to the data line, and the second terminal of the pixel transistor is connected to the pixel electrode; An auxiliary transistor is provided, wherein the control terminal of the auxiliary transistor is connected to the auxiliary driving line, the first terminal of the auxiliary transistor is connected to the data line, and the second terminal of the auxiliary transistor is connected to the pixel electrode.

3. The pixel array according to claim 1, characterized in that, The logic control unit includes: A first transistor, the control terminal of the first transistor is connected to the nth row of scan lines, and the first terminal of the first transistor is connected to the first compensation control terminal; The second transistor has a control terminal connected to the nth row of scan lines, a first terminal connected to the second compensation control terminal, and a second terminal connected to the auxiliary drive line. The third transistor has its control terminal connected to the (n+1)th scan line, its first terminal connected to the second terminal of the first transistor, and its second terminal connected to the second terminal of the second transistor. The fourth transistor has its control terminal connected to the (n+1)th scan line, its first terminal connected to the first terminal of the second transistor, and its second terminal connected to the second terminal of the third transistor. The first and third transistors are both N-type transistors, and the second and fourth transistors are both P-type transistors.

4. The pixel array according to claim 1, characterized in that, The logic control unit includes: The fifth transistor, wherein the control terminal of the fifth transistor is connected to the nth row of scan lines, and the first terminal of the fifth transistor is connected to the power supply terminal; The sixth transistor, wherein the control terminal of the sixth transistor is connected to the nth row of scan lines, and the first terminal of the sixth transistor is connected to the second terminal of the fifth transistor; The seventh transistor has its control terminal connected to the (n+1)th scan line, its first terminal connected to the first terminal of the fifth transistor, and its second terminal connected to the first terminal of the sixth transistor. The eighth transistor has its control terminal connected to the (n+1)th scan line, its first terminal connected to the second terminal of the sixth transistor, and its second terminal grounded. The ninth transistor has a control terminal connected to the first terminal of the sixth transistor, and the first terminal of the ninth transistor is connected to the first compensation control terminal. The tenth transistor has a control terminal connected to the control terminal of the ninth transistor, a first terminal connected to a second compensation control terminal, and a second terminal connected to the second terminal of the ninth transistor. The fifth, seventh, and ninth transistors are all P-type transistors, while the sixth, eighth, and tenth transistors are all N-type transistors.

5. A display panel, characterized in that, The display panel includes: The pixel array according to any one of claims 1-4; A temperature detection circuit is configured to detect the current temperature of the display panel and generate a compensation trigger signal when the current temperature is lower than a preset temperature. A timing controller, connected to the temperature detection circuit, is configured to output a compensation enable signal according to the compensation trigger signal; The power management chip, connected to the timing controller and the logic control unit of the pixel array, is configured to generate a corresponding compensation control signal based on the compensation enable signal, so that the logic control unit responds to the compensation control signal to establish a second charging path for the pixel circuit.

6. The display panel according to claim 5, characterized in that, The temperature detection circuit includes: The temperature detection module is configured to detect the current ambient temperature and convert the current ambient temperature into a current detection voltage; A voltage comparison module, connected to the output of the temperature detection module, is configured to output the compensation trigger signal when the current detected voltage is less than the reference voltage corresponding to the preset temperature.

7. The display panel according to claim 6, characterized in that, The temperature detection module includes: A thermistor, wherein the first end of the thermistor is connected to a power supply terminal; A first resistor, the first end of which is connected to the second end of the thermistor, and the second end of the first resistor is grounded; An amplifier, wherein the first input terminal of the amplifier is connected to the second terminal of the thermistor; The second resistor has a first end connected to the power supply terminal and a second end connected to the second input terminal of the amplifier. The third resistor has its first end connected to the second end of the second resistor, and the second end of the third resistor is grounded. A fourth resistor, the first end of which is connected to the second end of the second resistor, and the second end of which is connected to the output terminal of the amplifier.

8. The display panel according to claim 6, characterized in that, The voltage comparison module includes: A comparator, wherein the first input terminal of the comparator is connected to the output terminal of the temperature detection module, and the output terminal of the comparator is connected to the timing controller; The fifth resistor has its first end connected to the second input terminal of the comparator and its second end connected to the output terminal of the comparator. The sixth resistor has its first end connected to the second input terminal of the comparator and its second end connected to the reference voltage terminal.

9. A panel driving method, characterized in that, Applied to the display panel according to any one of claims 5-8, the panel driving method includes: Obtain the current temperature of the display panel; When the current temperature is lower than the preset temperature, a compensation control signal is generated; A compensation charging path is established for the pixel electrode according to the compensation control signal.

10. The panel driving method according to claim 9, characterized in that, Each row of pixels in the display panel includes a scan line, an auxiliary driving line, a logic control unit, and a pixel circuit. Based on the compensation control signal, a compensation charging path is established for the pixel circuit, including: In response to the compensation control signal, the logic control unit outputs an auxiliary drive signal to the auxiliary drive line when both the current row scan signal and the next row scan signal are at an active level. The pixel circuit responds to the current row scan signal to establish a first charging path from the data line to the pixel electrode; and responds to the auxiliary drive signal to establish a second charging path from the data line to the pixel electrode. The second charging path is a compensation charging path.

Images