Shield gate trench MOSFET device and preparation method thereof

Abstract

According to the shield gate trench MOSFET device and the preparation method thereof provided by the invention, the first contact hole and the second contact hole with different densities are manufactured in the interlayer dielectric layer of the cellular region, and the distribution density of the first contact hole is low, so that the ion concentration of the channel region of the cell where the first contact hole is located is low, and the threshold voltage is also low; the distribution density of the second contact holes is high, the channel ion concentration of the cells where the second contact holes are located is high, and the threshold voltage is also high, so that when the MOS device works, the cells with low threshold voltage are firstly started to conduct electricity, the cells with high threshold voltage are then started, the later started cells can serve as heat dissipation channels through the time-sharing starting mechanism, heat is dissipated for the cells started firstly, and the heat dissipation efficiency of the MOS device is improved. According to the preparation method, only the layout design of the contact hole mask needs to be adjusted, additional process steps do not need to be added, the reliability of the MOS device is improved, and the application range of the MOS device is widened with extremely low cost.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing, and particularly relates to a shielded gate trench MOSFET device and its fabrication method. Background Technology

[0002] Power devices, used in power management, power transmission, and high-speed switching control, can be categorized into several types based on their operating principles, including junction field-effect transistors (JFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), and thyristors (SCRs). Among metal-oxide-semiconductor field-effect transistors, the shielded gate trench MOSFET (SGT MOS) is an improvement over the traditional deep trench MOSFET. It reduces the gate-drain overlap area and gate-drain capacitance by adding a polysilicon electrode (called the shielded gate) below the gate electrode, thereby increasing switching speed, reducing dynamic losses, increasing cell density, and decreasing on-resistance. Therefore, it is widely used in low- and medium-voltage applications such as motor drives, power management, synchronous rectification, and energy storage control.

[0003] Due to factors such as chip area, cell design, and packaging performance, shielded trench MOS devices have an energy range within which they can safely handle drain-source voltage and drain current, known as the SOA (Safe Operating Area). However, with the continuous changes and development of the application environment for shielded trench MOS devices, on the one hand, there is a requirement for shielded trench MOS devices to have lower conduction losses; on the other hand, there is a requirement for shielded trench MOS devices to operate for longer periods under high voltage and high current, that is, to have better SOA performance.

[0004] Existing shielded trench MOS devices have poor SOA performance and only have one type of source contact hole. Moreover, the source contact hole is generally located in the central region between adjacent trenches, which means that different cells in the shielded trench MOS device have the same threshold voltage. This results in the shielded trench MOS device being applicable only to circuits with specific requirements, limiting its application range. Furthermore, changes in ambient temperature and the heat generated during operation can increase the operating resistance of the shielded trench MOS device, generating more heat. Ultimately, poor heat dissipation may lead to the shielded trench MOS device burning out.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a shielded gate trench MOSFET device and its preparation method, so as to solve the problems of poor SOA performance, limited application range, and poor heat dissipation leading to burnout of shielded gate trench MOSFET devices in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating a shielded gate trench MOSFET device, comprising the following steps:

[0008] A semiconductor substrate having an epitaxial layer is provided, wherein trenches are formed in the epitaxial layer at intervals along the X direction, and the trenches extend downward from the upper surface of the epitaxial layer along the Y direction;

[0009] A dielectric material layer and a conductive material layer are sequentially formed in the trench. The dielectric material layer is located on the inner wall and bottom surface of the trench and wraps around the side wall and bottom surface of the conductive material layer. The upper surface of the dielectric material layer is lower than the upper surface of the epitaxial layer.

[0010] A gate dielectric layer and a gate conductive layer are sequentially formed on the surface of the dielectric material layer, wherein the gate dielectric layer covers the sidewalls of the trench and wraps the sidewalls and bottom surface of the gate conductive layer;

[0011] An interlayer dielectric layer is formed on the gate dielectric layer and the epitaxial layer, and the interlayer dielectric layer is etched to form a plurality of first contact holes and a plurality of second contact holes penetrating the interlayer dielectric layer. The plurality of first contact holes are arranged sequentially along the Z direction at a first interval distance, and the plurality of second contact holes are arranged sequentially along the Z direction at a second interval distance. The X direction, the Y direction and the Z direction are perpendicular to each other.

[0012] Metal is deposited on the interlayer dielectric layer to form a source electrode that fills the first contact hole and the second contact hole.

[0013] Optionally, the first contact hole and the second contact hole are located in the central region between two adjacent grooves, and the first contact hole and the plurality of second contact holes are arranged alternately along the X direction.

[0014] Optionally, the lateral width of the second contact hole is equal to the lateral width of the first contact hole, and the lateral widths of both the first and second contact holes are 0.2~0.6μm.

[0015] Optionally, the plurality of first contact holes have the same size, and the first spacing distance is 250~500nm.

[0016] Optionally, the plurality of second contact holes have the same size, and the second spacing distance is 50~200nm.

[0017] Optionally, the dimension of a single first contact hole along the Z direction is larger than the dimension of a single second contact hole along the Z direction.

[0018] Optionally, the width of the groove is 0.8~1.2μm, and the spacing between adjacent grooves is 2.4~3μm.

[0019] Optionally, after forming the gate conductive layer, the method further includes forming a second conductivity type body region and a first conductivity type source region, wherein the body region is located on the epitaxial layer between two adjacent trenches in the X direction, and the source region is located on the body region.

[0020] Optionally, after forming the source, the method further includes forming a passivation layer, etching the passivation layer to form metal leads, and forming a drain, wherein the passivation layer is located on the surface of the source, and the drain is electrically connected to the back side of the semiconductor substrate.

[0021] The present invention also provides a shielded gate trench MOSFET device, comprising:

[0022] A semiconductor substrate and an epitaxial layer disposed on the semiconductor substrate;

[0023] At least one cell unit is located in the epitaxial layer, the cell unit including trenches spaced apart along the X direction and extending downward from the upper surface of the epitaxial layer along the Y direction;

[0024] A shielding grid, comprising a dielectric material layer and a conductive material layer, wherein the dielectric material layer is located on the inner wall and bottom surface of the trench, the dielectric material layer wraps around the sidewall and bottom surface of the conductive material layer, and the upper surface of the dielectric material layer is lower than the upper surface of the epitaxial layer;

[0025] A trench gate structure, comprising a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer is located on the inner wall of the trench and the upper surface of the dielectric material layer and wraps around the sidewalls and bottom surface of the gate conductive layer;

[0026] A second conductivity type body region and a first conductivity type source region, wherein the body region is located on the upper surface of the epitaxial layer, and the source region is located on the upper surface of the body region and is flush with the upper surface of the trench gate structure;

[0027] An interlayer dielectric layer is located on the upper surface of the source region. The interlayer dielectric layer has a plurality of first contact holes and a plurality of second contact holes that penetrate the source region and expose the body region. The plurality of first contact holes are arranged sequentially along the Z direction at a first interval distance, and the plurality of second contact holes are arranged sequentially along the Z direction at a second interval distance. The X direction, the Y direction and the Z direction are perpendicular to each other. The size of the plurality of first contact holes along the Z direction is larger than the size of the plurality of second contact holes along the Z direction, and the first interval distance is larger than the second interval distance.

[0028] The source electrode is located on the interlayer dielectric layer and fills the first contact hole and the second contact hole.

[0029] As described above, the shielded gate trench MOSFET device and its fabrication method of the present invention, by forming a plurality of first contact holes and a plurality of second contact holes of different sizes along the Z direction in the interlayer dielectric layer between adjacent trenches, and the first spacing distance of the plurality of first contact holes along the Z direction is greater than the second spacing distance of the plurality of second contact holes along the Z direction, results in a low density of first contact holes in the cell containing the first contact holes, a low ion concentration in the region between the first contact holes and the channel, and a low threshold voltage; conversely, a high density of second contact holes in the cell containing the second contact holes, a high ion concentration in the region between the second contact holes and the channel, and a high threshold voltage. When the shielded gate trench MOSFET device is working, the channels with different threshold voltages are turned on sequentially. The time-division multiplexing mechanism mentioned above allows the cells with higher threshold voltages that are turned on later to also serve as heat dissipation channels for the channels with higher threshold voltages that are turned on earlier. This not only increases the SOA performance of the shielded gate trench MOSFET device and expands its application range, but also improves the heat dissipation performance of the shielded gate trench MOSFET device. Moreover, the fabrication method of this shielded gate trench MOSFET device can be achieved simply by changing the mask pattern design for forming the first contact hole and the second contact hole. It does not require additional photolithography steps or complex processes, and hardly increases the manufacturing cost. Attached Figure Description

[0030] Figure 1 The diagram shows the process flow of the fabrication method of the shielded gate trench MOSFET device of the present invention.

[0031] Figure 2 The diagram shows a cross-sectional structure after a trench is formed in the epitaxial layer according to the present invention.

[0032] Figure 3 The diagram shows a cross-sectional structure after a dielectric material layer and a conductive material layer are formed in the trench according to the present invention.

[0033] Figure 4 The diagram shows a cross-sectional structure after etching the dielectric and conductive material layers.

[0034] Figure 5 The diagram shows a cross-sectional view of the structure after the gate dielectric layer and the gate conductive layer are formed in the trench according to the present invention.

[0035] Figure 6 The diagram shows a cross-sectional structure after etching the gate dielectric layer and the gate conductive layer.

[0036] Figure 7 The diagram shows a cross-sectional structure after the body region and the source region are formed on the epitaxial layer in this invention.

[0037] Figure 8 The diagram shown is a cross-sectional view of the structure after the interlayer dielectric layer is formed in this invention.

[0038] Figure 9 The diagram shows a cross-sectional structure after the formation of the first and second contact holes in this invention.

[0039] Figure 10 The diagram shown is a top view of the structure after the first and second contact holes are formed in this invention.

[0040] Figure 11 The diagram shown is a cross-sectional view of the source electrode after it has been formed in this invention.

[0041] Figure 12 The diagram shown is a cross-sectional view of the structure after the passivation layer and drain electrode are formed in this invention.

[0042] Explanation of icon numbers

[0043] 110. Semiconductor substrate; 111. Epitaxial layer; 112. Trench; 113. Dielectric material layer; 114. Conductive material layer; 115. Gate dielectric layer; 116. Gate conductive layer; 117. Body region; 118. Source region; 119. Interlayer dielectric layer; 120. First contact hole; 121. Second contact hole; 124. Source electrode; 125. Passivation layer; 126. Drain electrode; S1~S5. Steps. Detailed Implementation

[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0046] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0047] Please see Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0048] Example 1

[0049] This embodiment provides a method for fabricating a shielded gate trench MOSFET device, such as... Figure 1 The diagram shown illustrates the process flow of the fabrication method for the shielded gate trench MOSFET device, including the following steps:

[0050] S1: A semiconductor substrate 110 having an epitaxial layer 111 is provided, wherein trenches 112 spaced apart along the X direction are formed in the epitaxial layer 111, and the trenches 112 extend downward from the upper surface of the epitaxial layer 111 along the Y direction.

[0051] S2: A dielectric material layer 113 and a conductive material layer 114 are sequentially formed in the trench 112. The dielectric material layer 113 is located on the inner wall and bottom surface of the trench 112 and wraps around the side wall and bottom surface of the conductive material layer 114. The upper surface of the dielectric material layer 113 is lower than the upper surface of the epitaxial layer 111.

[0052] S3: A gate dielectric layer 115 and a gate conductive layer 116 are sequentially formed on the surface of the dielectric material layer 113. The gate dielectric layer 115 covers the sidewall of the trench 112 and wraps the sidewall and bottom surface of the gate conductive layer 116.

[0053] S4: An interlayer dielectric layer 119 is formed on the gate dielectric layer 115 and the epitaxial layer 111, and the interlayer dielectric layer 119 is etched to form a plurality of first contact holes 120 and a plurality of second contact holes 121 penetrating the interlayer dielectric layer 119. The plurality of first contact holes 120 are arranged sequentially along the Z direction at a first interval distance, and the plurality of second contact holes 121 are arranged sequentially along the Z direction at a second interval distance. The X direction, the Y direction and the Z direction are perpendicular to each other.

[0054] S5: Deposit metal on the interlayer dielectric layer 119 to form a source 124 that fills the first contact hole 120 and the second contact hole 121.

[0055] Specifically, since the shielded gate trench MOSFET device can be an N-type device or a P-type device, in this embodiment, the N-type device will be used as an example for detailed explanation. That is, the first conductivity type is N-type and the second conductivity type is P-type. When the shielded gate trench MOSFET device is a P-type device, it is only necessary to interchange the corresponding N-type and P-type devices.

[0056] The fabrication method of the shielded gate trench MOSFET device of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0057] like Figure 2 As shown, in step S1, a semiconductor substrate 110 having an epitaxial layer 111 is provided, and trenches 112 spaced apart along the X direction are formed in the epitaxial layer 111, the trenches 112 extending downward from the upper surface of the epitaxial layer 111 along the Y direction.

[0058] Specifically, such as Figure 2The diagram shows a cross-sectional view of the semiconductor substrate 110. In this embodiment, the semiconductor substrate 110 is an N-type semiconductor substrate 110, and an N-type epitaxial layer 111 is formed on the front side of the semiconductor substrate 110. While ensuring device performance, the thickness, size, doping concentration, and shape of the semiconductor substrate 110 can be selected according to actual conditions and are not limited here. The thickness, size, doping concentration, and shape of the epitaxial layer 111 can be selected according to actual conditions and are not limited here.

[0059] Optionally, in this embodiment, the semiconductor substrate 110 can be an N+ type doped silicon substrate, a germanium silicon substrate, a silicon carbide substrate, etc., and the epitaxial layer 111 is selected as a single-crystal silicon epitaxial layer 111 of the first conductivity type. Before performing subsequent processes, the semiconductor substrate 110 can be cleaned, for example, by sequentially cleaning with an organic solvent such as acetone and deionized water to remove contaminants from the surface of the semiconductor substrate 110, followed by drying; or by first removing the natural oxide layer on the surface of the semiconductor substrate 110 with a diluted acid solution, then cleaning with deionized water, and finally drying; or by performing multiple cleanings using the aforementioned methods.

[0060] Furthermore, such as Figure 2 As shown, a plurality of trenches 112 are formed in the epitaxial layer 111 at intervals along the X direction. The trenches 112 extend downward from the upper surface of the epitaxial layer 111 along the Y direction. The number and depth of the trenches 112 can be selected according to actual conditions while ensuring device performance, and are not limited here. The width of the trenches 112 is 0.8~1.2μm, for example, the width of the trenches 112 is 0.8μm, 1μm or 1.2μm. The spacing between adjacent trenches 112 is 2.4~3μm, for example, the spacing between adjacent trenches 112 is 2.4μm, 2.6μm or 3μm. The specific steps for forming multiple trenches 112 spaced apart along the X-direction are as follows: First, a hard mask layer is formed on the upper surface of the epitaxial layer 111. The mask layer includes, but is not limited to, an oxide layer, a silicon nitride layer, or other suitable film layers. Using the hard mask layer, the regions where the trenches 112 to be formed are defined by photolithography, thereby etching out the desired trenches 112. After forming the trenches 112, residual hard mask layers are removed using processes including, but not limited to, etching. Specific implementation methods of the photolithography and etching processes can be achieved using conventional methods known to those skilled in the art, and are not specifically limited here.

[0061] like Figure 3 and Figure 4As shown, in step S2, a dielectric material layer 113 and a conductive material layer 114 are sequentially formed in the trench 112. The dielectric material layer 113 is located on the inner wall and bottom surface of the trench 112 and wraps around the side wall and bottom surface of the conductive material layer 114. The upper surface of the dielectric material layer 113 is lower than the upper surface of the epitaxial layer 111.

[0062] Specifically, such as Figure 3 The diagram shows a cross-sectional structure after a dielectric material layer 113 and a conductive material layer 114 of a certain thickness have been grown on the surface of the epitaxial layer 111 and the inner wall of the trench 112. The methods for forming the dielectric material layer 113 and the conductive material layer 114 include chemical vapor deposition, physical vapor deposition or other suitable methods.

[0063] Specifically, the dielectric material layer 113 can be a high-k dielectric layer, including but not limited to silicon oxide, silicon nitride, aluminum oxide or other suitable dielectric materials, and the conductive material layer 114 is made of polycrystalline silicon.

[0064] Specifically, while ensuring device performance, the thickness of the dielectric material layer 113 covering the inner wall of the trench 112 can be selected according to the actual situation, and is not limited here.

[0065] like Figure 4 As shown, the dielectric material layer 113 and the conductive material layer 114 within the trench 112 are etched to obtain the shielding gate layer of a preset height. Specifically, while ensuring device performance, the height of the shielding gate layer can be selected according to actual conditions, and is not limited here. The height here refers to the distance between the bottom surface of the shielding gate layer and the top surface of the shielding gate layer.

[0066] Specifically, such as Figure 4 As shown, anisotropic etching is performed on the dielectric material layer 113 and the conductive material layer 114 so that the upper surface of the dielectric material layer 113 is lower than the upper surface of the epitaxial layer 111. Then, the dielectric material layer 113 and the conductive material layer 114 are planarized, or CMP process is directly used to make the dielectric material layer 113 and the conductive material layer 114 located in the trench 112 have the same height. Both of the above processing methods can make the dielectric material layer 113 and the conductive material layer 114 have flush surfaces. The planarization process can include mechanical polishing or CMP, which is not excessively limited here.

[0067] Optionally, after anisotropic etching and planarization of the dielectric material layer 113 and the conductive material layer 114, the dielectric material layer 113 needs to be deposited again on the surface of the dielectric material layer 113 and the conductive material layer 114, so that the dielectric material layer 113 is located on the inner wall and bottom surface of the trench 112 and wraps the side wall and bottom surface of the conductive material layer 114.

[0068] like Figure 5 and Figure 6 As shown, in step S3, a gate dielectric layer 115 and a gate conductive layer 116 are sequentially formed on the surface of the dielectric material layer 113. The gate dielectric layer 115 covers the sidewall of the trench 112 and wraps the sidewall and bottom surface of the gate conductive layer 116.

[0069] Specifically, such as Figure 5 The diagram shows a cross-sectional structure after the gate dielectric layer 115 and the gate conductive layer 116 of a certain thickness are grown on the surface of the epitaxial layer 111 and the inner wall of the trench 112. The methods for forming the gate dielectric layer 115 and the gate conductive layer 116 include thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0070] Specifically, the gate dielectric layer 115 can be a high-k dielectric layer, including but not limited to silicon oxide, silicon nitride, aluminum oxide or other suitable dielectric materials, and the gate conductive layer 116 is made of polycrystalline silicon.

[0071] Specifically, forming the gate dielectric layer 115 and the gate conductive layer 116 includes the following steps: forming a gate dielectric layer 115 covering the surface of the dielectric material layer 113, the sidewalls of the trench 112, and the upper surface of the epitaxial layer 111; and then forming the gate conductive layer 116 in the trench 112 in the middle of the gate dielectric layer 115 and on the upper surface of the epitaxial layer 111; as shown Figure 6 As shown, the gate dielectric layer 115 and the gate conductive layer 116 are subjected to anisotropic etching and planarization to obtain a trench gate structure located in the trench 112.

[0072] Specifically, the planarization methods for the gate dielectric layer 115 and the gate conductive layer 116 include chemical mechanical polishing, dry etching, wet etching, or other suitable methods.

[0073] Specifically, while ensuring device performance, the thickness of the gate dielectric layer 115 covering the inner wall of the trench 112 can be selected according to the actual situation, and is not limited here.

[0074] As an example, after forming the gate conductive layer 116 and before forming the interlayer dielectric layer 119, the method further includes forming a second conductivity type body region 117 and a first conductivity type source region 118, wherein the body region 117 is located on the epitaxial layer 111 between two adjacent trenches 112 in the X direction, and the source region 118 is located on the body region 117.

[0075] Specifically, in this embodiment, such as Figure 7 As shown, the body region 117 is a body region of the second conductivity type. The method for forming the body region 117 of the second conductivity type includes ion implantation and high-temperature annealing. For example, ion implantation can be used to implant second conductivity type impurities into the top of the epitaxial layer 111 doped with the first conductivity type on both sides of the trench 112, and then a high-temperature annealing process can be performed to invert the top of the epitaxial layer 111 doped with the first conductivity type into the body region 117 of the second conductivity type. The body region 117 is isolated from the gate conductive layer 116 through the gate dielectric layer 115.

[0076] Specifically, while ensuring device performance, the doping concentration and thickness of the body region 117 can be selected according to actual conditions, and are not limited here. The thickness here refers to the distance between the lower surface and the upper surface of the body region 117.

[0077] Specifically, the source region 118 is a first conductivity type source region 118. The method for forming the first conductivity type source region 118 includes ion implantation and high-temperature annealing. For example, ion implantation can be used to implant first conductivity type impurities into the top of the second conductivity type body region 117, followed by a high-temperature annealing process to reverse the top of the second conductivity type body region 117 into the first conductivity type source region 118 again. The final formed first conductivity type source region 118 has a flush surface with the gate dielectric layer 115. The source region 118 and the gate conductive layer 116 are isolated by the gate dielectric layer 115.

[0078] Specifically, while ensuring device performance, the doping concentration, size, thickness, and shape of the source region 118 can be selected according to actual conditions, and are not limited here. The thickness here refers to the distance between the lower surface and the upper surface of the source region 118.

[0079] Specifically, such as Figure 7 As shown, the lower surface of the gate conductive layer 116 is lower than the upper surface of the source region 118, so that the gate conductive layer 116 can control the opening and closing of the conductive channel.

[0080] like Figures 8 to 10As shown, in step S4, an interlayer dielectric layer 119 is formed on the gate dielectric layer 115 and the epitaxial layer 111, and the interlayer dielectric layer 119 is etched to form a plurality of first contact holes 120 and a plurality of second contact holes 121 penetrating the interlayer dielectric layer 119. The plurality of first contact holes 120 are arranged sequentially along the Z direction at a first interval, and the plurality of second contact holes 121 are arranged sequentially along the Z direction at a second interval. The X direction, the Y direction and the Z direction are perpendicular to each other.

[0081] Specifically, such as Figure 8 As shown, an interlayer dielectric layer 119 is formed on the source region 118. The method for forming the interlayer dielectric layer 119 includes chemical vapor deposition, physical vapor deposition, or other suitable methods. Optionally, the interlayer dielectric layer 119 includes one or a combination of silicon oxide layer, silicon nitride layer, and silicon phosphate glass layer.

[0082] Specifically, a photoresist mask layer is formed on the interlayer dielectric layer 119. The photoresist mask layer is exposed using a mask, and a first contact hole 120 region and a second contact hole 121 region are defined in the developed photoresist mask layer. A plurality of first contact holes 120 and a plurality of second contact holes 121 are formed through a dry etching process, penetrating the interlayer dielectric layer 119 and the source region 118, with the bottom surface exposing the body region 117. In this embodiment, due to the good anisotropy of dry etching, costs can be saved. Furthermore, compared to the traditional mask-based contact hole fabrication process, this process only requires changing the mask pattern design for forming the first contact holes 120 and the second contact holes 121, without adding additional photolithography steps or complex processes, thus increasing manufacturing costs almost nothing.

[0083] Specifically, such as Figure 9 As shown, a plurality of first contact holes 120 are located in the central region between two adjacent grooves 112, and a plurality of second contact holes 121 are located in the central region between two adjacent grooves 112. The first contact holes 120 and the plurality of second contact holes 121 are arranged alternately along the X direction. The lateral width of the second contact hole 121 is equal to the lateral width of the first contact hole 120, and the lateral widths of the first contact hole 120 and the second contact hole 121 are both 0.2~0.6μm. For example, the lateral widths of the first contact hole 120 and the second contact hole 121 are both 0.2μm, 0.4μm or 0.6μm, which is not limited here.

[0084] Specifically, such as Figure 10The diagram shows a top view of the structure after the formation of the first contact hole 120 and the second contact hole 121. The dimension of a single first contact hole 120 along the Z-direction is larger than the dimension of a single second contact hole 121 along the Z-direction. The X-direction, Y-direction, and Z-direction are perpendicular to each other. In this embodiment, multiple first contact holes 120 have the same size and are arranged sequentially along the Z-direction at a first interval distance of 250~500 nm, for example, 250 nm, 400 nm, or 500 nm. Multiple second contact holes 121 have the same size and are arranged sequentially along the Z-direction at a second interval distance of 50~200 nm, for example, 50 nm, 100 nm, 150 nm, or 200 nm.

[0085] Because the first spacing distance of the multiple first contact holes 120 along the Z direction is greater than the second spacing distance of the multiple second contact holes 121 along the Z direction, the density of the first contact holes 120 in the cell containing the first contact holes 120 is low, and the ion concentration in the region between the first contact holes 120 and the channel is low, resulting in a lower threshold voltage. On the other hand, the density of the second contact holes 121 in the cell containing the second contact holes 121 is high, and the ion concentration in the region between the second contact holes 121 and the channel is high, resulting in a higher threshold voltage. Based on the different threshold voltages between different cells of the shielded gate trench MOSFET device, the shielded gate trench MOSFET device can have the function of sequential turn-on. Furthermore, the channel that is turned on later can also serve as a heat dissipation channel when the channel that is turned on earlier is working, thereby improving the SOA performance of the shielded gate trench MOSFET device and enhancing the device's processing power and reliability.

[0086] like Figure 11 As shown, step S5 is performed to deposit metal on the interlayer dielectric layer 119 to form a source 124 that fills the first contact hole 120 and the second contact hole 121.

[0087] Specifically, such as Figure 11 The diagram shown is a cross-sectional view of the source electrode 124 after it has been formed. The methods for forming the source electrode 124 include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0088] Specifically, in order to ensure that the exposed body area 117 at the bottom of the first contact hole 120 and the second contact hole 121 has a good metal connection with the outside, this embodiment uses metal to fill the first contact hole 120 and the second contact hole 121. The metal material forming the source electrode 124 includes titanium, titanium nitride, silver, gold, copper, aluminum, tungsten or other suitable conductive materials.

[0089] Specifically, the source 124 also covers the upper surface of the interlayer dielectric layer 119 above the gate conductive layer 116.

[0090] As an example, such as Figure 12 As shown, after forming the source 124, the process further includes forming a passivation layer 125, etching the passivation layer 125 to form metal leads, and forming a drain 126. The passivation layer 125 is located on the surface of the source 124, and the drain 126 is electrically connected to the back side of the semiconductor substrate 110.

[0091] Optionally, the passivation layer 125 can be a single-layer or multi-layer stacked structure. For example, the passivation layer 125 may consist only of a silicon nitride layer, or it may consist of a silicon nitride layer and a polymer layer located on the silicon nitride layer. Preferably, in this embodiment, the passivation layer 125 is selected to include a silicon nitride layer and a polyimide layer. The silicon nitride layer can be formed by chemical vapor deposition, and the polyimide layer can be formed by spin coating, so that the passivation layer 125 can better protect the underlying structure.

[0092] Specifically, the MOS device also includes a drain 126, which is located on the back side of the semiconductor substrate 110 and forms an electrical connection with the semiconductor substrate 110.

[0093] Example 2

[0094] This embodiment also provides a shielded gate trench MOSFET device, which is fabricated using the preparation method described in Embodiment 1 or other suitable similar methods. For details regarding the fabrication method, materials, and structure of the shielded gate trench MOSFET device, please refer to Embodiment 1. Specifically, since the shielded gate trench MOSFET device can be an N-type device or a P-type device, this embodiment uses an N-type device as an example for detailed explanation. See [link to previous embodiment]. Figure 12 The diagram shows a cross-sectional view of the shielded gate trench MOSFET device, wherein the shielded gate trench 112 type MOSFET device includes:

[0095] The system includes: a semiconductor substrate 110 and an epitaxial layer 111 disposed on the semiconductor substrate 110; at least one cell unit located in the epitaxial layer 111, the cell unit including trenches 112 spaced apart along the X direction and extending downward from the upper surface of the epitaxial layer 111 along the Y direction; and a shielding gate including a dielectric material layer 113 and a conductive material layer 114, the dielectric material layer 113 being located on the inner wall and bottom surface of the trenches 112. 113 encloses the sidewalls and bottom surface of the conductive material layer 114, and the upper surface of the dielectric material layer 113 is lower than the upper surface of the epitaxial layer 111; a trench gate structure, the trench gate structure including a gate dielectric layer 115 and a gate conductive layer 116, the gate dielectric layer 115 being located on the inner wall of the trench 112 and the upper surface of the dielectric material layer 113 and enclosing the sidewalls and bottom surface of the gate conductive layer 116; a second conductivity type body region 117 and a first conductivity type source region 118, the body... Region 117 is located on the upper surface of the epitaxial layer 111, and source region 118 is located on the upper surface of body region 117 and is flush with the upper surface of the trench gate structure; interlayer dielectric layer 119 is located on the upper surface of source region 118, and has a plurality of first contact holes 120 and a plurality of second contact holes 121 penetrating the source region 118 and exposing the body region 117. The plurality of first contact holes 120 are arranged sequentially along the Z direction at a first interval, and the plurality of second contact holes 121 are arranged sequentially along the Z direction at a second interval. The X direction, the Y direction and the Z direction are perpendicular to each other. The size of the plurality of first contact holes 120 along the Z direction is larger than the size of the plurality of second contact holes 121 along the Z direction, and the first interval is larger than the second interval; source electrode 124 is located on the interlayer dielectric layer 119 and fills the first contact holes 120 and the second contact holes 121.

[0096] Specifically, the shielded gate trench MOSFET device also includes a passivation layer 125 and a drain 126, with the drain 126 electrically connected to the bottom surface of the semiconductor substrate 110.

[0097] In summary, the shielded gate trench MOSFET device and its fabrication method of the present invention, by forming a plurality of first contact holes and a plurality of second contact holes of different sizes along the Z direction in the interlayer dielectric layer between adjacent trenches, and wherein the first spacing distance of the plurality of first contact holes along the Z direction is greater than the second spacing distance of the plurality of second contact holes along the Z direction, results in a low density of first contact holes in the cell containing the first contact holes, a low ion concentration in the region between the first contact holes and the channel, and a low threshold voltage; conversely, a high density of second contact holes in the cell containing the second contact holes, a high ion concentration in the region between the second contact holes and the channel, and a high threshold voltage. The shielded gate trench MOSFET device operates with channels having different threshold voltages turning on sequentially. This time-division multiplexing mechanism allows the later-turning cells with higher threshold voltages to also serve as heat dissipation channels for the earlier-turning channels with higher threshold voltages. This enhances both the SOA performance of the shielded gate trench MOSFET device, expanding its application range, and improves its heat dissipation. Furthermore, this shielded gate trench MOSFET device can be implemented simply by changing the mask pattern design for forming the first and second contact holes, without requiring additional photolithography steps or complex processes, thus increasing manufacturing costs almost entirely. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0098] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a shielded gate trench MOSFET device, characterized in that, Includes the following steps: A semiconductor substrate having an epitaxial layer is provided, wherein trenches are formed in the epitaxial layer at intervals along the X direction, and the trenches extend downward from the upper surface of the epitaxial layer along the Y direction; A dielectric material layer and a conductive material layer are sequentially formed in the trench. The dielectric material layer is located on the inner wall and bottom surface of the trench and wraps around the side wall and bottom surface of the conductive material layer. The upper surface of the dielectric material layer is lower than the upper surface of the epitaxial layer. A gate dielectric layer and a gate conductive layer are sequentially formed on the surface of the dielectric material layer, wherein the gate dielectric layer covers the sidewalls of the trench and wraps the sidewalls and bottom surface of the gate conductive layer; An interlayer dielectric layer is formed on the gate dielectric layer and the epitaxial layer, and the interlayer dielectric layer is etched to form a plurality of first contact holes and a plurality of second contact holes penetrating the interlayer dielectric layer. The plurality of first contact holes are arranged sequentially along the Z direction at a first interval distance, and the plurality of second contact holes are arranged sequentially along the Z direction at a second interval distance. The X direction, the Y direction and the Z direction are perpendicular to each other. Metal is deposited on the interlayer dielectric layer to form a source electrode that fills the first contact hole and the second contact hole.

2. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that: The first contact hole and the second contact hole are respectively located in the central region between two adjacent grooves, and the first contact hole and a plurality of second contact holes are arranged alternately along the X direction.

3. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that: The lateral width of the second contact hole is equal to the lateral width of the first contact hole, and the lateral widths of both the first and second contact holes are 0.2~0.6μm.

4. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that: The plurality of first contact holes have the same size, and the first spacing distance is 250~500nm.

5. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that: The plurality of second contact holes have the same size, and the second spacing distance is 50~200nm.

6. The method for fabricating a shielded gate trench MOSFET device according to any one of claims 4 to 5, characterized in that: The dimension of the first contact hole along the Z direction is larger than the dimension of the second contact hole along the Z direction.

7. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that: The width of the groove is 0.8~1.2μm, and the spacing between adjacent grooves is 2.4~3μm.

8. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that: After forming the gate conductive layer, the method further includes forming a second conductivity type body region and a first conductivity type source region, wherein the body region is located on the epitaxial layer between two adjacent trenches in the X direction, and the source region is located on the body region.

9. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that: After forming the source electrode, the process further includes forming a passivation layer, etching the passivation layer to form metal leads, and forming a drain electrode, wherein the passivation layer is located on the surface of the source electrode, and the drain electrode is electrically connected to the back side of the semiconductor substrate.

10. A shielded gate trench MOSFET device, characterized in that, include: A semiconductor substrate and an epitaxial layer disposed on the semiconductor substrate; At least one cell unit is located in the epitaxial layer, the cell unit including trenches spaced apart along the X direction and extending downward from the upper surface of the epitaxial layer along the Y direction; A shielding grid, comprising a dielectric material layer and a conductive material layer, wherein the dielectric material layer is located on the inner wall and bottom surface of the trench, the dielectric material layer wraps around the sidewall and bottom surface of the conductive material layer, and the upper surface of the dielectric material layer is lower than the upper surface of the epitaxial layer; A trench gate structure, comprising a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer is located on the inner wall of the trench and the upper surface of the dielectric material layer and wraps around the sidewalls and bottom surface of the gate conductive layer; A second conductivity type body region and a first conductivity type source region, wherein the body region is located on the upper surface of the epitaxial layer, and the source region is located on the upper surface of the body region and is flush with the upper surface of the trench gate structure; An interlayer dielectric layer is located on the upper surface of the source region. The interlayer dielectric layer has a plurality of first contact holes and a plurality of second contact holes that penetrate the source region and expose the body region. The plurality of first contact holes are arranged sequentially along the Z direction at a first interval distance, and the plurality of second contact holes are arranged sequentially along the Z direction at a second interval distance. The X direction, the Y direction and the Z direction are perpendicular to each other. The size of the plurality of first contact holes along the Z direction is larger than the size of the plurality of second contact holes along the Z direction, and the first interval distance is larger than the second interval distance. The source electrode is located on the interlayer dielectric layer and fills the first contact hole and the second contact hole.

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