Method for improving threshold voltage stability of trench MOSFET

Abstract

The invention provides a method for improving the threshold voltage stability of a trench MOSFET, and the method comprises the steps: 1, providing a substrate, forming an epitaxial layer on the substrate, and forming a trench in the epitaxial layer; 2, sequentially forming a gate dielectric layer and a gate material layer in the groove; 3, after the gate material layer is etched, annealing treatment is carried out on the gate material layer in the groove; step 4, performing first etching on the exposed gate dielectric layer to enable the thickness of the gate dielectric layer to meet the requirement of subsequent body region injection; 5, implementing body region injection, and forming a body region in the epitaxial layer; step 6, performing second etching on the gate dielectric layer to enable the thickness of the gate dielectric layer to meet the requirement of subsequent source region injection; and step 7, implementing source region injection, and forming a source region above the body region. According to the invention, the gate leakage current of the trench MOSFET is reduced, and the stability of the threshold voltage is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and specifically to a method for improving the threshold voltage stability of trench MOSFETs. Background Technology

[0002] Due to microstructural issues such as defects, interface states, and traps in the oxide layer within the material, a small number of charge carriers can pass through the gate oxide layer through direct tunneling or hot carrier injection, thus forming gate leakage current (IGSS).

[0003] For trench MOSFETs, in order to achieve lower gate leakage current, the thickness of the gate dielectric layer is increased, which leads to a decrease in threshold voltage stability. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method for improving the threshold voltage stability of trench MOSFETs, in order to solve the problem that the threshold voltage stability of trench MOSFETs deteriorates after the thickness of the gate dielectric layer increases.

[0005] To achieve the above and other related objectives, this application provides a method for improving the threshold voltage stability of a trench MOSFET, comprising: Step 1: Provide a substrate, form an epitaxial layer on the substrate, and form trenches in the epitaxial layer; Step 2: Sequentially form a gate dielectric layer and a gate material layer in the trench; Step 3: After etching the gate material layer, anneal the gate material layer in the trench. Step 4: Perform the first etching on the exposed gate dielectric layer to make the thickness of the gate dielectric layer meet the requirements of subsequent body region implantation; Step 5: Perform volume region injection to form a volume region in the epitaxial layer; Step 6: Perform a second etching on the gate dielectric layer to ensure that the thickness of the gate dielectric layer meets the requirements for subsequent source region implantation; Step 7: Perform source region injection to form a source region above the body region.

[0006] Preferably, the first and second etching processes are anisotropic dry etching.

[0007] Preferably, an epitaxial layer is formed on the substrate using an epitaxial growth process.

[0008] Preferably, the material of the gate dielectric layer includes silicon oxide, and the material of the gate material layer includes polysilicon.

[0009] Preferably, the etching in step three is dry etching.

[0010] Preferably, for an N-type trench MOSFET, the body region formed by body region implantation is P-type.

[0011] Preferably, for an N-type trench MOSFET, the source region formed by source injection is N+ type.

[0012] Preferably, the energy injected into the source region is .

[0013] As described above, the method for improving the threshold voltage stability of trench MOSFETs provided in this application has the following beneficial effects: it reduces the gate leakage current of trench MOSFETs while improving the stability of the threshold voltage. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0015] Figure 1 The image shows a photograph of a pit in the gate dielectric layer at the top of the trench when a trench MOSFET is fabricated according to the prior art. Figure 2 The flowchart shown is a method for improving the threshold voltage stability of a trench MOSFET according to an embodiment of this application. Figure 3 The image shown is an electronic photograph showing that no pits appeared in the gate dielectric layer at the top of the trench when a trench MOSFET was fabricated using the method for improving the threshold voltage stability of a trench MOSFET according to an embodiment of this application. Detailed Implementation

[0016] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0017] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0020] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0021] When fabricating trench MOSFETs using existing technology, after depositing the gate material layer in the trench, over-etching is required to avoid leaving gate material residue on the epitaxial layer surface. As the gate dielectric layer thickens, to maintain consistent implantation depths in the subsequent body and source regions, the isotropic etching used will increase the amount of etched gate dielectric layer exposed, leading to issues such as… Figure 1 The pits shown are more pronounced with thicker gate dielectric layers and greater etching. As the gate dielectric layer thickens, the implantation dose needs to be reduced during implantation in the substrate region to maintain a constant threshold voltage. Furthermore, the implanted material tends to follow these pits, making the channel concentration more susceptible to subsequent source region implantation. Additionally, the thinner gate dielectric layer at the location of the pits leads to unstable junction depths, resulting in poorer threshold voltage stability.

[0022] To address this issue, this application provides a method for improving the threshold voltage stability of trench MOSFETs.

[0023] Please see Figure 2 The diagram illustrates a flowchart of a method for improving the threshold voltage stability of a trench MOSFET according to an embodiment of this application.

[0024] like Figure 2 As shown, the method for improving the threshold voltage stability of a trench MOSFET includes the following steps: Step 1: Provide a substrate, form an epitaxial layer on the substrate, and form trenches in the epitaxial layer; Step 2: Sequentially form a gate dielectric layer and a gate material layer in the trench; Step 3: After etching the gate material layer, anneal the gate material layer in the trench. Step 4: Perform the first etching on the exposed gate dielectric layer to make the thickness of the gate dielectric layer meet the requirements of subsequent body region implantation; Step 5: Perform volume region injection to form a volume region in the epitaxial layer; Step 6: Perform a second etching on the gate dielectric layer to ensure that the thickness of the gate dielectric layer meets the requirements for subsequent source region implantation; Step 7: Perform source region injection to form a source region above the body region.

[0025] In step one, the substrate may optionally be a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate; alternatively, the substrate material may include other materials, such as gallium arsenide or other III-V compounds. Those skilled in the art can select the substrate material based on the type of device structure formed on the substrate; therefore, the type of substrate should not limit the scope of protection of this invention.

[0026] As an example, an epitaxial layer is formed on a substrate using an epitaxial growth process. Exemplarily, a P-type epitaxial layer is formed on a P-type substrate, and the dopant in the P-type epitaxial layer includes ions such as B, In, Al, and Ga.

[0027] As an example, the steps of forming a trench in an epitaxial layer include: forming a hard mask layer on the surface of the epitaxial layer, the material of which may be silicon oxide or silicon nitride; coating photoresist on the surface of the hard mask layer and defining the trench formation area using a photolithography process; etching the hard mask layer using the photoresist as a mask, the etching process removing the hard mask layer located in the formation area and retaining the hard mask layer outside the formation area; removing the photoresist and etching the epitaxial layer using the hard mask layer as a mask to form a trench; removing the hard mask layer, and then forming a sacrificial oxide layer on the bottom surface and side surfaces of the trench and the epitaxial layer surface outside the trench and removing it by wet etching to repair the damage caused during the dry etching process of forming the trench.

[0028] In step two, a gate dielectric layer is first formed on the inner surface of the trench, and then a gate material layer is filled in the trench where the gate dielectric layer is formed.

[0029] As an example, the gate dielectric layer may be made of silicon oxide, and the gate material layer may be made of polysilicon. The polysilicon may be doped; for example, dopants in N-type polysilicon may include ions such as P, As, and Sb.

[0030] For example, the gate dielectric layer is formed by thermal oxidation or by deposition.

[0031] In step three, the gate material layer is etched to remove any gate material residue from the epitaxial layer surface. For example, this etching is a dry etching process. Annealing repairs the lattice damage caused by the etching process, reducing defects in the gate dielectric layer and thus enhancing its withstand voltage and long-term stability.

[0032] In step four, the first etching is anisotropic dry etching, which ensures that the thickness of the gate dielectric layer meets the requirements of subsequent body region implantation, while preventing the thickness of the gate dielectric layer at the top of the trench from becoming thinner.

[0033] In step five, taking an N-type trench MOSFET as an example, the body region formed by body implantation is P-type, and the doping materials include ions such as B, In, Al, and Ga.

[0034] In step six, the second etching is anisotropic dry etching, ensuring that the thickness of the gate dielectric layer meets the requirements for subsequent source region implantation without making the thickness of the gate dielectric layer at the top of the trench thinner. Extensive testing has proven that after the second etching, as... Figure 3 As shown, it will not appear Figure 1 The pitting defect shown.

[0035] In step seven, taking an N-type trench MOSFET as an example, the source region formed by source implantation is N+ type, and the doped materials include P, As, Sb ions. As an example, the energy of the source implantation is... It enhances current conduction when the channel is open.

[0036] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0037] In summary, the method for improving the threshold voltage stability of trench MOSFETs provided in this application reduces the gate leakage current of the trench MOSFET while improving the stability of the threshold voltage. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0038] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A method for improving the threshold voltage stability of a trench MOSFET, characterized in that, The method includes: Step 1: Provide a substrate, form an epitaxial layer on the substrate, and form trenches in the epitaxial layer; Step 2: A gate dielectric layer and a gate material layer are sequentially formed in the trench; Step 3: After etching the gate material layer, anneal the gate material layer in the trench. Step four: Perform a first etching on the exposed gate dielectric layer to ensure that the thickness of the gate dielectric layer meets the requirements for subsequent body region implantation. Requirements; Step 5: Perform volume region injection to form a volume region in the epitaxial layer; Step six: Perform a second etching on the gate dielectric layer to make the thickness of the gate dielectric layer meet the requirements of subsequent source region implantation; Step 7: Perform source region injection to form a source region above the body region.

2. The method according to claim 1, characterized in that, The first etching and the second etching are anisotropic dry etching.

3. The method according to claim 1, characterized in that, The epitaxial layer is formed on the substrate using an epitaxial growth process.

4. The method according to claim 1, characterized in that, The material of the gate dielectric layer includes silicon oxide, and the material of the gate material layer includes polycrystalline silicon.

5. The method according to claim 1, characterized in that, The etching in step three is dry etching.

6. The method according to claim 1, characterized in that, For an N-type trench MOSFET, the body region formed by the aforementioned body injection is P-type.

7. The method according to claim 1, characterized in that, For an N-type trench MOSFET, the source region formed by the aforementioned source injection is of type N+.

8. The method according to claim 1, characterized in that, The energy injected into the source region is .

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