Shield gate trench MOSFET device and preparation method thereof

Abstract

The invention provides a shield gate trench MOSFET device and a preparation method thereof, a strip-shaped continuous asymmetric contact hole is formed in an interlayer dielectric layer between adjacent trenches, a first distance between the contact hole and a first trench is smaller than a second distance between the contact hole and a second trench, and the contact hole and the second trench are separated from each other. The ion concentration of one side, close to the first groove, of the contact hole is relatively high, so that the threshold voltage is relatively high; the ion concentration of the side, far away from the second groove, of the contact hole is low, so that the threshold voltage is low, when voltage is applied to the grid electrode, the channel with the low threshold voltage is firstly started for conduction, the channel with the high threshold voltage is then started for conduction, the channel which is started later can serve as a heat dissipation channel through the time-sharing starting mechanism, heat is dissipated for the channel which is started firstly, and the heat dissipation efficiency is improved. According to the method, only the shape of the contact hole mask layout needs to be adjusted, additional process steps do not need to be added, the reliability of the MOS device can be improved, and the application range of the MOS device can be widened with extremely low cost.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing, and particularly relates to a shielded gate trench MOSFET device and its fabrication method. Background Technology

[0002] Power devices, used in power management, power transmission, and high-speed switching control, can be categorized into several types based on their operating principles, including junction field-effect transistors (JFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), and thyristors (SCRs). Among metal-oxide-semiconductor field-effect transistors, the shielded gate trench MOSFET (SGT MOS) is an improvement over the traditional deep trench MOSFET. It reduces the gate-drain overlap area and gate-drain capacitance by adding a polysilicon electrode (called the shielded gate) below the gate electrode, thereby increasing switching speed, reducing dynamic losses, increasing cell density, and decreasing on-resistance. Therefore, it is widely used in low- and medium-voltage applications such as motor drives, power management, synchronous rectification, and energy storage control.

[0003] Due to factors such as chip area, cell design, and packaging performance, shielded trench MOS devices have an energy range within which they can safely handle drain-source voltage and drain current, known as the SOA (Safe Operating Area). However, with the continuous changes and development of the application environment for shielded trench MOS devices, on the one hand, there is a requirement for shielded trench MOS devices to have lower conduction losses; on the other hand, there is a requirement for shielded trench MOS devices to operate for longer periods under high voltage and high current, that is, to have better SOA performance.

[0004] Existing shielded trench MOS devices have poor SOA performance and only have one type of source contact hole. Moreover, the source contact hole is generally located in the central region between adjacent trenches, which means that different cells in the shielded trench MOS device have the same threshold voltage. This results in the shielded trench MOS device being applicable only to circuits with specific requirements, limiting its application range. Furthermore, changes in ambient temperature and the heat generated during operation can increase the operating resistance of the shielded trench MOS device, generating more heat. Ultimately, poor heat dissipation may lead to the shielded trench MOS device burning out.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a shielded gate trench MOSFET device and its preparation method, so as to solve the problems of poor SOA performance, limited application range, and poor heat dissipation leading to burnout of shielded gate trench MOSFET devices in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating a shielded gate trench MOSFET device, comprising the following steps:

[0008] A semiconductor substrate having an epitaxial layer is provided, wherein a first trench and a second trench are formed in the epitaxial layer at a horizontal distance, the first trench and the second trench both opening from the upper surface of the epitaxial layer and extending downward;

[0009] A dielectric material layer and a conductive material layer are sequentially formed in the first trench and the second trench. The dielectric material layer is located on the inner wall and bottom surface of the first trench and the second trench and wraps around the side wall and bottom surface of the conductive material layer. The upper surface of the dielectric material layer is lower than the upper surface of the epitaxial layer.

[0010] A gate dielectric layer and a gate conductive layer are sequentially formed on the surface of the dielectric material layer. The gate dielectric layer covers the sidewalls of the first trench and the second trench and wraps the sidewalls and bottom surface of the gate conductive layer.

[0011] Ion implantation is performed on the upper surface of the epitaxial layer on both sides of the first trench and the second trench to form a body region, and ion implantation is performed on the upper surface of the body region to form a source region;

[0012] An interlayer dielectric layer is formed on the source region, and the interlayer dielectric layer, the source region, and the body region are etched to form a contact hole that penetrates the interlayer dielectric layer and the source region and exposes the body region;

[0013] A metal is deposited on the interlayer dielectric layer to form a source electrode that fills the contact hole.

[0014] Optionally, the lateral width of the contact hole is 0.2~0.3μm and it is symmetrically distributed on both sides of the first groove.

[0015] Optionally, the contact hole has a first distance from the first groove, and the contact hole has a second distance from the second groove, wherein the value of the second distance is greater than the first distance.

[0016] Optionally, the ratio of the second distance to the first distance is 1.5 to 2.5.

[0017] Optionally, the upper surfaces of the gate dielectric layer, the gate conductive layer, and the source region are flush.

[0018] Optionally, after forming the source, the method further includes forming a passivation layer, etching the passivation layer to form metal leads, and forming a drain, wherein the passivation layer is located on the surface of the source, and the drain is electrically connected to the back side of the semiconductor substrate.

[0019] Optionally, the first trench and the second trench have equal lateral widths of 0.8~1.2μm, and the ratio of the lateral width of the conductive material layer to the lateral width of the dielectric material layer is 0.5~3.

[0020] The present invention also provides a shielded gate trench MOSFET device, comprising:

[0021] A semiconductor substrate and an epitaxial layer disposed on the semiconductor substrate;

[0022] At least one cell unit is located in the epitaxial layer, the cell unit including a first trench and a second trench spaced apart in the horizontal direction;

[0023] A shielding grid, comprising a dielectric material layer and a conductive material layer, wherein the dielectric material layer is located on the inner wall and bottom surface of the first trench and the second trench, the dielectric material layer wraps around the side wall and bottom surface of the conductive material layer, and the upper surface of the dielectric material layer is lower than the upper surface of the epitaxial layer;

[0024] A trench gate structure, comprising a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer is located on the inner wall of the first trench and the second trench and on the upper surface of the dielectric material layer and wraps the sidewall and bottom surface of the gate conductive layer;

[0025] A second conductivity type body region and a first conductivity type source region, wherein the body region is located on the upper surface of the epitaxial layer and is adjacent to the first trench and the second trench, and the source region is located on the upper surface of the body region and is flush with the upper surface of the trench gate structure;

[0026] An interlayer dielectric layer is located on the upper surface of the source region, and the interlayer dielectric layer has contact holes that expose the body region;

[0027] The source electrode is located on the interlayer dielectric layer and fills the contact hole.

[0028] Optionally, the lateral width of the contact hole is 0.2~0.3μm and it is symmetrically distributed on both sides of the first groove.

[0029] Optionally, the contact hole has a first distance from the first groove, the contact hole has a second distance from the second groove, and the ratio of the second distance to the first distance is 1.5 to 2.5.

[0030] As described above, the shielded gate trench MOSFET device and its fabrication method of the present invention form elongated continuous asymmetric contact holes in the interlayer dielectric layer between adjacent trenches. The first distance between the contact hole and the first trench is less than the second distance between the contact hole and the second trench, resulting in a higher ion concentration and thus a higher threshold voltage on the side of the contact hole closer to the first trench, and a lower ion concentration and thus a lower threshold voltage on the side of the contact hole farther from the second trench. When a voltage is applied to the gate, the channel with the lower threshold voltage turns on first, and the channel with the higher threshold voltage turns on later. This time-division multiplexing mechanism allows the later-turned-on channel to act as a heat dissipation channel, dispersing heat from the earlier-turned channel, thereby significantly improving the SOA performance and heat dissipation capability of the device. Furthermore, this method only requires adjusting the shape of the contact hole mask pattern, without adding any additional process steps, and thus increases manufacturing costs almost entirely. Attached Figure Description

[0031] Figure 1 The diagram shows the process flow of the fabrication method of the shielded gate trench MOSFET device of the present invention.

[0032] Figure 2 The diagram shows a cross-sectional structure after the formation of the first and second trenches in the epitaxial layer according to the present invention.

[0033] Figure 3 The diagram shows a cross-sectional view of the structure after the dielectric material layer and the conductive material layer are formed in the first trench and the second trench in this invention.

[0034] Figure 4 The diagram shows a cross-sectional structure after etching the dielectric and conductive material layers.

[0035] Figure 5 The diagram shows a cross-sectional structure after the gate dielectric layer and the gate conductive layer are formed in the first trench and the second trench in this invention.

[0036] Figure 6 The diagram shows a cross-sectional structure after etching the gate dielectric layer and the gate conductive layer.

[0037] Figure 7The diagram shows a cross-sectional structure after the body region and the source region are formed on the epitaxial layer in this invention.

[0038] Figure 8 The diagram shown is a cross-sectional view of the structure after the interlayer dielectric layer is formed in this invention.

[0039] Figure 9 The diagram shown is a cross-sectional view of the structure after the contact hole is formed in this invention.

[0040] Figure 10 The diagram shown is a top view of the structure after the contact hole is formed in this invention.

[0041] Figure 11 The diagram shown is a cross-sectional view of the source electrode after it has been formed in this invention.

[0042] Figure 12 The diagram shown is a cross-sectional view of the structure after the passivation layer and drain electrode are formed in this invention.

[0043] Component designation explanation

[0044] 10. Semiconductor substrate; 11. Epitaxial layer; 121. First trench; 122. Second trench; 13. Dielectric material layer; 14. Conductive material layer; 15. Gate dielectric layer; 16. Gate conductive layer; 17. Body region; 18. Source region; 19. Interlayer dielectric layer; 20. Contact hole; 21. First distance; 22. Second distance; 23. Source electrode; 24. Passivation layer; 25. Drain electrode; S1~S6, Steps. Detailed Implementation

[0045] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0047] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0048] Please see Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0049] Example 1

[0050] This embodiment provides a method for fabricating a shielded gate trench MOSFET device, such as... Figure 1 The diagram shown illustrates the process flow of the fabrication method for the shielded gate trench MOSFET device, including the following steps:

[0051] S1: A semiconductor substrate 10 having an epitaxial layer 11 is provided, wherein a first trench 121 and a second trench 122 arranged at intervals in the horizontal direction are formed in the epitaxial layer 11, wherein the first trench 121 and the second trench 122 both open from the upper surface of the epitaxial layer 11 and extend downward.

[0052] S2: A dielectric material layer 13 and a conductive material layer 14 are sequentially formed in the first trench 121 and the second trench 122. The dielectric material layer 13 is located on the inner wall and bottom surface of the first trench 121 and the second trench 122 and wraps around the side wall and bottom surface of the conductive material layer 14. The upper surface of the dielectric material layer 13 is lower than the upper surface of the epitaxial layer 11.

[0053] S3: A gate dielectric layer 15 and a gate conductive layer 16 are sequentially formed on the surface of the dielectric material layer 13. The gate dielectric layer 15 covers the sidewalls of the first trench 121 and the second trench 122 and wraps the sidewalls and bottom surface of the gate conductive layer 16.

[0054] S4: Ion implantation is performed on the upper surface of the epitaxial layer 11 on both sides of the first trench 121 and the second trench 122 to form a body region 17, and ion implantation is performed on the upper surface of the body region 17 to form a source region 18.

[0055] S5: An interlayer dielectric layer 19 is formed on the source region 18, and the interlayer dielectric layer 19, the source region 18 and the body region 17 are etched to form a contact hole 20 that penetrates the interlayer dielectric layer 19 and the source region 18 and exposes the body region 17.

[0056] S6: Deposit metal on the interlayer dielectric layer 19 to form a source electrode 23 that fills the contact hole 20.

[0057] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite. In this embodiment, a shielded gate trench MOSFET device is used as an example of an N-type device for detailed explanation; that is, in this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. When the shielded gate trench MOSFET device is a P-type device, it is only necessary to interchange the corresponding N-type and P-type types.

[0058] The fabrication method of the shielded gate trench MOSFET device of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0059] like Figure 2 As shown, in step S1, a semiconductor substrate 10 having an epitaxial layer 11 is provided, and a first trench 121 and a second trench 122 arranged horizontally in the epitaxial layer 11 are formed therein. The first trench 121 and the second trench 122 both open from the upper surface of the epitaxial layer 11 and extend downward.

[0060] Specifically, such as Figure 2 The diagram shows a cross-sectional view of the semiconductor substrate 10. In this embodiment, the semiconductor substrate 10 is an N-type semiconductor substrate 10, and an N-type epitaxial layer 11 is formed on the front side of the semiconductor substrate 10. While ensuring device performance, the thickness, size, doping concentration, and shape of the semiconductor substrate 10 can be selected according to actual conditions, and are not limited here. The thickness, size, doping concentration, and shape of the epitaxial layer 11 can be selected according to actual conditions, and are not limited here.

[0061] Optionally, in this embodiment, the semiconductor substrate 10 can be an N+ type doped silicon substrate, a germanium silicon substrate, a silicon carbide substrate, etc., and the epitaxial layer 11 is selected as a single-crystal silicon epitaxial layer 11 of the first conductivity type. Before performing subsequent processes, the semiconductor substrate 10 can be cleaned, for example, by sequentially cleaning with an organic solvent such as acetone and deionized water to remove contaminants from the surface of the semiconductor substrate 10, followed by drying; or by first removing the natural oxide layer on the surface of the semiconductor substrate 10 with a diluted acid solution, then cleaning with deionized water, and finally drying; or by performing multiple cleaning operations using the aforementioned methods.

[0062] Furthermore, such as Figure 2 As shown, a plurality of first trenches 121 and second trenches 122 are formed in the epitaxial layer 11 at intervals along the X direction. The first trenches 121 and the second trenches 122 both extend downward from the upper surface of the epitaxial layer 11 along the Y direction. While ensuring device performance, the number of the first trenches 121 and the second trenches 122 and their depths can be selected according to actual conditions and are not limited here. The width of the first trenches 121 and the second trenches 122 is 0.8~1. For example, the width of the groove is 0.8μm, 1μm, or 1.2μm. The width of the first groove 121 and the width of the second groove 122 may be equal or unequal. Preferably, in this embodiment, the width of the first groove 121 and the width of the second groove 122 are equal. The distance between adjacent first grooves 121 and second grooves 122 is 2.4~3μm. For example, the distance between adjacent first grooves 121 and second grooves 122 is 2.4μm, 2.6μm, or 3μm. The specific steps for forming multiple first trenches 121 and second trenches 122 spaced apart along the X-direction are as follows: First, a hard mask layer is formed on the upper surface of the epitaxial layer 11. The mask layer includes, but is not limited to, an oxide layer, a silicon nitride layer, or other suitable film layer. Using the hard mask layer, the regions where the first trenches 121 and second trenches 122 to be formed are defined by photolithography, thereby etching out the first trenches 121 and second trenches 122. After forming the first trenches 121 and second trenches 122, residual hard mask layer is removed using processes including, but not limited to, etching. Specific implementation methods of the photolithography and etching processes can be achieved using conventional methods known to those skilled in the art, and are not specifically limited here.

[0063] like Figure 3 and Figure 4As shown, in step S2, a dielectric material layer 13 and a conductive material layer 14 are sequentially formed in the first trench 121 and the second trench 122. The dielectric material layer 13 is located on the inner wall and bottom surface of the first trench 121 and the second trench 122 and wraps around the side wall and bottom surface of the conductive material layer 14. The upper surface of the dielectric material layer 13 is lower than the upper surface of the epitaxial layer 11.

[0064] Specifically, such as Figure 3 The diagram shows a cross-sectional view of the dielectric material layer 13 and conductive material layer 14 of a certain thickness grown on the surface of the epitaxial layer 11 and on the inner walls of the first trench 121 and the second trench 122. The ratio of the lateral width of the conductive material layer 14 to the lateral width of the dielectric material layer 13 is 0.5 to 3. For example, the ratio of the lateral width of the conductive material layer 14 to the lateral width of the dielectric material layer 13 is 0.5, 1.5, 2.5 or 3. No specific limitation is made here. The method for forming the dielectric material layer 13 and the conductive material layer 14 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0065] Specifically, the dielectric material layer 13 can be a high-k dielectric layer, including but not limited to silicon oxide, silicon nitride, aluminum oxide or other suitable dielectric materials, and the conductive material layer 14 is made of polycrystalline silicon.

[0066] Specifically, while ensuring device performance, the thickness of the dielectric material layer 13 covering the inner walls of the first trench 121 and the second trench 122 can be selected according to the actual situation, and is not limited here.

[0067] like Figure 4 As shown, the dielectric material layer 13 and conductive material layer 14 within the first trench 121 and the second trench 122 are etched to obtain the shielding gate layer of a preset height. Specifically, while ensuring device performance, the height of the shielding gate layer can be selected according to actual conditions, and is not limited here. The height here refers to the distance between the bottom surface of the shielding gate layer and the top surface of the shielding gate layer.

[0068] Specifically, such as Figure 4As shown, anisotropic etching is performed on the dielectric material layer 13 and the conductive material layer 14 so that the upper surface of the dielectric material layer 13 is lower than the upper surface of the epitaxial layer 11. Then, planarization is performed on the dielectric material layer 13 and the conductive material layer 14, or CMP process is directly used to make the dielectric material layer 13 and the conductive material layer 14 located in the first trench 121 and the second trench 122 have the same height. Both of the above processing methods can make the dielectric material layer 13 and the conductive material layer 14 have flush surfaces. The planarization process can include mechanical polishing or CMP, which is not excessively limited here.

[0069] Optionally, after anisotropic etching and planarization of the dielectric material layer 13 and the conductive material layer 14, the dielectric material layer 13 needs to be deposited again on the surface of the dielectric material layer 13 and the conductive material layer 14, so that the dielectric material layer 13 is located on the inner wall and bottom surface of the first trench 121 and the second trench 122 and wraps the side wall and bottom surface of the conductive material layer 14.

[0070] like Figure 5 and Figure 6 As shown, in step S3, a gate dielectric layer 15 and a gate conductive layer 16 are sequentially formed on the surface of the dielectric material layer 13. The gate dielectric layer 15 covers the sidewalls of the first trench 121 and the second trench 122 and wraps the sidewalls and bottom surface of the gate conductive layer 16.

[0071] Specifically, such as Figure 5 The diagram shows a cross-sectional view of the gate dielectric layer 15 and gate conductive layer 16 after a certain thickness has been grown on the surface of the epitaxial layer 11 and on the inner walls of the first trench 121 and the second trench 122. The methods for forming the gate dielectric layer 15 and the gate conductive layer 16 include thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0072] Specifically, the gate dielectric layer 15 can be a high-k dielectric layer, including but not limited to silicon oxide, silicon nitride, aluminum oxide or other suitable dielectric materials, and the gate conductive layer 16 is made of polycrystalline silicon.

[0073] Specifically, forming the gate dielectric layer 15 and the gate conductive layer 16 includes the following steps: forming a gate dielectric layer 15 covering the surface of the dielectric material layer 13, the sidewalls of the first trench 121 and the second trench 122, and the upper surface of the epitaxial layer 11; and then forming the gate conductive layer 16 in the first trench 121 and the second trench 122 in the middle of the gate dielectric layer 15 and on the upper surface of the epitaxial layer 11; as shown Figure 6As shown, the gate dielectric layer 15 and the gate conductive layer 16 are subjected to anisotropic etching and planarization to obtain a trench gate structure located in the first trench 121 and the second trench 122.

[0074] Specifically, the planarization methods for the gate dielectric layer 15 and the gate conductive layer 16 include chemical mechanical polishing, dry etching, wet etching, or other suitable methods.

[0075] Specifically, while ensuring device performance, the thickness of the gate dielectric layer 15 covering the inner walls of the first trench 121 and the second trench 122 can be selected according to the actual situation, and is not limited here.

[0076] like Figure 7 As shown, in step S4, ion implantation is performed on the upper surface of the epitaxial layer 11 on both sides of the first trench 121 and the second trench 122 to form a body region 17, and ion implantation is performed on the upper surface of the body region 17 to form a source region 18.

[0077] Specifically, in this embodiment, such as Figure 7 As shown, the body region 17 is a body region of the second conductivity type. The method for forming the body region 17 of the second conductivity type includes ion implantation and high-temperature annealing. For example, ion implantation can be used to implant second conductivity type impurities into the top of the epitaxial layer 11 doped with the first conductivity type on both sides of the first trench 121 and the second trench 122, and then a high-temperature annealing process can be performed to invert the top of the epitaxial layer 11 doped with the first conductivity type into the body region 17 of the second conductivity type. The body region 17 is isolated from the gate conductive layer 16 through the gate dielectric layer 15.

[0078] Specifically, while ensuring device performance, the doping concentration and thickness of the body region 17 can be selected according to actual conditions, and are not limited here. The thickness here refers to the distance between the lower surface and the upper surface of the body region 17.

[0079] Specifically, the source region 18 is a first conductivity type source region 18. The method for forming the first conductivity type source region 18 includes ion implantation and high-temperature annealing. For example, ion implantation can be used to implant first conductivity type impurities into the top of the second conductivity type body region 17, followed by a high-temperature annealing process to reverse the top of the second conductivity type body region 17 back into the first conductivity type source region 18, making the upper surfaces of the gate dielectric layer 15, the gate conductive layer 16, and the source region 18 flush. The source region 18 and the gate conductive layer 16 are isolated by the gate dielectric layer 15.

[0080] Specifically, while ensuring device performance, the doping concentration, size, thickness, and shape of the source region 18 can be selected according to actual conditions, and are not limited here. The thickness here refers to the distance between the lower surface and the upper surface of the source region 18.

[0081] like Figures 8 to 10 As shown, step S5 is performed to form an interlayer dielectric layer 19 on the source region 18, and to etch the interlayer dielectric layer 19, the source region 18 and the body region 17 to form a contact hole 20 that penetrates the interlayer dielectric layer 19 and the source region 18 and exposes the body region 17.

[0082] Specifically, such as Figure 8 As shown, an interlayer dielectric layer 19 is formed on the source region 18. The method for forming the interlayer dielectric layer 19 includes chemical vapor deposition, physical vapor deposition, or other suitable methods. Optionally, the interlayer dielectric layer 19 includes one or a combination of silicon oxide layer, silicon nitride layer, and silicon phosphate glass layer.

[0083] Specifically, a photoresist mask layer is formed on the interlayer dielectric layer 19. The photoresist mask layer is exposed using a photomask, and the area of ​​the contact hole 20 is defined in the developed photoresist mask layer. A dry etching process is then used to form the contact hole 20, which penetrates the interlayer dielectric layer 19 and the source region 18, and exposes the body region 17 on its bottom surface. In this embodiment, dry etching offers good anisotropy, thus saving costs. Furthermore, compared to the traditional photomask-based fabrication of the contact hole 20, this process only requires changing the photomask pattern design of the contact hole 20, without adding additional photolithography steps or complex processes, resulting in almost no increase in manufacturing costs.

[0084] As an example, the lateral width of the contact hole 20 is 0.2~0.3μm and it is symmetrically distributed on both sides of the first groove 121. Specifically, as shown in the example... Figure 9 As shown, the contact holes 20 are distributed in the region between the first trench 121 and the second trench 122, and there is a first distance 21 between the contact holes 20 and the first trench 121, and a second distance 22 between the contact holes 20 and the second trench 122. The value of the second distance 22 is greater than the first distance 21, which makes the ion concentration on the side of the contact hole 20 closer to the first trench 121 higher, and thus the threshold voltage higher; the ion concentration on the side of the contact hole 20 farther from the second trench 122 is lower, and thus the threshold voltage is lower. When a voltage is applied to the gate, the channel with the lower threshold voltage turns on first and the channel with the higher threshold voltage turns on later. The above-mentioned time-division turning mechanism allows the channel that turns on later to act as a heat dissipation channel to disperse the heat of the channel that turns on first.

[0085] As an example, the ratio of the second distance 22 to the first distance 21 is 1.5 to 2.5.

[0086] Specifically, such as Figure 10 The diagram shown is a top view of the structure after the contact hole 20 is formed. In this embodiment, the contact hole 20 is a continuous elongated shape, and the ratio of the second distance 22 to the first distance 21 is 1.5 to 2.5. For example, the ratio of the second distance 22 to the first distance 21 is 1.5, 2, or 2.5, and no excessive limitation is made here.

[0087] like Figure 11 As shown, step S6 is performed to deposit metal on the interlayer dielectric layer 19 to form a source electrode 23 that fills the contact hole 20.

[0088] Specifically, such as Figure 11 The diagram shown is a cross-sectional view of the source electrode 23 after its formation. The methods for forming the source electrode 23 include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0089] Specifically, in order to ensure that the exposed body area 17 at the bottom of the contact hole 20 has a good metal connection with the outside, this embodiment uses metal to fill the contact hole 20. The metal material forming the source electrode 23 includes titanium, titanium nitride, silver, gold, copper, aluminum, tungsten or other suitable conductive materials.

[0090] Specifically, the source electrode 23 also covers the upper surface of the interlayer dielectric layer 19 above the gate conductive layer 16.

[0091] As an example, such as Figure 12 As shown, after forming the source electrode 23, the process further includes forming a passivation layer 24, etching the passivation layer 24 to form metal leads, and forming a drain electrode 25. The passivation layer 24 is located on the surface of the source electrode 23, and the drain electrode 25 is electrically connected to the back side of the semiconductor substrate 10.

[0092] Optionally, the passivation layer 24 can be a single-layer or multi-layer stacked structure. For example, the passivation layer 24 can include only a silicon nitride layer, or it can include a silicon nitride layer and a polymer layer located on the silicon nitride layer. Preferably, in this embodiment, the passivation layer 24 includes a silicon nitride layer and a polyimide layer. The silicon nitride layer can be formed by chemical vapor deposition, and the polyimide layer can be formed by spin coating, so that the passivation layer 24 can better protect the underlying structure.

[0093] Specifically, the MOS device also includes a drain 25, which is located on the back side of the semiconductor substrate 10 and forms an electrical connection with the semiconductor substrate 10.

[0094] Example 2

[0095] This embodiment also provides a shielded gate trench MOSFET device, which is fabricated using the preparation method described in Embodiment 1 or other suitable similar methods. For details regarding the fabrication method, materials, and structure of the shielded gate trench MOSFET device, please refer to Embodiment 1; these will not be repeated here. Specifically, since the shielded gate trench MOSFET device can be an N-type device or a P-type device, this embodiment uses an N-type device as an example for detailed explanation. See [link to relevant documentation]. Figure 12 The image shows a cross-sectional view of the shielded gate trench MOSFET device, wherein the shielded gate trench MOSFET device includes:

[0096] A semiconductor substrate 10 and an epitaxial layer 11 disposed on the semiconductor substrate 10; at least one cell unit located in the epitaxial layer 11, the cell unit including a first trench 121 and a second trench 122 spaced apart in a horizontal direction; a shielding gate, the shielding gate including a dielectric material layer 13 and a conductive material layer 14, the dielectric material layer 13 being located on the inner wall and bottom surface of the first trench 121 and the second trench 122, the dielectric material layer 13 wrapping the sidewall and bottom surface of the conductive material layer 14, the upper surface of the dielectric material layer 13 being lower than the upper surface of the epitaxial layer 11; a trench gate structure, the trench gate structure including a gate dielectric layer 15 and a gate conductive layer 16, the gate dielectric layer 15... The inner walls of the first trench 121 and the second trench 122, and the upper surface of the dielectric material layer 13, and the sidewalls and bottom surface of the gate conductive layer 16 are located therein; a second conductivity type body region 17 and a first conductivity type source region 18, wherein the body region 17 is located on the upper surface of the epitaxial layer 11 and is adjacent to the first trench 121 and the second trench 122, and the source region 18 is located on the upper surface of the body region 17 and is flush with the upper surface of the trench gate structure; an interlayer dielectric layer 19 is located on the upper surface of the source region 18, and the interlayer dielectric layer 19 has a contact hole 20 that exposes the body region 17; and a source electrode 23 is located on the interlayer dielectric layer 19 and fills the contact hole 20.

[0097] Specifically, the contact hole 20 has a lateral width of 0.2~0.3μm and is symmetrically distributed on both sides of the first groove 121. Here, symmetry means that the contact hole 20 is symmetrical about the first groove 121.

[0098] Specifically, the contact hole 20 has a first distance 21 between it and the first trench 121, and the contact hole 20 has a second distance 22 between it and the second trench 122, with the ratio of the second distance 22 to the first distance 21 being 1.5 to 2.5. This arrangement allows for a closer distance between the contact hole 20 and the first trench 121, resulting in a higher ion concentration in the channel region and thus a higher threshold voltage; conversely, a greater distance between the contact hole 20 and the second trench 122 results in a lower ion concentration in the channel region and thus a lower threshold voltage. Furthermore, by considering the different threshold voltages between different cells of the shielded gate trench MOSFET device, the shielded gate trench MOSFET device can have a sequential turn-on function, and the later-turned channel can also serve as a heat dissipation channel for the earlier-turned channel during operation.

[0099] Specifically, the shielded gate trench MOSFET device is further provided with a passivation layer 24 and a drain 25, and the drain 25 is electrically connected to the bottom surface of the semiconductor substrate 10.

[0100] In summary, the shielded gate trench MOSFET device and its fabrication method of the present invention form elongated, continuous, asymmetric contact holes in the interlayer dielectric layer between adjacent trenches. Here, asymmetry is defined as the first distance between the contact hole and the first trench being less than the second distance between the contact hole and the second trench. This results in a higher ion concentration and thus a higher threshold voltage on the side of the contact hole closer to the first trench, and a lower ion concentration and thus a lower threshold voltage on the side of the contact hole farther from the second trench. When a voltage is applied to the gate, the channel with the lower threshold voltage turns on first, followed by the channel with the higher threshold voltage. This time-division multiplexing mechanism allows the later-turned-on channel to act as a heat dissipation channel, dispersing heat from the earlier-turned channel, thereby significantly improving the SOA performance and heat dissipation capability of the device. Furthermore, this method only requires adjusting the shape of the contact hole mask pattern, without adding any additional process steps, and thus increases manufacturing costs almost entirely. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0101] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a shielded gate trench MOSFET device, characterized in that, Includes the following steps: A semiconductor substrate having an epitaxial layer is provided, wherein a first trench and a second trench are formed in the epitaxial layer at a horizontal distance, the first trench and the second trench both opening from the upper surface of the epitaxial layer and extending downward; A dielectric material layer and a conductive material layer are sequentially formed in the first trench and the second trench. The dielectric material layer is located on the inner wall and bottom surface of the first trench and the second trench and wraps around the side wall and bottom surface of the conductive material layer. The upper surface of the dielectric material layer is lower than the upper surface of the epitaxial layer. A gate dielectric layer and a gate conductive layer are sequentially formed on the surface of the dielectric material layer. The gate dielectric layer covers the sidewalls of the first trench and the second trench and wraps the sidewalls and bottom surface of the gate conductive layer. Ion implantation is performed on the upper surface of the epitaxial layer on both sides of the first trench and the second trench to form a body region, and ion implantation is performed on the upper surface of the body region to form a source region; An interlayer dielectric layer is formed on the source region, and the interlayer dielectric layer, the source region, and the body region are etched to form a contact hole that penetrates the interlayer dielectric layer and the source region and exposes the body region; A metal is deposited on the interlayer dielectric layer to form a source electrode that fills the contact hole.

2. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that: The contact holes have a lateral width of 0.2~0.3μm and are symmetrically distributed on both sides of the first groove.

3. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that: The contact hole has a first distance from the first groove, and the contact hole has a second distance from the second groove, the value of the second distance being greater than the first distance.

4. The method for fabricating a shielded gate trench MOSFET device according to claim 3, characterized in that: The ratio of the second distance to the first distance is 1.5 to 2.

5.

5. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that: The upper surfaces of the gate dielectric layer, the gate conductive layer, and the source region are flush.

6. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that: After forming the source electrode, the process further includes forming a passivation layer, etching the passivation layer to form metal leads, and forming a drain electrode, wherein the passivation layer is located on the surface of the source electrode, and the drain electrode is electrically connected to the back side of the semiconductor substrate.

7. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that: The first trench and the second trench have equal lateral widths, both ranging from 0.8 to 1.2 μm, and the ratio of the lateral width of the conductive material layer to the lateral width of the dielectric material layer is 0.5 to 3.

8. A shielded gate trench MOSFET device, characterized in that, include: A semiconductor substrate and an epitaxial layer disposed on the semiconductor substrate; At least one cell unit is located in the epitaxial layer, the cell unit including a first trench and a second trench spaced apart in the horizontal direction; A shielding grid, comprising a dielectric material layer and a conductive material layer, wherein the dielectric material layer is located on the inner wall and bottom surface of the first trench and the second trench, the dielectric material layer wraps around the side wall and bottom surface of the conductive material layer, and the upper surface of the dielectric material layer is lower than the upper surface of the epitaxial layer; A trench gate structure, comprising a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer is located on the inner wall of the first trench and the second trench and on the upper surface of the dielectric material layer and wraps the sidewall and bottom surface of the gate conductive layer; A second conductivity type body region and a first conductivity type source region, wherein the body region is located on the upper surface of the epitaxial layer and is adjacent to the first trench and the second trench, and the source region is located on the upper surface of the body region and is flush with the upper surface of the trench gate structure; An interlayer dielectric layer is located on the upper surface of the source region, and the interlayer dielectric layer has contact holes that expose the body region; The source electrode is located on the interlayer dielectric layer and fills the contact hole.

9. The shielded gate trench MOSFET device according to claim 8, characterized in that: The contact holes have a lateral width of 0.2~0.3μm and are symmetrically distributed on both sides of the first groove.

10. The shielded gate trench MOSFET device according to claim 8, characterized in that: The contact hole has a first distance from the first groove, and the contact hole has a second distance from the second groove, wherein the ratio of the second distance to the first distance is 1.5 to 2.5.

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