Manufacturing method of transistor base metal
By depositing a dielectric layer on the emitter layer and etching an inverted trapezoidal channel followed by evaporating a Y-shaped base metal, the problems of insufficient base metal contact and increased parasitic capacitance were solved, resulting in a reduction of rb and an increase of fmax and Gain.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-18
- Publication Date
- 2026-04-07
AI Technical Summary
In the prior art, insufficient base metal contact area of transistors leads to an increase in rb, the exposed base layer is easily oxidized, increasing resistance, and increasing the base metal width leads to an increase in parasitic capacitance, affecting fmax and Gain.
After depositing a dielectric layer on the emitter layer, an inverted trapezoidal channel is etched and a Y-shaped base metal is deposited, so that the upper part is suspended and does not directly contact the dielectric layer, thereby increasing the metal volume and covering the exposed base layer and reducing parasitic capacitance.
It effectively reduces resistance (rb) and increases maximum operating frequency (fmax) and gain (Gain) without requiring optimization of the transistor epitaxial structure.
Smart Images
Figure CN121815962A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of transistor technology, in particular to a method for manufacturing a transistor base metal. BACKGROUND
[0002] As shown in the prior art, Figure 9 The area of the base layer exposed after etching of the emitter layer is larger than the contact area of the base metal, and the covered area essentially changes a part of the intrinsic base region that should have metal contact into an external base resistance, which increases the path from the base pin to the actual edge of the emission junction, and at the same time, the exposed surface of the base layer is prone to oxidation, resulting in an increase in rb, and the exposed area increases the resistance due to interface defects. In addition, although increasing the width of the base metal can reduce rb, the parasitic capacitance will also increase, resulting in a decrease in fmax and Gain. SUMMARY
[0003] The purpose of the present application is to provide a new method for manufacturing a transistor base metal, which takes into account the reduction of rb and the improvement of fmax and Gain.
[0004] To achieve the above-mentioned purpose, the present application provides the following technical solutions:
[0005] The present application provides a method for manufacturing a transistor base metal, which further comprises the following steps:
[0006] (1) depositing a layer of dielectric layer on the surface of the emitter layer of the epitaxial wafer;
[0007] (2) coating two layers of photoresist on the surface of the dielectric layer, after exposure and development, etching the exposed dielectric layer;
[0008] (3) etching a channel with an inverted trapezoidal cross-section on the exposed emitter layer;
[0009] (4) evaporating Y-shaped base metal on the channel, the lower part of the base metal filling the channel;
[0010] (5) removing the photoresist to complete the manufacturing of the transistor base metal.
[0011] Further, the material of the dielectric layer is one or more of SiN, Si3N4, Si2N3, SiO2, SiON, Al2O3, AlN and PI.
[0012] Further, the base metal is a conductive material.
[0013] Further, the base metal is a one-layer or multi-layer structure.
[0014] Further, the conductive material is one or more of Ti, Pt, Au, Al, Cu, and Ni.
[0015] Compared with the prior art, the application manufactures the upper-suspended Y-shaped base metal, the upper-suspended design of the base metal effectively reduces the parasitic capacitance without optimizing the epitaxial structure of the transistor, and the maximum operating frequency of the device is improved. Meanwhile, the volume of the base metal is increased, the rb is reduced, the exposed base layer is fully covered by the base metal, the interface defects of the base layer are improved, the surface recombination is reduced, the base oxidation is prevented, and the rb is further effectively reduced. BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 It is a cross-sectional view after a dielectric layer is deposited on the surface of an epitaxial wafer of an emitter layer.
[0017] Figure 2 It is a cross-sectional view after two photoresists are coated and part of the dielectric layer is etched.
[0018] Figure 3 It is a cross-sectional view after part of the emitter layer is etched on the emitter layer.
[0019] Figure 4 It is a cross-sectional view after the base metal is evaporated.
[0020] Figure 5 It is a cross-sectional view after the photoresist is removed.
[0021] Figure 6 It is an ft-Jc characteristic curve graph (the existing data in the figure is the data measured by the prior art, and the improved data is the data measured by the application).
[0022] Figure 7 It is an fmax-Jc relationship graph (the existing data in the figure is the data measured by the prior art, and the improved data is the data measured by the application).
[0023] Figure 8 It is a load traction test result graph (the improved technology in the figure refers to the technology of the application).
[0024] Figure 9 It is a cross-sectional view of the prior art. DETAILED DESCRIPTION
[0025] The technical solutions of the application will be further described below in combination with specific embodiments. It should be understood that the following embodiments are only illustrative and explanatory of the application, and should not be interpreted as limiting the scope of protection of the application. Any technology realized based on the above description of the application is covered within the scope of protection intended by the application.
[0026] Embodiment 1
[0027] Fabricate the transistor base metal according to the following steps:
[0028] (1) Refer to Figure 1 Depositing a dielectric layer on the surface of the Emitter layer wafer;
[0029] (2) Refer to Figure 2 Coating two layers of photoresist on the surface of the dielectric layer, after exposure and development, etching to remove the exposed dielectric layer;
[0030] (3) Refer to Figure 3 Etching a channel with an inverted trapezoidal cross-section on the exposed Emitter layer;
[0031] (4) Refer to Figure 4 Evaporating Y-shaped base metal on the channel, the lower part of the base metal fills the channel;
[0032] (5) Refer to Figure 5 Removing the photoresist to complete the fabrication of the transistor base metal.
[0033] The material of the dielectric layer is one or more of SiN, Si3N4, Si2N3, SiO2, SiON, Al2O3, AlN, PI.
[0034] The base metal is one or more of Ti, Pt, Au, Al, Cu, Ni.
[0035] The Y-shaped base metal with the upper part suspended is fabricated by the above-mentioned technology, which increases the volume of the base metal, reduces rb, and the base metal can fully cover the exposed base layer, improve the interface defects of the base layer, reduce surface recombination, prevent the oxidation of the exposed base, and further effectively reduce rb. At the same time, the upper part of the base metal is suspended and does not directly contact the dielectric layer, effectively reducing the parasitic capacitance.
[0036] By comparing the small signal electrical measurement results of the prior art and the present technology, Figure 6 It can be seen that the ft of the present technology is basically the same as that of the prior art; and referring to Figure 7 The fmax of the present technology is increased by about 19%, which is due to the fact that the rb of the present technology is reduced by about 27% compared with the prior art; Figure 8 The measurement results of Loadpull show that the Gain value of the present technology is increased by 1 dB compared with the prior art, and the present technology does not need to optimize the epitaxial structure of the transistor to increase the maximum operating frequency of the device.
[0037] Embodiment 2
[0038] Fabricate the transistor base metal according to the steps:
[0039] (1) Deposit a dielectric layer on the surface of the epitaxial wafer of the emitter layer;
[0040] (2) Apply two layers of photoresist on the surface of the dielectric layer, after exposure and development, etch and remove the exposed dielectric layer (SiN);
[0041] (3) Etch a channel with an inverted trapezoidal cross-section on the exposed emitter layer;
[0042] (4) Evaporate Y-shaped base metal (Ti) on the channel, the lower part of the base metal fills the channel;
[0043] (5) Remove the photoresist, complete the fabrication of the transistor base metal.
[0044] Example 3
[0045] Fabricate the transistor base metal according to the steps:
[0046] (1) Deposit a dielectric layer on the surface of the epitaxial wafer of the emitter layer;
[0047] (2) Apply two layers of photoresist on the surface of the dielectric layer, after exposure and development, etch and remove the exposed dielectric layer (SiO2);
[0048] (3) Etch a channel with an inverted trapezoidal cross-section on the exposed emitter layer;
[0049] (4) Evaporate Y-shaped base metal (Al) on the channel, the lower part of the base metal fills the channel;
[0050] (5) Remove the photoresist, complete the fabrication of the transistor base metal.
[0051] Although the specific embodiments of the present application are described above, it should be understood by those skilled in the art that the specific examples described are illustrative only and not limiting to the scope of the present application, and equivalent modifications and variations made in accordance with the spirit of the present application should be encompassed within the scope of the claims of the present application.
Claims
1. A method for fabricating a transistor base metal, characterized in that: Includes the following steps: (1) Deposit a dielectric layer on the surface of the epitaxial wafer of the emitter layer; (2) Two layers of photoresist are coated on the surface of the dielectric layer. After exposure and development, the exposed dielectric layer is etched away. (3) Etch a channel with an inverted trapezoidal cross section on the exposed emitter layer; (4) A Y-shaped base metal is deposited on the channel, the lower part of the base metal filling the channel; (5) Remove the photoresist to complete the fabrication of the transistor base metal.
2. The method for fabricating a transistor base metal according to claim 1, characterized in that: The material of the dielectric layer is one or more of SiN, Si3N4, Si2N3, SiO2, SiON, Al2O3, AlN, and PI.
3. The method for fabricating a transistor base metal according to claim 1, characterized in that: The base metal is a conductive material.
4. The method for fabricating a transistor base metal according to claim 1, characterized in that: The base metal has one or more layers.
5. The method for fabricating a transistor base metal according to claim 3, characterized in that: The conductive material is one or more of Ti, Pt, Au, Al, Cu, and Ni.