Microprocessor-based electrophysiological signal acquisition and wireless transmission system and signal acquisition method

Abstract

This invention discloses a microprocessor-based electrophysiological signal acquisition and wireless transmission system and method, including the following steps: converting the acquired electrophysiological analog signal into an electrophysiological digital signal; compressing the electrophysiological digital signal using a dynamic reference value compression algorithm via a zero-copy DMA transmission architecture to obtain a compressed electrophysiological digital signal; encapsulating the compressed electrophysiological digital signal through protocol transparency to generate a layered data packet; and transmitting the data packet to a host computer via a dual-mode data transmission module, providing the host computer with a data packet containing the electrophysiological signal. This invention avoids crosstalk and coherence distortion caused by phase misalignment in multi-channel signal analysis, eliminates MCU core data transfer overhead, and achieves strictly synchronous sampling across multiple channels.

Description

Technical Field

[0001] This invention relates to the field of embedded bioengineering technology, specifically to a microprocessor-based electrophysiological signal acquisition and wireless transmission system and signal acquisition method. Background Technology

[0002] Brain-computer interface (BCI) technology enables information interaction between the human brain and external devices by acquiring bioelectrical signals (such as EEG, EMG, and LFP) from the central nervous system, and has significant application value in fields such as neurorehabilitation and motor control. High-performance multimodal electrophysiological acquisition systems are the technological foundation for these applications, but existing solutions have significant limitations in terms of channel density, noise suppression, dynamic configuration capabilities, and power consumption control.

[0003] Existing technical solutions and their shortcomings:

[0004] 1. Traditional MCU-based multi-channel acquisition systems employ a modular architecture, achieving a peak detection rate of 62.5 kS / s via wireless transmission, with an input reference noise of 8 µVrms (<100Hz–10kHz bandwidth). The limited number of channels (≤64 channels) makes it difficult to meet the requirements for synchronous acquisition of high-density bioelectrical signals; the relatively high noise level (8 µVrms) fails to meet the detection accuracy requirements for µV-level weak signals (such as EEG); and the limited wireless transmission bandwidth makes it difficult to support real-time transmission at full data rates of 128 channels or higher.

[0005] 2. Integrated Circuit (ASIC) Solution: Achieves high channel density through ASIC, with a single channel power consumption of 5μW and support for 200Mbps data transmission. Hardware parameters are fixed (such as gain / bandwidth), making it impossible to dynamically adapt to multimodal signal characteristics (such as low-frequency EEG / high-frequency EMG); UWB transmission distance is limited (≤5 meters), and its anti-interference capability is insufficient, making it susceptible to environmental noise.

[0006] 3. High-bandwidth BCI system, achieving ultra-high channel count, supports USB-C wired high-speed data transmission; requires invasive implantation, not suitable for surface electrophysiological signal (such as SEMG) acquisition; high system complexity, power consumption and size are difficult to meet the needs of wearable devices.

[0007] 4. Domestic low-power front-end design, based on low-power mixed-signal design, optimizes dynamic range and noise performance. However, the number of channels is severely insufficient (≤8 channels), making it unable to support high-density electrode arrays; it also lacks real-time power frequency interference suppression capabilities, leading to signal quality degradation.

[0008] In summary, existing electrophysiological acquisition systems have the following core defects:

[0009] Firstly, poor channel scalability: traditional MCU or ASIC solutions struggle to achieve synchronous acquisition of >100 channels under low power consumption constraints;

[0010] Secondly, insufficient noise suppression: existing power frequency filtering schemes (such as notch filters) introduce phase distortion or have high computational overhead, and cannot balance real-time performance and accuracy.

[0011] Third, lack of dynamic adaptation: the hardware parameters are fixed and cannot be dynamically configured according to the signal spectrum characteristics;

[0012] Fourth, transmission bottlenecks: Wireless solutions (UWB) have limited bandwidth, and wired solutions (such as USB 2.0) cannot meet the 480Mbps data throughput requirement of 128 channels at 20kHz. Brain-computer interface (BCI) systems typically require wireless transmission of collected bioelectrical signals to a host computer for processing to achieve real-time monitoring and analysis. Existing wireless transmission solutions have significant limitations in terms of channel count, transmission rate, anti-interference capability, and power consumption, especially in high-density, multi-channel signal acquisition scenarios.

[0013] Fifth, existing wireless transmission solutions mostly use Bluetooth (BLE), ZigBee, or proprietary ISM band protocols. Existing electrophysiological acquisition systems have the following core defects in wireless transmission: Wireless bandwidth bottleneck: Unable to achieve stable transmission of ≥40Mbps under low power consumption constraints, restricting the real-time performance of high-channel-count, high-sampling-rate systems; Insufficient reliability: Wireless links are susceptible to interference in complex electromagnetic environments, leading to data packet loss or bit errors, affecting signal integrity; Lack of dynamic adaptation: Existing wireless protocol parameters (such as transmit power, channel selection) are fixed and cannot be dynamically adjusted according to environmental noise or data priority, making it difficult to balance power consumption and reliability. Summary of the Invention

[0014] This invention overcomes the shortcomings of the prior art and provides a microprocessor-based electrophysiological signal acquisition and wireless transmission system and signal acquisition method. It avoids crosstalk and coherence distortion caused by phase loss in multi-channel signal analysis, establishes a zero-copy DMA channel, directly maps the SPI receive register (DR) to the USB 3.0 transmit buffer, eliminates the data transfer overhead of the MCU core, and achieves strict synchronous sampling of 128 channels.

[0015] To achieve the above objectives, the technical solution adopted by the present invention is as follows: an electrophysiological signal acquisition method, comprising the following steps:

[0016] Acquire electrophysiological analog signals and convert them into electrophysiological digital signals;

[0017] The electrophysiological digital signal is compressed using a dynamic reference value compression algorithm through a zero-copy DMA transfer architecture to obtain the compressed electrophysiological digital signal.

[0018] The compressed electrophysiological digital signals are transparently encapsulated through a protocol to generate layered data packets;

[0019] The data packet is transmitted to the host computer through the dual-mode data transmission module, providing the host computer with a data packet containing electrophysiological signals.

[0020] In a preferred embodiment of the present invention, the dynamic reference value compression algorithm includes:

[0021] For each frame of electrophysiological digital signal to be transmitted, which contains N channels, the average value M of all channel sample values ​​in the frame is calculated in real time; the average value M is used as the dynamic reference value of the data in this frame.

[0022] Calculate the raw sample value S for each channel sequentially. i The difference D between the dynamic reference value M and the dynamic reference value M i D i =S i -M, where i=1..N;

[0023] The floating-point difference D i Perform fixed-point quantization to obtain the quantization difference;

[0024] Multiply the quantization difference by a predefined precision scaling factor to convert the floating-point difference into a numerical value with fixed precision, thus obtaining the scaled data;

[0025] Convert the scaled data into a signed 16-bit integer Q. i And establish an overflow protection mechanism to make Q i The value is limited to the range of a 16-bit signed integer, and the scaled result is obtained; dynamic reference value compression is completed.

[0026] In a preferred embodiment of the present invention, the protocol transparency encapsulation adopts a three-layer data encapsulation structure, including: a compression header, a compressed data block, and a VOFA+ protocol encapsulation; wherein the compression header is the metadata layer; the compressed data block is the algorithm layer; and the VOFA+ protocol encapsulation is the transport layer.

[0027] In a preferred embodiment of the present invention, zero-value run-length encoding optimization is achieved by compressing the quantized zero difference in the quantization difference.

[0028] In a preferred embodiment of the present invention, a hybrid data structure is used to encapsulate and construct a layered data packet, which includes: a compressed metadata header; the generation of the compressed metadata header includes: creating a fixed-format data header structure CompressHeader_t, the fields of which include: compress_type: identifying the type of compression algorithm used; channel_count: the number of channels N contained in this frame of data; original_size: the total number of bytes of the original data; compressed_size: the total number of bytes of the compressed data block;

[0029] Compressed data block assembly includes: storing data sequentially into a contiguous byte buffer.

[0030] The reference value includes: storing the dynamic reference reference value M in its original IEEE 754 single-precision floating-point format;

[0031] The quantization difference sequence includes: a 16-bit integer Q quantized from each channel. i Store each Q in the buffer sequentially according to channel order, in little-endian or big-endian format. i Occupies 2 bytes;

[0032] Zero-value compression includes: after assembling compressed data blocks, the continuous quantization difference zero value Q can be compressed. i ==0 is used for run-length encoding.

[0033] In a preferred embodiment of the present invention, protocol transparent encapsulation transmission includes:

[0034] Adding an application layer protocol header includes the following steps: adding a preamble sequence of bytes before the compressed data block, the preamble sequence being used to identify that what follows is a compressed data packet conforming to a custom format;

[0035] Transport layer frame encapsulation includes the following steps: appending a frame end identifier to the end of the complete data packet; the frame end identifier matches the data frame parsing rules of the target debugging tool, enabling the host computer to correctly identify and capture the complete data frame.

[0036] Condition-triggered transmission includes the following steps: The system triggers the compression and encapsulation process only when all N channels of new data within a frame are ready, and then sends the final generated complete data packet at once through the physical interface; after transmission is completed, the "data ready" flag of each channel is cleared.

[0037] In a preferred embodiment of the present invention, a fixed-size buffer is statically allocated during system initialization for compressed calculations and temporary data storage, avoiding dynamic memory allocation in real-time tasks, eliminating memory fragmentation and ensuring time determinism.

[0038] In a preferred embodiment of the present invention, the decoding end adopts formula S i =M+Q i / 1000.0 accurately restores the original signal.

[0039] In a preferred embodiment of the present invention, the dual-mode data transmission module includes:

[0040] The single-chip wireless interface hardware integration includes: using a SoC chip as the core processor and communication unit;

[0041] Connect the RF_IN and RF_OUT pins of the SoC chip to the 2.4GHz onboard ceramic antenna or external antenna interface via a π-type matching network; use at least one set of TX and RX pins of a universal asynchronous transceiver as spare wired serial ports for the SoC chip.

[0042] In a preferred embodiment of the present invention, a microprocessor-based electrophysiological signal acquisition and wireless transmission system includes: a controller, and a power supply module, an analog front-end chipset, a filter module, an analog-to-digital conversion module, and a dual-mode data transmission module electrically connected to the controller;

[0043] The analog front-end chipset is used to acquire analog signals and preprocess the analog signals to obtain preprocessed analog signals.

[0044] The pre-processed analog signal is converted into a digital signal through the filter module and the analog-to-digital converter module, and the digital signal is transmitted to the controller.

[0045] The controller transmits the acquired digital signals to the processing mechanism through the dual-mode data transmission module.

[0046] The filter module is used for filtering and noise reduction.

[0047] The timer module connected to the controller generates a sampling frequency and sends the sampling frequency to the analog-to-digital converter module to provide timing signals to the analog-to-digital converter module;

[0048] The dual-mode data transmission module includes a wired communication module and a wireless communication module for data transmission.

[0049] This invention addresses the deficiencies in the technical background, and the beneficial technical effects of this invention are:

[0050] A microprocessor-based electrophysiological signal acquisition and wireless transmission system and signal acquisition method avoid crosstalk and coherence distortion caused by phase loss in multi-channel signal analysis, establish a zero-copy DMA channel, directly map the SPI receive register (DR) to the USB 3.0 transmit buffer, eliminate the data transfer overhead of the MCU core, and achieve strict synchronous sampling of 128 channels. Attached Figure Description

[0051] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0052] Figure 1 This is a framework diagram of a microprocessor-based electrophysiological signal acquisition and wireless transmission system in a preferred embodiment of the present invention.

[0053] Figure 2 This is a flowchart illustrating a preferred embodiment of the present invention;

[0054] Figure 3 This is a data flow diagram in a preferred embodiment of the present invention;

[0055] Figure 4 The amplitude, phase, and frequency characteristics of the electroencephalogram (EEG) signal acquired in wired mode in a preferred embodiment of the microprocessor-based electrophysiological signal acquisition and wireless transmission system of the present invention are shown in the diagram.

[0056] Figure 5 This is a diagram showing the amplitude, phase, and frequency characteristics of an electroencephalogram (EEG) signal acquired in wireless mode using a microprocessor-based electrophysiological signal acquisition and wireless transmission system in a preferred embodiment of the present invention.

[0057] Figure 6 The amplitude, phase, and frequency characteristics of brain region electrical signals synchronously acquired under wireless conditions by a microprocessor-based electrophysiological signal acquisition and wireless transmission system in a preferred embodiment of the present invention. Figure 1 ;

[0058] Figure 7 The amplitude, phase, and frequency characteristics of brain region electrical signals synchronously acquired under wireless conditions by a microprocessor-based electrophysiological signal acquisition and wireless transmission system in a preferred embodiment of the present invention. Figure 2 ;

[0059] Figure 8 The amplitude, phase, and frequency characteristics of brain region electrical signals synchronously acquired under wireless conditions by a microprocessor-based electrophysiological signal acquisition and wireless transmission system in a preferred embodiment of the present invention. Figure 3 ;

[0060] Figure 9 This is the amplitude-phase-frequency characteristic diagram of the system noise floor at a sampling rate of 20 kHz in a preferred embodiment of the present invention;

[0061] Figure 10 This is a signal processing data diagram of the spike signal acquired at a sampling rate of 20 kHz in the electrophysiological signal processing of the microprocessor-based electrophysiological signal acquisition and wireless transmission system in a preferred embodiment of the present invention.

[0062] Figure 11This is a schematic diagram of a single spike waveform separated after threshold processing in a microprocessor-based electrophysiological signal acquisition and wireless transmission system according to a preferred embodiment of the present invention.

[0063] Figure 12 This is a schematic diagram of the average waveform separated after threshold processing in a microprocessor-based electrophysiological signal acquisition and wireless transmission system according to a preferred embodiment of the present invention.

[0064] Figure 13 The circuit structure of the microprocessor-based electrophysiological signal acquisition and wireless transmission system in a preferred embodiment of the present invention is shown below. Figure 1 (Power supply module);

[0065] Figure 14 The circuit structure of the microprocessor-based electrophysiological signal acquisition and wireless transmission system in a preferred embodiment of the present invention is shown below. Figure 2 (Front-end data acquisition module);

[0066] Figure 15 The circuit structure of the microprocessor-based electrophysiological signal acquisition and wireless transmission system in a preferred embodiment of the present invention is shown below. Figure 3 (MCU control module);

[0067] Figure 16 The circuit structure of the microprocessor-based electrophysiological signal acquisition and wireless transmission system in a preferred embodiment of the present invention is shown below. Figure 4 (Filtering module);

[0068] Figure 17 The circuit structure of the microprocessor-based electrophysiological signal acquisition and wireless transmission system in a preferred embodiment of the present invention is shown below. Figure 5 (The wireless circuit in the dual-mode data transmission module uses a 2.4G radio frequency signal transmission circuit.)

[0069] Figure 18 The circuit structure of the microprocessor-based electrophysiological signal acquisition and wireless transmission system in a preferred embodiment of the present invention is shown below. Figure 6 (Crystal oscillator circuit of MCU control module);

[0070] Figure 19 The circuit structure of the microprocessor-based electrophysiological signal acquisition and wireless transmission system in a preferred embodiment of the present invention is shown below. Figure 7 (Program download circuit);

[0071] Figure 20 The circuit structure of the microprocessor-based electrophysiological signal acquisition and wireless transmission system in a preferred embodiment of the present invention is shown below. Figure 8 (USB port circuit in dual-mode data transmission module). Detailed Implementation

[0072] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. These drawings are simplified schematic diagrams, which are only used to illustrate the basic structure of the present invention and therefore only show the components relevant to the present invention.

[0073] It should be noted that if directional indicators (such as up, down, bottom, top, etc.) are involved in the embodiments of the present invention, these directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more of that feature. Unless otherwise explicitly specified and limited, the terms "set," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components. For those skilled in the art, the specific meaning of the above terms in the present invention can be understood according to the specific circumstances.

[0074] Example 1, as Figures 1-3 As shown, an electrophysiological signal acquisition method includes the following steps:

[0075] Step 1: Acquire electrophysiological analog signals and convert them into electrophysiological digital signals.

[0076] Step 2: The electrophysiological digital signal is compressed using a dynamic reference value compression algorithm through a zero-copy DMA transfer architecture to obtain the compressed electrophysiological digital signal.

[0077] The zero-copy DMA transfer architecture includes the use of a hybrid data structure to encapsulate and construct layered data packets, which in turn include:

[0078] The generation of the compressed metadata header includes: creating a fixed-format header structure CompressHeader_t, with fields including: compress_type: identifying the type of compression algorithm used; channel_count: the number of channels N contained in this frame of data; original_size: the total number of bytes of the original data; compressed_size: the total number of bytes of the compressed data block;

[0079] Compressed data block assembly includes: storing data sequentially into a contiguous byte buffer.

[0080] The reference value includes: storing the dynamic reference reference value M in its original IEEE 754 single-precision floating-point format;

[0081] The quantization difference sequence includes: a 16-bit integer Q quantized from each channel. i Store each Q in the buffer sequentially according to channel order, in little-endian or big-endian format. i Occupies 2 bytes;

[0082] Zero-value compression includes: after assembling compressed data blocks, the continuous quantization difference zero value Q can be compressed. i ==0 is used for run-length encoding.

[0083] The dynamic reference value compression algorithm includes:

[0084] For each frame of electrophysiological digital signal to be transmitted, containing N channels, the average value M of all channel samples within that frame is calculated in real time. This average value M is then used as the dynamic reference value for the data in that frame. Specifically, for multi-channel bioelectrical signals (such as neural signals), a compression algorithm based on the dynamic reference value is proposed. Instead of using a fixed reference value, the real-time average value of each frame's data is used as the compression reference. Compared to compression based on a fixed reference value, this approach can adapt to signal fluctuations and improve compression efficiency.

[0085] Calculate the raw sample value S for each channel sequentially. i The difference D between the dynamic reference value M and the dynamic reference value M i D i =S i -M, where i=1..N;

[0086] The floating-point difference D i Perform fixed-point quantization to obtain the quantization difference;

[0087] Multiply the quantization difference by a predefined precision scaling factor to convert the floating-point difference into a numerical value with fixed precision, thus obtaining the scaled data;

[0088] Convert the scaled data into a signed 16-bit integer Q. i And establish an overflow protection mechanism to make Q i The value is limited to a 16-bit signed integer representation to obtain the scaled result; dynamic reference value compression is completed. Specifically, a floating-point reference value (32 bits) is retained as the base difference, which is then quantized using 16-bit fixed-point quantization and maintained at 0.001 precision through a scaling factor of 1000; dynamic range limitation prevents overflow. This achieves a 50% reduction in data volume while maintaining accuracy.

[0089] Specifically, zero-value run-length encoding optimization is achieved by compressing the zero-difference value after quantization in the quantization difference. This is particularly optimized for quiet periods or periods of low change commonly found in neural signals, further improving the compression ratio and reducing redundant transmission.

[0090] Step 3: The compressed electrophysiological digital signal is transparently encapsulated through the protocol to generate layered data packets.

[0091] The protocol transparency encapsulation adopts a three-layer data encapsulation structure, including: a compression header, a compressed data block, and a VOFA+ protocol encapsulation; the compression header is the metadata layer; the compressed data block is the algorithm layer; and the VOFA+ protocol encapsulation is the transport layer.

[0092] Furthermore, protocol-transparent encapsulation of transmission includes:

[0093] The application layer protocol header addition includes the following steps: adding a preamble byte sequence (e.g., 'C', 'M', 'P', 0x01) to the front of the compressed data block (including metadata header). The preamble byte sequence is used to identify that what follows is a compressed data packet conforming to a custom format.

[0094] Transport layer frame encapsulation includes the following steps: appending a frame end identifier (e.g., byte sequence 0x00,0x00,0x80,0x7f) to the end of the complete data packet (i.e., a combination of application layer protocol header and compressed data block); the frame end identifier matches the data frame parsing rules of the target debugging tool, enabling the host computer to correctly identify and capture the complete data frame;

[0095] Condition-triggered transmission includes the following steps: The system triggers the compression and encapsulation process only when all N channels within a frame have new data ready, and then sends the final generated complete data packet all at once through the physical interface; after transmission is complete, the "data ready" flag of each channel is cleared. Specifically, protocol-transparent encapsulation transmission ensures that the compressed data is seamlessly compatible with existing data stream debugging tools (such as VOFA+).

[0096] Step four: The data packet is transmitted to the host computer through the dual-mode data transmission module, providing the host computer with a data packet containing electrophysiological signals.

[0097] The dual-mode data transmission module includes:

[0098] The system employs a single-chip wireless interface hardware integration, including: using a SoC chip (CH570Q type) as the core processor and communication unit; connecting the RF_IN and RF_OUT pins of the SoC chip to a 2.4GHz onboard ceramic antenna or external antenna interface via a π-type matching network; and using at least one set of Universal Asynchronous Transceiver (UART) TX and RX pins as spare wired serial ports for the SoC chip. Specifically, the SoC chip integrates a Bluetooth Low Energy 5.0 RF transceiver and a protocol stack hardware acceleration unit, providing multiple UART interfaces.

[0099] Working principle:

[0100] Existing technologies exhibit unstable sampling rates, collecting only 14 and 19 data points per 1ms, resulting in packet loss and failing to meet the requirement of collecting 20 data points (20kHz) per 1ms. This invention performs transmit area buffering at the MCU end, sending 10 sets of data at a time. The data is then collaboratively verified with the host computer, and after timestamp processing, the sampling rate is stabilized at 20 times per 1ms (20kHz).

[0101] like Figure 10 , Figure 11 , Figure 12 As shown, this describes the preprocessing (spikestoring) of action electrical signals (i.e., spike signals acquired at a sampling rate of 20 kHz) in electrophysiological signal processing. The horizontal axis represents time t, and the vertical axis represents voltage value v. MATLAB was used for data processing, with a 2 ms time window selected based on the characteristic time window of the spike signal, and a threshold set to four times the signal's standard deviation. Figure 11 and Figure 12 This is a schematic diagram of the separated individual spikes and average waveforms after thresholding, along with corresponding enlarged views.

[0102] The front-end electrode wire of this invention is fabricated with 4 channels per electrode, i.e., 4 × 8 = 32 channels. The continuity of the number of channels in the three sets of different field potentials also illustrates the rationality of this phenomenon. Because the local discharge of the field potentials is highly synchronized, the local field potentials of the three brain regions collected in this study were generally discharged at the same time (electrophysiological signals of the three brain regions are as follows). Figure 6 , Figure 7 , Figure 8 (As shown). This also verifies that the device has the function of acquiring EEG signals from different brain regions in a single 32-channel acquisition module.

[0103] Example 2: Based on Example 1, a fixed-size buffer (such as usb_buffer

[1024] , compress_buffer) is statically allocated during system initialization for compression calculation and temporary data storage, avoiding dynamic memory allocation in real-time tasks, eliminating memory fragmentation and ensuring time determinism.

[0104] Furthermore, the decoding end uses formula S i =M+Q i / 1000.0 accurately restores the original signal. By using a precision scaling factor (1000) and 16-bit integer representation, lossless reconstruction of the original floating-point data is achieved within the dynamic range of the signal, realizing lossless precision design.

[0105] Specifically, the dual-mode data transmission module includes: a single-chip wireless interface hardware integration, comprising: a SoC chip (CH570Q type) as the core processor and communication unit; the SoC chip integrates: a Bluetooth Low Energy (BLE) 5.0 RF transceiver and protocol stack hardware acceleration unit; and multiple Universal Asynchronous Receiver / Transmitter (UART) interfaces.

[0106] A 32MHz crystal oscillator is used as the main clock source for the SoC chip. This main clock source provides the operating clock for the CPU, USB controller, and RF module via an internal phase-locked loop (PLL) within the SoC chip. Precise sampling trigger pulses are generated using an internal timer within the SoC chip. These trigger pulses are output through GPIO pins to the conversion start (CONVST) input of an external multi-channel ADC, achieving hardware synchronous sampling across all channels. A unified clock and sampling synchronization are achieved. Furthermore, the internal timer within the SoC chip serves as the system's absolute time base, and its count value is used to generate a synchronization timestamp for each frame of sampled data. Specifically, the entire compression process involves only addition, multiplication, comparison, and memory copy operations, without involving complex entropy encoding or dictionary lookups. This results in low computational complexity, making it suitable for low-computing-power microcontrollers and other similar devices.

[0107] Example 3: A microprocessor-based electrophysiological signal acquisition and wireless transmission system, comprising: a controller, and a power supply module, an analog front-end chipset, a filter module, an analog-to-digital conversion module, and a dual-mode data transmission module electrically connected to the controller;

[0108] The analog front-end chipset is used to acquire analog signals and preprocess the analog signals to obtain preprocessed analog signals.

[0109] The pre-processed analog signal is converted into a digital signal through the filter module and the analog-to-digital converter module, and the digital signal is transmitted to the controller.

[0110] The controller transmits the acquired digital signals to the processing mechanism through the dual-mode data transmission module.

[0111] The filter module is used for filtering and noise reduction.

[0112] The timer module connected to the controller generates a sampling frequency and sends the sampling frequency to the analog-to-digital converter module to provide timing signals to the analog-to-digital converter module;

[0113] The dual-mode data transmission module includes a wired communication module and a wireless communication module for data transmission.

[0114] Example 4, based on Example 3:

[0115] The analog front-end chipset includes multiple analog front-end chips. The outputs of the analog front-end chips are connected to the controller via a cascaded SPI bus, and the inputs are connected to a data transmission interface to acquire analog signals from the device under test. Preprocessing of the analog front-end chipset includes amplification and conditioning of the acquired analog signals. The processing unit includes a host computer or a physical computer.

[0116] Specifically, such as Figure 13 As shown, the power supply module includes: a power supply (3.7V lithium battery), which is introduced through the power interface CN1. One pin of the power interface CN1 is grounded, and the other pin is led out through the power switch SW1 to supply power to the analog-to-digital conversion module. The power supply supplies power to the analog LDO circuit (including the differential voltage regulator chip U12) and the digital LDO circuit (including the differential voltage regulator chip U3) in the analog-to-digital conversion module.

[0117] The analog LDO circuit outputs AVCC power, and the input of the AVCC power supply is grounded and filtered through capacitor C39; the output of the AVCC power supply is grounded through an AVCC filter circuit (capacitor C41), and the input of the digital LDO circuit is grounded and filtered through capacitor C29; the output of the DVCC power supply is grounded through a DVCC filter circuit (converted in parallel by capacitors C44 and C30). Figure 16 As shown, the filter module includes: the digital LDO circuit outputting the DVCC power supply is also connected in parallel with capacitors C11, C12, C13, C14, and C15, which are grounded at the same point to achieve power supply filtering. The analog LDO circuit outputting the AVCC power supply is also connected in parallel with capacitors C16 and C17, which are grounded at the same point to achieve power supply filtering.

[0118] Specifically, such as Figure 15 As shown, the controller includes: an MCU control chip (control chip U1), and the crystal oscillator terminal of the MCU control chip (control chip U1) is connected to a crystal oscillator circuit (such as...). Figure 18 As shown, it includes a crystal oscillator chip X1. Figure 15As shown, the CLK pin, NSS pin, MISO pin, and MOSI pin of the IO port groups PA, PB, PC, and PD of the MCU control chip are connected to the corresponding data transmission interface FPC connectors (including connector FPC6 chip, connector FPC7 chip, connector FPC8 chip, and connector FPC9 chip) through the corresponding analog front-end chipset channel digital isolators (including channel digital isolator U6 chip, channel digital isolator U7 chip, channel digital isolator U10 chip, and channel digital isolator U11 chip).

[0119] like Figure 20 As shown, the debug interface of the MCU control chip is also connected to an FPC connector (connector FPC1). The FPC connector uses existing products, and the specific models will not be described or listed here.

[0120] Specifically, the dual-mode data transmission module includes: a USB interface circuit for the wired communication module and a 2.4GHz onboard ceramic antenna for the wireless communication module. For example... Figure 20 As shown, the MCU control chip is also connected to a USB interface circuit (including a USB3 chip). Figure 17 As shown, the 2.4GHz onboard ceramic antenna includes a 2.4G RF signal transmitting chip. The port of the 2.4G RF signal transmitting chip is connected to a crystal oscillator X3 (parameter is 32MHz). The PA7 port is connected in series with the light-emitting diode LED1 (antenna data transmission indicator) through the resistor R11 and then connected to the DVCC power supply. The XI port of the 2.4G RF signal transmitting chip is connected to the antenna E1 on the 2.4G RF board.

[0121] Example 5, based on Example 4, such as Figure 14 As shown, the CLK pin, NSS pin, MISO pin, and MOSI pin of the IO port groups PA, PE, PC, and PD of the MCU control chip are connected to the corresponding data transmission interface FPC connectors (including connector FPC6 chip, connector FPC9 chip, connector FPC8 chip, and connector FPC7 chip) through the multi-channel digital isolators of the corresponding analog front-end chipset (including channel digital isolator U8 chip, channel digital isolator U9 chip, channel digital isolator U10 chip, and channel digital isolator U11 chip; the selected chip is a four-channel digital isolator, model CA-IS3741HW).

[0122] like Figures 13-20As shown, the analog front-end chipset uses four analog front-end chips, the model of which is INTANRHD2132; it is connected to the controller via a cascaded SPI bus. The controller used is an STM321723VGT6 controller. The data transmission interface uses a TSB3.0 chip. The analog LDO circuit uses an LT3045EMSE chip, and the digital LDO circuit uses an SPX3819 voltage conversion chip. The selection of component models is not limited to these; in other embodiments, existing product models can be selected according to actual usage requirements, as long as they can basically achieve the functions to be performed by the corresponding chips in this embodiment. Furthermore, a filter for 50Hz power frequency filtering is used for filtering operations; the filtering operation is implemented on the KEIL5 embedded operating platform. The specific implementation process is to perform two-stage delay and subtraction operations on the acquired discrete-time digital signal to suppress signals of specific frequencies.

[0123] In this embodiment, one end of resistor R3 is connected to analog ground, and the other end is connected to digital ground. Resistor R3 is a 0-ohm resistor, providing physical isolation and a single-ended connection. The function of resistor R3 is to provide a single-ended connection between the analog and digital circuits in the circuit diagram, preventing digital signals from interfering with analog signals. The function of connecting both ends of inductor L1 to digital ground is to connect the negative terminal of the power supply to the negative terminal of the digital circuit, while suppressing the influence of high-frequency signals in the digital circuit on the power supply.

[0124] Working principle:

[0125] This invention discloses a microprocessor-based electrophysiological signal acquisition and wireless transmission system and signal acquisition method, which avoids crosstalk and coherence distortion caused by phase loss in multi-channel signal analysis, establishes a zero-copy DMA channel, directly maps the SPI receive register (DR) to the USB 3.0 transmit buffer, eliminates the data transfer overhead of the MCU core, and achieves strict synchronous sampling of 128 channels.

[0126] First, achieving strictly synchronized acquisition and high-frequency sampling of 128 channels of electrophysiological signals: This involves achieving fully synchronized, high-fidelity acquisition of 128 channels of neurophysiological signals. The core of this achievement lies in employing a high-precision, low-jitter global master clock circuit to provide a unified sampling clock reference for all analog front-ends (AFEs) and analog-to-digital converters (ADCs), eliminating clock phase deviations between channels at the source. Through precise layout and timing-driven design, the sampling time uncertainty (clock jitter) introduced by the clock distribution network between channels is strictly controlled within ±5ns, ensuring strict timing alignment of sampling points across all channels at a maximum sampling rate of 20kS / s / channel. This design effectively avoids crosstalk and coherence distortion problems caused by phase misalignment in multi-channel signal analysis, providing a high-quality data foundation for subsequent time-frequency analysis and network oscillation research.

[0127] Second, an on-chip lossless / near-lossless compression algorithm based on inter-channel correlation: To address the challenges posed by the massive data generated by high channel counts and high sampling rates to transmission and storage, the system integrates a highly efficient on-chip real-time compression algorithm. This algorithm innovatively utilizes the characteristic that multi-channel local field potential (LFP) signals share similar low-frequency trends in space. The specific process is as follows: First, the instantaneous average value of all 128 channels is calculated as a common reference baseline; then, the original sampled value of each channel is subtracted from this common baseline to obtain a differential signal containing only the channel-specific high-frequency components and slight deviations; finally, this differential signal is quantized and encoded into a 16-bit integer. Through this "de-common mode + differential encoding" strategy, while maintaining the integrity of key neural information, the original data volume is approximately halved (compression ratio close to 2:1), significantly reducing data bandwidth requirements and subsequent storage costs.

[0128] Third, the adaptive wired / wireless dual-mode data transmission solution: The system is equipped with a USB 3.0 wired and 2.4G RF wireless dual-mode data transmission interface to flexibly adapt to the needs of different experimental scenarios. This solution is not a simple hardware stacking, but rather dynamically controlled through an integrated intelligent link management unit. Users can dynamically select or switch the main transmission link according to experimental needs (e.g., for zero-latency, high-reliability motion signal recording, or for long-term recording of local field potentials requiring greater freedom of device movement), either at the firmware level (e.g., through the KEIL5 integrated development environment) or via host computer commands. The wired mode provides maximum bandwidth and highest stability; the wireless mode provides greater freedom of device movement. The dual-mode design ensures that the system can meet the high-performance requirements of fixed experimental platforms as well as mobile scenarios such as free-moving animal experiments, greatly improving the applicability and convenience of the equipment.

[0129] The above specific embodiments are specific support for the concept proposed in this invention, and should not be used to limit the scope of protection of this invention. Any equivalent changes or modifications made on the basis of this technical solution in accordance with the technical concept proposed in this invention shall still fall within the scope of protection of this invention.

Claims

1. A method for acquiring electrophysiological signals, characterized in that: Includes the following steps: Acquire electrophysiological analog signals and convert them into electrophysiological digital signals; The electrophysiological digital signal is compressed using a dynamic reference value compression algorithm through a zero-copy DMA transfer architecture to obtain the compressed electrophysiological digital signal. The compressed electrophysiological digital signals are transparently encapsulated through a protocol to generate layered data packets; The data packet is transmitted to the host computer through the dual-mode data transmission module, providing the host computer with a data packet containing electrophysiological signals; The dynamic reference value compression algorithm includes: For each frame of electrophysiological digital signal to be transmitted, which contains N channels, the average value M of all channel samples in the frame is calculated in real time. The average value M is used as the dynamic reference baseline value for the data in this frame. Calculate the raw sample value S for each channel sequentially. i The difference D between the dynamic reference value M and the dynamic reference value M i D i =S i -M, where i=1..N; The floating-point difference D i Perform fixed-point quantization to obtain the quantization difference; Multiply the quantization difference by a predefined precision scaling factor to convert the floating-point difference into a numerical value with fixed precision, thus obtaining the scaled data; Convert the scaled data into a signed 16-bit integer Q. i And establish an overflow protection mechanism to make Q i The value is limited to the range of a 16-bit signed integer, and the scaled result is obtained; dynamic reference value compression is completed.

2. The electrophysiological signal acquisition method according to claim 1, characterized in that: The protocol transparent encapsulation adopts a three-layer data encapsulation structure, including: compression header, compressed data block, and VOFA+ protocol encapsulation; where the compression header is the metadata layer; the compressed data block is the algorithm layer; and the VOFA+ protocol encapsulation is the transport layer.

3. The electrophysiological signal acquisition method according to claim 2, characterized in that: Zero-value run-length encoding optimization is achieved by compressing the quantized zero difference in the quantization difference.

4. The electrophysiological signal acquisition method according to claim 3, characterized in that: The zero-copy DMA transfer architecture includes: A hybrid data structure is used to encapsulate and construct layered data packets, which include: a compressed metadata header; The generation of the compressed metadata header includes: creating a fixed-format header structure CompressHeader_t, with fields including: compress_type: identifying the type of compression algorithm used; channel_count: the number of channels N contained in this frame of data; original_size: the total number of bytes of the original data; compressed_size: the total number of bytes of the compressed data block; Compressed data block assembly includes: storing data sequentially into a contiguous byte buffer. The reference value includes: storing the dynamic reference reference value M in its original IEEE 754 single-precision floating-point format; The quantization difference sequence includes: a 16-bit integer Q quantized from each channel. i Store each Q in the buffer sequentially according to channel order, in little-endian or big-endian format. i Occupies 2 bytes; Zero-value compression includes: after assembling compressed data blocks, the continuous quantization difference zero value Q can be compressed. i ==0 is used for run-length encoding.

5. The electrophysiological signal acquisition method according to claim 4, characterized in that: Protocol transparent encapsulation transmission includes: Adding an application layer protocol header includes the following steps: adding a preamble sequence of bytes before the compressed data block, the preamble sequence being used to identify that what follows is a compressed data packet conforming to a custom format; Transport layer frame encapsulation includes the following steps: appending a frame end identifier to the end of the complete data packet; the frame end identifier matches the data frame parsing rules of the target debugging tool, enabling the host computer to correctly identify and capture the complete data frame. Condition-triggered transmission includes the following steps: The system triggers the compression and encapsulation process only when all N channels of new data are ready within a frame, and then sends the final generated complete data packet at once through the physical interface; after the transmission is completed, the "data ready" flag of each channel is cleared.

6. The electrophysiological signal acquisition method according to claim 5, characterized in that: A fixed-size buffer is statically allocated during system initialization for compressed calculations and temporary data storage, avoiding dynamic memory allocation in real-time tasks, eliminating memory fragmentation, and ensuring time determinism.

7. The electrophysiological signal acquisition method according to claim 6, characterized in that: The decoding end uses formula S i =M+Q i / 1000.0 restores the original signal.

8. The electrophysiological signal acquisition method according to claim 7, characterized in that: The dual-mode data transmission module includes: The single-chip wireless interface hardware integration includes: using a SoC chip as the core processor and communication unit; Connect the RF_IN and RF_OUT pins of the SoC chip to the 2.4GHz onboard ceramic antenna or external antenna interface via a π-type matching network; use at least one set of TX and RX pins of a universal asynchronous transceiver as spare wired serial ports for the SoC chip.

9. A microprocessor-based electrophysiological signal acquisition and wireless transmission system, characterized in that, The method for acquiring electrophysiological signals according to any one of claims 1-8 includes: The controller, and a power supply module, an analog front-end chipset, a filter module, an analog-to-digital conversion module, and a dual-mode data transmission module electrically connected to the controller; The analog front-end chipset is used to acquire analog signals and preprocess the analog signals to obtain preprocessed analog signals. The pre-processed analog signal is converted into a digital signal through the filter module and the analog-to-digital converter module, and the digital signal is transmitted to the controller. The controller transmits the acquired digital signals to the processing mechanism through the dual-mode data transmission module. The filter module is used for filtering and noise reduction. The timer module connected to the controller generates a sampling frequency and sends the sampling frequency to the analog-to-digital converter module to provide timing signals to the analog-to-digital converter module; The dual-mode data transmission module includes a wired communication module and a wireless communication module for data transmission.

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