LDO circuit with current limiting value changing along with output voltage
By designing an LDO circuit with a current limiting value that varies with the output voltage, the problem of chip damage in high-voltage, high-current LDOs when the output voltage changes or is short-circuited is solved, synchronous control of the output current is achieved, and the reliability of the LDO is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUXI MILESTONE SEMICON INC
- Filing Date
- 2025-12-25
- Publication Date
- 2026-04-10
AI Technical Summary
High-voltage, high-current LDOs may be damaged when the output voltage changes or short circuits occur, and existing technologies make it difficult to synchronously control the output current value.
An LDO circuit with a current limiting value varying with the output voltage was designed, including an LDO output module, a current limiting module, and a power supply module. Through a circuit structure composed of PMOS and NMOS transistors, capacitors, resistors, etc., the current limiting value is positively correlated with the output voltage, and is fixed at the short-circuit current limiting value during short circuit.
When the output voltage changes or is short-circuited, the output current value is controlled synchronously, which avoids chip damage caused by sudden voltage drops or large currents and improves the reliability of LDO.
Smart Images
Figure CN121832684A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of voltage stabilizing circuit, in particular to a LDO circuit with current limit value changing with output voltage. BACKGROUND
[0002] With the progress of society, more and more lithium batteries and high-voltage power supply application scenarios, high-voltage output LDO is used more and more widely. But high-voltage and large-current LDO has a fatal defect, such as when the LDO output is 12V, the output power of the LDO with current limit of 1A is 12W, but when the output power is large and the output voltage is high, the output power is pulled from 12V to 0V in an instant, due to the large output current and the inductive and capacitive load of the output line, the output end may produce negative voltage, resulting in chip damage. Therefore, the output current value needs to be controlled synchronously when the LDO output voltage changes or the output is short-circuited. SUMMARY
[0003] The present application relates to the technical field of voltage stabilizing circuit, in particular to a LDO circuit with current limit value changing with output voltage. A LDO circuit with current limit value changing with output voltage, comprising an LDO output module, a current limit module and a power supply module, wherein, The power supply module is connected with the current limit module, the current limit module is connected with the LDO output module, the LDO output module is used for outputting output voltage VOUT, the power supply module is used for supplying power to the current limit module, and the current limit module is used for limiting the output current of the LDO output module to a current limit value, wherein, The LDO output module is in normal operation, and the current limit value is positively correlated with the output voltage VOUT; when the LDO output module is short-circuited, the current limit value is fixed as a short-circuit current limit value.
[0004] Further technical solutions are that the current limit module comprises a PMOS tube P6, a PMOS tube P7, a resistor R2, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3 and a capacitor C1, wherein, The gate of the PMOS tube P6 and the gate of the PMOS tube P7 are connected with the LDO output module, the source of the PMOS tube P6 is connected with one end of the resistor R2 and the power supply module, the other end of the resistor R2 is connected with the source of the PMOS tube P7, and the drain of the PMOS tube P6 is connected with the drain of the NMOS tube N1 and the gate of the NMOS tube N1.
[0005] Further, the gate of the NMOS transistor N1 is connected with the gate of the NMOS transistor N2, the drain of the PMOS transistor P7 is connected with the drain of the NMOS transistor N2 and the gate of the NMOS transistor N3, the source of the NMOS transistor N1, the NMOS transistor N2 and the NMOS transistor N3 is grounded, one end of the capacitor C1 is connected with the gate of the NMOS transistor N3, and the other end of the capacitor C1 is connected with the gate of the PMOS transistor P6.
[0006] Further, the LDO output module comprises a sampling unit, a current mirror unit and an output unit which are connected, the output unit comprises an operational amplifier U1, a PMOS transistor P3 and an NMOS transistor N4. The non-inverting input end of the operational amplifier U1 is connected with a reference voltage, the inverting input end of the operational amplifier U1 is connected with the sampling unit, the output end of the operational amplifier U1 is connected with the drain of the NMOS transistor N3 and the gate of the NMOS transistor N4, the source of the NMOS transistor N4 is grounded, the drain of the NMOS transistor N4 is connected with the drain of the PMOS transistor P3 and the gate of the PMOS transistor P3, and the source of the PMOS transistor P3 is connected with an input voltage VIN.
[0007] Further, the current mirror unit comprises a PMOS transistor P4 and a PMOS transistor P5, the gate of the PMOS transistor P4 and the gate of the PMOS transistor P5 are connected with the gate of the PMOS transistor P3, the source of the PMOS transistor P4 and the PMOS transistor P5 is connected with the input voltage VIN, and the drain of the PMOS transistor P4 and the PMOS transistor P5 is connected with the sampling unit.
[0008] Further, the sampling unit comprises a resistor R3, a resistor R4 and a resistor R5, one end of the resistor R4 is connected with the drain of the PMOS transistor P5 and forms an output end of an output voltage VOUT, the other end of the resistor R4 is connected with the inverting input end of the operational amplifier U1, the gate of the PMOS transistor P7 and one end of the resistor R5, one end of the resistor R3 is connected with the drain of the PMOS transistor P4 and the gate of the PMOS transistor P6, and the other end of the resistor R3 and the resistor R5 is grounded.
[0009] Further, the width-length ratio of the PMOS transistor P3, the PMOS transistor P4 and the PMOS transistor P5 is P:M:N.
[0010] A further technical scheme is that the power supply module comprises a PMOS tube P1, a PMOS tube P2, an NMOS tube ND1 and a resistor R1, the source of the PMOS tube P1 and the source of the PMOS tube P2 are connected to an input voltage VIN, the drain of the PMOS tube P1 is connected to the gate of the PMOS tube P1, the gate of the PMOS tube P1 is connected to the gate of the PMOS tube P2, the drain of the PMOS tube P2 is connected to the source of a PMOS tube P6 and one end of the resistor R2, the drain of the PMOS tube P1 is connected to the drain of the NMOS tube ND1, the gate of the NMOS tube ND1 is grounded, and the source of the NMOS tube ND1 is grounded through the resistor R1.
[0011] A further technical scheme is that the short-circuit current limiting value IOUT1 can be represented as:
[0012] Wherein, IB1 is the current flowing through the PMOS tube P2.
[0013] A further technical scheme is that when the LDO output module is normally working, the current limiting value IOUT can be represented as: .
[0014] The beneficial technical effects of the present application are: The LDO circuit with a current limiting value changing with an output voltage provided by the present application can reduce the current limiting value with the decrease of the output voltage VOUT when the LDO output module normally outputs, and the current limiting value is fixed as a small short-circuit current limiting value when the LDO output module outputs a short circuit, i.e., the output voltage VOUT=0. Thus, the output current value can be synchronously controlled when the LDO output voltage changes or outputs a short circuit, avoiding the failure damage caused by large current when the output voltage suddenly drops or outputs a short circuit. BRIEF DESCRIPTION OF DRAWINGS
[0015] Figure 1 is a circuit schematic diagram of an embodiment of the LDO circuit with a current limiting value changing with an output voltage provided by the present application.
[0016] Figure 2 is a simulation result diagram of the LDO circuit with a current limiting value changing with an output voltage provided by the present application. DETAILED DESCRIPTION
[0017] The specific embodiments of the present application will be further described in conjunction with the accompanying drawings. It can be understood that the specific embodiments described herein are only used to explain the related content, and are not a limitation on the present disclosure.
[0018] The present application discloses an LDO circuit with a current limiting value changing with an output voltage, comprising an LDO output module, a current limiting module and a power supply module, wherein, The power supply module is connected with a current limiting module, the current limiting module is connected with an LDO output module, the LDO output module is used for outputting an output voltage VOUT, the power supply module is used for supplying power for the current limiting module, and the current limiting module is used for limiting an output current of the LDO output module to a current limiting value, wherein, When the LDO output module works normally, the current limiting value is positively correlated with the output voltage VOUT, that is, the current limiting value decreases with the decrease of the output voltage VOUT; when the LDO output module outputs a short circuit, that is, the output voltage VOUT=0, the current limiting value is fixed at a short circuit current limiting value.
[0019] Specifically, as shown in the figure, Figure 1 The current limiting module includes a PMOS tube P6, a PMOS tube P7, a resistor R2, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3 and a capacitor C1, wherein, The gate of the PMOS tube P6 and the gate of the PMOS tube P7 are connected with the LDO output module, the source of the PMOS tube P6 is connected with one end of the resistor R2 and the power supply module, the other end of the resistor R2 is connected with the source of the PMOS tube P7, and the drain of the PMOS tube P6 is connected with the drain of the NMOS tube N1 and the gate of the NMOS tube N1. The gate of the NMOS tube N1 is connected with the gate of the NMOS tube N2, the drain of the PMOS tube P7 is connected with the drain of the NMOS tube N2 and the gate of the NMOS tube N3, the sources of the NMOS tube N1, the NMOS tube N2 and the NMOS tube N3 are grounded, one end of the capacitor C1 is connected with the gate of the NMOS tube N3, and the other end of the capacitor C1 is connected with the gate of the PMOS tube P6. The capacitor C1 is used for ensuring that the current limiting module works normally without oscillation, and the resistor R2 is used for providing bias for the current limiting module. The specific working principle of the current limiting module can be referred to the following description.
[0020] The power supply module includes a PMOS tube P1, a PMOS tube P2, an NMOS tube ND1 and a resistor R1, the sources of the PMOS tube P1 and the PMOS tube P2 are connected with an input voltage VIN, the drain of the PMOS tube P1 is connected with the gate of the PMOS tube P1, the gate of the PMOS tube P1 is connected with the gate of the PMOS tube P2, the drain of the PMOS tube P2 is connected with the source of the PMOS tube P6 and one end of the resistor R2, the drain of the PMOS tube P1 is connected with the drain of the NMOS tube ND1, the gate of the NMOS tube ND1 is grounded, and the source of the NMOS tube ND1 is grounded through the resistor R1. The NMOS tube ND1 is a depletion mode NMOS tube, a reference current is generated by the NMOS tube ND1, the resistor R1 and the PMOS tube P1, the PMOS tube P1 and the PMOS tube P2 constitute a current mirror, and the reference current is copied to the current limiting module to supply power for the current limiting module.
[0021] Further, the LDO output module comprises a sampling unit, a current mirror unit and an output unit connected in sequence, wherein the output unit comprises an operational amplifier U1, a PMOS tube P3 and an NMOS tube N4. The non-inverting input terminal of the operational amplifier U1 is connected to a reference voltage, the inverting input terminal of the operational amplifier U1 is connected to the sampling unit, the output terminal of the operational amplifier U1 is connected to the drain of the NMOS tube N3 and the gate of the NMOS tube N4, the source of the NMOS tube N4 is grounded, the drain of the NMOS tube N4 is connected to the drain of the PMOS tube P3 and the gate of the PMOS tube P3, and the source of the PMOS tube P3 is connected to an input voltage VIN. The reference voltage can be provided by a BANDGAP module, the NMOS tube N4 is used as the output tube of the operational amplifier U1, and the PMOS tube P3 is used as the adjusting tube. In this embodiment, the BANDGAP module provides a 1.2V reference voltage to the non-inverting input terminal of the operational amplifier U1.
[0022] The current mirror unit comprises a PMOS tube P4 and a PMOS tube P5, the gates of the PMOS tube P4 and the PMOS tube P5 are connected to the gate of the PMOS tube P3, the sources of the PMOS tube P4 and the PMOS tube P5 are connected to the input voltage VIN, the drains of the PMOS tube P4 and the PMOS tube P5 are connected to the sampling unit, and the PMOS tube P5 is a power MOS. The PMOS tube P4 and the PMOS tube P5 form a current mirror with the PMOS tube P3, and the width-length ratio of the PMOS tube P3, the PMOS tube P4 and the PMOS tube P5 is in the ratio of P:M:N.
[0023] The sampling unit comprises resistors R3, R4 and R5, one end of the resistor R4 is connected with the drain of PMOS tube P5 and forms an output end of output voltage VOUT, the other end of the resistor R4 is connected with the inverting input end of operational amplifier U1, the gate of PMOS tube P7 and one end of resistor R5, one end of the resistor R3 is connected with the drain of PMOS tube P4 and the gate of PMOS tube P6, the other ends of the resistors R3 and R5 are grounded. The resistors R4 and R5 generate VFB1 by sampling output voltage VOUT through voltage division, VFB1=VOUT×R5 / (R4+R5), VFB1 is loaded to the inverting input end of operational amplifier U1 and the gate of PMOS tube P7. Resistor R3 is a current-limiting sampling resistor, the voltage VFB2 between the two ends of resistor R3 is IP4×R3, IP4 is the current flowing through PMOS tube P4, since the width-length ratio of the PMOS tube P3, the PMOS tube P4 and the PMOS tube P5 is P:M:N, the current flowing through PMOS tube P5 is output current IOUT, then IP4=IOUT×M / N, VFB2=IOUT×R3×M / N can be obtained, then IOUT=VFB2×N / MR3.
[0024] The working principles of each circuit in the LDO circuit with the current-limiting value changing with the output voltage are described in detail as follows: The working principle of the LDO output module is that when VFB1 is less than the reference voltage 1.2V, the output end of operational amplifier U1 outputs high level, so that NMOS tube N4 is turned on, and thus PMOS tube P3, PMOS tube P4 and PMOS tube P5 are turned on, the output end of output voltage VOUT is raised to output output voltage VOUT; similarly, when VFB1 is greater than the reference voltage 1.2V, NMOS tube N4 is turned off, and thus PMOS tube P3, PMOS tube P4 and PMOS tube P5 are turned off.
[0025] The working principle of the current-limiting module is that when the current flowing through PMOS tube P3 increases, i.e. the load current of PMOS tube P5 increases, the current flowing through PMOS tube P4 increases, and VFB2 is raised. When VFB2 is raised to a value greater than VFB1, since VFB2 is raised, PMOS tube P6 is turned off, NMOS tube N1 and NMOS tube N2 are turned off, PMOS tube P7 is turned on, the gate of NMOS tube N3 is pulled high, NMOS tube N3 is turned on, and the gate of NMOS tube N4 is pulled to ground potential, so that the currents flowing through PMOS tube P3, PMOS tube P4 and PMOS tube P5 are reduced, and output current IOUT is reduced to play a current-limiting role.
[0026] The resistor R2 provides bias for the current limiting module, ensuring that there is an initial current (short circuit current) when the output voltage VOUT is 0V, so that the LDO output can be normally pulled high. When the LDO output module outputs a short circuit, i.e., the output voltage VOUT = 0, VFB2 = IB1 x R2 / 2, IB1 is the current flowing through the PMOS tube P2, i.e., the reference current provided by the power supply module, and then the short circuit current limiting value IOUT1 can be represented as:
[0027] When the output voltage VOUT is lifted, the LDO output module normally outputs, VFB2 = VFB1 + IB1 x R2 / 2, and because IOUT = VFB2 x N / MR3, then the current limiting value IOUT can be represented as:
[0028] The LDO circuit with the above-mentioned current limiting value changing with the output voltage is simulated and verified, as shown in FIG. 1, when the output voltage VOUT = 0, the output current IOUT is limited to a small short circuit current limiting value (about 0.12A), and after the output voltage VOUT is lifted, the current limiting value increases with the increase of the output voltage VOUT. Figure 2
[0029] In summary, the present application can synchronously control the output current value when the LDO output voltage changes or is short-circuited, provide a short circuit current when the LDO output module is short-circuited, and make the output current change with the output voltage when the LDO normally works, so as to avoid the failure and damage caused by large current when the LDO output voltage suddenly drops or is short-circuited, and improve the reliability.
[0030] In the description of the present specification, the terms "first", "second", "third", "fourth" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise specifically limited.
[0031] Reference to terms "one embodiment / way", "some embodiments / ways", "an example", "a specific example", or "some examples" etc. means that a particular feature, structure, material or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. Descriptive terms of the above-mentioned terms in the specification are not necessarily directed to the same embodiment or example. Moreover, the described specific features, structures, materials or characteristics can be combined in any appropriate manner in any one or more embodiments or examples. Furthermore, different embodiments or examples described in the specification and features of different embodiments or examples can be combined and combined by those skilled in the art without contradiction, if any.
[0032] The above-mentioned is only the preferred embodiment of the application, and the application is not limited to the above-mentioned embodiments. It can be understood that other improvements and changes directly derived or thought by those skilled in the art without departing from the spirit and concept of the application should be considered to be included in the protection scope of the application.
Claims
1. An LDO circuit in which the current limiting value varies with the output voltage, characterized in that, The LDO output module, the current limiting module and the power supply module are connected, the current limiting module is connected with the LDO output module, the LDO output module is used for outputting output voltage VOUT, the power supply module is used for supplying power for the current limiting module, and the current limiting module is used for limiting the output current of the LDO output module to a current limiting value, wherein The current limiting value is positively correlated with the output voltage VOUT when the LDO output module is in normal operation, and the current limiting value is fixed as a short circuit current limiting value when the LDO output module outputs short circuit. The current limiting module comprises a PMOS tube P6, a PMOS tube P7, a resistor R2, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3 and a capacitor C1, wherein 2. The LDO circuit of claim 1, wherein, The gate of the PMOS tube P6 and the gate of the PMOS tube P7 are connected with the LDO output module, the source of the PMOS tube P6 is connected with one end of the resistor R2 and the power supply module, the other end of the resistor R2 is connected with the source of the PMOS tube P7, and the drain of the PMOS tube P6 is connected with the drain of the NMOS tube N1 and the gate of the NMOS tube N1. The gate of the NMOS tube N1 is connected with the gate of the NMOS tube N2, the drain of the PMOS tube P7 is connected with the drain of the NMOS tube N2 and the gate of the NMOS tube N3, the sources of the NMOS tube N1, the NMOS tube N2 and the NMOS tube N3 are grounded, one end of the capacitor C1 is connected with the gate of the NMOS tube N3, and the other end of the capacitor C1 is connected with the gate of the PMOS tube P6.
3. The LDO circuit of claim 2, wherein, The LDO output module comprises a sampling unit, a current mirror unit and an output unit connected with each other, and the output unit comprises an operational amplifier U1, a PMOS tube P3 and an NMOS tube N4.
4. The LDO circuit of claim 3, wherein, The non-inverting input end of the operational amplifier U1 is connected with a reference voltage, the inverting input end of the operational amplifier U1 is connected with the sampling unit, the output end of the operational amplifier U1 is connected with the drain of the NMOS tube N3 and the gate of the NMOS tube N4, the source of the NMOS tube N4 is grounded, the drain of the NMOS tube N4 is connected with the drain of the PMOS tube P3 and the gate of the PMOS tube P3, and the source of the PMOS tube P3 is connected with an input voltage VIN. The current mirror unit comprises a PMOS tube P4 and a PMOS tube P5, the gates of the PMOS tube P4 and the PMOS tube P5 are connected with the gate of the PMOS tube P3, the sources of the PMOS tube P4 and the PMOS tube P5 are connected with the input voltage VIN, and the drains of the PMOS tube P4 and the PMOS tube P5 are connected with the sampling unit.
5. The LDO circuit of claim 4, wherein, 6. The LDO circuit of claim 5, wherein, The sampling unit comprises resistors R3, R4 and R5, one end of the resistor R4 is connected with the drain of PMOS tube P5 and forms the output end of output voltage VOUT, the other end of the resistor R4 is connected with the inverting input end of operational amplifier U1, the gate of PMOS tube P7 and one end of resistor R5, one end of the resistor R3 is connected with the drain of PMOS tube P4 and the gate of PMOS tube P6, the other ends of the resistors R3 and R5 are grounded.
7. The LDO circuit of claim 5, wherein, The width-length ratio of the PMOS tube P3, the PMOS tube P4 and the PMOS tube P5 is P:M:N.
8. The LDO circuit of claim 6, wherein, The power supply module comprises PMOS tube P1, PMOS tube P2, NMOS tube ND1 and resistor R1, the sources of the PMOS tube P1 and PMOS tube P2 are connected with input voltage VIN, the drain of the PMOS tube P1 is connected with the gate, the gate of the PMOS tube P1 is connected with the gate of PMOS tube P2, the drain of the PMOS tube P2 is connected with the source of PMOS tube P6 and one end of resistor R2, the drain of the PMOS tube P1 is connected with the drain of NMOS tube ND1, the gate of the NMOS tube ND1 is grounded, the source of the NMOS tube ND1 is grounded through resistor R1.
9. The LDO circuit of claim 8, wherein, The short-circuit current limiting value IOUT1 can be represented as: Wherein, IB1 is the current flowing through the PMOS tube P2.
10. The LDO circuit of claim 8, wherein, When the LDO output module works normally, the current limiting value IOUT can be represented as: 。