hardware synchronization lock

By using hardware synchronization locks and counter mechanisms, the problems of insufficient scalability of AI computing hardware units and low collaborative efficiency of general processing units are solved, realizing efficient hardware computing unit collaboration and supporting the computing needs of new AI algorithms and models.

CN121833299BActive Publication Date: 2026-06-19MOXIN ARTIFICIAL INTELLIGENCE TECH (SHENZHEN) CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
MOXIN ARTIFICIAL INTELLIGENCE TECH (SHENZHEN) CO LTD
Filing Date
2026-03-12
Publication Date
2026-06-19

AI Technical Summary

Technical Problem

Existing AI computing hardware units lack scalability when processing new algorithms and models, and general-purpose processing units suffer from low collaborative efficiency when supporting new computing tasks.

Method used

A hardware synchronization lock is adopted, and a counter mechanism is used to coordinate the task execution among multiple hardware computing units to ensure that tasks are allowed to start only when specified conditions are met, thereby achieving efficient task scheduling and resource allocation.

Benefits of technology

It improves the collaborative efficiency between multiple hardware computing units, maximizes their respective performance and power consumption advantages, and supports the computing needs of various new AI algorithms and models.

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Abstract

A hardware synchronization lock is disclosed, including a counter configured to: when any one of the first hardware computing units holding the hardware synchronization lock releases the hardware synchronization lock to the same second hardware computing unit, increment the counter by 1; and when the counter's count is greater than or equal to a first specified value, allow the second hardware computing unit to execute the task to be executed, wherein the first specified value is equal to the initial value of the counter and the sum of the number of the first hardware computing units.
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