Scheduling circuit, data flow scheduling method and electronic device
By optimizing data flow scheduling through a multi-scheduler architecture and a buffered decoder, the redundancy and deadlock problems of crossbar bridges in multi-chip systems are solved, achieving high-efficiency data flow scheduling and communication.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI ORIENTAL COMPUTER TECHNOLOGY CO LTD
- Filing Date
- 2026-03-12
- Publication Date
- 2026-05-12
AI Technical Summary
In existing technologies, cross-connectors in multi-chip systems suffer from wasted redundancy, wasted chip area, low efficiency in locating simulation problems, and the risk of deadlock, resulting in inefficient data flow scheduling.
A multi-scheduler architecture is adopted, including a first scheduler, a second scheduler, a third scheduler, and a fourth scheduler, which respectively schedule and process different types of data streams. The transmission and parsing of data streams are optimized through buffers and decoders to achieve efficient scheduling.
The data stream scheduling timing was optimized, physical resources were reduced, the efficiency of locating scheduling problems was improved, the development efficiency of peripheral circuits was enhanced, deadlock scenarios were avoided, and communication efficiency was ensured.
Smart Images
Figure CN121833570B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of digital circuit technology, and in particular to a scheduling circuit, a data flow scheduling method, and an electronic device. Background Technology
[0002] In modern electronic systems, especially in fields such as high-performance computing, artificial intelligence, and the Internet of Things, multi-chip systems are increasingly widely used. These systems typically consist of multiple chips with different functions, such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), and various application-specific integrated circuits (ASICs). Efficient collaboration between different chips is crucial for the overall system performance, and data flow scheduling is a key technology to ensure this collaboration proceeds smoothly. In complex scenarios such as artificial intelligence and big data processing, data needs to be frequently transferred and processed between multiple chips. Optimized data flow scheduling can ensure the efficiency and reliability of these operations, thereby supporting more complex tasks and higher workloads.
[0003] In related technologies, crossbar bridges are used for data flow scheduling. However, because crossbar bridges support a lot of redundancy features, and some of these redundancy features cannot be trimmed, chip area is wasted. Furthermore, the register transfer level (RTL) code of crossbar bridges is encrypted or generated using scripts, resulting in low efficiency in problem localization when using crossbar bridges for simulation. In addition, crossbar bridges support interconnection and access between multiple master devices and multiple slave devices, meaning that a master device may access multiple slave devices, and a slave device may also be accessed by multiple master devices. If there is a data dependency between master and slave devices, deadlock can easily occur, making it impossible to efficiently schedule different types of data flows. Summary of the Invention
[0004] This application provides a scheduling circuit, a data stream scheduling method, and an electronic device that can efficiently schedule different types of data streams.
[0005] The technical solution of this application embodiment is implemented as follows:
[0006] This application embodiment provides a scheduling circuit, the scheduling circuit comprising:
[0007] The first scheduler is used to schedule and process the first request data stream initiated by the remote chip;
[0008] The second scheduler is used to schedule the first response data stream and the second response data stream returned to the local chip. The local chip and the remote chip are interconnected through a preset bus system. The second response data stream is the data stream returned to the remote chip by the scheduling node and the local preset bus system. The scheduling node is a logic module at the same level as the scheduling circuit.
[0009] The third scheduler is used to perform scheduling processing on the first scheduling result of the first scheduler and the second scheduling result of the second scheduler, and to loop back the second request data stream and the second response data stream to the fourth scheduler. The second request data stream is the data stream in which the remote chip initiates a request to the scheduling node and the local preset bus system.
[0010] The fourth scheduler is used to schedule the second request data stream, the second response data stream, the third request data stream initiated by the local chip, and the third response data stream, wherein the third response data stream is the data stream returned by the local chip to the remote chip.
[0011] This application provides a data stream scheduling method, the method comprising:
[0012] The first scheduler processes the first request data stream initiated by the remote chip.
[0013] The second scheduler schedules the first response data stream and the second response data stream returned to the local chip. The local chip and the remote chip are interconnected through a preset bus system. The second response data stream is the data stream returned to the remote chip by the scheduling node and the local preset bus system. The scheduling node is a logic module at the same level as the scheduling circuit.
[0014] The third scheduler processes the first scheduling result of the first scheduler and the second scheduling result of the second scheduler, and loops the second request data stream and the second response data stream back to the fourth scheduler. The second request data stream is the data stream in which the remote chip initiates a request to the scheduling node and the local preset bus system.
[0015] The fourth scheduler schedules the second request data stream, the second response data stream, the third request data stream initiated by the local chip, and the third response data stream. The third response data stream is the data stream returned by the local chip to the remote chip.
[0016] This application provides an electronic device, which includes the scheduling circuit provided in this application.
[0017] The present application provides a scheduling circuit, data stream scheduling method, and electronic device. In the scheduling circuit, a first scheduler is used to schedule and process a first request data stream initiated by a remote chip; a second scheduler is used to schedule and process a first response data stream and a second response data stream returned to the local chip. The local chip and the remote chip are interconnected through a preset bus system, and the scheduling node is a logic module at the same level as the scheduling circuit; a third scheduler is used to schedule and process the first scheduling result of the first scheduler and the second scheduling result of the second scheduler, and loops the second request data stream and the second response data stream back to the fourth scheduler; the fourth scheduler is used to schedule and process the second request data stream, the second response data stream, the third request data stream initiated by the local chip, and the third response data stream. In this way, by clearly defining the data flow scheduling functions of each scheduler in the scheduling circuit, the designed scheduling circuit can be used to achieve efficient scheduling of different types of data flows. This addresses the complex scheduling scenarios involving multiple data flows mixed between different chips, simplifies the communication scenario while ensuring communication efficiency, streamlines the design of the data flow scheduled by each scheduler to avoid deadlock scenarios, reduces physical implementation resources, optimizes data flow scheduling timing, improves the efficiency of scheduling problem localization, and thus improves the development efficiency of peripheral circuits. Attached Figure Description
[0018] Figure 1 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application;
[0019] Figure 2 This is a schematic diagram of the composition structure of the scheduling circuit provided in the embodiments of this application;
[0020] Figure 3 This is a flowchart illustrating the data flow scheduling method provided in an embodiment of this application;
[0021] Figure 4 This is a first structural diagram of data flow scheduling provided in an embodiment of this application;
[0022] Figure 5 This is a schematic diagram of the second structure of data flow scheduling provided in the embodiments of this application;
[0023] Figure 6 This is a schematic diagram of the third structure for data flow scheduling provided in the embodiments of this application.
[0024] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation
[0025] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0026] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.
[0027] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.
[0028] In the implementation of this application, the collection and processing of relevant data should strictly comply with the requirements of relevant laws and regulations, obtain the informed consent or separate consent of the personal information subject, and carry out subsequent data use and processing within the scope of laws and regulations and the authorization of the personal information subject.
[0029] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.
[0030] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.
[0031] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.
[0032] 1) System on Chip (SoC): A complete electronic system integrated on a single chip, typically including a central processing unit, graphics processor, memory controller, interface modules, storage units (such as flash memory), and various peripheral controllers.
[0033] 2) Peripheral Component Interconnect Express (PCIe) protocol: a high-speed serial computer expansion bus standard used to connect high-performance peripherals and processors.
[0034] 3) Scheduler: The scheduler is the core component of the system responsible for managing and allocating resources. Its main responsibility is to determine the execution order and priority of tasks, ensuring efficient utilization of system resources (such as CPU time and memory). Schedulers are widely used in operating systems, real-time systems, distributed systems, and other fields to optimize system performance and response time.
[0035] 4) Decoder: A decoder is a device or software module used to restore encoded data to its original form. During data transmission and processing, raw data is often encoded (e.g., compressed, encrypted) to improve efficiency or security. The decoder's role is to decode this encoded data, restoring it to a readable or processable form. Decoders are widely used in communication systems, multimedia processing (such as video and audio decoding), and data storage.
[0036] 5) Loopback: This involves directly feeding back the system's output signal to the input, forming a closed loop. This can generate the data stream to be transmitted and then transmit the generated data stream through the system's output.
[0037] 6) Local Chip: This is the main processing chip directly responsible for core data processing and system control. It is usually a core component of the system, responsible for performing major computing tasks, managing other peripheral chips, and coordinating the operation of the entire system. The performance and functionality of the local chip directly affect the overall system performance and user experience. In multi-chip systems, the local chip typically works in conjunction with remote chips to jointly complete complex data processing and task allocation.
[0038] 7) Remote Chip: This is a chip located outside the system and connected to the local chip via a communication interface. Its main function is to extend the system's functionality or handle specific tasks, such as data acquisition, communication management, and sensor control. Remote chips typically have independent processing capabilities and communication interfaces, enabling efficient data interaction with the local chip. Application scenarios for remote chips include IoT devices, industrial automation systems, and remote monitoring systems. Common types of remote chips include microcontroller units (MCUs), field-programmable gate arrays (FPGAs), and digital signal processors (DSPs).
[0039] 8) Request Data Stream: This is a data stream that sends requests from one device or module to another. These streams are typically used to acquire resources, perform operations, or exchange data. The purpose of request data streams is to ensure that the various parts of the system can work together to achieve efficient data transmission and processing. In distributed systems, network communications, and multi-chip systems, request data streams are fundamental to system operation.
[0040] 9) Response Data Stream: This is the data stream corresponding to the request data stream, referring to the receiver's response to the request. The response data stream contains processing results, status information, or feedback data, ensuring that the requester can understand the execution status of the operation. The quality of the response data stream directly affects the reliability of the system and the user experience; therefore, when designing the system, it is necessary to ensure the timeliness and accuracy of the response data stream.
[0041] This application provides a scheduling circuit, a data stream scheduling method, and an electronic device that can efficiently schedule different types of data streams.
[0042] The following describes exemplary applications of the electronic devices provided in the embodiments of this application. The electronic devices provided in the embodiments of this application can be implemented as various types of terminals such as laptops, tablets, desktop computers, set-top boxes, smartphones, smart speakers, smartwatches, smart TVs, and vehicle terminals.
[0043] See Figure 1 , Figure 1 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Figure 1 The electronic device shown includes a scheduling circuit 420, which includes a first scheduler 421, a second scheduler 422, a third scheduler 423, and a fourth scheduler 424.
[0044] The first scheduler 421 is used to schedule and process the first request data stream initiated by the remote chip.
[0045] Here, the local and remote chips in the circuit are interconnected via a pre-defined bus system, which is an interface system based on the Peripheral Component Interconnect (PCIe) protocol. The local chip includes the local pre-defined bus system, core processor, memory controller, cache system, interrupt controller, debug and test modules, etc. The remote chip includes the remote pre-defined bus system, dedicated processor, peripheral modules, power management modules, etc.
[0046] The first request data stream initiated by the remote chip includes: a data stream requesting the local chip from the remote chip, a data stream requesting the scheduling node from the remote chip, and a data stream requesting the local preset bus system from the remote chip. The scheduling node is a logical module at the same level as the scheduling circuit; that is, the scheduling node and the scheduling circuit are at the same logical level and perform the same type or dimension of functional roles. They have a peer-to-peer cooperative relationship, rather than a hierarchical one. The scheduling circuit's role is to manage the transmission order of the data streams, while the scheduling node's role is to convert and guide the transmission format and path of the data streams.
[0047] The data stream initiating a request from a remote chip to a local chip, i.e., a request stream from a remote chip to access the local chip's bus, can be represented as REQ_RP3. The data stream initiating a request from a remote chip to a scheduling node, i.e., a request stream from a remote chip to access the scheduling node, can be represented as REQ_RA. The data stream initiating a request from a remote chip to the local preset bus system can be represented as REQ_RP0.
[0048] The scheduling strategy of the first scheduler 421 can be either the priority of the data stream or a round-robin scheduling algorithm (RR). When the scheduling strategy is the priority of the data stream, the preset priority of each request data stream in the first request data stream is first obtained. Then, based on the order of the preset priorities from high to low, the sending order of each request data stream is sorted to obtain the data stream scheduling order of the first scheduler 421, so as to realize the scheduling processing of the first request data stream. When the scheduling strategy is the round-robin scheduling algorithm, the sending order of each request data stream in the first request data stream is sorted based on the receiving order of each request data stream in the first request data stream to obtain the data stream scheduling order of the first scheduler 421.
[0049] The second scheduler 422 is used to schedule and process the first response data stream and the second response data stream returned to the local chip.
[0050] Here, the first response data stream includes: the data stream returned by the scheduling node to the local chip, the data stream returned by the remote preset bus system to the local chip, and the data stream returned by the remote chip to the local chip. Specifically, the data stream returned by the scheduling node to the local chip, i.e., the return stream from the scheduling node to the local chip's bus, can be represented as DATA_LA or DATA_LB. The data stream returned by the remote preset bus system to the local chip, i.e., the return stream from the remote preset bus system to the local chip's bus, can be represented as DATA_LP0 or DATA_LP1. The data stream returned by the remote chip to the local chip, i.e., the return stream from the remote chip to the local chip's bus, can be represented as DATA_LP2.
[0051] The second response data stream is the data stream returned by the scheduling node and the local preset bus system to the remote chip, including: the data stream returned by the scheduling node to the remote chip and the data stream returned by the local preset bus system to the remote chip. The data stream returned by the scheduling node to the remote chip can be represented as DATA_RA, and the data stream returned by the local preset bus system to the remote chip can be represented as DATA_RP0.
[0052] The scheduling strategy of the second scheduler 422 can be either the priority corresponding to the data stream or a round-robin scheduling algorithm. When the scheduling strategy is the priority corresponding to the data stream, the preset priority corresponding to each response data stream in the first response data stream and the second response data stream is first obtained. Then, based on the order of the preset priorities from high to low, the sending order of each response data stream is sorted to obtain the data stream scheduling order of the second scheduler 422, so as to realize the scheduling processing of the first response data stream and the second response data stream. When the scheduling strategy is the round-robin scheduling algorithm, the sending order of each response data stream is sorted based on the receiving order of each response data stream in the first response data stream and the second response data stream to obtain the data stream scheduling order of the second scheduler 422.
[0053] The third scheduler 423 is used to perform scheduling processing on the first scheduling result of the first scheduler 421 and the second scheduling result of the second scheduler 422, and to loop back the second request data stream and the second response data stream to the fourth scheduler.
[0054] Here, the first scheduling result includes the sending order of each request data stream in the first request data stream. The second scheduling result includes the sending order of each response data stream in the first response data stream and the second response data stream. The scheduling strategy of the third scheduler 423 can be a round-robin scheduling algorithm. Based on the receiving order of each data stream in the first and second scheduling results, the sending order of each data stream is reordered to obtain the data stream scheduling order of the third scheduler 423, so as to realize the scheduling processing of the first and second scheduling results. The third scheduler 423 also loops the second request data stream and the second response data stream back to the fourth scheduler to ensure that the second request data stream and the second response data stream are not tampered with or lost during transmission.
[0055] The second request data stream consists of data streams from the remote chip to the scheduling node and the local preset bus system, including: data streams from the remote chip to the scheduling node and data streams from the remote chip to the local preset bus system (PCIe system). The data stream from the remote chip to the scheduling node, i.e., the request stream for the remote chip to access the scheduling node, can be represented as REQ_RA. The data stream from the remote chip to the local preset bus system, i.e., the request stream for the remote chip to access the configuration space (registers, etc.) in the local preset bus system, can be represented as REQ_RP0.
[0056] The fourth scheduler 424 is used to schedule and process the second request data stream, the second response data stream, the third request data stream initiated by the local chip, and the third response data stream.
[0057] Here, the third request data stream includes: a data stream initiating a request from the local chip to the scheduling node, a data stream initiating a request from the local chip to the remote preset bus system, and a data stream initiating a request from the local chip to the remote chip. Specifically, the data stream initiating a request from the local chip to the scheduling node, i.e., the request stream for the local chip's bus to access the scheduling node, can be represented as REQ_LA or REQ_LB. The data stream initiating a request from the local chip to the remote preset bus system, i.e., the request stream for the local chip's bus to access the configuration space (registers, etc.) in the remote preset bus system, can be represented as REQ_LP0 or REQ_LP1. The data stream initiating a request from the local chip to the remote chip, i.e., the request stream for the local chip's bus to access the remote chip, can be represented as REQ_LP2. The third response data stream is the data stream returned from the local chip to the remote chip, i.e., the return stream from the local chip's bus to the remote chip, and can be represented as DATA_RP3.
[0058] The scheduling strategy of the fourth scheduler 424 can be either the priority of the data streams or a round-robin scheduling algorithm. When the scheduling strategy is the priority of the data streams, the preset priority of each data stream in the second request data stream, the second response data stream, the third request data stream, and the third response data stream is first obtained. Then, based on the order of the preset priorities from high to low, the sending order of each data stream is sorted to obtain the data stream scheduling order of the fourth scheduler 424, so as to perform scheduling processing on the second request data stream, the second response data stream, the third request data stream, and the third response data stream. When the scheduling strategy is the round-robin scheduling algorithm, the sending order of each data stream in the second request data stream, the second response data stream, the third request data stream, and the third response data stream is sorted based on the receiving order of each data stream to obtain the data stream scheduling order of the fourth scheduler 424.
[0059] In this embodiment, a first scheduler is used to schedule and process a first request data stream initiated by a remote chip, a second scheduler is used to schedule and process a first response data stream and a second response data stream returned to the local chip, and a third scheduler is used to schedule and process the first scheduling result of the first scheduler and the second scheduling result of the second scheduler, and loop the second request data stream and the second response data stream back to the fourth scheduler. The fourth scheduler is used to schedule and process the second request data stream, the second response data stream, the third request data stream initiated by the local chip, and the third response data stream. This realizes the use of multiple schedulers in the scheduling circuit to schedule and manage different types of data streams, and can directly use the designed scheduling circuit to efficiently schedule different types of data streams, thereby dealing with complex scheduling scenarios where multiple data streams are mixed between different chips.
[0060] In some embodiments, see Figure 2 , Figure 2 This is a schematic diagram of the composition structure of the scheduling circuit provided in the embodiment of this application. The scheduling circuit 420 also includes a first buffer 428, the function of which will be described below.
[0061] The first buffer 428 is used to buffer the first response data stream and the fourth request data stream.
[0062] Here, the first buffer 428 is the local buffer corresponding to the local chip, and the fourth request data stream is the data stream initiating a request from the remote chip to the local chip, that is, the request stream for the remote chip to access the local chip bus, which can be represented as REQ_RP3.
[0063] The first buffer 428 is also used to parse the first response data stream and the fourth request data stream, and send the parsed first response data stream and the parsed fourth request data stream to the local chip.
[0064] Here, the first buffer 428 can also parse the first response data stream in a preset format. The preset format is a data stream format suitable for sending to the local chip, to obtain the parsed first response data stream, which is then sent to the local chip. The first buffer 428 can also parse the fourth request data stream in a preset format, to obtain the parsed fourth request data stream, which is then sent to the local chip.
[0065] In this embodiment, the first buffer is used to buffer the first response data stream and the fourth request data stream, enabling buffering of different types of data streams sent to the local chip, effectively reducing duplicate transmission of different types of data streams. The first buffer is also used to parse the first response data stream and the fourth request data stream, and send the parsed first response data stream and the parsed fourth request data stream to the local chip, realizing intelligent allocation of different types of data streams and improving data stream transmission efficiency.
[0066] In some embodiments, continue to refer to Figure 2 The scheduling circuit 420 also includes a first decoder 425, a second buffer 429, and a third buffer 430. The functions of the first decoder 425, the second buffer 429, and the third buffer 430 will be described below.
[0067] The second cache 429 is used to cache the data stream of the request type.
[0068] Here, the second buffer 429 is a request data stream buffer (Req), and the request type data streams are the second request data stream and the third request data stream.
[0069] The third buffer 430 is used to buffer the data stream of the response type.
[0070] Here, the third buffer 430 is a response data stream buffer (Rsp), and the response type data streams are the second response data stream and the third response data stream.
[0071] In this embodiment, the second buffer is used to cache the request type data stream, and the third buffer is used to cache the response type data stream. By caching the request type data stream and the response type data stream separately, the conflicts and congestion caused by the two types of data streams competing for resources during transmission can be reduced, thereby improving the efficiency of data transmission and reducing the overall system latency.
[0072] The first decoder 425 is used to decode the fourth scheduling result of the fourth scheduler and determine the data stream type of each data stream in the fourth scheduling result.
[0073] Here, the fourth scheduling result includes the sending order of each data stream in the second request data stream, the second response data stream, the third request data stream, and the third response data stream. For each data stream in the fourth scheduling result, when decoding the data stream, the first decoder 425 can obtain the data stream type of each data stream by parsing the fields or flags indicating the data stream direction in the data stream, where the data stream type is either a request type or a response type.
[0074] The first decoder 425 is also used to store the request type data stream in the fourth scheduling result to the second buffer 429, and to store the response type data stream in the fourth scheduling result to the third buffer 430.
[0075] Here, the first decoder 425 can also store the second request data stream and the third request data stream in the fourth scheduling result to the second buffer 429, and can also store the second response data stream and the third response data stream in the fourth scheduling result to the third buffer 430.
[0076] In some embodiments, continue to refer to Figure 2 The scheduling circuit 420 also includes a second decoder 426, the function of which is described below.
[0077] The second decoder 426 is used to parse the data stream in the second buffer 429 to obtain the target port information.
[0078] Here, the second decoder 426 performs target port resolution on the second request data stream and the third request data stream in the second buffer 429, respectively. Target port resolution is the process of determining the final destination of the data stream. In implementation, target port resolution can be performed by extracting the address, port number, or port identifier of the target port from the second request data stream and the third request data stream to obtain target port information, which includes the target port address corresponding to the data stream.
[0079] The second decoder 426 is also used to send the data stream in the second buffer 429 to the target port corresponding to the target port information.
[0080] Here, the second decoder 426 can also send the second request data stream to the target port corresponding to the target port information based on the target port information corresponding to the second request data stream in the second buffer 429. The second decoder 426 can also send the third request data stream to the target port corresponding to the target port information based on the target port information corresponding to the third request data stream in the second buffer 429.
[0081] In this embodiment, the second decoder is used to perform target port parsing on the data stream in the second buffer to obtain target port information, and then sends the data stream in the second buffer to the target port corresponding to the target port information. This enables accurate target port parsing of request type data streams, which can reduce the risk of request type data streams being lost or mistransmitted during transmission and improve the reliability of data transmission.
[0082] In some embodiments, continue to refer to Figure 2 The scheduling circuit 420 also includes a third decoder 427. The function of the second decoder is described below.
[0083] The third decoder 427 is used to perform source-end parsing on the data stream in the third buffer 430 to obtain source-end information.
[0084] Here, the third decoder 427 performs source-end parsing on the second and third response data streams in the third buffer 430, respectively. Source-end parsing is the process of determining the source of the data stream. Source-end parsing of the data streams can involve extracting the source address, port number, or port identifier from the second and third response data streams to obtain source information, which includes the source address corresponding to the data stream.
[0085] The third decoder 427 is also used to send the data stream in the third buffer 430 to the source end corresponding to the source end information.
[0086] Here, the third decoder 427 can also send the second response data stream to the source end corresponding to the source end information based on the source end information corresponding to the second response data stream in the third buffer 430. The third decoder 427 can also send the third request data stream to the source end corresponding to the source end information based on the source end information corresponding to the third response data stream in the third buffer 430.
[0087] In this embodiment, the third decoder is used to perform source-end parsing on the data stream in the third buffer to obtain source-end information, and then sends the data stream in the third buffer to the source end corresponding to the source-end information. This enables accurate source-end parsing of response-type data streams, ensuring that response-type data streams are correctly transmitted and processed, reducing the risk of data loss and mistransmission, and improving the reliability of data transmission.
[0088] The data stream scheduling method provided in this application will now be described based on the scheduling circuit provided in the above embodiments. (See also...) Figure 3 , Figure 3 This is a flowchart illustrating the data flow scheduling method provided in the embodiments of this application, which will be combined with... Figure 3 The steps shown are explained.
[0089] In step 301, the first request data stream initiated by the remote chip is scheduled and processed by the first scheduler.
[0090] Here, the first request data stream includes: a data stream from a remote chip to the local chip requesting data (REQ_RP3), a data stream from a remote chip to the scheduling node requesting data (REQ_RA), and a data stream from a remote chip to the local preset bus system requesting data (REQ_RP0). Using the scheduling policy of the first scheduler, the sending order of the first request data streams initiated by the remote chips is sorted to obtain the data stream scheduling order of the first scheduler, thereby realizing the scheduling processing of the first request data streams. The scheduling policy of the first scheduler can be the priority corresponding to the data stream or a round-robin scheduling algorithm (RR).
[0091] For example, the first request data streams are REQ_RP3, REQ_RA, and REQ_RP0. The scheduling policy of the first scheduler is based on the priority of the data streams. The preset priorities of REQ_RP3, REQ_RA, and REQ_RP0 in the first request data streams are 1, 2, and 3, respectively. Based on the order of the preset priorities from high to low, the sending order of each request data stream is sorted, resulting in the data stream scheduling order of the first scheduler as REQ_RP0→REQ_RA→REQ_RP3, in order to schedule and process the first request data streams.
[0092] In step 302, the first response data stream and the second response data stream returned to the local chip are scheduled and processed by the second scheduler.
[0093] Here, the local chip and the remote chip are interconnected through a preset bus system, and the scheduling node is a logic module at the same level as the scheduling circuit. The first response data stream includes: the data stream returned by the scheduling node to the local chip (DATA_LA or DATA_LB), the data stream returned by the remote preset bus system to the local chip (DATA_LP0 or DATA_LP1), and the data stream returned by the remote chip to the local chip (DATA_LP2). The second response data stream is the data stream returned by the scheduling node and the local preset bus system to the remote chip, including: the data stream returned by the scheduling node to the remote chip (DATA_RA) and the data stream returned by the local preset bus system to the remote chip (DATA_RP0).
[0094] The scheduling strategy of the second scheduler can be the priority of the data stream or the Round-Robin Scheduling Algorithm (RR). Using the scheduling strategy of the second scheduler, the sending order of the first and second response data streams returning to the local chip is sorted to obtain the data stream scheduling order of the second scheduler, thereby enabling the scheduling and processing of the first and second response data streams.
[0095] For example, the first response data stream is DATA_LA, DATA_LP0, and DATA_LP2. The second response data stream is DATA_RA and DATA_RP0. The scheduling policy of the second scheduler is based on the priority of the data streams. The preset priorities for DATA_LA, DATA_LP0, and DATA_LP2 in the first response data stream are 1, 2, and 3, respectively. The preset priorities for DATA_RA and DATA_RP0 in the second response data stream are 4 and 5, respectively. Based on the order of the preset priorities from high to low, the sending order of each response data stream is sorted, resulting in the data stream scheduling order of the second scheduler as DATA_RP0→DATA_RA→DATA_LP2→DATA_LP0→DATA_LA, thus enabling the scheduling and processing of the first and second response data streams.
[0096] In step 303, the first scheduling result of the first scheduler and the second scheduling result of the second scheduler are processed by the third scheduler, and the second request data stream and the second response data stream are looped back to the fourth scheduler.
[0097] Here, the second request data stream is the data stream initiating requests from the remote chip to the scheduling node and the local preset bus system, including: the data stream initiating requests from the remote chip to the scheduling node (REQ_RA) and the data stream initiating requests from the remote chip to the local preset bus system (REQ_RP0).
[0098] The first scheduling result includes the sending order of each request data stream in the first request data stream. The second scheduling result includes the sending order of each response data stream in the first response data stream and the second response data stream. The scheduling strategy of the third scheduler can be a round-robin scheduling algorithm (RR). Based on the receiving order of each data stream in the first and second scheduling results, the sending order of each data stream is reordered to obtain the data stream scheduling order of the third scheduler. Based on the data stream scheduling order of the third scheduler, the second request data stream and the second response data stream are looped back to the fourth scheduler to realize the scheduling processing of the first and second scheduling results.
[0099] Continuing with the example above, the first scheduling result is REQ_RP0→REQ_RA→REQ_RP3, and the second scheduling result is DATA_RP0→DATA_RA→DATA_LP2→DATA_LP0→DATA_LA. The receiving order of each data stream in the first and second scheduling results is REQ_RP0→REQ_RA→DATA_RP0→DATA_RA→DATA_LP2→DATA_LP0→DATA_LA→REQ_RP3. Therefore, the data stream scheduling order of the third scheduler is REQ_RP0→REQ_RA→DATA_RP0→DATA_RA→DATA_LP2→DATA_LP0→DATA_LA→REQ_RP3. The second request data streams REQ_RA and REQ_RP0, and the second response data streams DATA_RA and DATA_RP0 are looped back to the fourth scheduler to perform scheduling processing on the first and second scheduling results.
[0100] In some embodiments, a first buffer is used to buffer the first response data stream and the fourth request data stream, wherein the fourth request data stream is the data stream initiating a request from the remote chip to the local chip; the first buffer is used to parse the first response data stream and the fourth request data stream, and the parsed first response data stream and the parsed fourth request data stream are sent to the local chip.
[0101] Here, the first buffer is the local buffer corresponding to the local chip, and the fourth request data stream is the data stream (REQ_RP3) from the remote chip to the local chip. The first buffer parses the first response data stream into a preset format suitable for sending to the local chip, resulting in a parsed first response data stream, which is then sent to the local chip. Similarly, the first buffer parses the fourth request data stream into a preset format, resulting in a parsed fourth request data stream, which is also sent to the local chip.
[0102] Continue to refer to Figure 3 The following explanation will continue from step 303 above.
[0103] In step 304, the second request data stream, the second response data stream, the third request data stream initiated by the local chip, and the third response data stream are scheduled and processed by the fourth scheduler.
[0104] Here, the third request data stream includes: a data stream initiating a request from the local chip to the scheduling node (REQ_LA or REQ_LB), a data stream initiating a request from the local chip to the remote preset bus system (REQ_LP0 or REQ_LP1), and a data stream initiating a request from the local chip to the remote chip (REQ_LP2). The third response data stream is the data stream returned by the local chip to the remote chip (DATA_RP3).
[0105] The scheduling strategy of the fourth scheduler can be either the priority of the data stream or a round-robin scheduling algorithm. Using the scheduling strategy of the fourth scheduler, the sending order of the second request data stream, the second response data stream, the third request data stream, and the third response data stream is sorted to obtain the data stream scheduling order of the fourth scheduler, thereby enabling the scheduling and processing of the second request data stream, the second response data stream, the third request data stream, and the third response data stream.
[0106] For example, the scheduling strategy of the fourth scheduler is based on the priority of the data streams. The preset priorities of the second request data stream, the second response data stream, the third request data stream, and the third response data stream are 1, 2, 3, and 4, respectively. Based on the order of the preset priorities from high to low, the sending order of each data stream is sorted, resulting in the data stream scheduling order of the fourth scheduler as third response data stream → third request data stream → second response data stream → second request data stream, so as to realize the scheduling processing of the second request data stream, the second response data stream, the third request data stream, and the third response data stream.
[0107] In some embodiments, a second buffer is used to cache the request type data stream; a third buffer is used to cache the response type data stream; a first decoder is used to decode the fourth scheduling result of the fourth scheduler to determine the data stream type of each data stream in the fourth scheduling result, wherein the data stream type is either request type or response type; the first decoder stores the request type data stream in the fourth scheduling result in the second buffer and the response type data stream in the fourth scheduling result in the third buffer.
[0108] Here, the second buffer is the request data stream buffer (Req), and the request type data streams are the second request data stream and the third request data stream. The third buffer is the response data stream buffer (Rsp), and the response type data streams are the second response data stream and the third response data stream.
[0109] The fourth scheduling result includes the sending order of each data stream in the second request data stream, the second response data stream, the third request data stream, and the third response data stream. For each data stream in the fourth scheduling result, the first decoder parses the fields or flags indicating the data stream direction in the data stream to perform data stream type decoding processing, thereby obtaining the data stream type of each data stream, where the data stream type is either a request type or a response type.
[0110] The first decoder stores the second request data stream and the third request data stream in the fourth scheduling result into the second buffer, and stores the second response data stream and the third response data stream in the fourth scheduling result into the third buffer.
[0111] In some embodiments, the data stream in the second buffer is parsed for target port information by the second decoder; the data stream in the second buffer is then sent to the target port corresponding to the target port information by the second decoder.
[0112] Here, the second decoder performs target port resolution on the second and third request data streams in the second buffer, respectively. Target port resolution is the process of determining the final destination of the data stream. The target port address, port number, or port identifier is extracted from the second and third request data streams to obtain the target port information, which includes the target port address corresponding to the data stream.
[0113] Using the second decoder, based on the target port information corresponding to the second request data stream in the second buffer, the second request data stream is sent to the target port corresponding to the target port information. Using the second decoder, based on the target port information corresponding to the third request data stream in the second buffer, the third request data stream is sent to the target port corresponding to the target port information.
[0114] In some embodiments, the data stream in the third buffer is parsed at the source end by the third decoder to obtain the source end information; the data stream in the third buffer is then sent to the source end corresponding to the source end information by the third decoder.
[0115] Here, the third decoder performs source-end parsing on the second and third response data streams in the third buffer, which is the process of determining the source of the data stream. The source address, port number, or port identifier is extracted from the second and third response data streams to obtain source information, including the source address corresponding to the data stream.
[0116] Using a third decoder, based on the source information corresponding to the second response data stream in the third buffer, the second response data stream is sent to the source corresponding to the source information. Using the third decoder, based on the source information corresponding to the third response data stream in the third buffer, the third response data stream is sent to the source corresponding to the source information. After sending the second and third response data streams to the source corresponding to the source information, the source will parse the response data streams and, based on the parsing results, may perform specific operations, such as updating the state, triggering events, or starting new tasks.
[0117] In this embodiment, by clearly defining the data flow scheduling function of each scheduler, the data flow storage function of each buffer, and the data flow decoding function of each decoder in the scheduling circuit, the designed scheduling circuit can be used to achieve efficient scheduling of different types of data flows, so as to cope with the complex scheduling scenario of multiple data flows mixed between different chips.
[0118] The following will describe an exemplary application of the scheduling circuit provided in the embodiments of this application in a data flow scheduling scenario based on the Peripheral Component Interconnect (PCIe) protocol.
[0119] With the increasing demands for computing power in artificial intelligence (AI) applications, single chips are no longer sufficient. Multiple chips are typically interconnected to enhance computing power and meet application requirements. This interconnection is usually achieved using a PCIe interface for data exchange between chips. The PCIe interface operates in full-duplex mode, simultaneously sending and receiving request and return data packets in both directions. It can also handle scenarios where various application data flows, such as configuration streams, are mixed. For example, a local chip might send a read / write request packet to a remote chip, and the remote chip might return a read / write response packet to the local chip; conversely, a remote chip might send a read / write request packet to the local chip, and the local chip might return a read / write response packet to the remote chip. Depending on the chip's internal bus structure, read / write data packets may also be divided into control and data flows. When multiple types of data flows are intertwined, it increases the complexity of the scheduling circuit design between the chip's PCIe interface and internal bus.
[0120] This application proposes a scheduling circuit to address the problems existing in related technologies, which includes the following improvements compared to related technologies:
[0121] Design a reusable and efficient scheduling circuit based on the PCIe protocol for various mixed application scenarios to cope with the complex scheduling scenarios of multiple application data streams mixed between the chip's internal bus and the PCIe interface. The circuit structure can be directly reused to achieve efficient scheduling between applications and improve the development efficiency of PCIe interface peripheral circuits.
[0122] In some complex Systems-on-Chips (SoCs), the application scenarios based on the PCIe protocol are quite complex. Multiple data flows intertwine between the SoC's bus and the PCIe interface. Based on the direction and type of these data flows, they can be categorized into the following 12 types:
[0123] Type 1: Request flow for local bus access to the scheduling node;
[0124] Type 2: The return stream returned by the scheduling node to the local bus;
[0125] Type 3: Local bus accesses the request flow configured in the remote PCIe subsystem;
[0126] Type 4: Return stream from the remote PCIe subsystem to the local bus;
[0127] Type 5: Request stream for local bus to access remote chip;
[0128] Type 6: Return stream from the remote chip to the local chip bus;
[0129] Type 7: Request stream for remote chip to access local chip bus;
[0130] Type 8: Return stream from the local chip bus to the remote chip;
[0131] Type 9: Request stream for remote chip access to the scheduling node;
[0132] Type 10: The return stream from the scheduling node to the remote chip;
[0133] Type 11: Request stream for remote chip to access local PCIe subsystem configuration;
[0134] Type 12: Return stream from the local PCIe subsystem to the remote chip.
[0135] In addition, the types of request and response streams in each direction will increase as the variety of functional modules increases.
[0136] The following describes the process of data stream scheduling management performed by the scheduling circuit provided in the embodiments of this application. For example, refer to... Figure 4 , Figure 4 This is a schematic diagram of the first structure for data flow scheduling provided in an embodiment of this application. The first structure includes a local chip bus 401, a scheduling node 402, and a remote chip 403. The remote chip 403 is a peer chip interconnected with the local chip bus 401 via a PCIe interface. The scheduling node 402 includes a scheduler (Schedule), module A, and module B. Modules A and B are logical blocks at the same level as the scheduler and located between the local chip bus and the remote PCIe subsystem.
[0137] The data stream sent from the local chip bus 401 to the scheduling node 402 includes DATA_RP3, REQ_LP0, REQ_LP1, REQ_LP2, REQ_LA, and REQ_LB. Specifically, DATA_RP3 represents the return stream from the local chip bus to the remote chip; REQ_LP0 and REQ_LP1 represent the request streams configured by the local chip bus to access the remote PCIe subsystem; REQ_LP2 represents the request stream from the local chip bus to access the remote chip; and REQ_LA and REQ_LB represent the request streams from the local chip bus to access the scheduling node.
[0138] The data stream returned by the scheduling node 402 to the local chip bus 401 includes DATA_LA, DATA_LB, DATA_LP0, DATA_LP1, DATA_LP2, and REQ_RP3. Specifically, DATA_LA and DATA_LB represent the return streams from the scheduling node to the local chip bus, DATA_LP0 and DATA_LP1 represent the return streams from the remote PCIe subsystem to the local chip bus, DATA_LP2 represents the return stream from the remote chip to the local chip bus, and REQ_RP3 represents the request stream from the remote chip to access the local chip bus.
[0139] The data stream sent from scheduling node 402 to remote chip 403 includes DATA_RP0, REQ_RP0, DATA_RP3, DATA_RA, REQ_LP0, REQ_LP1, and REQ_LP2. Specifically, DATA_RP0 represents the return stream from the local PCIe subsystem to the remote chip; REQ_RP0 represents the request stream from the remote chip to access the configuration of the local PCIe subsystem; DATA_RP3 represents the return stream from the local chip bus to the remote chip; REQ_LP0 and REQ_LP1 represent the request streams from the local chip bus to access the configuration of the remote PCIe subsystem; and REQ_LP2 represents the request stream from the local chip bus to access the remote chip.
[0140] The data stream returned by the remote chip 403 to the scheduling node 402 includes REQ_RP0, DATA_RP0, REQ_RP3, REQ_RA, DATA_LP0, DATA_LP1, and DATA_LP2. Specifically, REQ_RP0 represents the request stream from the remote chip to access the local PCIe subsystem configuration; DATA_RP0 represents the return stream from the local PCIe subsystem to the remote chip; REQ_RP3 represents the request stream from the remote chip to access the local chip bus; REQ_RA represents the request stream from the remote chip to access the scheduling node; DATA_LP0 and DATA_LP1 represent the return streams from the remote PCIe subsystem to the local chip bus; and DATA_LP2 represents the return stream from the remote chip to the local chip bus.
[0141] To efficiently schedule 12 mixed data streams, the scheduling circuit provided in this application includes 4 sets of schedulers, 3 sets of decoders, and 3 sets of buffers. For example, see reference... Figure 5 , Figure 5 This is a schematic diagram of the second structure for data flow scheduling provided in an embodiment of this application. The second structure 501 includes 4 groups of schedulers (Arb0, Arb1, Arb2 and Arb3), 3 groups of decoders (Dec0, Dec1 and Dec2), and 3 groups of buffers (Req, Rsp and Local).
[0142] Request streams (types 7, 9, and 11) from remote chips to local chips are scheduled by scheduler Arb0, and the scheduling policy can be set according to application priority. Data streams (types 2, 4, 6, 10, and 12) returned by remote chips and the PCIe subsystem are scheduled by scheduler Arb1, and the scheduling policy can be set according to application priority. Scheduler Arb2 schedules the data streams scheduled by Arb0 and Arb1. To ensure efficient scheduling of request and return streams, a round-robin scheduling algorithm (RR) can be used. The scheduled data stream may be a request stream from a remote chip to the local PCIe subsystem, or a return stream from the local PCIe subsystem to a remote chip. Both need to be sent to the subsequent decoder through the local chip's data stream sender (TX). Scheduler Arb2 needs to identify these two types of data streams (types 9, 10, 11, and 12) and loop them back to scheduler Arb3 to reuse the data path at the TX end. Specifically, the source data stream is a PCIe subsystem or an A / B module, which is looped back to scheduler Arb3.
[0143] The destination address is the data stream of the local chip, which is directly cached in the local buffer (Local). After parsing, it is sent to the local chip bus. Request data streams or return data streams (types 1, 3, 5, 8) issued by the local chip bus, as well as loopback data streams, are scheduled using scheduler Arb3. The scheduling strategy can be set according to application priority. After scheduling, the decoder Dec2 identifies the request stream and return stream, caches the request stream in buffer Req, and caches the return stream in buffer Rsp. Decoder Dec0 parses the data stream in buffer Req for the destination end of the request stream to send the data stream to the corresponding destination end. Decoder Dec1 parses the data stream in buffer Rsp for the source end of the return stream to return the data stream to the corresponding source end. The local buffer (Local) is used to cache the data stream sent to the local chip bus. In this embodiment, the above 12 types of data streams can all reuse the designed scheduling circuit for efficient data stream scheduling management.
[0144] The following describes the processes for 12 types of data flow scheduling provided in the embodiments of this application. For example, refer to... Figure 6 , Figure 6This is a schematic diagram of the third structure of data flow scheduling provided in the embodiments of this application. The third structure includes a local chip bus 401, a scheduling node 402 and a remote chip 403. The scheduling node 402 includes 4 groups of schedulers (Arb0, Arb1, Arb2 and Arb3), 3 groups of decoders (Dec0, Dec1 and Dec2) and 3 groups of buffers (Req, Rsp and Local).
[0145] All four schedulers employ the Round Robin Scheduling (RR) algorithm. Scheduler Arb0 schedules four different destination request streams (types 7, 9, and 11) resolved from the remote end. Scheduler Arb1 schedules three return streams from different functional modules on the local end and return streams resolved from the remote end (types 2, 4, 6, 10, and 12). Scheduler Arb2 schedules the request stream results from Arb0 and the return stream results from Arb1. Scheduler Arb3 schedules two streams: request streams (types 1, 3, and 5), return streams (type 8), and loopback request streams (types 9 and 11) and return streams (types 10 and 12) from the local bus. Decoder Dec0 performs four-way decoding of request streams accessing different modules on the local end and request streams accessing the remote end. Decoder Dec1 decodes four return streams sent back to the remote end. Decoder Dec2 is used for decoding request and return streams, using buffers Req and Rsp to cache the results, respectively. The local buffer is used to cache the data stream sent to the local chip bus.
[0146] The following description continues to illustrate the exemplary structure of the scheduling circuit 420 provided in the embodiments of this application as a software module. In some embodiments, such as... Figure 1As shown, the software modules in the scheduling circuit 420 may include: a first scheduler 421, used to schedule and process the first request data stream initiated by the remote chip; a second scheduler 422, used to schedule and process the first response data stream and the second response data stream returned to the local chip, wherein the local chip and the remote chip are interconnected through a preset bus system, and the second response data stream is the data stream returned by the scheduling node and the local preset bus system to the remote chip, and the scheduling node is a logic module at the same level as the scheduling circuit; a third scheduler 423, used to schedule and process the first scheduling result of the first scheduler and the second scheduling result of the second scheduler, and loop the second request data stream and the second response data stream back to the fourth scheduler, wherein the second request data stream is the data stream initiating a request from the remote chip to the scheduling node and the local preset bus system; and a fourth scheduler 424, used to schedule and process the second request data stream, the second response data stream, the third request data stream initiated by the local chip, and the third response data stream, wherein the third response data stream is the data stream returned by the local chip to the remote chip.
[0147] In some embodiments, the scheduling circuit further includes a first buffer 428, which is used to buffer the first response data stream and the fourth request data stream, wherein the fourth request data stream is a data stream in which a remote chip initiates a request to the local chip.
[0148] In some embodiments, the first buffer 428 is further configured to parse the first response data stream and the fourth request data stream, and send the parsed first response data stream and the parsed fourth request data stream to the local chip.
[0149] In some embodiments, the scheduling circuit further includes a first decoder 425, a second buffer 429, and a third buffer 430. The second buffer 429 is used to buffer request-type data streams; the third buffer 430 is used to buffer response-type data streams; and the first decoder 425 is used to decode the fourth scheduling result of the fourth scheduler to determine the data stream type of each data stream in the fourth scheduling result, wherein the data stream type is either request-type or response-type.
[0150] In some embodiments, the first decoder 425 is further configured to store the request type data stream in the fourth scheduling result to the second buffer and the response type data stream in the fourth scheduling result to the third buffer.
[0151] In some embodiments, the scheduling circuit further includes a second decoder 426, which is used to perform target port parsing on the data stream in the second buffer to obtain target port information.
[0152] In some embodiments, the second decoder 426 is further configured to send the data stream in the second buffer to the target port corresponding to the target port information.
[0153] In some embodiments, the scheduling circuit further includes a third decoder 427, which is used to perform source-end parsing on the data stream in the third buffer to obtain source-end information.
[0154] In some embodiments, the third decoder 427 is further configured to send the data stream in the third buffer to the source end corresponding to the source end information.
[0155] In some embodiments, the first request data stream includes: a data stream initiating a request from a remote chip to a local chip, a data stream initiating a request from a remote chip to a scheduling node, and a data stream initiating a request from a remote chip to a local preset bus system.
[0156] In some embodiments, the first response data stream includes: a data stream returned by the scheduling node to the local chip, a data stream returned by the remote preset bus system to the local chip, and a data stream returned by the remote chip to the local chip.
[0157] In some embodiments, the third request data stream includes: a data stream initiating a request from the local chip to the scheduling node, a data stream initiating a request from the local chip to the remote preset bus system, and a data stream initiating a request from the local chip to the remote chip.
[0158] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.
Claims
1. A scheduling circuit, characterized in that, The scheduling circuit includes: The first scheduler is used to schedule and process the first request data stream initiated by the remote chip; The second scheduler is used to schedule the first response data stream and the second response data stream returned to the local chip. The local chip and the remote chip are interconnected through a preset bus system. The second response data stream is the data stream returned to the remote chip by the scheduling node and the local preset bus system. The scheduling node is a logic module at the same level as the scheduling circuit. The third scheduler is used to perform scheduling processing on the first scheduling result of the first scheduler and the second scheduling result of the second scheduler, and to loop back the second request data stream and the second response data stream to the fourth scheduler. The second request data stream is the data stream in which the remote chip initiates a request to the scheduling node and the local preset bus system. The fourth scheduler is used to schedule the second request data stream, the second response data stream, the third request data stream initiated by the local chip, and the third response data stream, wherein the third response data stream is the data stream returned by the local chip to the remote chip.
2. The scheduling circuit according to claim 1, characterized in that, The scheduling circuit further includes a first buffer, wherein: The first buffer is used to buffer the first response data stream and the fourth request data stream, wherein the fourth request data stream is the data stream in which the remote chip initiates a request to the local chip; The first buffer is further configured to parse the first response data stream and the fourth request data stream, and send the parsed first response data stream and the parsed fourth request data stream to the local chip.
3. The scheduling circuit according to claim 1, characterized in that, The scheduling circuit further includes a first decoder, a second buffer, and a third buffer, wherein: The second cache is used to cache the data stream of the request type; The third buffer is used to cache response-type data streams; The first decoder is used to decode the fourth scheduling result of the fourth scheduler and determine the data stream type of each data stream in the fourth scheduling result, wherein the data stream type is a request type or a response type. The first decoder is further configured to store the request type data stream in the fourth scheduling result to the second buffer, and to store the response type data stream in the fourth scheduling result to the third buffer.
4. The scheduling circuit according to claim 3, characterized in that, The scheduling circuit further includes a second decoder, wherein: The second decoder is used to parse the data stream in the second buffer to obtain the target port information; The second decoder is also used to send the data stream in the second buffer to the target port corresponding to the target port information.
5. The scheduling circuit according to claim 3, characterized in that, The scheduling circuit also includes a third decoder, wherein: The third decoder is used to perform source-end parsing on the data stream in the third buffer to obtain source-end information; The third decoder is also used to send the data stream in the third buffer to the source end corresponding to the source end information.
6. The scheduling circuit according to any one of claims 1 to 5, characterized in that, The first request data stream includes: a data stream initiating a request from the remote chip to the local chip, a data stream initiating a request from the remote chip to the scheduling node, and a data stream initiating a request from the remote chip to the local preset bus system.
7. The scheduling circuit according to any one of claims 1 to 5, characterized in that, The first response data stream includes: the data stream returned by the scheduling node to the local chip, the data stream returned by the remote preset bus system to the local chip, and the data stream returned by the remote chip to the local chip.
8. The scheduling circuit according to any one of claims 1 to 5, characterized in that, The third request data stream includes: a data stream initiating a request from the local chip to the scheduling node, a data stream initiating a request from the local chip to the remote preset bus system, and a data stream initiating a request from the local chip to the remote chip.
9. A data stream scheduling method, characterized in that, The method is applied to the scheduling circuit according to any one of claims 1 to 8, and the method includes: The first scheduler processes the first request data stream initiated by the remote chip. The second scheduler schedules the first response data stream and the second response data stream returned to the local chip. The local chip and the remote chip are interconnected through a preset bus system. The second response data stream is the data stream returned to the remote chip by the scheduling node and the local preset bus system. The scheduling node is a logic module at the same level as the scheduling circuit. The third scheduler processes the first scheduling result of the first scheduler and the second scheduling result of the second scheduler, and loops the second request data stream and the second response data stream back to the fourth scheduler. The second request data stream is the data stream in which the remote chip initiates a request to the scheduling node and the local preset bus system. The fourth scheduler schedules the second request data stream, the second response data stream, the third request data stream initiated by the local chip, and the third response data stream. The third response data stream is the data stream returned by the local chip to the remote chip.
10. An electronic device, characterized in that, The electronic device includes the scheduling circuit according to any one of claims 1 to 8.