A synchronization detection circuit and a synchronization detection method of a high-speed serial bus

Abstract

The application provides a synchronization detection circuit and method of a high-speed serial bus. The circuit comprises a data stream acquisition module configured to acquire an ordered set data stream, determine a plurality of candidate start positions in the ordered set data stream, and acquire a plurality of candidate ordered sets by taking each candidate start position as a start position of a candidate ordered set; a first accumulator configured to perform weight accumulation calculation on each candidate ordered set bit by bit to obtain a first weight accumulation value, and determine a target start position of a target ordered set according to a plurality of first weight accumulation values; and a second accumulator configured to acquire data of a subsequent ordered set of the target ordered set, perform weight accumulation calculation on the subsequent ordered set bit by bit to obtain a second weight accumulation value, and confirm that the target start position of the target ordered set is a valid start position if the second weight accumulation value is greater than or equal to a second weight threshold. The application also provides a synchronization detection method of a high-speed serial bus. The application can improve the accuracy of lock-in.

Description

Technical Field

[0001] This invention relates to the technical field of digital circuit synchronization detection, specifically to a high-speed serial bus synchronization detection circuit and a method for operating such a detection circuit. Background Technology

[0002] In PCIe (Peripheral Component Interconnect Express) high-speed communication, the sending end typically sends an ordered set of data streams at fixed time intervals. The receiving end needs to detect the ordered set of data streams to determine the starting position of the ordered set, that is, to determine the starting bit of the ordered set, thereby realizing data alignment detection.

[0003] Data alignment detection first requires bit locking, which is typically performed by a clock data recovery circuit. This circuit recovers the clock signal from the received data stream and uses it to determine the optimal sampling point for each unit time interval (UI), ensuring that each individual bit can be correctly identified—that is, whether the data sent by the transmitter is a 0 or a 1. PCIe symbol locking builds upon bit locking. PCIe uses various encoding schemes; for example, first and second generations use 8b / 10b encoding, third to fifth generations use 128b / 130b encoding, and sixth generation uses 1b / 1b encoding. These encoding schemes divide the data into fixed-size "symbol" blocks, such as 10 bits, 1 bit, 130 bits, or 128 bits. The purpose of symbol locking is to determine symbol boundaries, thereby ensuring that the receiver can correctly parse the serial bit stream into meaningful parallel data.

[0004] Existing symbol locking methods typically rely on detecting specific control symbols such as the Electrical Idle Exit Ordered Set (EIEOS) and the Start of Data Stream (SDS) markers to determine the alignment of the data stream. In other words, after identifying the EIEOS or SDS markers in the data stream, the positions of these specific markers within the data stream are determined based on them, thereby determining the positions of other data within the stream. Typically, the receiving end designates a position in the data stream as the starting position of the EIEOS and uses this position to detect the EIEOS, thus achieving symbol locking.

[0005] However, in practical applications, signal quality is affected by a variety of factors. For example, interference signals in the environment and communication distance can lead to poor channel quality and increased channel loss, which in turn leads to a higher bit error rate. Electrically idle signals detected by the receiver may result in a large number of bit errors. Existing symbol locking methods are prone to misjudging symbol boundaries. Once the symbol boundaries are misjudged, subsequent data detection errors will occur, affecting the stability of the communication link. Summary of the Invention

[0006] The first objective of this invention is to provide a synchronous detection circuit for a high-speed serial bus that improves the accuracy of symbol detection.

[0007] The second objective of this invention is to provide a synchronization detection method for a high-speed serial bus that can reduce the probability of false positives in symbol detection.

[0008] To achieve the first objective of this invention, the high-speed serial bus synchronization detection circuit provided by this invention includes a data stream acquisition module for acquiring an ordered set data stream and identifying multiple candidate starting positions in the ordered set data stream, using each candidate starting position as the starting position of a candidate ordered set, and acquiring multiple sets of candidate ordered sets; it also includes a first accumulator for performing bit-by-bit weight accumulation calculation on each candidate ordered set to obtain a first weight accumulation value, and determining the target starting position of the target ordered set based on multiple first weight accumulation values; it also includes a second accumulator for acquiring the data of subsequent ordered sets of the target ordered set, performing bit-by-bit weight accumulation calculation on the subsequent ordered sets to obtain a second weight accumulation value, and confirming the target starting position of the target ordered set as a valid starting position if the second weight accumulation value is greater than or equal to a second weight threshold.

[0009] As can be seen from the above scheme, the present invention proposes multiple candidate starting positions to obtain multiple candidate ordered sets. For each of these candidate ordered sets, the corresponding first weight accumulation value is calculated. If the first weight accumulation value meets the preset condition, the candidate starting position is taken as the target starting position. That is, one of the multiple candidate starting positions is determined as the target starting position, and then the subsequent ordered sets are calculated.

[0010] Therefore, this invention does not simply rely on a predetermined position as the starting position of the target ordered set, but rather determines one of multiple predetermined candidate starting positions as the target starting position. By performing weighted calculations on the candidate ordered sets bit by bit, one that meets the requirements is determined as the target starting position of the target ordered set, thereby obtaining an accurate and effective starting position. This makes the symbol locking calculation more accurate, thus providing an accurate basis for data synchronization.

[0011] A preferred approach is that when the first accumulator determines the target starting position of the target ordered set based on multiple first weight accumulation values, it determines whether the first weight accumulation value corresponding to the candidate ordered set is greater than or equal to the first weight threshold. If so, it confirms that the candidate starting position corresponding to the candidate ordered set is the target starting position.

[0012] Therefore, by setting a first weight threshold as a comparison benchmark, an accurate benchmark is provided for determining the target ordered set and the target starting position, thereby enabling a more precise determination of the target starting position.

[0013] A preferred embodiment is that when the first accumulator performs weighted accumulation calculation on each bit of each candidate ordered set, it compares each bit of the candidate ordered set with the corresponding bit of the first reference ordered set. If the bit of the candidate ordered set is the same as the corresponding bit of the first reference ordered set, it assigns a first weight value; otherwise, it assigns a second weight value. The first accumulator accumulates the weight values ​​corresponding to each bit of the candidate ordered set to obtain the first weighted accumulation value.

[0014] Therefore, by comparing each data point in the candidate ordered set with the corresponding data point in the first reference ordered set one by one, and using two different weight values ​​to distinguish between the same or different data, the first weight accumulation value obtained when the candidate starting position is accurate will be different from the first weight accumulation value obtained when the candidate starting position is inaccurate. Combined with the set first weight threshold, the target starting position can be accurately calculated.

[0015] A further approach is to assign a positive first weight and a zero or negative second weight. It is evident that when the data in the candidate ordered set is identical to the corresponding bit data in the first reference ordered set, the first weight is greater than the first weight when the data is different. Thus, the accumulated first weight, obtained when the candidate's starting position is accurate, will necessarily be greater than the accumulated first weight, obtained when the candidate's starting position is inaccurate. Therefore, this method can improve the accuracy of identifying the target ordered set and the target's starting position.

[0016] A further approach is that when the second accumulator performs weighted accumulation calculation on each bit of the subsequent ordered set, it compares each bit of the subsequent ordered set with the corresponding bit of the second reference ordered set. If the bit of the subsequent ordered set is the same as the corresponding bit of the second reference ordered set, it assigns a third weight value; otherwise, it assigns a fourth weight value. The second accumulator then accumulates the weight values ​​corresponding to each bit of the subsequent ordered set to obtain the second weighted accumulated value.

[0017] Therefore, the identification of subsequent ordered sets also involves comparing each bit of the subsequent ordered set with the corresponding bit of the second reference ordered set, and calculating the second weight accumulation value by setting two different weight values, so as to accurately identify whether the current target starting position is correct.

[0018] To achieve the second objective mentioned above, the high-speed serial bus synchronization detection method provided by the present invention includes: acquiring an ordered set data stream; identifying multiple candidate start positions in the ordered set data stream; using each candidate start position as the start position of a candidate ordered set; acquiring multiple sets of candidate ordered sets; performing weight accumulation calculation bit by bit for each candidate ordered set to obtain a first weight accumulation value; determining the target start position of the target ordered set based on multiple first weight accumulation values; acquiring data from subsequent ordered sets of the target ordered set; performing weight accumulation calculation bit by bit for subsequent ordered sets to obtain a second weight accumulation value; if the second weight accumulation value is greater than or equal to a second weight threshold, then confirming the target start position of the target ordered set as a valid start position.

[0019] As can be seen from the above scheme, the present invention does not use a single starting position to calculate the target ordered set, but rather pre-determines multiple candidate starting positions to obtain multiple candidate ordered sets, and calculates the corresponding first weight accumulation value for each of these candidate ordered sets. If the first weight accumulation value meets a preset condition, the candidate starting position is taken as the target starting position. Therefore, the present invention determines one of the multiple candidate starting positions as the target starting position. In this way, the accuracy of the identified target starting position can be improved, thereby improving the accuracy of symbol locking detection.

[0020] A further approach is to obtain new candidate starting positions and calculate new target starting positions if the accumulated value of the second weight is less than the second weight threshold.

[0021] Therefore, if the second weight accumulation value is found to be less than the second weight threshold after calculating the subsequent ordered set, it indicates that the target starting position determined by the first accumulator is not accurate. Therefore, the accuracy of symbol locking is ensured by recalculating the target starting position.

[0022] A further approach is to determine the target starting position of the target ordered set based on multiple accumulated first weight values, including: determining whether the accumulated first weight value corresponding to the candidate ordered set is greater than or equal to the first weight threshold; if so, confirming the candidate starting position corresponding to the candidate ordered set as the target starting position.

[0023] A further approach is to pre-set multiple candidate first weight thresholds and determine one of them as the first weight threshold based on the operating parameters of the high-speed serial bus; and / or pre-set multiple candidate second weight thresholds and determine one of them as the second weight threshold based on the operating parameters of the high-speed serial bus.

[0024] Therefore, the present invention can dynamically adjust the first weight threshold and the second weight threshold according to the operating conditions of the high-speed serial bus, such as the actual bit error rate, so as to meet the symbol lock detection requirements under different operating conditions and improve the accuracy of target start position identification.

[0025] A further approach is to convert the state of the symbol alignment state machine from an unaligned state to an aligned state after confirming that the target starting position of the ordered set is a valid starting position.

[0026] Therefore, if the accumulated value of the second weight of the subsequent ordered set is also greater than the second weight threshold, it indicates that the determined starting position of the target is accurate. At this time, the state of the symbol alignment state machine changes from the unaligned state to the aligned state, and the receiving end can perform subsequent data detection and data recognition, providing the necessary conditions for subsequent communication. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of an ordered set data flow.

[0028] Figure 2 This is a structural block diagram of an embodiment of the synchronization detection circuit for the high-speed serial bus of the present invention.

[0029] Figure 3 This is a flowchart of an embodiment of the high-speed serial bus synchronization detection method of the present invention.

[0030] Figure 4 This is a schematic diagram illustrating data calculation in an embodiment of the high-speed serial bus synchronization detection method of the present invention.

[0031] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0032] The high-speed serial bus synchronization detection circuit of this invention is used to realize data synchronization of PCIe high-speed communication channels, especially to realize symbol locking detection. By proposing multiple candidate start positions, one is determined as the target start position from the multiple proposed candidate start positions, and this is used as the reference for symbol locking. Through the above method, this invention can improve the accuracy of symbol locking.

[0033] Example of a synchronization detection circuit for a high-speed serial bus:

[0034] In PCIe high-speed communication, the sending end transmits ordered sets of data streams at fixed time intervals. These ordered sets can be of various types, including electrically idle exit (EILE) ordered sets, SKP ordered sets, TS1 ordered sets, and TS2 ordered sets. Typically, the sending end first transmits the EILE ordered set, followed immediately by the other ordered sets. (See also...) Figure 1 The ordered set sent by the sending end includes an ordered set header (sync header) located at the very beginning of the data stream, which is... Figure 1 The HD portion is followed by 16 ordered sets, each consisting of one byte. Therefore, the ordered set header is followed by 16 bytes of data. The data following the ordered set header typically indicates an electrical idle exit from the ordered set. Figure 1 In the sequence OS0, there are other ordered sets, such as OS1 through OS15. Therefore, accurately identifying the starting position of the electrical idle exit from the ordered set is crucial for accurately identifying the content of the ordered set data stream.

[0035] See Figure 2 The synchronization detection circuit of the high-speed serial bus in this embodiment includes a data stream acquisition module 11, a first accumulator 12, a second accumulator 13, and a symbol alignment state machine 14. The data stream acquisition module 11 acquires the data stream sent by the transmitting end, which is a data stream containing an ordered set. After receiving the data stream, the data stream acquisition module 11 performs a shift comparison with a pre-set electrical idle exit ordered set data stream sequence, thereby identifying multiple candidate starting positions in the ordered set data stream. For example, in... Figure 1 In this process, multiple positions such as H0, H1, and S0 and S1 of OS0 can be used as proposed candidate starting positions. Subsequently, these candidate starting positions will be used as the starting positions of each candidate ordered set, thereby obtaining multiple candidate ordered sets. In this embodiment, the electrical idle exit ordered set is used as a reference to determine the target starting position. Therefore, these candidate ordered sets are all candidate electrical idle exit ordered sets.

[0036] The first accumulator 12 receives data from the data stream acquisition module 11 and calculates the weight value for each candidate ordered set. Specifically, for each candidate ordered set, it compares it bit-by-bit with a first reference ordered set (e.g., an ordered set specified by the PCIe protocol), that is, it marks each bit of data in the candidate ordered set with the corresponding bit in the first reference ordered set to determine the weight value of each bit in the candidate ordered set. Then, the first accumulator 12 accumulates the weight values ​​of each bit in the candidate ordered set to obtain a first weight accumulation value. Then, a target ordered set is determined based on the first weight accumulation values ​​of multiple candidate ordered sets. Specifically, if the first weight accumulation value of a candidate ordered set is greater than or equal to a first weight threshold, then the candidate ordered set is taken as the target ordered set, and the starting position corresponding to the target ordered set is the target starting position.

[0037] After determining the target ordered set, the data of subsequent ordered sets are obtained. These subsequent ordered sets are those that exit the electrical idle state based on the target ordered set, and are used to determine other subsequent ordered sets. The second accumulator 13 performs bit-by-bit weighted accumulation calculations on the subsequent ordered sets to obtain a second weighted accumulation value. Specifically, the second accumulator 13 compares each bit of data in the subsequent ordered set with the corresponding bit of the second reference ordered set (e.g., the ordered set specified by the PCIe protocol), that is, it marks each bit of data in the subsequent ordered set with the corresponding bit of the second reference ordered set to determine the weight value of each bit of data in the subsequent ordered set. The second accumulator 13 accumulates the weight values ​​of each bit of data in the subsequent ordered set to obtain the second weighted accumulation value. If the second weighted accumulation value is greater than or equal to a preset second weight threshold, the target starting position of the target ordered set is confirmed as a valid starting position.

[0038] After determining the valid starting position, that is, after the symbol lock detection is considered successful, the state of the symbol alignment state machine 14 is changed. Specifically, the state of the symbol alignment state machine 14 changes from the unaligned state to the aligned state.

[0039] Example of a synchronization detection method for a high-speed serial bus:

[0040] The following is combined Figure 3 This paper introduces a method for implementing synchronization detection using a high-speed serial bus synchronization detection circuit. First, step S11 is executed, where the data stream acquisition module acquires the data stream sent by the transmitting end. This data stream contains an ordered set, such as... Figure 1 The data stream is shown. However, the receiving end is not sure which bit in the data stream is the starting position of the ordered set. Therefore, this embodiment needs to first propose multiple candidate starting positions, and then perform calculations for each of these proposed starting positions to determine one of them as the target starting position.

[0041] Therefore, step S12 needs to be executed, in which multiple candidate starting positions are determined from the data stream obtained in step S11, for example, ... Figure 1 The positions H0, H1, and S0, S1 of OS0 are used as candidate starting positions. Thus, for each candidate starting position, a candidate ordered set can be obtained. In this embodiment, the electrical idle exit ordered set is used as a reference to determine the target starting position. Since the length of the electrical idle exit ordered set is 8 bits, each candidate starting position is used as the starting position of a candidate ordered set, and 8 bits of data are acquired starting from that position to obtain a candidate ordered set.

[0042] Next, step S13 is executed, where the weight values ​​for each candidate ordered set are accumulated bit by bit. Specifically, a pre-defined first reference ordered set is obtained. This first reference ordered set is set according to the standard electrical idle exit ordered set; therefore, each bit of data in the first reference ordered set is the correct data for the electrical idle exit ordered set. Then, each bit of data in each candidate ordered set is compared with the corresponding bit of data in the first reference ordered set. For example, the first bit of data in the candidate ordered set is compared with the first bit of data in the first reference ordered set, and the second bit of data in the candidate ordered set is compared with the second bit of data in the first reference ordered set, and so on. Since each bit of data is binary data, with only high and low levels, the comparison result is either the same or different. If the data in the candidate ordered set is the same as the data in the first reference ordered set, the bit is assigned a first weight value; if the data in the candidate ordered set is different from the data in the first reference ordered set, the bit is assigned a second weight value. Preferably, the first weight value is positive and the second weight value is negative; for example, the first weight value is +1 and the second weight value is -1. As can be seen, the absolute values ​​of the first and second weight values ​​are the same, but their signs are opposite.

[0043] Of course, in other embodiments, the second weight value is not necessarily -1; it can be set to other numbers, such as 0. Furthermore, the second weight value must be less than the first weight value. Alternatively, the absolute values ​​of the first and second weight values ​​can be different, for example, the first weight value is +2 and the second weight value is -1.

[0044] Then, in step S13, the weight values ​​corresponding to each data point in the candidate ordered set need to be accumulated to obtain the first accumulated weight value. It can be understood that if all 8 data points in the candidate ordered set are the same as all 8 data points in the first reference ordered set, the result of the first accumulated weight value is +8; if all 8 data points in the candidate ordered set are different from all 8 data points in the first reference ordered set, the result of the first accumulated weight value is -8; if only 4 of the 8 data points in the candidate ordered set are the same as all 8 data points in the first reference ordered set, the result of the first accumulated weight value is 0. Through the above method, the first accumulated weight value for each candidate ordered set can be obtained, meaning there are multiple data points for the first accumulated weight value.

[0045] Then, step S14 is executed, comparing the accumulated first weight value of each candidate ordered set with a pre-set first weight threshold to determine whether the accumulated first weight value of the candidate ordered set is greater than or equal to the first weight threshold. If the accumulated first weight value of a candidate ordered set is greater than or equal to the first weight threshold, then the candidate ordered set is determined as the target ordered set, and the candidate starting position corresponding to the target ordered set is determined as the target starting position. In principle, among multiple candidate starting positions, at most one is the correct starting position. Therefore, among multiple candidate ordered sets, at most one is the correct candidate ordered set whose accumulated first weight value is greater than or equal to the first weight threshold. Thus, at most one target starting position is determined.

[0046] It is evident that setting the first weight threshold is crucial, as it determines whether the target's starting position can be accurately identified. However, due to the influence of various factors on channel signal quality, such as communication distance and external interference signals, channel signal quality varies significantly under different operating conditions. The operating parameters of the high-speed bus (e.g., the channel's bit error rate) also vary considerably. If the same first weight threshold is used under different operating conditions, under a high bit error rate, it is possible that the accumulated first weight value of no candidate ordered set will be greater than or equal to the first weight threshold, resulting in the inability to obtain the target's starting position. Conversely, if the first weight threshold is set too low, under a low bit error rate, the accumulated first weight values ​​of multiple candidate ordered sets may be greater than or equal to the first weight threshold, again failing to obtain the target's starting position.

[0047] Therefore, in this embodiment, multiple candidate first weight thresholds are pre-set, and a suitable first weight threshold is dynamically selected based on the operating parameters of the high-speed bus. Specifically, multiple candidate first weight thresholds are pre-set according to different bit error rates, each candidate first weight threshold corresponding to a range of bit error rates. During operation, the bit error rate of the channel is first obtained, and then the corresponding first weight threshold is selected from the multiple candidate first weight thresholds as the actual first weight threshold used, based on the actual bit error rate of the channel. In this way, the first weight threshold is dynamically adjusted to meet the usage requirements under different bit error rate scenarios, thereby enabling accurate detection of the target starting position under different bit error rate scenarios.

[0048] Next, step S15 is executed to determine the positions of subsequent ordered sets based on the determined target ordered set, and to determine the data of the subsequent ordered sets. Since the sending end will immediately send data from other ordered sets after completing the transmission of the data from the electrically idle exit ordered set, the other ordered sets immediately following the electrically idle exit ordered set are called subsequent ordered sets. Typically, subsequent ordered sets are also fixed, meaning they have a fixed order and fixed data.

[0049] In step S15, the weight values ​​of the subsequent ordered sets need to be accumulated bit by bit. Specifically, a pre-set second reference ordered set is obtained. The second reference ordered set is a reference ordered set set according to other ordered sets following the electrical idle exit ordered set. Therefore, each bit of data in the second reference ordered set is the correct data of other ordered sets following the electrical idle exit ordered set. Then, each bit of data in the subsequent ordered set is compared with the corresponding bit of data in the second reference ordered set. For example, the first bit of data in the subsequent ordered set is compared with the first bit of data in the second reference ordered set, and so on. Since each bit of data is binary data, it only has high and low levels. Therefore, the comparison result can only be the same or different. If the data in the subsequent ordered set is the same as the data in the second reference ordered set, the bit is assigned a third weight value. If the data in the subsequent ordered set is different from the data in the second reference ordered set, the bit is assigned a fourth weight value. Preferably, the third weight value is positive and the fourth weight value is negative. For example, the third weight value is +1 and the fourth weight value is -1. It can be seen that the absolute values ​​of the third weight value and the fourth weight value are the same, but opposite in sign.

[0050] Of course, in other embodiments, the fourth weight value is not necessarily -1; it can be set to other numbers, such as 0. Alternatively, the absolute value of the third weight value may not be equal to the absolute value of the fourth weight value; for example, the third weight value may be +2 and the fourth weight value may be -1.

[0051] Then, the weight values ​​corresponding to each data point in the subsequent ordered set are summed to obtain the second weight sum. Since the subsequent ordered set has a large number of bits, such as 32 bits or 64 bits, if each data point in the subsequent ordered set is the same as the corresponding data point in the second reference ordered set, the second weight sum will be larger.

[0052] Next, step S16 is executed, comparing the accumulated second weight value with the second weight threshold to determine if the accumulated second weight value is greater than or equal to the second weight threshold. If it is, it indicates that the target starting position determined by the target ordered set is correct, and step S17 is executed to confirm that the target starting position is valid, and the symbolic state machine is switched from an unaligned state to an aligned state. If the result of step S16 is negative, it indicates that the target starting position determined by the target ordered set is incorrect, and step S18 needs to be executed to obtain a new candidate starting position, and then the process returns to step S13 to recalculate the target starting position.

[0053] This embodiment also sets multiple candidate second weight thresholds and dynamically selects an appropriate second weight threshold based on the operating parameters of the high-speed bus. Specifically, multiple candidate second weight thresholds are pre-set according to different bit error rates, each candidate second weight threshold corresponding to a range of bit error rates. During runtime, the channel's bit error rate is first obtained, and then the corresponding second weight threshold is selected from the multiple candidate second weight thresholds as the actual second weight threshold used based on the channel's bit error rate. This achieves dynamic adjustment of the second weight threshold to meet the usage requirements under different bit error rate scenarios.

[0054] As can be seen, the present invention does not use a single candidate starting position to determine the target starting position, but rather proposes multiple candidate starting positions and selects one of them as the target starting position through a series of calculations. This ensures that the calculated target starting position is more accurate.

[0055] See Figure 4 The present invention pre-determines multiple candidate starting positions, such as a first candidate starting position 31, a second candidate starting position 41, and a third candidate starting position 51. For each candidate starting position, a candidate ordered set is obtained. For example, a first candidate ordered set 32 ​​is obtained based on the first candidate starting position 31, a second candidate ordered set 42 is obtained based on the second candidate starting position 41, and a third candidate ordered set 52 is obtained based on the third candidate starting position 51. Then, the first weight accumulation values ​​33, 43, and 53 of the three candidate ordered sets need to be calculated respectively. The candidate ordered set corresponding to the first weight accumulation value that is greater than or equal to the first weight threshold is taken as the target ordered set, and the corresponding subsequent starting position is taken as the target starting position 60.

[0056] The present invention also uses subsequent ordered sets to verify the target starting position 60. That is, the target starting position 60 is used to determine the data of the subsequent ordered set, and the weight value of each bit of the subsequent ordered set is accumulated to obtain the second weight accumulation value. If the second weight accumulation value is greater than or equal to the second weight threshold, the target starting position is confirmed to pass the verification, and the target starting position is determined to be a valid starting position 61. Only then will the state of the symbol alignment state machine 14 change from the unaligned state 62 to the aligned state 63, thus realizing the synchronous detection of data.

[0057] Compared to traditional data synchronization methods, this invention can more accurately detect the starting position of an ordered set, especially precisely detecting electrical idle exits from the ordered set, thus providing a foundation for subsequent data identification of the ordered set. Furthermore, considering potential fluctuations in channel signal quality, this invention pre-sets multiple candidate first weight thresholds and multiple candidate second weight thresholds, and selects appropriate first and second weight thresholds based on the channel's bit error rate. This allows the first and second weight thresholds to be dynamically adjusted according to the bit error rate, meeting the needs of different bit error rate conditions and enabling more accurate identification of the precise starting position of the ordered set.

[0058] Finally, it should be emphasized that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A synchronization detection circuit for a high-speed serial bus, characterized in that, include: The data stream acquisition module is used to acquire an ordered set data stream, and to determine multiple candidate starting positions in the ordered set data stream, using each candidate starting position as the starting position of a candidate ordered set, to acquire multiple sets of candidate ordered sets. The first accumulator is used to perform weight accumulation calculation bit by bit for each of the candidate ordered sets to obtain a first weight accumulation value, and to determine the target starting position of the target ordered set based on multiple first weight accumulation values. The second accumulator is used to obtain the data of the subsequent ordered set of the target ordered set, perform weighted accumulation calculation on the subsequent ordered set bit by bit to obtain the second weighted accumulation value. If the second weighted accumulation value is greater than or equal to the second weight threshold, the target starting position of the target ordered set is confirmed as a valid starting position. When the first accumulator performs weighted accumulation calculation on each candidate ordered set bit by bit, it compares each bit of the candidate ordered set with the corresponding bit of the first reference ordered set. If the bit of the candidate ordered set is the same as the corresponding bit of the first reference ordered set, it assigns a first weight value; otherwise, it assigns a second weight value. The first accumulator calculates the weight value corresponding to each bit of the candidate ordered set by accumulating the weight values ​​to obtain the first weight accumulation value.

2. The synchronization detection circuit for a high-speed serial bus according to claim 1, characterized in that: When the first accumulator determines the target starting position of the target ordered set based on multiple first weight accumulation values, it determines whether the first weight accumulation value corresponding to the candidate ordered set is greater than or equal to the first weight threshold. If so, it confirms that the candidate starting position corresponding to the candidate ordered set is the target starting position.

3. The synchronization detection circuit for a high-speed serial bus according to claim 1, characterized in that: The first weight value is positive, and the second weight value is 0 or negative.

4. The synchronization detection circuit for a high-speed serial bus according to claim 1 or 2, characterized in that: When the second accumulator performs weighted accumulation calculation on the subsequent ordered set bit by bit, it compares each bit of the data in the subsequent ordered set with the corresponding bit of the data in the second reference ordered set. If the bit of the data in the subsequent ordered set is the same as the corresponding bit of the data in the second reference ordered set, it assigns a third weight value; otherwise, it assigns a fourth weight value. The second accumulator accumulates the weight values ​​corresponding to each bit of the subsequent ordered set to obtain the second weight accumulation value.

5. A synchronization detection method for a high-speed serial bus, characterized in that, include: Obtain an ordered set data stream, determine multiple candidate starting positions in the ordered set data stream, and use each candidate starting position as the starting position of a candidate ordered set to obtain multiple sets of candidate ordered sets. For each candidate ordered set, the weights are accumulated bit by bit to obtain a first accumulated weight value, and the target starting position of the target ordered set is determined based on multiple first accumulated weight values. Obtain the data of the subsequent ordered set of the target ordered set, perform weight accumulation calculation on the subsequent ordered set bit by bit to obtain the second weight accumulation value. If the second weight accumulation value is greater than or equal to the second weight threshold, then confirm that the target starting position of the target ordered set is a valid starting position. When performing weighted accumulation calculation on each candidate ordered set bit by bit, each bit of the candidate ordered set is compared with the corresponding bit of the first reference ordered set. If the bit of the candidate ordered set is the same as the corresponding bit of the first reference ordered set, a first weight value is assigned; otherwise, a second weight value is assigned. The first weight accumulation value is obtained by accumulating the weight values ​​corresponding to each data point in the candidate ordered set.

6. The synchronization detection method for a high-speed serial bus according to claim 5, characterized in that: If the second weight accumulation value is less than the second weight threshold, a new candidate starting position is obtained and a new target starting position is calculated.

7. The synchronization detection method for a high-speed serial bus according to claim 5 or 6, characterized in that: Determining the target starting position of the target ordered set based on multiple first weight accumulation values ​​includes: determining whether the first weight accumulation value corresponding to the candidate ordered set is greater than or equal to the first weight threshold; if so, confirming the candidate starting position corresponding to the candidate ordered set as the target starting position.

8. The synchronization detection method for a high-speed serial bus according to claim 7, characterized in that, The method also includes: Multiple candidate first weight thresholds are preset, and one of the multiple candidate first weight thresholds is determined as the first weight threshold based on the operating parameters of the high-speed serial bus; and / or Multiple candidate second weight thresholds are preset, and one of the multiple candidate second weight thresholds is determined as the second weight threshold based on the operating parameters of the high-speed serial bus.

9. The synchronization detection method for a high-speed serial bus according to claim 5 or 6, characterized in that: After confirming that the target starting position of the target ordered set is a valid starting position, the state of the symbol alignment state machine changes from the unaligned state to the aligned state.

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