Lossless data conversion system and method from spi to i2s format based on master-slave synchronization mechanism

Abstract

The application belongs to the field of embedded hardware data transmission, and particularly relates to a SPI to I2S format lossless data conversion system and method based on a master-slave synchronization mechanism. The system comprises an SPI interface sensor, a slave module and a host control module. The slave module reads 24-bit acceleration and 14-bit temperature complement data output by the sensor, performs bit segment extraction, complement to original code and 32-bit I2S format alignment through a data format conversion unit, and sends the data through a non-blocking data sending unit based on DMA cyclic transmission. The host module multiplexes the SPI peripheral into an I2S interface and serves as a unique clock source, synchronously receives and reconstructs data frames through a DMA receiving unit. The scheme does not require a dedicated conversion chip, realizes lossless, stable and master-slave synchronous transmission of SPI sensor complement data to standard I2S format, and has the advantages of low hardware cost, high data precision and good communication stability.

Description

Technical Field

[0001] This invention belongs to the field of embedded hardware data transmission technology, specifically relating to a lossless data conversion system and method for SPI to I2S format based on a master-slave synchronization mechanism. It is suitable for master-slave synchronous data interaction between SPI interface sensors and I2S interface embedded devices, and is especially suitable for lossless conversion and non-blocking transmission of raw data from two's complement output SPI sensors to standard I2S format. Background Technology

[0002] In embedded systems, SPI (Serial Peripheral Interface) is a widely used synchronous serial bus. It features a simple protocol, low hardware resource consumption, and is suitable for short-range, high-speed master-slave communication. Many front-end data acquisition devices, such as accelerometers, gyroscopes, and pressure sensors, output multi-byte raw data encoded in two's complement form via the SPI interface, such as 24-bit accelerometer complement combined with 14-bit temperature complement. On the other end, I2S (Inter-Chip Audio Bus) serves as a dedicated serial interface for continuous data streams such as audio. It boasts advantages such as a well-defined clock and frame structure and strong anti-interference capabilities, making it a primary data input interface on many control boards, processing boards, and expansion modules. In practical engineering scenarios, it's common for existing sensor front-ends to only provide SPI interfaces, while the back-end host board only provides I2S interfaces. Redesigning the hardware to change the interface type not only increases costs but also disrupts an already stable platform. Therefore, establishing a reliable data transmission link between the SPI sensor and the I2S host becomes a typical requirement.

[0003] To address this need, common existing approaches include using dedicated protocol conversion chips or programmable logic devices such as FPGAs / CPLDs to bridge protocols and convert formats between SPI and I2S. While this approach offers greater flexibility, it requires additional hardware and circuitry, increasing overall cost and power consumption, PCB area, and debugging workload. This makes it unsuitable for cost- and size-sensitive embedded applications. On the other hand, some solutions attempt to rely entirely on the MCU's internal peripherals, driving SPI and I2S data transfer via software. For example, polling is used to repeatedly read the I2S status flags, with the CPU writing and reading data when the transmit buffer is empty or the receive buffer is full. This approach is acceptable when the interface is simple and the data volume is small, but in continuous data stream scenarios, it consumes a significant amount of CPU time, making it difficult for the main loop to handle other tasks promptly. If the master and slave clocks are out of sync or the communication line malfunctions, the polling process may fail to meet the conditions, causing prolonged system blocking or even a "freeze."

[0004] Furthermore, the data format output by SPI interface sensors often differs significantly from the standard transmission format of the I2S interface. Taking 24-bit accelerometer complement and 14-bit temperature complement as examples, the original data is scattered across multiple bytes. It requires not only correct concatenation to obtain a complete value but also precise processing of the sign bit and effective bit width. If only simple shifting and concatenation are performed without considering the meaning of the complement and masking, errors in sign bit identification, truncated effective data bits, or improper padding can easily occur, leading to numerical deviations. Meanwhile, many microcontrollers' I2S peripherals are multiplexed from SPI peripherals, and their data registers are typically 16 bits wide. When transmitting 32-bit I2S frame data, a "32-bit split into two 16-bit" framing process must be performed on the software or DMA side. If the framing order, triggering timing, or loop method is not properly controlled, the host-side reassembly process may experience high-low bit misalignment, inconsistent frame start and end boundaries, ultimately manifesting as all data at the receiving end being zero, intermittent data errors, or unreproducible garbled data. At the same time, if the configurations of the I2S interfaces at both the master and slave ends are not completely consistent in terms of parameters such as data bit width, sampling frequency, clock polarity, and master clock output, it will directly affect the transmission stability and increase the difficulty of debugging.

[0005] In summary, achieving lossless data format conversion and stable master-slave synchronous transmission between an SPI complement output sensor and an I2S interface host, relying solely on the MCU's internal SPI, I2S, and DMA peripherals without adding dedicated hardware devices, remains a technical problem that needs to be solved in embedded systems at present. Summary of the Invention

[0006] The technical problem to be solved by this invention is: how to utilize the existing SPI, I2S and DMA peripherals of the microcontroller to achieve lossless data format conversion, master-slave synchronization and non-blocking stable transmission between the SPI interface complement output sensor and the I2S interface host without adding a dedicated conversion chip, thereby avoiding the defects of the prior art such as high hardware cost, system blocking and data distortion caused by polling, and communication asynchrony.

[0007] In order to achieve the above objectives:

[0008] On one hand, the present invention provides a lossless data conversion system from SPI to I2S format based on a master-slave synchronization mechanism, comprising:

[0009] An SPI interface sensor is used to acquire target physical quantities and output raw digital data in SPI format, including raw acceleration data and raw temperature data.

[0010] The slave control module includes:

[0011] An SPI peripheral, whose SPI communication port is connected to the SPI communication port of the SPI interface sensor, is used to read the raw digital data in SPI format;

[0012] I2S peripheral, wherein the I2S peripheral is multiplexed from the SPI peripheral and configured as an I2S slave transmit mode;

[0013] A data format conversion unit, connected to the SPI peripheral and the I2S peripheral, is used to convert raw digital data in SPI format into I2S format data adapted to the I2S transmission protocol.

[0014] A non-blocking data transmission unit, connected to the I2S peripheral, is used to transmit the I2S format data via DMA.

[0015] The host control module includes:

[0016] An SPI peripheral is multiplexed as an I2S interface and configured in I2S master receive mode. Its I2S interface is connected one-to-one with the I2S peripheral of the slave control module to receive I2S format data.

[0017] The DMA receiving unit, connected to the I2S interface, is used to transfer the received I2S format data to the receiving buffer.

[0018] A data visualization unit, connected to the DMA receiving unit and an OLED display screen, is used to parse and output the I2S format data in the receiving buffer.

[0019] The host control module is configured as a clock source to generate a serial clock signal and a frame synchronization signal. The I2S peripheral of the slave control module passively receives the serial clock signal and the frame synchronization signal and sends I2S format data under the control of the serial clock signal and the frame synchronization signal.

[0020] As an optional implementation, the data format conversion unit is configured to extract and concatenate bit segments of the SPI format raw digital data to obtain raw acceleration data and raw temperature data;

[0021] The data format conversion unit is further configured to perform a two's complement to original code conversion operation on the raw acceleration data to obtain a signed effective acceleration value, and to perform a two's complement to original code conversion operation on the raw temperature data to obtain a signed effective temperature value.

[0022] The data format conversion unit is further configured to shift and mask the effective acceleration value and the effective temperature value so that the effective acceleration value is aligned with the acceleration data bit segment of the I2S data frame.

[0023] As an optional implementation, the raw acceleration data output by the SPI interface sensor is 24-bit two's complement data, and the raw temperature data is 14-bit two's complement data;

[0024] The data format conversion unit is configured to expand the 24-bit two's complement form of the original acceleration data into 32-bit acceleration data through left shift and masking operations, and to convert the 14-bit two's complement form of the original temperature data into 16-bit temperature data through left shift and two's complement to original code operations.

[0025] The data format conversion unit is configured to use the 32-bit acceleration data as an acceleration data segment in a 32-bit I2S data frame.

[0026] As an optional implementation, the non-blocking data transmission unit includes a DMA transmission channel bound to the I2S peripheral, the DMA transmission channel being configured to:

[0027] Each frame of N-bit I2S format data is split into multiple M-bit subframe data, where N is a bit width greater than M, and the multiple M-bit subframe data includes the high-bit data segment and the low-bit data segment of the I2S format data.

[0028] In cyclic transfer mode, multiple M-bit frame data are sequentially transferred to the data register of the I2S peripheral.

[0029] The DMA receiving unit in the host control module includes a DMA receiving channel bound to the I2S interface. The DMA receiving channel is configured to, in cyclic transmission mode, transfer multiple M-bit framed data received from the I2S interface to the receiving buffer and concatenate them into N-bit I2S format data according to a preset order.

[0030] As an optional implementation, the non-blocking data transmission unit further includes a transmission timeout monitoring unit. The transmission timeout monitoring unit is used to monitor the transmission status flag of the I2S peripheral during the framed data transfer process of the DMA transmission channel. When the transmission status flag remains unchanged within a preset time threshold, the DMA transmission channel is controlled to exit the current data transfer process.

[0031] As an optional implementation, the I2S communication parameters of the host control module and the slave control module are consistent, and the I2S communication parameters include:

[0032] The I2S data format is a 32-bit data frame;

[0033] The I2S sampling frequency is 48kHz;

[0034] The I2S clock polarity is active low;

[0035] The host control module disables the master clock output.

[0036] As an optional implementation, the data acquisition period of the SPI interface sensor is 10ms;

[0037] The DMA transmit buffer length in the non-blocking data transmission unit is configured to be 4, storing 2 sets of I2S format data;

[0038] The DMA receive buffer in the DMA receive unit is configured with a length of 4, storing 2 sets of I2S format data;

[0039] The data format conversion unit is configured to update the I2S format data in the DMA transmit buffer according to the data acquisition cycle.

[0040] As an optional implementation, the SPI interface sensor includes an accelerometer and an integrated temperature detection unit;

[0041] The slave control module also includes a serial port debugging auxiliary unit, which is connected to the data format conversion unit and is used to output the SPI format raw digital data and the data output by the data format conversion unit through a serial interface.

[0042] The data visualization unit is configured to display I2S left channel data and I2S right channel data on the OLED display screen, respectively.

[0043] On the other hand, the present invention also provides a lossless data conversion method from SPI to I2S format based on a master-slave synchronization mechanism, applied to the above-mentioned system, including:

[0044] S1. The slave control module communicates with the SPI interface sensor's SPI communication port through the SPI peripheral to read SPI format raw digital data containing raw acceleration data and raw temperature data;

[0045] S2. The data format conversion unit in the slave control module extracts and splices the bit segments of the SPI format raw digital data to obtain the acceleration raw data and temperature raw data. It performs two's complement to original code conversion and shift and mask processing on the acceleration raw data and temperature raw data to generate I2S format data adapted to the I2S transmission protocol.

[0046] S3. In DMA cyclic transfer mode, the non-blocking data transmission unit in the slave control module splits the I2S format data into multiple frame data and moves them to the data register of the I2S peripheral, which then sends them to the host control module through the I2S interface.

[0047] S4. The host control module multiplexes its own SPI peripheral into an I2S interface, configures it in I2S host receiving mode, outputs a serial clock signal and a frame synchronization signal, and uses the DMA receiving unit in DMA loop transmission mode to transfer the framed data received from the I2S interface to the receiving buffer and splice it into I2S format data.

[0048] S5. The data visualization unit in the host control module parses the I2S format data in the receiving buffer to obtain the effective values ​​of acceleration and temperature, and outputs them to the OLED display screen.

[0049] As an optional implementation, step S2 includes:

[0050] Shift and mask operations are performed on the original 24-bit two's complement acceleration data to obtain 32-bit acceleration data. The most significant bit of the 24-bit two's complement data is then checked. If the most significant bit is 1, 2 is subtracted from the original 24-bit two's complement acceleration data. 24 The negative acceleration effective value is obtained. When the highest bit is 0, the original acceleration data in 24-bit two's complement form is directly taken as the positive acceleration effective value.

[0051] Shift operations and two's complement to original code operations are performed on the original temperature data in 14-bit two's complement form to obtain a 16-bit effective temperature value.

[0052] Step S3 includes:

[0053] Each frame of 32-bit I2S format data is split into two 16-bit frames, and in the cyclic transmission mode of the DMA transmit channel, the two 16-bit frames are written to the data register of the I2S peripheral in sequence.

[0054] During the frame data transfer process in the DMA transmission channel, the transmission status flag of the I2S peripheral is monitored. When the transmission status flag remains unchanged within a preset time threshold, the current loop transmission is terminated.

[0055] Compared with the prior art, the present invention has the following advantages:

[0056] First, by constructing a complete data path within the microcontroller that consists of "SPI acquisition - data format conversion - I2S and DMA transmission - I2S and DMA reception - data parsing and display", the connection method between the SPI interface sensor and the I2S host is unified in structure, and the introduction of external conversion chips is avoided, thereby reducing the system complexity at the hardware level.

[0057] Secondly, for the 24-bit acceleration complement and 14-bit temperature complement output by the SPI sensor, the data format conversion unit of this invention achieves lossless conversion from the original sensor data to the I2S transmission data through explicit bit segment extraction and splicing rules, complement to original code conversion operation, and shift and masking processing to align to the 32-bit I2S data frame, so that the acceleration and temperature information can be accurately recovered numerically.

[0058] Furthermore, to address the issue that traditional software polling methods can easily cause main loop blocking, this invention employs DMA loop mode on both the slave and master sides to drive the transmission and reception of I2S data. On this basis, a timeout monitoring mechanism is introduced to actively exit the current loop when the I2S transmission or reception status flag remains unchanged for an extended period of time. This ensures continuous data transmission capability while avoiding the freezing phenomenon under abnormal conditions.

[0059] Finally, by uniformly configuring the host-side I2S interface as the clock source and uniformly constraining the I2S configuration parameters (including data bit width, sampling frequency, clock polarity, master clock output configuration, etc.) of the host and slave, this invention ensures that the clocks and frame structures of the master and slave ends are strictly matched at the system level, reducing the debugging difficulty and transmission error risk caused by parameter inconsistencies.

[0060] Through the combination of the above structure and process, the present invention not only has advantages in terms of hardware resources and system cost, but also achieves comprehensive improvements in data accuracy, real-time transmission and system robustness. At the same time, it retains good versatility and portability, and can be extended to different microcontroller platforms and various SPI interface sensors. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0062] Figure 1 A structural block diagram of the SPI to I2S format lossless data conversion system based on master-slave synchronization mechanism provided by the present invention;

[0063] Figure 2 A flowchart of the lossless data conversion method from SPI to I2S format based on master-slave synchronization mechanism provided by the present invention;

[0064] Figure 3 This is a schematic diagram illustrating the principle of the specific data format conversion logic provided by the present invention. Detailed Implementation

[0065] To make the objectives, technical solutions, and advantages of this invention clearer, the following description is provided in conjunction with the appendix to the specification. Figure 1 To be continued Figure 3 This paper provides a more detailed description of the lossless data conversion system and method for SPI to I2S format based on a master-slave synchronization mechanism proposed in this invention. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the scope of the invention.

[0066] Example 1:

[0067] This embodiment provides a lossless data conversion system from SPI to I2S format based on a master-slave synchronization mechanism, such as... Figure 1 As shown, the entire system is physically divided into three main parts: an SPI interface sensor that performs environmental sensing and electrical signal conversion; a slave control module that handles real-time data protocol conversion and push; and a master control module that serves as the system clock reference and initiates data reception. In the specific physical deployment, the SPI interface sensor is installed at the vibration or temperature monitoring point of the object being measured. The slave control module is physically connected to the SPI interface sensor via a short-distance SPI bus, while the slave control module and the master control module can communicate across modules via a three-wire I2S bus. This architecture effectively achieves electrical decoupling between front-end data acquisition and back-end processing.

[0068] Regarding hardware selection and installation connections, the slave control module can preferably use the STM32F103ZET6 development board as its core computing unit, while the master control module can use the STM32F103RCT6 master development board. It should be noted that this embodiment uses the STM32F103 series microcontroller as an example, but the technical solution of this invention is also applicable to other microcontroller platforms with SPI multiplexing as I2S and DMA functions, such as other STM32 series, ESP32, GD32, etc., which are not listed in this embodiment. The SPI interface sensor is configured to acquire target physical quantities and output raw digital data in SPI format, including raw acceleration data and raw temperature data. Specifically, the SPI interface sensor is connected to the SPI peripheral port of the STM32F103ZET6 development board through the clock line SCK, chip select line CS, master input / slave output line MISO, and master output / slave input line MOSI. The acceleration data output by the SPI interface sensor is in 24-bit two's complement format, and the temperature data is in 14-bit two's complement format.

[0069] The slave control module, i.e., the STM32F103ZET6 development board, has internal logic units including an SPI peripheral, an I2S peripheral, a data format conversion unit, and a non-blocking data transmission unit. In an optional implementation, a serial port debugging auxiliary unit is also provided, which outputs the raw SPI data and the format-converted I2S data to the host computer for verification via a UART peripheral. This serial port debugging auxiliary unit does not change the core data transmission link. The SPI communication port of the SPI peripheral is physically peer-to-peer connected to the interface of the aforementioned SPI interface sensor, used to capture raw bytes at a preset frequency. To achieve maximum reuse of hardware resources, the I2S peripheral is configured in I2S mode by register mapping from another SPI peripheral within the development board, and is strictly set to I2S slave transmission mode. This means that the module does not generate a clock signal independently, but passively receives the bit clock signal BCLK and the channel selection signal WS issued by the STM32F103RCT6 host development board through its pins, and sends I2S format data to the host control module through the I2S interface under the control of the serial clock signal and frame synchronization signal. The data format conversion unit is logically connected between the SPI receiver and the I2S transmitter, responsible for executing complex shift concatenation and two's complement restoration algorithms. The non-blocking data transmission unit consists of a DMA transmission channel bound to the I2S peripheral, configured to operate in DMA cyclic transfer mode, ensuring that the CPU does not need to intervene in the shifting process of each bit of data. Specifically, the memory address of the DMA transmission channel points to a transmission buffer with a length of 4, used to cyclically store the I2S format data to be transmitted. In this embodiment, the transmission buffer can store two sets of I2S format data, each set corresponding to two 16-bit frames obtained by splitting a 32-bit data frame.

[0070] As the clock hub of the entire system, the master control module, namely the STM32F103RCT6 master development board, internally includes an SPI peripheral, a DMA receiver unit, and a data visualization unit. The master's SPI peripheral is multiplexed as an I2S interface and set to I2S master receive mode, responsible for driving the deterministic timing of the entire bus. Specifically, it acts as a clock source, generating the serial clock signal BCLK and the frame synchronization signal WS, providing a unified timing reference for the slave control module's I2S peripheral to send I2S format data. The I2S interface of the STM32F103RCT6 master development board is connected one-to-one with the slave control module's I2S peripheral via signal lines. The WS and BCLK pins on the master side serve as outputs, while the serial data line SD serves as an input. The master's DMA receiver unit is connected to the I2S interface and is responsible for automatically pushing the received data stream into the memory receive buffer. The DMA receive channel also operates in circular transfer mode, and its memory address points to a receive buffer configured with a length of 4, used to store two sets of I2S format data received from the I2S interface. The data visualization unit is further connected to the external OLED display and serial PC display terminal to convert the invisible binary bit stream into intuitive acceleration and temperature values, and to display the I2S left channel data and I2S right channel data on the OLED display, so that the acceleration data and temperature data can be distinguished at the display level.

[0071] like Figure 3 As shown, since the raw data output by the SPI interface sensor is scattered in multiple 8-bit registers, the data format conversion unit is configured to first extract and concatenate the bit segments of the read data. Taking 24-bit acceleration raw data as an example, assuming the raw bytes are stored in the array DataArray, the conversion unit performs the following concatenation operation logic: by operating on the array storing the raw data, firstly, the lower 7 bits of the first byte DataArray[0] are extracted and shifted 17 bits to the left, then all 8 bits of the second byte DataArray[1] are extracted and shifted 9 bits to the left, then all 8 bits of the third byte DataArray[2] are extracted and shifted 9 bits to the left, and finally the 7th bit of the fourth byte DataArray[3] is extracted. The processed data segments are then logically concatenated by bitwise OR operation to reconstruct the complete 24-bit acceleration raw data. On this basis, in order to ensure the accuracy of the positive and negative attributes of the physical quantity, the conversion unit performs a two's complement to original code operation on the extracted acceleration raw data. Specifically, the system will detect the highest bit of the 24-bit data, i.e., the 23rd bit, as the sign bit. When the highest bit is 1, it is determined to be a negative number. In this case, 2 is subtracted from the original 24-bit two's complement acceleration data. 24That is, subtract 16777216 to obtain the correct negative acceleration effective value; when the highest bit is 0, the 24-bit original data is directly taken as the positive acceleration effective value.

[0072] For temperature data, the system also adopts conversion logic that conforms to the distribution pattern of sensor registers. The system performs a concatenation operation on the 14-bit two's complement temperature data: by extracting the lower 6 bits of DataArray[3] and all 8 bits of DataArray[4], the higher bits are shifted left by 8 bits and combined with the lower bits using a bitwise OR operation, thus obtaining the 14-bit original temperature value. After concatenation, the system also checks its highest bit, the 13th bit; if it is 1, it subtracts 2. 14 Subtracting 16384 yields a 16-bit bandwidth signed RMS temperature value. After restoring the RMS acceleration and temperature values, the data format conversion unit is configured to perform shifting and masking processing on these values ​​to adapt to the I2S transmission protocol. This ensures the RMS acceleration value is aligned with a predetermined acceleration data bit segment in the I2S data frame and that the effective bit width of the temperature value is not interfered with by high or low bit noise. In this embodiment, I2S is configured as a 32-bit data frame format. To achieve lossless alignment, the conversion unit shifts the 24-bit RMS acceleration value left by 8 bits, aligning its most significant bit with the most significant bit of the I2S frame. The remaining low bits are filtered and padded with zeros using a mask. The processed 32-bit acceleration data is mapped to the left channel data segment of the standard I2S data frame, while the 16-bit temperature RMS value or zero value is mapped to the right channel data segment, thus forming a complete dual-channel I2S data frame for easy identification and parsing by the host.

[0073] To verify the accuracy of the conversion logic, this embodiment conducted simulation tests using multiple sets of experimental data. For example, when the system obtains the original hexadecimal two's complement code of the positive acceleration corresponding to 0x000FFF, the conversion unit determines that its highest bit is 0, classifying it as a positive value. The resulting decimal effective value is 4095, which is represented as 0x000FFF00 in the 32-bit frame output of the I2S. As another example, when the system detects the original hexadecimal two's complement code of the negative acceleration corresponding to 0xFFF000, the system detects that its highest bit is 1, classifying it as a negative number. By subtracting 16777216, the system obtains a decimal effective value of -4096, which is represented as 0xFFF00000 in the corresponding 32-bit frame output on the I2S bus. Under extreme conditions, if the original two's complement is 0x7FFFFF, the sign bit is 0, the converted decimal effective value is 8388607, and the I2S output is 0x7FFFFF00. However, if the original two's complement reaches the extreme negative value of 0x800000, the sign bit is 1, and the decimal effective value obtained after subtraction is -8388608, ultimately outputting 0x80000000 on the I2S bus. This processing method ensures that even if the data bit width changes during subsequent transmission, the weight ratio remains constant, thus achieving truly lossless conversion.

[0074] At the physical transport layer, the non-blocking data transmission unit exhibits extremely high communication robustness. Due to the bit width limitation of the I2S data register on the STM32F103ZET6 development board, the non-blocking data transmission unit splits each frame of 32-bit I2S format data into two 16-bit subframes. The DMA transmission channel, in cyclic transmission mode, sequentially writes these two 16-bit subframes into the register. Correspondingly, the DMA receiving unit in the STM32F103RCT6 host development board also includes a channel operating in cyclic mode. It moves the received multiple 16-bit subframes to a buffer and reassembles them into complete 32-bit data according to their sequence. To prevent deadlock caused by hardware malfunctions, the system incorporates a timeout protection mechanism. The transmission timeout monitoring unit in the non-blocking data transmission unit polls the transmission status flag in real time. If the flag is not updated within a preset 10ms threshold, a forced reset is performed. Similarly, the DMA receiving unit of the host control module also includes a receive timeout monitoring unit to prevent the receiver from freezing. In addition, the data acquisition cycle (10ms), I2S transmission rate (48kHz), and DMA single transmission data volume (2 groups of 32-bit frames) of the SPI interface sensor are matched to ensure the continuity of the data stream.

[0075] This embodiment provides a lossless data conversion system for SPI to I2S format based on a master-slave synchronization mechanism. Through efficient collaboration between the STM32F103ZET6 development board and the STM32F103RCT6 host development board, it achieves heterogeneous protocol interoperability without additional hardware chips. The system utilizes a two's complement to original code algorithm to completely eliminate the quantization bias of sensor data, with a data conversion error of less than 0.1% and a system CPU utilization of less than 5%. The DMA cyclic transfer mode combined with timeout protection logic gives the system strong self-healing capabilities under asynchronous power-on of the master and slave devices or transient line interference, allowing for continuous operation for 72 hours without freezing or garbled data. Furthermore, the system achieves hardware-level data bridging through pure software configuration, significantly reducing the R&D and material costs of embedded devices.

[0076] Example 2:

[0077] This embodiment, based on the system described in Embodiment 1, provides a method for lossless data conversion from SPI to I2S format based on a master-slave synchronization mechanism, such as... Figure 2 As shown, the method first executes step S1 to initialize the system and align peripheral parameters. During this process, the slave control module enables all relevant multiplexed function clocks through internal instructions. Specifically, the I2S channel select pin WS and bit clock pin BCLK of the STM32F103ZET6 development board are configured as input modes to be controlled by the host. Simultaneously, the STM32F103RCT6 host development board initializes its I2S peripherals to host mode, sets the sampling frequency to 48kHz according to the formula, and configures the clock polarity to be active low. It is important to emphasize that initialization must be performed with a fixed priority, prioritizing I2S and DMA configurations before configuring SPI to avoid hardware resource conflicts. The I2S parameters of the master and slave devices, including data format (32-bit), sampling frequency (48kHz), clock polarity (active low), and whether the master clock output is disabled, must be completely consistent. This is the foundation for achieving precise synchronization. In this embodiment, the master control module disables the master clock output and acts as the clock source, outputting a serial clock signal BCLK and a frame synchronization signal WS to the slave control module. The slave control module's I2S peripheral passively receives these signals and uses them to complete the transmission of I2S formatted data. The master side synchronously starts the DMA receive channel and allocates a continuous receive storage space as a buffer.

[0078] Then, step S2 is executed, where the slave control module performs timed acquisition of sensor data via the SPI peripheral, and the data format conversion unit executes the core algorithm. In a preferred embodiment, the SPI acquisition period is set to 10ms to balance the sensor refresh rate and the microcontroller's processing capability. The core logic of this step is lossless mapping for heterogeneous bit widths. Specifically, a splicing operation is performed on the 24-bit two's complement form of the original acceleration data: by reading the first 4 bytes in the original data storage array, the lower 7 bits of DataArray[0] are shifted left by 17 bits, all 8 bits of DataArray[1] are shifted left by 9 bits, all 8 bits of DataArray[2] are shifted left by 9 bits, and the 7th bit of DataArray[3] is directly extracted. The above segments are combined into a 24-bit original value by bitwise OR operation. Based on this, 32-bit acceleration data is obtained by left shifting by 8 bits and masking operation. The highest bit of the 24-bit two's complement form is detected. When the highest bit is 1, 2 is subtracted from the 24-bit two's complement form of the original acceleration data. 24 The negative acceleration effective value is obtained. When the highest bit is 0, the 24-bit two's complement form of the original acceleration data is directly taken as the positive acceleration effective value. At the same time, the 14-bit two's complement form of the original temperature data is concatenated: the lower 6 bits of DataArray[3] and all 8 bits of DataArray[4] are extracted, the high bit part is shifted left by 8 bits and then combined with the low bit part by bitwise OR to obtain the 14-bit original temperature value, and the two's complement to original code operation is performed, that is, when the highest bit is 1, 2 is subtracted. 14 This yields a 16-bit effective temperature value. After the bit segment extraction and concatenation, two's complement to original code conversion, and shifting and masking processes described above, the data format conversion unit generates I2S format data adapted to the I2S transmission protocol, where the effective acceleration value is aligned with the acceleration data bit segment of the I2S data frame. The converted data is then encapsulated into a predefined standard frame structure.

[0079] Following step S3, the non-blocking data transmission process is initiated. The slave control module preferentially fills the left channel segment of the DMA transmit buffer with the converted N-bit I2S format core data, and fills the right channel segment with zero values. Based on this, each frame of 32-bit I2S format data is split into two 16-bit frames, and in the cyclic transmission mode of the DMA transmit channel, the two 16-bit frames are sequentially written to the data register of the I2S peripheral. To improve robustness, during the frame data transfer process in the DMA transmit channel, the monitoring unit monitors the transmit status flag of the I2S peripheral in real time. When the transmit status flag remains unchanged within a preset time threshold, it indicates that the bus is blocked. At this time, the program automatically terminates the current cyclic transmission and performs a reset operation.

[0080] Next, step S4 is executed, where the host side performs synchronous reception. Since the host initiates the clock, its generated BCLK signal drives the slave-side registers to pop bits one by one. The STM32F103RCT6 host development board captures these level changes through its I2S interface, and the DMA receiving unit automatically moves the received framed data to the memory buffer in cyclic transfer mode. In memory, the host, according to preset splicing instructions, reassembles the successively arriving high 16 bits and low 16 bits of data into a logical 32-bit integer value, thereby reconstructing the original acceleration and temperature information sent by the slave.

[0081] Finally, step S5 is executed, entering the result display stage. The data visualization unit in the STM32F103RCT6 host development board periodically extracts the stitched I2S format data from the receive buffer. The visualization unit integrates a range conversion formula to convert the raw digital quantities into physically meaningful acceleration and temperature values, and displays the acceleration data corresponding to the left channel and the temperature data corresponding to the right channel of the I2S on the OLED display screen. At the same time, when needed, the parsed data is uploaded to the PC display interface for feedback and recording via a serial port link.

[0082] The conversion method provided in this embodiment achieves real-time data transfer between heterogeneous buses by pre-processing complex logic operations at the acquisition end and utilizing the high-efficiency concurrency capabilities of DMA. The closed-loop logic of the method, through rigorous bit operations and two's complement restoration, ensures that the data flow from the sensor physical end to the host display end is completely deterministic and lossless. The introduction of multiple timeout monitoring mechanisms enables this method to adapt to the harsh electromagnetic interference environment of industrial sites. Verified, it can guarantee long-term stable system operation and has extremely high engineering practical value. Furthermore, this method cleverly solves the sampling slippage problem caused by crystal oscillator frequency offset through a master-slave synchronous clock architecture.

Claims

1. A lossless data conversion system from SPI to I2S format based on a master-slave synchronization mechanism, characterized in that, include: An SPI interface sensor is used to acquire target physical quantities and output raw digital data in SPI format, including raw acceleration data and raw temperature data. The slave control module includes: An SPI peripheral, whose SPI communication port is connected to the SPI communication port of the SPI interface sensor, is used to read the raw digital data in SPI format; I2S peripheral, wherein the I2S peripheral is multiplexed from the SPI peripheral and configured as an I2S slave transmit mode; A data format conversion unit, connected to the SPI peripheral and the I2S peripheral, is used to convert raw digital data in SPI format into I2S format data adapted to the I2S transmission protocol. A non-blocking data transmission unit, connected to the I2S peripheral, is used to transmit the I2S format data via DMA. The host control module includes: An SPI peripheral is multiplexed as an I2S interface and configured in I2S master receive mode. Its I2S interface is connected one-to-one with the I2S peripheral of the slave control module to receive I2S format data. The DMA receiving unit, connected to the I2S interface, is used to transfer the received I2S format data to the receiving buffer. A data visualization unit, connected to the DMA receiving unit and an OLED display screen, is used to parse and output the I2S format data in the receiving buffer. The host control module is configured as a clock source to generate a serial clock signal and a frame synchronization signal. The I2S peripheral of the slave control module passively receives the serial clock signal and the frame synchronization signal and sends I2S format data under the control of the serial clock signal and the frame synchronization signal. The data format conversion unit is configured to extract and concatenate bit segments of the raw digital data in SPI format to obtain raw acceleration data and raw temperature data. The data format conversion unit is further configured to perform a two's complement to original code conversion operation on the raw acceleration data to obtain a signed effective acceleration value, and to perform a two's complement to original code conversion operation on the raw temperature data to obtain a signed effective temperature value. The data format conversion unit is further configured to perform shift and masking processing on the effective acceleration value and the effective temperature value, so that the effective acceleration value is aligned with the acceleration data bit segment of the I2S data frame; The raw acceleration data output by the SPI interface sensor is 24-bit two's complement data, and the raw temperature data is 14-bit two's complement data; The data format conversion unit is configured to expand the 24-bit two's complement form of the original acceleration data into 32-bit acceleration data through left shift and masking operations, and to convert the 14-bit two's complement form of the original temperature data into 16-bit temperature data through left shift and two's complement to original code operations. The data format conversion unit is configured to use the 32-bit acceleration data as an acceleration data segment in a 32-bit I2S data frame.

2. The lossless data conversion system from SPI to I2S format based on master-slave synchronization mechanism according to claim 1, characterized in that: The non-blocking data transmission unit includes a DMA transmission channel bound to the I2S peripheral, and the DMA transmission channel is configured as follows: Each frame of N-bit I2S format data is split into multiple M-bit subframe data, where N is a bit width greater than M, and the multiple M-bit subframe data includes the high-bit data segment and the low-bit data segment of the I2S format data. In cyclic transfer mode, multiple M-bit frame data are sequentially transferred to the data register of the I2S peripheral. The DMA receiving unit in the host control module includes a DMA receiving channel bound to the I2S interface. The DMA receiving channel is configured to, in cyclic transmission mode, transfer multiple M-bit framed data received from the I2S interface to the receiving buffer and concatenate them into N-bit I2S format data according to a preset order.

3. The lossless data conversion system from SPI to I2S format based on master-slave synchronization mechanism according to claim 2, characterized in that: The non-blocking data transmission unit also includes a transmission timeout monitoring unit. The transmission timeout monitoring unit is used to monitor the transmission status flag of the I2S peripheral during the framed data transfer process of the DMA transmission channel. When the transmission status flag remains unchanged within a preset time threshold, the DMA transmission channel is controlled to exit the current data transfer process.

4. The lossless data conversion system from SPI to I2S format based on master-slave synchronization mechanism according to claim 1, characterized in that: The I2S communication parameters of the host control module and the slave control module are consistent, and the I2S communication parameters include: The I2S data format is a 32-bit data frame; The I2S sampling frequency is 48kHz; The I2S clock polarity is active low; The host control module disables the master clock output.

5. The lossless data conversion system from SPI to I2S format based on master-slave synchronization mechanism according to claim 1, characterized in that: The data acquisition period of the SPI interface sensor is 10ms; The DMA transmit buffer length in the non-blocking data transmission unit is configured to be 4, storing 2 sets of I2S format data; The DMA receive buffer in the DMA receive unit is configured with a length of 4, storing 2 sets of I2S format data; The data format conversion unit is configured to update the I2S format data in the DMA transmit buffer according to the data acquisition cycle.

6. The lossless data conversion system from SPI to I2S format based on master-slave synchronization mechanism according to claim 1, characterized in that: The SPI interface sensor includes an accelerometer and an integrated temperature detection unit; The slave control module also includes a serial port debugging auxiliary unit, which is connected to the data format conversion unit and is used to output the SPI format raw digital data and the data output by the data format conversion unit through a serial interface. The data visualization unit is configured to display I2S left channel data and I2S right channel data on the OLED display screen, respectively.

7. A method for lossless data conversion from SPI to I2S format based on a master-slave synchronization mechanism, applied to the system described in any one of claims 1 to 6, characterized in that, include: S1. The slave control module communicates with the SPI interface sensor's SPI communication port through the SPI peripheral to read SPI format raw digital data containing raw acceleration data and raw temperature data; S2. The data format conversion unit in the slave control module extracts and splices the bit segments of the SPI format raw digital data to obtain the acceleration raw data and temperature raw data. It performs two's complement to original code conversion and shift and mask processing on the acceleration raw data and temperature raw data to generate I2S format data adapted to the I2S transmission protocol. S3. In DMA cyclic transfer mode, the non-blocking data transmission unit in the slave control module splits the I2S format data into multiple frame data and moves them to the data register of the I2S peripheral, which then sends them to the host control module through the I2S interface. S4. The host control module multiplexes its own SPI peripheral into an I2S interface, configures it in I2S host receiving mode, outputs a serial clock signal and a frame synchronization signal, and uses the DMA receiving unit in DMA loop transmission mode to transfer the framed data received from the I2S interface to the receiving buffer and splice it into I2S format data. S5. The data visualization unit in the host control module parses the I2S format data in the receiving buffer to obtain the effective values ​​of acceleration and temperature, and outputs them to the OLED display screen.

8. The method for lossless data conversion from SPI to I2S format based on master-slave synchronization mechanism according to claim 7, characterized in that: Step S2 includes: Shift and mask operations are performed on the original 24-bit two's complement acceleration data to obtain 32-bit acceleration data. The most significant bit of the 24-bit two's complement data is then checked. If the most significant bit is 1, 2 is subtracted from the original 24-bit two's complement acceleration data. 24 The negative acceleration effective value is obtained. When the highest bit is 0, the original acceleration data in 24-bit two's complement form is directly taken as the positive acceleration effective value. Shift operations and two's complement to original code operations are performed on the original temperature data in 14-bit two's complement form to obtain a 16-bit effective temperature value. Step S3 includes: Each frame of 32-bit IS format data is split into two 16-bit frames, and in the cyclic transmission mode of the DMA transmit channel, the two 16-bit frames are written to the data register of the I2S peripheral in sequence. During the frame data transfer process in the DMA transmission channel, the transmission status flag of the I2S peripheral is monitored. When the transmission status flag remains unchanged within a preset time threshold, the current loop transmission is terminated.

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