A system and method for calibrating frequency offset of a serial communication interface
By using a serial communication interface frequency offset calibration system, frequency offset is detected and PLL frequency modulation coefficients are calculated through signal comparison and phase-locked loop (PLL) modules. This solves the compatibility problem of the same-source reference clock scheme, realizes the synchronization of the device and host clock signals, reduces hardware overhead, and improves compatibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BESTECHNIC SHANGHAI CO LTD
- Filing Date
- 2024-11-29
- Publication Date
- 2026-06-16
Smart Images
Figure CN119561812B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of serial communication technology, and in particular to a calibration system and method for frequency offset of a serial communication interface. Background Technology
[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard that is now widely used. In PCIe communication, devices typically use a 100MHz SSC (Spread Spectrum Clocking) signal provided by the host as the reference input for the device's PLL (Phase-Locked Loop). Because the triangular wave spreading frequency of the SSC clock signal is relatively slow, it can be approximated that the device's clock frequency is consistent with the host's. Then, the host transmits 100MHz reference clock stability information via the PERST signal to ensure clock synchronization.
[0003] However, the aforementioned co-source reference clock scheme heavily relies on a 100MHz differential clock and the PERST signal, increasing additional hardware cost and complexity. Furthermore, when using the SSC clock signal between the host and the device, compatibility issues often arise because different hosts have different activation times from the PERST signal to the stable output of the 100MHz reference clock. Therefore, there are areas for improvement. Summary of the Invention
[0004] The purpose of this invention is to provide a calibration system and method for frequency offset of serial communication interfaces, which solves the technical problem that the existing co-source reference clock scheme has poor compatibility and increases additional hardware costs and complexity.
[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:
[0006] This invention provides a calibration system for frequency offset of a serial communication interface, applied in a device serially connected to a host, comprising:
[0007] The analog front-end module is used to receive data signals sent by the host and extract the corresponding data edge information, wherein the data edge information represents the time point of the rising edge or falling edge of the data signal;
[0008] The signal comparison module is used to compare the device's internal clock signal with the data edge information to generate frequency offset information;
[0009] The frequency offset coefficient generation module is used to calculate and process the frequency offset information based on a preset modulation coefficient to generate a frequency offset modulation coefficient.
[0010] A phase-locked loop module is used to adjust the frequency of the internal clock signal according to the frequency offset modulation coefficient.
[0011] In one embodiment of the present invention, the phase-locked loop module is provided with a voltage-controlled oscillator, which is used to generate the internal clock signal.
[0012] In one embodiment of the present invention, the signal comparison module includes:
[0013] A phase detector is used to compare the phase error between the device's internal clock signal and the data edge information to generate phase error information;
[0014] A second-order low-pass filter is used to integrate the phase error information to generate frequency offset information.
[0015] In one embodiment of the present invention, the signal comparison module further includes a phase interpolator, which is used to adjust the phase of the internal clock signal.
[0016] In one embodiment of the present invention, the second-order low-pass filter is further configured to generate phase adjustment information based on the phase error information, and the phase interpolator is further configured to adjust the phase of the internal clock signal based on the phase adjustment information and send the adjusted internal clock signal to the phase detector.
[0017] In one embodiment of the present invention, the second-order low-pass filter is provided with a proportional path and an integral path, wherein the proportional path is used to generate phase adjustment information based on the amplitude of the phase error information, and the integral path is used to generate frequency offset information based on the integral of the phase error information over time.
[0018] In one embodiment of the present invention, the integration path is a 16-bit integration path accumulator.
[0019] In one embodiment of the present invention, the frequency offset modulation coefficient is expressed as:
[0020]
[0021] Among them, f vco f represents the frequency of the internal clock signal. ref Indicates the clock frequency of the data signal, 2 23 The `floor()` function is used as a scaling factor to round down, and the `dec2hex()` function is used to convert the calculation result to hexadecimal representation. The value represents the proportion of the frequency offset information, and k represents the preset modulation coefficient.
[0022] The present invention also provides a method for calibrating the frequency offset of a serial communication interface, comprising:
[0023] The system receives data signals sent by the host and extracts the corresponding data edge information, wherein the data edge information represents the time point of the rising or falling edge of the data signal;
[0024] The device's internal clock signal is compared with the data edge information to generate frequency offset information;
[0025] Based on the preset modulation coefficients, the frequency offset information is calculated and processed to generate frequency offset modulation coefficients;
[0026] The frequency of the internal clock signal is adjusted according to the frequency offset modulation coefficient.
[0027] In one embodiment of the present invention, the step of comparing the internal clock signal of the device with the data edge information to generate frequency offset information includes:
[0028] The phase error between the device's internal clock signal and the data edge information is compared to generate phase error information;
[0029] Based on the phase error information, phase adjustment information and frequency offset information are generated;
[0030] The internal clock signal is phase-adjusted according to the phase adjustment information.
[0031] As described above, the present invention provides a calibration system and method for frequency offset of serial communication interface, which has the following beneficial effects: the present invention can realize that the internal clock signal of the device follows the frequency offset of the host's SSC clock signal in real time, solves the dependence on the host's 100MHz reference clock in PCIe communication, saves hardware overhead, and improves device compatibility.
[0032] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description
[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 This is a schematic diagram of the structure of a serial communication interface frequency offset calibration system according to an embodiment of the present invention.
[0035] Figure 2 This is a schematic diagram of the signal comparison module in one embodiment of the present invention.
[0036] Figure 3 This is a schematic diagram illustrating how the internal clock signal of the device follows the host clock signal in one embodiment of the present invention.
[0037] Figure 4 This is a schematic diagram illustrating the frequency difference between the internal clock signal of the device and the clock signal of the host in one embodiment of the present invention.
[0038] Figure 5 This is a flowchart illustrating a method for calibrating the frequency offset of a serial communication interface according to an embodiment of the present invention.
[0039] In the picture:
[0040] 100. Equipment; 110. Analog front-end module; 120. Signal comparison module; 121. Phase detector; 122. Second-order low-pass filter; 123. Phase interpolator; 130. Frequency offset coefficient generation module; 140. Phase-locked loop module.
[0041] 200 host;
[0042] 301. First frequency curve; 302. Second frequency curve. Detailed Implementation
[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0044] First, it's important to clarify that PCIe (Peripheral Component Interconnect Express) is a high-speed serial bus standard widely used in modern computer systems to connect various internal computer components, such as graphics cards, storage devices, and network adapters. The PCIe specification supports two reference clock architectures: a common reference clock architecture and an independent reference clock architecture. In the independent reference clock architecture, both the transmitting and receiving ends have their own independent 100MHz local reference clock. In PCIe communication, jitter refers to the variation or fluctuation of the clock signal relative to its ideal position. Frequency jitter can be categorized into several types, including random, periodic, and deterministic frequency jitter. Frequency jitter directly affects signal quality and system performance. When there is a frequency jitter difference between the 100MHz local clocks at both ends, the clock after being multiplied by the internal PLL (Phase-Locked Loop) will also have a frequency jitter difference.
[0045] In existing co-referenced clock schemes, the device uses a 100MHz SSC (Spread Spectrum Clocking) signal provided by the host as the reference clock input for the PLL (Phase-Locked Loop) to achieve clock synchronization between the device and the host. However, this method increases hardware overhead and may lead to compatibility issues between different host systems.
[0046] In SSC (Spread Spectrum Clocking) communication, the data clock is modulated at a low frequency (such as a triangular wave of 30kHz-33kHz) to reduce electromagnetic interference (EMI). This modulation causes the frequency and phase of the clock signal to change constantly, so a mechanism is needed to ensure that the receiving device can accurately follow these changes.
[0047] This invention provides a calibration system and method for frequency offset of a serial communication interface, relating to the field of serial communication technology. It can be specifically applied to solve the technical problems of poor compatibility and additional hardware costs and complexity associated with co-source reference clock schemes. This invention utilizes CDR (Clock Data Recovery) to detect SSC frequency offset and calculate the PLL frequency modulation coefficient, effectively synchronizing the clock signals of the device and the host while reducing hardware overhead and improving compatibility. Detailed descriptions are provided below through specific embodiments.
[0048] Please see Figure 1In one embodiment of the present invention, a serial communication interface frequency offset calibration system may include an analog front-end module 110, a signal comparison module 120, a frequency offset coefficient generation module 130, and a phase-locked loop module 140. This calibration system can be applied to a device 100 that is communicatively connected to a host 200. The analog front-end module 110 is electrically connected to the host 200 and can receive data signals transmitted by the host 200, extracting corresponding data center information and data edge information from the data signals. The signal comparison module 120 is electrically connected to the analog front-end module 110 and can compare the device 100's internal clock signal with the data edge information to generate phase adjustment information and frequency offset information, and can adjust the phase of the internal clock signal according to the phase adjustment information. The frequency offset coefficient generation module 130 is electrically connected to the signal comparison module 120 and can calculate the frequency offset information based on a preset modulation coefficient to generate a frequency offset modulation coefficient. The phase-locked loop module 140 is electrically connected between the signal comparison module 120 and the frequency offset coefficient generation module 130, and can be used to adjust the frequency of the internal clock signal of the device according to the phase adjustment information and the frequency offset modulation coefficient.
[0049] In one embodiment of the present invention, in a signal processing or communication system, the analog front-end module 110 is responsible for capturing analog signals from various sensors, devices, or other signal sources. The analog front-end module 110 integrates an analog-to-digital converter (ADC) to convert the acquired analog signals into digital signals or to preprocess the analog signals for subsequent digital processing. In this embodiment, the data signal output by the host 200 is an analog signal. The analog front-end module 110 is the starting point for processing the data signal sent by the host 200. It first performs analog-to-digital conversion on the data signal sent by the host 200, and then extracts the corresponding data center information and data edge information from the converted data signal. The data center information refers to the valid value of the data, i.e., the actual value of the data bits (0 or 1). The data edge information refers to the time point of the rising or falling edge of the data signal. The data edge information is crucial for recovering the clock signal, as it provides the time of data change.
[0050] In one embodiment of the present invention, the signal comparison module 120 compares the phase of the internal clock signal of the device 100 with the data edge information to generate phase adjustment information and frequency offset information. The phase adjustment information is obtained by measuring the phase difference between the data edge information and the internal clock signal to determine whether the internal clock signal needs to be adjusted to better align with the data signal. The frequency offset information is obtained by statistically analyzing the phase difference over a period of time to estimate the average frequency deviation between the clock signal of the data signal and the internal clock signal. This deviation can be represented by a coefficient for subsequent frequency adjustment.
[0051] Please see Figure 2 In one embodiment of the present invention, the signal comparison module 120 may include a phase detector 121, a second-order low-pass filter 122, and a phase interpolator 123. The phase detector 121 is electrically connected to the analog front-end module 110. The second-order low-pass filter 122 is electrically connected to the phase detector 121. The phase interpolator 123 is electrically connected between the second-order low-pass filter 122 and the phase detector 121. The phase detector 121 can be used to detect the phase difference between two signals. Specifically, the phase detector 121 is used to detect the phase difference between the clock signal (i.e., data edge information) in the data signal sent by the host 200 and the clock signal output by the phase interpolator 123, thereby generating error information. The second-order low-pass filter 122 is an electronic filter that allows signals below the cutoff frequency to pass through, while signals above the cutoff frequency are attenuated or blocked. In signal processing, the second-order low-pass filter 122 can be used to remove noise, smooth signals, etc. In this embodiment, the second-order low-pass filter 122 receives error information from the phase detector 121 and generates phase adjustment information and frequency offset information based on the error information. The phase interpolator 123 can be used to adjust the phase of the internal clock signal according to the phase adjustment information and send the adjusted internal clock signal to the phase detector 121.
[0052] In one embodiment of the present invention, a voltage-controlled oscillator (VCO) is provided within the phase-locked loop module 140. A VCO is an oscillation circuit whose output frequency corresponds to the input control voltage. Its operating state or the component parameters of the oscillation circuit are controlled by the input control voltage, thereby changing the output frequency. The VCO is used to generate the internal clock signal of the device 100. In this embodiment, a phase interpolator 123 is also electrically connected to the VCO. The phase interpolator 123 obtains the internal clock signal of the device 100 from the VCO and, based on phase adjustment information, aligns the clock edge of the internal clock signal with the center point of the clock signal in the data signal.
[0053] In one embodiment of the present invention, the second-order low-pass filter 122 includes a proportional path and an integral path. The proportional path processes the phase information of the signal, generating phase adjustment information based on the amplitude of the phase error. In this embodiment, the proportional path directly amplifies the input error signal proportionally, rapidly responding to phase changes and ensuring that the sampling clock can quickly follow the phase changes of the data center. The integral path processes frequency deviation, generating frequency offset information based on the accumulation of phase error information over time. In this embodiment, when there is a frequency mismatch between the host 200 and the device, the integral path gradually adjusts the device's clock frequency by accumulating the error signal to achieve long-term stable synchronization. The processing mechanism of the integral path ensures that even small frequency deviations can be compensated for through time accumulation.
[0054] In one embodiment of the present invention, when the integration path uses a 16-bit integration path accumulator, its output frequency offset information can be represented as tlf. i (15:0). Furthermore, the output of the integral path is converted into a proportional value between 0 and 1. This proportional value can be expressed as:
[0055]
[0056] In one embodiment of the present invention, the frequency offset coefficient generation module 130 is used to generate a frequency offset modulation coefficient based on the frequency offset coefficient. The frequency offset modulation coefficient is used to indicate how the phase-locked loop module 140 adjusts its output frequency to compensate for the detected frequency offset. The frequency offset modulation coefficient can be expressed as:
[0057]
[0058] Among them, f vco This indicates the output frequency of the voltage-controlled oscillator (VCO), i.e., the target frequency, f. ref Indicates the reference clock frequency, 2 23 The floor() function is used as a scaling factor in frequency division or multiplication calculations, rounding down, and the dec2hex() function is used to convert the calculation result to hexadecimal representation. In this embodiment, This represents the proportion of frequency deviation of the integration path. The integration path accumulator is 16 bits. k represents the modulation coefficient and represents the proportion of the deviation between the device's clock frequency and the host 200's SSC signal frequency.
[0059] In one embodiment of the present invention, the phase-locked loop module 140 is used to adjust the internal clock signal of the device 100 according to the frequency offset modulation coefficient. Specifically, the phase-locked loop module 140 controls the frequency offset of the voltage-controlled oscillator output signal according to the frequency offset modulation coefficient. By adjusting the frequency offset modulation coefficient, precise control of the clock signal frequency can be achieved.
[0060] Furthermore, in one embodiment of the present invention, the phase-locked loop module 140 can also precisely control the phase of the voltage-controlled oscillator (VCO) output signal according to the phase adjustment information, so that it remains synchronized with the phase of the reference signal or changes in a predetermined manner. This helps to reduce the phase error of the clock signal and improve the stability and synchronization of the system.
[0061] Please see Figure 3 In one embodiment of the present invention, the serial communication interface frequency offset calibration system of the present invention is applied at the device end. The first frequency curve 301 is the triangular wave SSC frequency output by the analog host, with a center frequency of 2.5 GHz and a spread spectrum range of ±6.25 MHz. The second frequency curve 302 is the device modulation frequency. Figure 3 As shown, the frequency output by the phase-locked loop module 140 of the device can keep up with the triangular wave SSC frequency modulation of the host in real time.
[0062] Please see Figure 4 The maximum frequency difference between the second frequency curve 302 and the first frequency curve 301 is -666.6kHz and 491kHz, respectively. Converting these frequency differences to frequency offsets, they are -266ppm and 196ppm. This demonstrates that excellent frequency tracking can be achieved without relying on a 100MHz clock from the host as a reference clock, saving hardware overhead. Furthermore, for the M.2 protocol, complex power-on sequences can be eliminated. As soon as the host powers on the device, it can automatically power on and lock the PLL module, saving initialization time and avoiding compatibility issues between different hosts.
[0063] In one embodiment of the present invention, if the relevant interface product does not explicitly indicate the use of a 100MHz host reference clock in its datasheet, or if, when using a 100MHz reference clock, the TX signal appears before the reset signal (PERST) by capturing the online transmission (TX) waveform, then it can be roughly determined that the product adopts the technical solution of the present invention.
[0064] Please see Figure 5 The present invention also provides a calibration method for the frequency offset of a serial communication interface, applicable to the calibration system for the frequency offset of a serial communication interface in any of the above embodiments, and may include the following steps:
[0065] Step S100: Receive the data signal sent by the host and extract the corresponding data edge information. The data edge information represents the time point of the rising or falling edge of the data signal.
[0066] Step S200: Compare and process the internal clock signal of the device with the data edge information to generate frequency offset information;
[0067] Step S300: Based on the preset modulation coefficients, calculate and process the frequency offset information to generate frequency offset modulation coefficients;
[0068] Step S400: Adjust the frequency of the internal clock signal according to the frequency offset modulation coefficient.
[0069] In one embodiment of the present invention, when step S100 is executed, that is, the data signal sent by the host is received and the corresponding data edge information is extracted. The data edge information represents the time point of the rising or falling edge of the data signal. Specifically, the data signal sent by the host 200 is first converted from analog to digital, and then the corresponding data center information and data edge information are extracted from the converted data signal. The data center information refers to the valid value of the data, that is, the actual value of the data bits (0 or 1). The data edge information refers to the time point of the rising or falling edge of the data signal.
[0070] In one embodiment of the present invention, when step S200 is executed, the internal clock signal of the device is compared with the data edge information to generate frequency offset information. Specifically, this may include the following steps:
[0071] Step S210: Compare the phase error between the device's internal clock signal and the data edge information to generate phase error information;
[0072] Step S220: Generate phase adjustment information and frequency offset information based on the phase error information;
[0073] Step S230: Adjust the phase of the internal clock signal according to the phase adjustment information.
[0074] In one embodiment of the present invention, when step S210 is executed, phase error information is generated by comparing the phase error between the internal clock signal of the device and the data edge information. Specifically, the phase difference between the clock signal (i.e., data edge information) in the data signal sent by the host 200 and the clock signal output by the phase interpolator 123 is compared to generate error information.
[0075] In one embodiment of the present invention, when step S220 is executed, phase adjustment information and frequency offset information are generated based on the phase error information. Specifically, this may include the following steps:
[0076] Step S221: Generate phase adjustment information based on the amplitude of the phase error information;
[0077] Step S222: Generate frequency offset information based on the accumulation of phase error information over time.
[0078] In one embodiment of the present invention, when steps S221 to S222 are executed, specifically, the second-order low-pass filter 122 is provided with a proportional path and an integral path. The proportional path can be used to process the phase information of the signal, and it can generate phase adjustment information based on the amplitude of the phase error information. In this embodiment, the proportional path directly amplifies the input error signal proportionally, quickly responding to phase changes and ensuring that the sampling clock can rapidly follow the phase changes of the data center. The integral path can be used to process frequency deviation, and it can generate frequency deviation information based on the accumulation of phase error information over time. In this embodiment, when there is a frequency mismatch between the host 200 and the device, the integral path gradually adjusts the clock frequency of the device by accumulating the error signal to achieve long-term stable synchronization. The processing mechanism of the integral path ensures that even small frequency deviations can be compensated for through time accumulation.
[0079] In one embodiment of the present invention, when step S230 is executed, the internal clock signal is phase-adjusted according to the phase adjustment information. Specifically, the internal clock signal is phase-adjusted according to the phase adjustment information, and the adjusted internal clock signal is sent to the phase detector 121.
[0080] In one embodiment of the present invention, when step S300 is executed, the frequency offset information is calculated and processed based on the preset modulation coefficients to generate frequency offset modulation coefficients. Specifically, when the integration path uses a 16-bit integration path accumulator, its output frequency offset information can be represented as tlf. i (15:0). Convert the output of the integral path to a proportional value between 0 and 1. This proportional value can be expressed as:
[0081]
[0082] In this embodiment, frequency offset information is calculated and processed based on preset modulation coefficients to generate frequency offset modulation coefficients. The frequency offset modulation coefficients indicate how to adjust the output frequency to compensate for the detected frequency offset. The frequency offset modulation coefficients can be expressed as:
[0083]
[0084] Among them, f vco This indicates the output frequency of the voltage-controlled oscillator (VCO), i.e., the target frequency, f.ref This represents the reference clock frequency, i.e., the clock signal contained in the data signal output by the host. 23 The `floor()` function is used as a scaling factor to round down, and the `dec2hex()` function is used to convert the calculation result to hexadecimal representation. In this embodiment, The value represents the proportion of frequency deviation of the integration path, k represents the preset modulation coefficient, and represents the deviation ratio between the clock frequency of the device and the SSC signal frequency of the host 200 at this time.
[0085] In one embodiment of the present invention, when step S400 is executed, the frequency of the internal clock signal is adjusted according to the frequency offset modulation coefficient. Specifically, the frequency offset of the output signal of the voltage-controlled oscillator (VCO) is controlled according to the frequency offset modulation coefficient. By adjusting the frequency offset modulation coefficient, precise control of the clock signal frequency can be achieved.
[0086] Furthermore, in one embodiment of the present invention, the phase of the voltage-controlled oscillator output signal can also be precisely controlled according to the phase adjustment information, so that it remains synchronized with the phase of the reference signal or changes in a predetermined manner. This helps to reduce the phase error of the clock signal and improve the stability and synchronization of the system.
[0087] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and application structures according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.
[0088] The modules described in the embodiments of the present invention can be implemented in software or hardware, and can also be located in a processor. The names of these modules do not necessarily limit the module itself.
[0089] In summary, this invention provides a calibration system and method for frequency offset of a serial communication interface, which solves the technical problems of poor compatibility and increased hardware cost and complexity associated with existing co-source reference clock schemes. This invention generates frequency modulation coefficients by calculating the output of the integrator channel in the signal comparison module, and modulates the frequency of the phase-locked loop module accordingly. This enables the internal clock signal of the device to follow the frequency offset of the host's SSC clock signal in real time, eliminating the dependence on the host's 100MHz reference clock in PCIe communication, saving hardware overhead, and improving device compatibility.
[0090] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A calibration system for frequency offset of a serial communication interface, characterized in that, Applied in devices that are serially connected to a host, including: The analog front-end module is used to receive the SSC data signal sent by the host and extract the corresponding data edge information, wherein the data edge information represents the time point of the rising edge or falling edge of the SSC data signal. The signal comparison module is used to compare the device's internal clock signal with the data edge information, generate phase error information for phase adjustment, and generate frequency offset information representing the relationship between the clock signal of the SSC data and the device clock signal based on the integral of the phase error information over time. The frequency offset coefficient generation module is used to calculate and process the frequency offset information based on a preset modulation coefficient to generate a frequency offset modulation coefficient. A phase-locked loop module is used to adjust the frequency of the internal clock signal according to the frequency offset modulation coefficient.
2. The calibration system for frequency offset of a serial communication interface according to claim 1, characterized in that, The phase-locked loop module is equipped with a voltage-controlled oscillator (VCO), which is used to generate the internal clock signal.
3. The serial communication interface frequency offset calibration system according to claim 1, characterized in that, The signal comparison module includes: A phase detector is used to compare the phase error between the device's internal clock signal and the data edge information to generate phase error information; A second-order low-pass filter is used to integrate the phase error information to generate frequency offset information.
4. The serial communication interface frequency offset calibration system according to claim 3, characterized in that, The signal comparison module also includes a phase interpolator, which is used to adjust the phase of the internal clock signal.
5. The serial communication interface frequency offset calibration system according to claim 4, characterized in that, The second-order low-pass filter is also used to generate phase adjustment information based on the phase error information, and the phase interpolator is also used to adjust the phase of the internal clock signal based on the phase adjustment information and send the adjusted internal clock signal to the phase detector.
6. The serial communication interface frequency offset calibration system according to claim 3, characterized in that, The second-order low-pass filter has a proportional path and an integral path. The proportional path is used to generate phase adjustment information based on the amplitude of the phase error information, and the integral path is used to generate frequency offset information based on the integral of the phase error information over time.
7. The serial communication interface frequency offset calibration system according to claim 6, characterized in that, The integration path is a 16-bit integration path accumulator.
8. The serial communication interface frequency offset calibration system according to claim 7, characterized in that, The frequency offset modulation coefficient is expressed as: in, This indicates the frequency of the internal clock signal. This indicates the clock frequency of the data signal. Scaling factor The function is used to round down. The function is used to convert the calculation result into a hexadecimal representation. The value represents the proportion of the frequency offset information, and k represents the preset modulation coefficient.
9. A method for calibrating the frequency offset of a serial communication interface, characterized in that, include: The system receives SSC data signals sent by the host and extracts the corresponding data edge information, wherein the data edge information represents the time point of the rising or falling edge of the SSC data signal. The device's internal clock signal is compared with the data edge information to generate phase error information for phase adjustment. Based on the integral of the phase error information over time, frequency offset information representing the SSC data's clock signal and the device's clock signal is generated. Based on the preset modulation coefficients, the frequency offset information is calculated and processed to generate frequency offset modulation coefficients; The frequency of the internal clock signal is adjusted according to the frequency offset modulation coefficient.
10. The calibration method for frequency offset of a serial communication interface according to claim 9, characterized in that, The step of comparing the device's internal clock signal with the data edge information to generate frequency offset information includes: The phase error between the device's internal clock signal and the data edge information is compared to generate phase error information; Based on the phase error information, phase adjustment information and frequency offset information are generated; The internal clock signal is phase-adjusted according to the phase adjustment information.