Universal serial bus type-c connector chip, test system, and method of calibrating a universal serial bus type-c connector chip

Abstract

The present disclosure relates to a USB-C connector chip, a test system, and a calibration method of a USB-C connector chip. The present disclosure provides a USB-C connector chip, a test system, and a calibration method of a USB-C connector chip. The USB-C connector chip comprises a judgment circuit and a calibration control circuit. The judgment circuit is used to judge whether a detection voltage on a detection pin of the USB-C connector chip reaches a threshold voltage. In a first calibration stage, the calibration control circuit sets the detection voltage to a first DC level to obtain a first calibration value of the threshold voltage. In a second calibration stage, the calibration control circuit sets the detection voltage to a second DC level to obtain a second calibration value of the threshold voltage. In particular, the calibration control circuit determines a final calibration value of the threshold voltage according to the first calibration value and the second calibration value.

Description

Technical Field

[0001] This invention relates to a Universal Serial Bus (USB) Type-C connector, and more particularly to a USB-C connector chip, a testing system, and a calibration method for the USB-C connector chip. Background Technology

[0002] The Universal Serial Bus (USB-C) connector determines the orientation of the USB-C connection by detecting the voltage levels of the configuration channel (CC) and VBUS (Voltage Bus) pins, enabling functions such as charging and data transfer. Different voltage level detection results correspond to different application scenarios, especially given the wide variety of USB-C applications. For example, different voltage levels connected to the CC pin represent different power supply capabilities of the USB-C connector's source, and different charging wattages of USB Power Delivery (USB-PD) correspond to different VBUS pin voltages. Therefore, numerous comparators and corresponding threshold voltages are required to detect these voltage levels. Furthermore, during chip mass production, a calibration process is necessary to ensure the accuracy of these voltage level detections.

[0003] Some related technologies can use additional high-precision circuitry or automatic calibration circuitry to accurately monitor the threshold voltages involved in the aforementioned detection, ensuring detection accuracy. During chip manufacturing, system designers can impose stringent requirements on the chip's process technology to ensure that differences in characteristics at different locations on the wafer are within tolerable limits. However, the above solutions significantly increase design complexity and cost. Therefore, a novel architecture and related methods are needed to calibrate the voltage detection of USB-C connectors without or with minimal side effects. Summary of the Invention

[0004] The purpose of this invention is to provide a Universal Serial Bus (USB) Type-C connector chip, a testing system, and a calibration method for the USB Type-C connector chip, so as to solve the problems of related technologies with little or no side effects.

[0005] At least one embodiment of the present invention provides a Universal Serial Bus (USB) Type-C connector chip. The USB Type-C connector chip includes a judgment circuit and a correction control circuit, wherein the correction control circuit is coupled to the judgment circuit. The judgment circuit is used to determine whether a detected voltage on a first input terminal of the judgment circuit reaches a threshold voltage on a second input terminal of the judgment circuit to generate a judgment signal, wherein the first input terminal is coupled to a detection pin of the USB Type-C connector chip. The correction control circuit is used to correct the threshold voltage transmitted to the second input terminal. In a first correction stage, the correction control circuit sets the detected voltage to a first DC level, sequentially sets the threshold voltage to a plurality of candidate correction levels to obtain a plurality of first judgment results of the judgment signal, and selects a first correction level from the plurality of candidate correction levels based on the plurality of first judgment results. In a second correction stage, the correction control circuit sets the detected voltage to a second DC level and sequentially sets the threshold voltage to the plurality of candidate correction levels to obtain a plurality of second judgment results of the judgment signal, and selects a second correction level from the plurality of candidate correction levels based on the plurality of second judgment results. Furthermore, the correction control circuit determines a final correction level for the threshold voltage based on the first correction level and the second correction level.

[0006] At least one embodiment of the present invention provides a test system. The test system includes a test circuit, a Universal Serial Bus (USB) Type-C connector chip, and a digital-to-analog converter (DTC) circuit. The USB Type-C connector chip is coupled to the test circuit, and the DTC circuit is coupled to the USB Type-C connector chip. The USB Type-C connector chip includes a judgment circuit and a calibration control circuit, wherein the calibration control circuit is coupled to the judgment circuit. The test circuit is used to transmit a test command. The judgment circuit is used to determine whether a detected voltage at a first input terminal of the judgment circuit reaches a threshold voltage at a second input terminal of the judgment circuit to generate a judgment signal, wherein the first input terminal is coupled to a detection pin of the USB Type-C connector chip. The calibration control circuit is used to calibrate the threshold voltage transmitted to the second input terminal according to the test command. The DTC circuit is used to output the detected voltage to the detection pin of the USB Type-C connector chip. In a first correction stage, the correction control circuit controls the digital-to-analog converter circuit to output a detection voltage having a first DC level, sequentially sets the threshold voltage to a plurality of candidate correction levels to obtain a plurality of first judgment results of the judgment signal, and selects a first correction level from the plurality of candidate correction levels based on the plurality of first judgment results. In a second correction stage, the correction control circuit controls the digital-to-analog converter circuit to output a detection voltage having a second DC level, sequentially sets the threshold voltage to the plurality of candidate correction levels to obtain a plurality of second judgment results of the judgment signal, and selects a second correction level from the plurality of candidate correction levels based on the plurality of second judgment results. Furthermore, the correction control circuit determines a final correction level for the threshold voltage based on the first correction level and the second correction level.

[0007] At least one embodiment of the present invention provides a calibration method for a Universal Serial Bus Type-C connector chip. The calibration method includes: in a first calibration stage, setting a detection voltage on a first input terminal of a judgment circuit to a first DC level; in the first calibration stage, sequentially setting a threshold voltage on a second input terminal of the judgment circuit to a plurality of candidate calibration levels; in the first calibration stage, using the judgment circuit to sequentially determine whether the plurality of candidate calibration levels reach the first DC level, thereby generating a plurality of first judgment results of a judgment signal; in the first calibration stage, selecting a first calibration level from the plurality of candidate calibration levels based on the plurality of first judgment results; and in a second calibration stage, the judgment signal is... The detected voltage at the first input terminal of the circuit is set to a second DC level; in the second correction stage, the threshold voltage at the second input terminal of the judgment circuit is sequentially set to the plurality of candidate correction levels; in the second correction stage, the judgment circuit sequentially judges whether the plurality of candidate correction levels have reached the second DC level to generate a plurality of second judgment results of the judgment signal; in the second correction stage, a second correction level is selected from the plurality of candidate correction levels based on the plurality of second judgment results; and a final correction level of the threshold voltage is determined based on the first correction level and the second correction level.

[0008] The universal serial bus C-type connector chip, testing system, and calibration method provided in the embodiments of the present invention obtain two calibration values ​​at two levels of the detected voltage, and determine which calibration value is closer to the target value by comparing these two calibration values, thereby improving calibration accuracy. Furthermore, the embodiments of the present invention do not significantly increase additional costs. Therefore, the present invention can complete threshold voltage calibration without or with minimal side effects. Attached Figure Description

[0009] Figure 1 This is a schematic diagram showing the source device and the drain device connected to each other via a cable according to an embodiment of the present invention.

[0010] Figure 2 This is a schematic diagram of a test system for testing Universal Serial Bus C-type connector chips according to an embodiment of the present invention.

[0011] Figure 3 This is a schematic diagram of the correction level for determining the threshold voltage according to an embodiment of the present invention.

[0012] Figure 4 This is a schematic diagram illustrating the workflow of a calibration method for a universal serial bus C-type connector chip according to an embodiment of the present invention.

[0013] Figure 5 According to an embodiment of the present invention Figure 4An example of the correction method is shown. Detailed Implementation

[0014] Figure 1This is a schematic diagram illustrating the interconnection of a source device 110 and a drain device 120 according to an embodiment of the present invention via a cable 100. The cable 100 may be a Universal Serial Bus (USB) Type-C cable (USB-C for short), and each of the source device 110 and the drain device 120 may have a USB-C connector to allow interconnection between them via USB-C. The configuration channel (CC) pins CC1 and CC2 of the source device 110 are coupled to resistors Rp1 and Rp2, respectively, while the configuration channel pins CC1 and CC2 of the drain device 120 are coupled to resistors Rd1 and Rd2, respectively. When the source device 110 and the drain device 120 are interconnected via cable 100, one of the configuration channel pins CC1 and CC2 of the source device 110 can be connected to one of the configuration channel pins CC1 and CC2 of the drain device 120 via cable 100, while the other is coupled to the resistor Ra of cable 100. Similarly, one of the configuration channel pins CC1 and CC2 of the drain device 110 can be connected to one of the configuration channel pins CC1 and CC2 of the source device 120 via cable 100, while the other is coupled to the resistor Ra of cable 100. Therefore, different voltage division results can represent different connection states. The source monitor 110M in the source device 110 can determine the current connection state (e.g., whether it is connected, whether it is reversed, the functions supported by the source device 120, etc.) by detecting the voltage levels of the configuration channel pins CC1 and CC2 of the source device 110. The source monitor 120M in the source device 120 can determine the current connection state (e.g., whether it is connected, whether it is reversed, the functions supported by the source device 120, etc.) by detecting the voltage levels of the configuration channel pins CC1 and CC2 of the source device 120. Since different connection states and usage scenarios can correspond to different voltage levels for each of the configuration channel pins CC1 and CC2, each of the source-side monitor 110M and the drain-side monitor 120M needs to include multiple judgment circuits (e.g., comparators). These judgment circuits can determine the voltage level of each of the configuration channel pins CC1 and CC2 based on different threshold voltages (e.g., 0.2V, 0.4V, 0.66V, 0.8V, 1.23V, 1.6V, and 2.6V). Furthermore, the voltage bus (VBUS) pins of each of the source-side device 110 and the drain-side device 120 can also have different voltage levels to support different power supply modes. Therefore, each of the source-side monitor 110M and the drain-side monitor 120M also has corresponding judgment circuits to determine whether the voltage level of the voltage bus pin has reached a specific level.After the source device 110 and the drain device 120 complete the USB-C connection, they must continue to monitor the configuration channel pins CC1 or CC2 and the voltage levels of the VBUS pins. For example, these voltage levels can be continuously monitored to enable USB Power Delivery (USB-PD) signal communication between the source device 110 and the drain device 120 on the configuration channel pins CC1 or CC2, allowing for higher power delivery on the VBUS pins. Alternatively, these voltage levels can be continuously monitored to detect disconnections and promptly remove the voltage on the VBUS pins in response to disconnection events.

[0015] As mentioned above, each of the source-side monitor 110M and the drain-side monitor 120M needs to have a large number of judgment circuits to deal with multiple connection states and usage scenarios. The accuracy requirements of the threshold voltages corresponding to each judgment circuit are quite high, so a corresponding correction mechanism is needed to correct these threshold voltages.

[0016] Figure 2 This is a schematic diagram of a test system 10 for testing a USB-C connector chip 220 according to an embodiment of the present invention. The test system 10 may include a test bench 20, a test circuit 210, a USB-C connector chip 220, and a digital-to-analog converter (DAC) circuit 230 (e.g., a high-precision DAC circuit disposed externally to the USB-C connector chip 220). Figure 2 As shown, the USB-C connector chip 220 is coupled to the test circuit 210 via an inter-integrated circuit (I2C) interface, and the DAC circuit 230 is coupled to the USB-C connector chip 220 via an I2C interface. In this embodiment, the test circuit 210, the USB-C connector chip 220, and the DAC circuit 230 can be mounted on the test board 200, and the test equipment 20 can transmit input / output (IO) signals to components on the test board 200 (e.g., the test circuit 210) via the input / output interface of the test board 200. In one embodiment, the test circuit 210 can be implemented by a field-programmable gate array (FPGA), but the invention is not limited thereto.

[0017] For example, the test equipment 20 can control a robotic arm to place a device under test (DUT), such as a USB-C connector chip 220, onto the test board 200, and control the test circuit 210 to begin executing the test process via I / O signals. The test circuit 210 can progressively execute multiple test / calibration operations, which may include calibration of the judgment circuit. Figure 2 As shown, the USB-C connector chip 220 may include a judgment circuit 222 and a calibration control circuit 221, wherein the calibration control circuit 221 is coupled to the judgment circuit 222. In this embodiment, the judgment circuit 222 may be implemented by a comparator. In this embodiment, the calibration control circuit 221 may include a processing circuit 221P and a storage device 221M, wherein the processing circuit 221P may execute the operation of the calibration control circuit 221 (e.g., calibration of the judgment circuit 222) according to the program code 221C (e.g., firmware) in the storage device 221M. In this embodiment, the test circuit 210 is used to transmit a test command (e.g., a test command corresponding to the calibration of the judgment circuit 222). Specifically, the judgment circuit 222 is used to determine the detected voltage V on the first input terminal (e.g., the terminal marked "+") of the judgment circuit 222. CCPIN Whether the threshold voltage V on the second input terminal (e.g., the terminal marked "-") of the determination circuit 222 has been reached TH To generate judgment signal D COMP The first input terminal of the judgment circuit 222 is coupled to a detection pin of the USB-C connector chip 220 (e.g., the channel pin CC1 or CC2, or the voltage bus pin, as described above), and the correction control circuit 221 is used to correct the threshold voltage V transmitted to the second input terminal of the judgment circuit 222 according to the test command. TH Additionally, the DAC circuit 230 is used to output a DC voltage, such as the detection voltage V. CCPIN The detection pins of the USB-C connector chip 220.

[0018] In the first calibration stage, the calibration control circuit 221 can detect the voltage V CCPIN Set to a first DC level (e.g., control the DAC circuit 230 to output a detection voltage V having the first DC level). CCPIN ), and the threshold voltage V TH Sequentially set to multiple candidate correction levels to obtain the judgment signal D COMP The correction control circuit 221 can select a first correction level from the multiple candidate correction levels based on the multiple first judgment results. In a second correction stage, the correction control circuit 221 can detect the voltage V. CCPINSet to a second DC level (e.g., control the DAC circuit 230 to output a detection voltage V with that second DC level). CCPIN ), and the threshold voltage V TH The multiple candidate correction levels are sequentially set to obtain the judgment signal D. COMP The correction control circuit 221 can select a second correction level from the plurality of candidate correction levels based on the plurality of second judgment results. Specifically, the correction control circuit 221 can determine the threshold voltage V based on the first correction level and the second correction level. TH The final calibration standard.

[0019] Figure 3 According to an embodiment of the present invention, the threshold voltage V is determined. TH The diagram shows the calibration levels, where calibration levels n-1, n, n+1, and n+2 can represent the threshold voltage V. TH The four consecutive correction levels, and these four correction levels can each correspond to any four consecutive correction levels from the plurality of candidate correction levels. In this embodiment, the plurality of candidate correction levels are spaced at fixed voltage differences ΔV, while Figure 3 The horizontal axis is divided into units equal to half the voltage difference ΔV (i.e., ΔV / 2). In this embodiment, the correction levels corresponding to correction gears n-1, n, n+1, and n+2 are arranged from low to high. It should be noted that when the voltage level of the first input terminal of the judgment circuit 222 is lower than the voltage level of the second input terminal of the judgment circuit 222 (e.g., V...), the correction level will be lower than the voltage level of the second input terminal of the judgment circuit 222. CCPIN <V TH The judgment signal DCOMP output by the judgment circuit 222 can have a logic value of "0". When the voltage level of the first input terminal of the judgment circuit 222 is higher than the voltage level of the second input terminal of the judgment circuit 222 (e.g., V...), CCPIN >V TH The judgment signal D output by the judgment circuit 222 is determined. COMP It can have a logic value of "1". In this embodiment, it is assumed that the correction control circuit 221 sets the correction levels sequentially to n-1, n, n+1, and n+2 so that the threshold voltage V TH Gradually increase, if the threshold voltage V TH The judgment signal D is triggered when switching from a certain calibration gear (e.g., calibration gear n) to the next calibration gear (e.g., calibration gear n+1). COMP When the logic value changes from "1" to "0", the correction control circuit 221 can record the correction level n as the selected correction level. Therefore, when the threshold voltage V THWhen the first correction level (e.g., the candidate correction level corresponding to the correction level value1 selected in the first correction stage) changes to the next candidate correction level of the first correction level, the judgment signal D is determined. COMP The logic value changes from "1" to "0". Similarly, when the threshold voltage V... TH When the second correction level (e.g., the candidate correction level corresponding to the correction level value2 selected in the first correction stage) changes to the next candidate correction level of the second correction level, the judgment signal D is determined. COMP Change from logical value "1" to logical value "0".

[0020] When the correction control circuit 221 selects the candidate correction level corresponding to the correction level n as the first correction level in the first correction stage, it indicates that the target voltage (i.e., the detection voltage V output by the DAC circuit 230 in the first correction stage) is... CCPIN The candidate correction level falls within the correction range n and the candidate correction level (n+1) (i.e., falls within the interval P1 or P2). In this second correction stage, the detection voltage V output by the DAC circuit 230... CCPIN An increment of ΔV / 2 can be added, indicating that the voltage difference between the first DC level and the second DC level is equal to half the voltage difference between any two consecutive candidate correction levels (i.e., ΔV / 2). If the candidate correction level corresponding to correction level n is closer to the target voltage than the candidate correction level corresponding to correction level n+1, it means that the target voltage falls within interval P1, and the second DC level can fall within interval P2, making the correction level value2 selected in the second correction stage correction level n. If the candidate correction level corresponding to correction level n+1 is closer to the target voltage than the candidate correction level corresponding to correction level n, it means that the target voltage falls within interval P2, and the second DC level can fall within interval P3, making the correction level value2 selected in the second correction stage correction level n+1. Therefore, when the first correction level is equal to the second correction level (e.g., correction gear value1 equals correction gear value2), the correction control circuit 221 can select the first correction level (e.g., the correction level corresponding to correction gear value1) as the final correction level. When the second DC level is greater than the first DC level (e.g., the second DC level is equal to the first DC level plus ΔV / 2) and the second correction level is greater than the first correction level (e.g., the correction level corresponding to correction gear value2 is greater than the correction level of correction gear value1), the correction control circuit 221 can select the second correction level (e.g., the correction level corresponding to correction gear value2) as the final correction level.

[0021] In some embodiments, the correction control circuit 221 can gradually switch the correction level from a high correction level to a low correction level, for example, by sequentially setting the correction levels to n+2, n+1, n, and n-1 so that the threshold voltage V TH Gradually decrease, if the threshold voltage V TH The judgment signal D is triggered when switching from a certain calibration gear (e.g., calibration gear n) to the next calibration gear (e.g., calibration gear n-1). COMP When the logic value changes from "0" to "1", the correction control circuit 221 can record the correction level n as the selected correction level. In this case, the correction control circuit 221 can control the DAC circuit 230 to set the second DC level to the first DC level minus ΔV / 2. Therefore, when the first correction level is equal to the second correction level (e.g., correction level value1 is equal to correction level value2), the correction control circuit 221 can select the first correction level (e.g., the correction level corresponding to correction level value1) as the final correction level. When the second DC level is less than the first DC level (e.g., the second DC level is equal to the first DC level minus ΔV / 2) and the second correction level is less than the first correction level (e.g., the correction level corresponding to correction level value2 is less than the correction level of correction level value1), the correction control circuit 221 can select the second correction level (e.g., the correction level corresponding to correction level value2) as the final correction level.

[0022] Table 1

[0023]

[0024]

[0025] Table 1 shows the threshold voltage V. TH Examples of these multiple candidate correction levels, where the threshold voltage V TH It can have multiple calibration levels such as #0, #1, #2, #3, #4, #5, #6, #7, #8, #9, #10, #11, #12, #13, #14, and #15, and these calibration levels can represent different values ​​in the judgment circuit's register. The calibration control circuit 221 can output the corresponding calibration level based on the values ​​stored in the judgment circuit's register. Specifically, the voltage difference between the calibration levels of any two consecutive calibration levels is fixed at 20mV. Assuming the judgment circuit 222 is used as a comparator with a threshold voltage of 1.23V, in practice, due to factors such as wafer size, doping concentration deviation, and process offset, the threshold voltage V received by the judgment circuit 222 on different chips will vary. THThey may not be exactly the same (for example, the same calibration range corresponds to different calibration levels), so a calibration mechanism is needed to find the calibration range that is closest to 1.23V from these calibration ranges.

[0026] In this embodiment, the correction control circuit 221 can control the DAC circuit 230 to output 1.23V and control the threshold voltage V. TH Gradually switch from a low correction level to a high correction level (e.g., from correction level #0 to correction level #15) to make the threshold voltage V... TH The bit preparation gradually increases. During this first correction phase, the correction control circuit 221 can control the DAC circuit 230 to output the first DC level, such as 1.23V, and the threshold voltage V. TH It can be gradually increased starting from 1.105V, where the threshold voltage V TH Self-calibration setting #6 (V) TH =1.225V) Switch to calibration setting #7 (V TH When the voltage is 1.245V, determine the signal D. COMP The logic value can be changed from "1" (1.23V > 1.225V) to "0" (1.23V < 1.245V), and the correction control circuit 221 can record the correction level corresponding to correction gear #6 as the first correction level. In the second correction stage, the correction control circuit 221 can control the DAC circuit 230 to output the second DC level, such as 1.24V (V... CCPIN =1.23V + (20mV) / 2), and threshold voltage V TH It can be gradually increased starting from 1.105V, where the threshold voltage V TH Self-calibration setting #6 (V) TH =1.225V) Switch to calibration setting #7 (V TH When the voltage is 1.245V, determine the signal D. COMP The logic value "1" (1.24V>1.225V) can be changed to the logic value "0" (1.24V<1.245V), and the correction control circuit 221 can record the correction level corresponding to the correction gear #6 as the second correction level.

[0027] As described above, the voltage difference between the first DC level (1.23V) and the second DC level (1.24V) is equal to half (10mV) of the voltage difference between any two consecutive candidate correction levels among the plurality of candidate correction levels. Therefore, when the first correction level is equal to the second correction level, it means that the first correction level is closer to the target voltage (i.e., 1.23V) than the second correction level. The correction control circuit 221 can select the first correction level as the final correction level and write the correction level #6 into the one-time programmable storage device for direct reading during subsequent operation.

[0028] Similarly, assuming the judgment circuit 222 is a comparator using 1.24V as a threshold, the correction control circuit 221 can record the correction level corresponding to correction level #6 as the first correction level in the first correction stage (DAC circuit 230 outputs 1.24V), and record the correction level corresponding to correction level #7 as the second correction level in the second correction stage (DAC circuit 230 outputs 1.25V). In this case, since the second DC level (1.25V) is greater than the first DC level (1.24V), when the second correction level is greater than the first correction level, it indicates that the second correction level is closer to the target voltage (i.e., the first DC level) than the first correction level. The correction control circuit 221 can select the second correction level as the final correction level. In this embodiment, the correction levels corresponding to the multiple correction levels in Table 1, such as #0 to #15, are theoretical values. In practice, the actual calibration level corresponding to each chip's calibration range may deviate from the theoretical value, so different chips may have different calibration levels. In some cases, when a specific calibration range (e.g., #0 or #15) of a chip exceeds the allowable range, that chip can be discarded. For example, if the calibration level corresponding to calibration range #0 of a chip is greater than 1.24V, that chip can be discarded directly. Similarly, if the calibration level corresponding to calibration range #15 of a chip is less than 1.24V, that chip can be discarded directly.

[0029] In some embodiments, the control threshold voltage V TH Gradually switch from a low correction level to a high correction level (e.g., from correction level #0 to correction level #15) to make the threshold voltage V... TH The voltage level is gradually increased, and the second DC level is set to the first DC level minus 10mV. Details regarding this setting can be deduced from the explanations in the preceding paragraphs, and will not be repeated here for the sake of brevity.

[0030] In some embodiments, the detection pin of the calibration control circuit 221 is a configuration channel pin, and multiple different levels of the detection voltage on the configuration channel pin correspond to multiple different connection states of the USB-C connector chip 220 (e.g., whether connected, reversible connection, functions supported by the mated device, etc.). In some embodiments, the detection pin of the calibration control circuit 221 is a voltage bus pin, and multiple different levels of the detection voltage on the voltage bus correspond to multiple different power supply states of the USB-C connector chip 220 (e.g., different levels of supply voltage).

[0031] Figure 4 This is a schematic diagram illustrating the workflow of a calibration method for a USB-C connector chip 220 (e.g., a determination circuit such as determination circuit 222) according to an embodiment of the present invention, wherein... Figure 4 The workflow can be provided by Figure 2 This is performed by the USB-C connector chip 220 shown (e.g., the calibration control circuit 221 within it). It should be noted that... Figure 4 The illustrated workflow is for illustrative purposes only and is not intended to limit the invention. For example, one or more steps may be performed... Figure 4 The workflow shown has been added, deleted, or modified. Furthermore, these steps do not necessarily need to be followed exactly to achieve the same result. Figure 4 Execute in the order shown.

[0032] In step 410, the USB-C connector chip 220 may set a detection voltage on a first input terminal of the judgment circuit, such as judgment circuit 222, to a first DC level during a first calibration phase.

[0033] In step 420, the USB-C connector chip 220 may sequentially set a threshold voltage on a second input terminal of the judgment circuit, such as judgment circuit 222, to a plurality of candidate correction levels during the first correction phase.

[0034] In step 430, the USB-C connector chip 220 can use the judgment circuit, such as judgment circuit 222, to sequentially judge whether the plurality of candidate correction levels have reached the first DC level in the first correction stage, so as to generate a plurality of first judgment results of a judgment signal.

[0035] In step 440, the USB-C connector chip 220 may select a first correction level from the plurality of candidate correction levels based on the plurality of first judgment results during the first correction stage.

[0036] In step 450, the USB-C connector chip 220 may set the detected voltage on the first input terminal of the judgment circuit, such as judgment circuit 222, to a second DC level in a second calibration phase.

[0037] In step 460, the USB-C connector chip 220 may sequentially set the threshold voltage on the second input terminal of the judgment circuit, such as judgment circuit 222, to the plurality of candidate correction levels during the second correction phase.

[0038] In step 470, the USB-C connector chip 220 may use the judgment circuit, such as judgment circuit 222, to sequentially judge whether the plurality of candidate correction levels have reached the second DC level in the second correction stage, so as to generate a plurality of second judgment results of the judgment signal.

[0039] In step 480, the USB-C connector chip 220 may select a second correction level from the plurality of candidate correction levels based on the plurality of second judgment results during the second correction stage.

[0040] In step 490, the USB-C connector chip 220 may determine a final correction level for the threshold voltage based on the first correction level and the second correction level.

[0041] Figure 5 According to an embodiment of the present invention Figure 4 The example of the correction method shown is as follows: Figure 5 The workflow can be provided by Figure 2 The test system 10 shown is used for execution. It should be noted that... Figure 5 The illustrated workflow is for illustrative purposes only and is not intended to limit the invention. For example, one or more steps may be performed... Figure 5 The workflow shown has been added, deleted, or modified. Furthermore, these steps do not necessarily need to be followed exactly to achieve the same result. Figure 5 Execute in the order shown.

[0042] In step S502, after the test machine 20 places the device under test (DUT), such as the USB-C connector chip 220, onto the test board 200, the test circuit 210 can set the current test item to be performed as the judgment circuit calibration, and send a judgment circuit calibration command to the device under test (DUT) accordingly.

[0043] In step S504, the DUT, such as the USB-C connector chip 220, can receive the judgment circuit correction instruction and start executing the judgment circuit correction process accordingly.

[0044] In step S506, the DUT, such as the USB-C connector chip 220, can control the DAC circuit 230 to output a DC voltage, wherein the voltage level of the DC voltage can be V. TARGET .

[0045] In step S508, the DUT, such as the USB-C connector chip 220, can adjust the value of the determination circuit register S508 to adjust the threshold voltage V. TH The calibration level.

[0046] In step S510, the DUT, such as the USB-C connector chip 220, can determine whether the determination circuit has changed state (e.g., determining signal D). COMP (Whether to change from logic value "1" to logic value "0" or from logic value "0" to logic value "1"). If the judgment result is "yes", the workflow proceeds to step S512. If the judgment result is "no", the workflow proceeds to step S508 to readjust the value of the judgment circuit register.

[0047] In step S512, the DUT, such as the USB-C connector chip 220, can record the value of the temporary register of the judgment circuit at the transition state as value1. For example, when the USB-C connector chip 220 determines the threshold voltage V through the operation of steps S508 and S510... TH Switching from a specific calibration level to the next calibration level causes the judgment signal D to... COMP When the logic value "1" changes to the logic value "0" (or the logic value "0" changes to the logic value "1"), the correction control circuit 221 can record the specific correction level as value1.

[0048] In step S514, the DUT, such as the USB-C connector chip 220, can control the DAC circuit 230 to output another DC voltage, wherein the voltage level of this DC voltage can be (V TARGET +ΔV / 2).

[0049] In step S516, the DUT, such as the USB-C connector chip 220, can adjust the value of the determination circuit register S508 to adjust the threshold voltage V. TH The calibration level.

[0050] In step S518, the DUT, such as the USB-C connector chip 220, can determine whether the determination circuit has changed state (e.g., determining signal D). COMP (Whether to change from logic value "1" to logic value "0" or from logic value "0" to logic value "1"). If the judgment result is "yes", the workflow proceeds to step S520. If the judgment result is "no", the workflow proceeds to step S516 to readjust the value of the judgment circuit register.

[0051] In step S520, the DUT, such as the USB-C connector chip 220, can record the value of the judgment circuit register at the time of state transition as value2. For example, when the USB-C connector chip 220 determines the threshold voltage V through the operation of steps S516 and S518... TH Switching from a specific calibration level to the next calibration level causes the judgment signal D to... COMP When the logic value "1" changes to the logic value "0" (or changes from the logic value "0" to the logic value "1"), the correction control circuit 221 can record the specific correction level as value2.

[0052] In step S522, the DUT, such as the USB-C connector chip 220, can determine whether value1 is equal to value2 (in Figure 5 (This is labeled as "value2-value1=0?" for simplicity). If the result is "yes", the workflow proceeds to step S524. If the result is "no", the workflow proceeds to step S526.

[0053] In step S524, the test circuit 210 can report the test results of the DUT, such as the USB-C connector chip 220, to the test machine 20, and the USB-C connector chip 220 can write value1 to the one-time programmable storage device as the final value of the calibration file bit.

[0054] In step S526, the DUT, such as the USB-C connector chip 220, can determine whether value2 is the next level after value1 (in... Figure 5 (This is labeled as "value2-value1=1?" for simplicity). If the result is "yes", the workflow proceeds to step S528. If the result is "no", the test circuit 210 can report the failure of the DUT, such as the USB-C connector chip 220, to the test machine 20.

[0055] In step S528, the test circuit 210 can report the test results of the DUT such as the USB-C connector chip 220 to the test machine 20, and the USB-C connector chip 220 can write value2 into the one-time programmable storage device as the final value of the calibration level.

[0056] After all tests on the USB-C connector chip 220 are completed, the test machine 20 can use a robotic arm to remove the USB-C connector chip 220 from the test board 200 and place another device under test on the test board 200 for testing and calibration of the next device under test.

[0057] In summary, the USB-C connector chip, testing system, and related calibration method provided by the embodiments of the present invention can obtain two calibration results by inputting two different DC voltages, and determine which calibration result is closer to the target value by judging whether these two calibration results are the same. Furthermore, the embodiments of the present invention do not significantly increase additional costs. Therefore, the present invention can solve the problems of related technologies without or with minimal side effects.

[0058] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0059] [Symbol Explanation]

[0060] 100: Cable

[0061] 110: Source end device

[0062] 110M: Source end monitor

[0063] 120: Pumping end device

[0064] 120M: End Monitor

[0065] CC1, CC2: Configuration channel pins

[0066] Rp1, Rp2, Rd1, Rd2: Resistors

[0067] 10: Testing System

[0068] 20: Testing equipment

[0069] 200: Test board

[0070] 210: Test Circuit

[0071] 220: USB-C connector chip

[0072] 221: Correction control circuit

[0073] 221P: Processing Circuit

[0074] 221M: Storage device

[0075] 221C: Program Code

[0076] 222: Judgment Circuit

[0077] 230: Digital-to-Analog Converter Circuit

[0078] V CCPIN Detect voltage

[0079] V TH Threshold voltage

[0080] D COMP Comparison signal

[0081] n-1,n,n+1,n+2: Correction gear

[0082] ΔV: Voltage difference between two consecutive candidate correction levels

[0083] P1, P2, P3: Intervals

[0084] 410~490: Steps

[0085] S502~S528: Procedures

Claims

1. A universal serial bus C-type connector chip, comprising: A judgment circuit is used to determine whether a detection voltage on a first input terminal of the judgment circuit reaches a threshold voltage on a second input terminal of the judgment circuit to generate a judgment signal, wherein the first input terminal is coupled to a detection pin of the Universal Serial Bus C-type connector chip; and A calibration control circuit, coupled to the judgment circuit, is used to calibrate the threshold voltage transmitted to the second input terminal; in: In a first correction stage, the correction control circuit sets the detected voltage to a first DC level, sequentially sets the threshold voltage to a plurality of candidate correction levels to obtain a plurality of first judgment results of the judgment signal, and selects a first correction level from the plurality of candidate correction levels based on the plurality of first judgment results. In a second correction stage, the correction control circuit sets the detected voltage to a second DC level, sequentially sets the threshold voltage to the plurality of candidate correction levels, to obtain a plurality of second judgment results of the judgment signal, and selects a second correction level from the plurality of candidate correction levels based on the plurality of second judgment results; and The correction control circuit determines a final correction level for the threshold voltage based on the first correction level and the second correction level.

2. The Universal Serial Bus Type-C connector chip according to claim 1, wherein when the threshold voltage changes from the first correction level to the next candidate correction level of the first correction level, the determination signal changes from a first logic value to a second logic value; and when the threshold voltage changes from the second correction level to the next candidate correction level of the second correction level, the determination signal changes from the first logic value to the second logic value.

3. The Universal Serial Bus Type-C connector chip according to claim 2, wherein the voltage difference between the first DC level and the second DC level is equal to half the voltage difference between any two consecutive candidate correction levels among the plurality of candidate correction levels.

4. The Universal Serial Bus Type-C connector chip according to claim 2, wherein when the first correction level is equal to the second correction level, the correction control circuit selects the first correction level as the final correction level.

5. The Universal Serial Bus Type-C connector chip according to claim 2, wherein when the second DC level is greater than the first DC level and the second correction level is greater than the first correction level, the correction control circuit selects the second correction level as the final correction level.

6. The Universal Serial Bus Type-C connector chip according to claim 2, wherein when the second DC level is less than the first DC level and the second correction level is less than the first correction level, the correction control circuit selects the second correction level as the final correction level.

7. The Universal Serial Bus Type-C connector chip according to claim 1, wherein the detection pin is a configuration channel pin, and multiple different levels of the detection voltage on the configuration channel pin respectively correspond to multiple different connection states of the Universal Serial Bus Type-C connector chip.

8. The Universal Serial Bus Type-C connector chip according to claim 1, wherein the detection pin is a voltage bus pin, and the multiple different levels of the detection voltage on the voltage bus correspond to multiple different power supply states of the Universal Serial Bus Type-C connector chip.

9. A testing system, comprising: A test circuit used to transmit a test command; A Universal Serial Bus (USB) Type-C connector chip is coupled to the test circuit, wherein the USB Type-C connector chip includes: A judgment circuit is used to determine whether a detection voltage on a first input terminal of the judgment circuit reaches a threshold voltage on a second input terminal of the judgment circuit to generate a judgment signal, wherein the first input terminal is coupled to a detection pin of the Universal Serial Bus C-type connector chip; and A calibration control circuit, coupled to the judgment circuit, is used to calibrate the threshold voltage transmitted to the second input terminal according to the test command; and A digital-to-analog converter circuit is coupled to the Universal Serial Bus Type-C connector chip to output the detected voltage to the detected pin of the Universal Serial Bus Type-C connector chip; in: In a first correction stage, the correction control circuit controls the digital-to-analog converter circuit to output the detection voltage having a first DC level, sequentially sets the threshold voltage to a plurality of candidate correction levels to obtain a plurality of first judgment results of the judgment signal, and selects a first correction level from the plurality of candidate correction levels based on the plurality of first judgment results. In a second correction stage, the correction control circuit controls the digital-to-analog converter circuit to output the detection voltage having a second DC level, sequentially sets the threshold voltage to the plurality of candidate correction levels to obtain a plurality of second judgment results of the judgment signal, and selects a second correction level from the plurality of candidate correction levels based on the plurality of second judgment results; and The correction control circuit determines a final correction level for the threshold voltage based on the first correction level and the second correction level.

10. A calibration method for a universal serial bus C-type connector chip, comprising: In a first calibration phase, a detection voltage on a first input terminal of a judgment circuit is set to a first DC level; In the first correction stage, a threshold voltage on a second input terminal of the judgment circuit is sequentially set to a plurality of candidate correction levels; In the first correction stage, the judgment circuit sequentially judges whether the plurality of candidate correction levels have reached the first DC level, so as to generate a plurality of first judgment results of a judgment signal; In the first correction stage, a first correction level is selected from the multiple candidate correction levels based on the multiple first judgment results; In a second calibration phase, the detected voltage on the first input terminal of the judgment circuit is set to a second DC level; In the second correction stage, the threshold voltage on the second input terminal of the judgment circuit is sequentially set to the plurality of candidate correction levels; In the second correction stage, the judgment circuit sequentially judges whether the plurality of candidate correction levels have reached the second DC level, so as to generate a plurality of second judgment results of the judgment signal; In the second correction stage, a second correction level is selected from the plurality of candidate correction levels based on the plurality of second judgment results; and A final correction level for the threshold voltage is determined based on the first correction level and the second correction level.

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