Plasma processing apparatus

Abstract

Techniques for stabilizing plasma are provided. Provided is a plasma processing apparatus including: a chamber; a substrate support portion disposed in the chamber and including at least one lower electrode; an upper electrode disposed above the substrate support part; a radio frequency signal generator electrically connected with any one of the at least one lower electrode or the upper electrode and configured to generate a radio frequency signal to generate plasma in the chamber; a first voltage signal generator electrically connected to any one of the at least one lower electrode and configured to generate a first voltage signal having a first voltage pulse sequence: a second voltage signal generator electrically connected to the upper electrode and configured to generate a second voltage signal; a capacitor; and a rectifying element including a first electrode electrically connected to a node between the upper electrode and the second voltage signal generator and a second electrode electrically connected to a ground potential via a capacitor.

Description

Technical Field

[0001] Exemplary embodiments of this disclosure relate to plasma processing apparatus. Background Technology

[0002] Patent Document 1 discloses a DC power supply for applying a negative DC voltage to the upper electrode. Patent Document 2 discloses a voltage pulse generator for applying a negative voltage pulse to the bias electrode of the substrate support.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2015-5755

[0006] Patent Document 2: U.S. Patent Application Publication No. 2022 / 37119 Summary of the Invention

[0007] This disclosure provides a technique for stabilizing plasma.

[0008] In one exemplary embodiment of this disclosure, a plasma processing apparatus is provided, comprising: a chamber; a substrate support disposed within the chamber, including at least one lower electrode; an upper electrode disposed above the substrate support; a radio frequency signal generator electrically connected to either the lower electrode or the upper electrode, configured to generate a radio frequency signal to generate plasma within the chamber; a first voltage signal generator electrically connected to either the lower electrode, configured to generate a first voltage signal having a first voltage pulse sequence; a second voltage signal generator electrically connected to the upper electrode, configured to generate a second voltage signal; a capacitor; and a rectifier element including a first electrode and a second electrode, the first electrode being electrically connected to a node located between the upper electrode and the second voltage signal generator, and the second electrode being electrically connected to a ground potential via the capacitor.

[0009] Invention Effects

[0010] According to an exemplary embodiment of this disclosure, a technique for providing stable plasma can be provided. Attached Figure Description

[0011] Figure 1 This is a diagram used to illustrate an example of the configuration of a plasma system.

[0012] Figure 2 This is a diagram used to illustrate an example of the configuration of a capacitively coupled plasma device.

[0013] Figure 3 This is a diagram illustrating an example of the coupling between the power supply 30 and the chamber 10.

[0014] Figure 4A This is a timing diagram showing an example of the voltage waveforms of the first DC signal and the second DC signal.

[0015] Figure 4B This is a timing diagram showing an example of the voltage waveforms of the first DC signal and the second DC signal.

[0016] Figure 4C This is a timing diagram showing an example of the voltage waveforms of the first DC signal and the second DC signal.

[0017] Figure 4D This is a timing diagram showing an example of the voltage waveforms of the first DC signal and the second DC signal.

[0018] Figure 5 This is a diagram illustrating an example of the configuration of the plasma stabilization circuit according to the first embodiment.

[0019] Figure 6A This is a diagram illustrating an example of the first filter.

[0020] Figure 6B This is a diagram illustrating an example of the second filter.

[0021] Figure 7A This is a diagram showing another configuration example of node N1.

[0022] Figure 7B This is a diagram showing another configuration example of node N1.

[0023] Figure 8A This diagram illustrates the function of the plasma stabilization circuit 70.

[0024] Figure 8B This diagram illustrates the function of the plasma stabilization circuit 70.

[0025] Figure 9A This diagram illustrates the rectification function of the first rectifier element D1.

[0026] Figure 9B This diagram illustrates the rectification function of the first rectifier element D1.

[0027] Figure 10 This is a diagram illustrating an example of the configuration of the plasma stabilization circuit according to the second embodiment.

[0028] Figure 11 This is a diagram showing an example of a second rectifier element.

[0029] Figure 12 This is a diagram showing an example of a second rectifier element.

[0030] Figure 13This is a diagram showing other examples of coupling between the power supply 30 and the chamber 10.

[0031] Figure 14 This is a diagram showing an example of the configuration of the plasma stabilization circuit according to the third embodiment.

[0032] Figure 15A This is a diagram illustrating a variation of the first embodiment.

[0033] Figure 15B This is a diagram illustrating a variation of the second embodiment.

[0034] Figure 16 This is a diagram illustrating an example of a polarity switching circuit.

[0035] Figure 17 This is a diagram showing other examples of coupling between the power supply 30 and the chamber 10.

[0036] Figure 18 This is a diagram showing other examples of coupling between the power supply 30 and the chamber 10.

[0037] Figure 19 This is a diagram showing other examples of coupling between the power supply 30 and the chamber 10.

[0038] Explanation of reference numerals in the attached figures

[0039] 1: Plasma processing device; 2: Control unit; 10: Plasma processing chamber; 13: Nozzle; 31a: First radio frequency generation unit; 31b: Second radio frequency generation unit; 32a: First DC generation unit; 32b: Second DC generation unit; 50: Second waveform generation unit; 60: Impedance fixing circuit; 70: Plasma stabilization circuit; 80: Polarity switching circuit; D1: First rectifier element; D2: Second rectifier element; F1: First filter; F2: Second filter; L1: Transmission line. Detailed Implementation

[0040] The following describes various embodiments of this disclosure.

[0041] In one exemplary embodiment, a plasma processing apparatus is provided, comprising: a chamber; a substrate support disposed within the chamber, including at least one lower electrode; an upper electrode disposed above the substrate support; a radio frequency signal generator electrically connected to either the at least one lower electrode or the upper electrode, configured to generate a radio frequency signal to generate plasma within the chamber; a first voltage signal generator electrically connected to either the at least one lower electrode, configured to generate a first voltage signal, wherein the first voltage signal has a first voltage pulse sequence; a second voltage signal generator electrically connected to the upper electrode, configured to generate a second voltage signal; a capacitor; and a rectifier element including a first electrode and a second electrode, wherein the first electrode is electrically connected to a node located between the upper electrode and the second voltage signal generator, and the second electrode is electrically connected to a ground potential via the capacitor.

[0042] In one exemplary embodiment, the second voltage signal has a second voltage pulse sequence.

[0043] In one exemplary embodiment, the second voltage signal has a certain voltage level.

[0044] In one exemplary embodiment, the second voltage signal has a negative polarity, the first electrode is a cathode electrode, and the second electrode is an anode electrode.

[0045] In one exemplary embodiment, the first voltage pulse sequence has a first pulse frequency in the range of 0.1 MHz to 2 MHz.

[0046] In one exemplary embodiment, the second voltage pulse sequence has a second pulse frequency in the range of 0.1 kHz to 50 kHz.

[0047] In one exemplary embodiment, a filter circuit is also provided on the transmission line between the upper electrode and the second voltage signal generator.

[0048] In one exemplary embodiment, a filter circuit is also provided on the transmission line between the upper electrode and the node.

[0049] In one exemplary embodiment, a filter circuit is also provided on the transmission line between the node and the second voltage signal generator.

[0050] In one exemplary embodiment, a first filter and a second filter are also provided. The first filter is disposed on the transmission line between the upper electrode and the node and is configured to filter the signal in the radio frequency band of the radio frequency signal. The second filter is disposed on the transmission line between the node and the second voltage signal generator and is configured to filter the signal in the pulse band of the first voltage pulse sequence.

[0051] In one exemplary embodiment, a plasma processing apparatus is provided, comprising: a chamber; a substrate support disposed within the chamber, including at least one lower electrode; an upper electrode disposed above the substrate support; a radio frequency signal generator electrically connected to either the at least one lower electrode or the upper electrode, configured to generate a radio frequency signal to generate plasma within the chamber; a voltage signal generator electrically connected to either the at least one lower electrode, configured to generate a voltage signal, wherein the voltage signal has a voltage pulse sequence; an impedance fixing circuit electrically connected to the upper electrode; a capacitor; and a rectifier element including a first electrode and a second electrode, wherein the first electrode is electrically connected to a node located between the upper electrode and the impedance fixing circuit, and the second electrode is electrically connected to a ground potential via the capacitor.

[0052] In one exemplary embodiment, the voltage pulse has a negative polarity, the first electrode is a cathode electrode, and the second electrode is an anode electrode.

[0053] In one exemplary embodiment, the voltage pulse sequence has a first pulse frequency in the range of 0.1 MHz to 2 MHz.

[0054] In one exemplary embodiment, the impedance-fixing circuit includes at least one of a capacitor and an inductor.

[0055] In one exemplary embodiment, a plasma processing apparatus is provided, comprising: a chamber; a substrate support disposed within the chamber and including electrodes; a first voltage signal generator electrically connected to the electrodes and configured to generate a first voltage signal, wherein the first voltage signal has a first voltage pulse sequence; a conductive component constituting part of the chamber or disposed within the chamber; a capacitor; and a rectifier element including a first electrode and a second electrode, wherein the first electrode is electrically connected to the conductive component, and the second electrode is electrically connected to a ground potential via the capacitor.

[0056] In one exemplary embodiment, a second voltage signal generator is also included, which is electrically connected to a node located between the first electrode of the conductive component and the rectifier element, configured to generate a second voltage signal.

[0057] In one exemplary embodiment, an impedance fixing circuit is also included, which is electrically connected to a node located between the conductive component and the first electrode of the rectifier element.

[0058] In one exemplary embodiment, the impedance-fixing circuit includes at least one of a capacitor and an inductor.

[0059] In one exemplary embodiment, the conductive component is any of the following components: (a) an upper electrode disposed above the substrate support, (b) a ring assembly disposed on the substrate support to surround the substrate on the substrate support, (c) a bushing disposed along the inner wall of the cavity, and (d) a baffle disposed to surround the substrate support.

[0060] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. Furthermore, the same or similar elements are labeled with the same symbols in the drawings, and repeated descriptions are omitted. Unless otherwise specified, positional relationships such as up, down, left, and right are described based on the positional relationships shown in the drawings. The scale of the drawings does not represent an actual scale, and the actual scale is not limited to the scale shown.

[0061] <Example of a plasma processing system>

[0062] Figure 1 This is a diagram illustrating an example of the configuration of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing apparatus 1 and a controller 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a plasma processing chamber 10, a substrate support portion 11, and a plasma generation portion 12. The plasma processing chamber 10 has a plasma processing space. Furthermore, the plasma processing chamber 10 has at least one gas supply port for supplying at least one processing gas into the plasma processing space and at least one gas outlet for discharging gas from the plasma processing space. The gas supply port is connected to the gas supply portion 20 (described later), and the gas outlet is connected to the exhaust system 40 (described later). The substrate support portion 11 is disposed within the plasma processing space and has a substrate support surface for supporting a substrate.

[0063] The plasma generation unit 12 is configured to generate plasma from at least one processing gas supplied to the plasma processing space. The plasma formed in the plasma processing space can be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), electron-cyclotron-resonance plasma (ECR), helicon wave plasma (HWP), or surface wave plasma (SWP), etc. Alternatively, various types of plasma generation units, including alternating current (AC) plasma generation units and direct current (DC) plasma generation units, can be used. In one embodiment, the AC signal (AC power) used in the AC plasma generation unit has a frequency in the range of 100 kHz to 10 GHz. Therefore, the AC signal includes radio frequency (RF) signals and microwave signals. In one embodiment, the RF signal has a frequency in the range of 100 kHz to 150 MHz.

[0064] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform the various processes described herein. The control unit 2 may be configured to control various elements of the plasma processing apparatus 1 to perform the various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may also include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 may be implemented, for example, by a computer 2a. The processing unit 2a1 may be configured to perform various control operations by reading a program from the storage unit 2a2 and executing the read program. The program may be pre-stored in the storage unit 2a2 or retrieved via a medium when needed. The retrieved program is stored in the storage unit 2a2 and read from and executed by the processing unit 2a1. The medium may be various storage media readable by the computer 2a and may be a communication line connected to the communication interface 2a3. The processing unit 2a1 may also be a CPU (Central Processing Unit). Storage unit 2a2 may include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination thereof. Communication interface 2a3 may also communicate with plasma processing device 1 via communication lines such as LAN (Local Area Network).

[0065] Hereinafter, an example of the configuration of a capacitively coupled plasma processing apparatus, which is an example of plasma processing apparatus 1, will be described. Figure 2 This is a diagram illustrating an example of the configuration of a capacitively coupled plasma processing device.

[0066] The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply 30, and an exhaust system 40. Additionally, the plasma processing apparatus 1 includes a substrate support 11 and a gas inlet. The gas inlet is configured to introduce at least one processing gas into the plasma processing chamber 10. The gas inlet includes a nozzle 13. The substrate support 11 is disposed within the plasma processing chamber 10. The nozzle 13 is disposed above the substrate support 11. In one embodiment, the nozzle 13 constitutes at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the nozzle 13, the sidewall 10a of the plasma processing chamber 10, and the substrate support 11. The plasma processing chamber 10 is grounded. The nozzle 13 and the substrate support 11 are electrically insulated from the frame of the plasma processing chamber 10.

[0067] The substrate support portion 11 includes a main body portion 111 and a ring assembly 112. The main body portion 111 has a central region 111a for supporting the substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of the substrate W. The annular region 111b of the main body portion 111 surrounds the central region 111a of the main body portion 111 when viewed from above. The substrate W is disposed on the central region 111a of the main body portion 111, and the ring assembly 112 is disposed on the annular region 111b of the main body portion 111 in such a way that it surrounds the substrate W on the central region 111a of the main body portion 111. Therefore, the central region 111a is also referred to as the substrate support surface for supporting the substrate W, and the annular region 111b is also referred to as the annular support surface for supporting the ring assembly 112.

[0068] In one embodiment, the body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive component. The conductive component of the base 1110 can function as a lower electrode. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic component 1111a and an electrostatic electrode 1111b disposed within the ceramic component 1111a. The ceramic component 1111a has a central region 111a. In one embodiment, the ceramic component 1111a also has an annular region 111b. Alternatively, other components surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating component, may also have an annular region 111b. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating component, or it may be disposed on both the electrostatic chuck 1111 and the annular insulating component. Additionally, at least one radio frequency / DC electrode coupled to the radio frequency power supply 31 and / or DC power supply 32 described later may be disposed within the ceramic component 1111a. In this configuration, at least one RF / DC electrode serves as a lower electrode. If the bias RF signal and / or DC signal described later are provided to the at least one RF / DC electrode, then the RF / DC electrode is also referred to as a bias electrode. Additionally, the conductive components of the base 1110 and the at least one RF / DC electrode can also function as multiple lower electrodes. Furthermore, the electrostatic electrode 1111b can also function as a lower electrode. Therefore, the substrate support 11 includes at least one lower electrode.

[0069] The ring assembly 112 includes one or more annular components. In one embodiment, the one or more annular components include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.

[0070] Additionally, the substrate support 11 may also include a temperature control module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature control module may include a heater, a heat transfer medium, a flow path 1110a, or a combination thereof. A heat transfer fluid, such as brine or gas, flows through the flow path 1110a. In one embodiment, the flow path 1110a is formed within the base 1110, and one or more heaters are disposed within the ceramic component 1111a of the electrostatic chuck 1111. Furthermore, the substrate support 11 may also include a heat transfer gas supply section configured to supply heat transfer gas to the gap between the back surface of the substrate W and the central region 111a.

[0071] The nozzle 13 is configured to introduce at least one process gas from the gas supply unit 20 into the plasma processing space 10s. The nozzle 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and a plurality of gas inlets 13c. The process gas supplied to the gas supply port 13a is introduced into the plasma processing space 10s through the gas diffusion chamber 13b and the plurality of gas inlets 13c. Additionally, the nozzle 13 includes at least one upper electrode. Furthermore, in addition to the nozzle 13, the gas inlet unit may also include one or more side gas injectors (SGIs) mounted on one or more openings formed on the sidewall 10a.

[0072] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one process gas from a corresponding gas source 21 to a nozzle 13 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Furthermore, the gas supply unit 20 may include at least one flow regulating device for adjusting or pulsed flow of the at least one process gas.

[0073] The power supply 30 includes a radio frequency (RF) power supply 31, which is coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power) to at least one lower electrode and / or at least one upper electrode. Plasma is thus formed from at least one processing gas supplied to the plasma processing space 10s. Therefore, the RF power supply 31 can function as at least a portion of the plasma generation unit 12. Furthermore, by supplying a bias RF signal to at least one lower electrode, a bias potential is generated on the substrate W, enabling the introduction of ionic components from the formed plasma into the substrate W.

[0074] In one embodiment, the radio frequency (RF) power supply 31 includes a first RF generation unit 31a and a second RF generation unit 31b. The first RF generation unit 31a is coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matching circuit, configured to generate a source RF signal (source RF power) for generating plasma. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generation unit 31a may be configured to generate multiple source RF signals with different frequencies. The generated one or more source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0075] The second RF generation unit 31b is coupled to at least one lower electrode via at least one impedance matching circuit, configured to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the frequency of the bias RF signal is lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generation unit 31b may be configured to generate multiple bias RF signals with different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. Furthermore, in various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0076] Furthermore, the power supply 30 may include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a first DC generating unit 32a and a second DC generating unit 32b. In one embodiment, the first DC generating unit 32a is connected to at least one lower electrode and configured to generate a first DC signal. The generated first DC signal is applied to at least one lower electrode. In one embodiment, the second DC generating unit 32b is connected to at least one upper electrode and configured to generate a second DC signal. The generated second DC signal is applied to at least one upper electrode.

[0077] In various embodiments, the first and second DC signals can be pulsed. In this case, a voltage pulse sequence is applied to at least one lower electrode and / or at least one upper electrode. The voltage pulses can have rectangular, trapezoidal, triangular, or combinations thereof pulse waveforms. In one embodiment, a waveform generation unit for generating the voltage pulse sequence from the DC signal is connected between the first DC generation unit 32a and at least one lower electrode. Therefore, the first DC generation unit 32a and the waveform generation unit constitute a voltage pulse generation unit. When the second DC generation unit 32b and the waveform generation unit constitute a voltage pulse generation unit, the voltage pulse generation unit is connected to at least one upper electrode. The voltage pulses can have positive or negative polarity. Furthermore, the voltage pulse sequence can include one or more positive voltage pulses and one or more negative voltage pulses within one cycle. Additionally, the first and second DC generation units 32a and 32b can also be provided together with the radio frequency power supply 31, and the first DC generation unit 32a can also be provided in place of the second radio frequency generation unit 31b.

[0078] The exhaust system 40 may be connected, for example, to a gas outlet 10e located at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure within the plasma processing space 10s is regulated by the pressure regulating valve. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0079] <Example of coupling between power supply 30 and plasma processing chamber 10>

[0080] Figure 3 This is a diagram showing an example of the coupling between the power supply 30 of the plasma processing apparatus 1 and the plasma processing chamber 10 (hereinafter also referred to as "chamber 10").

[0081] In one embodiment, the first radio frequency (RF) generation unit 31a is electrically connected to the lower electrode of the substrate support unit 11 via transmission line L2. Alternatively, one or more lower electrodes may be provided on the substrate support unit 11. In the case of multiple lower electrodes, the first RF generation unit 31a can be electrically connected to any one of the multiple lower electrodes. At least one impedance matching circuit is provided on transmission line L2. The first RF generation unit 31a is configured to generate a source RF signal for generating plasma. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generation unit 31a may be configured to generate multiple source RF signals with different frequencies. Additionally, in one embodiment, the first RF generation unit 31a may be electrically connected to the upper electrode via at least one impedance matching circuit. In this case, only one lower electrode may be provided on the substrate support unit (i.e., multiple lower electrodes may not be provided on the substrate support unit).

[0082] In one embodiment, the first DC generation unit 32a is electrically connected to the lower electrode of the substrate support unit 11 via the transmission line L3. When multiple lower electrodes are provided, the first DC generation unit 32a may be electrically connected to the same lower electrode as the first radio frequency generation unit 31a; alternatively, it may be electrically connected to a different lower electrode than the first radio frequency generation unit 31a. The first DC generation unit 32a is configured to generate a first DC signal.

[0083] In one embodiment, the first DC signal can be pulsed. For example, a first waveform generation unit can be provided on the output side (lower electrode side) of the first DC generation unit 32a. The first waveform generation unit generates a first voltage pulse sequence based on the first DC signal. Thus, a first voltage signal having the first voltage pulse sequence can be applied to the lower electrode. The first voltage pulse can have a rectangular, trapezoidal, triangular, or a combination thereof pulse waveform. Alternatively, the first waveform generation unit can be integrally provided within the first DC generation unit 32a.

[0084] In one implementation, the first DC signal may not be pulsed. For example, the first DC signal may have a certain voltage level, and the first DC signal with a certain voltage level is applied to the lower electrode.

[0085] In one embodiment, the second DC generating unit 32b is electrically connected to the upper electrode of the nozzle 13 via a transmission line L1. The second DC generating unit 32b is configured to generate a second DC signal. A rectifier element that limits the direction of current is provided on the transmission line L1 between the second DC generating unit 32b and the upper electrode. The configuration of the transmission line L1 including the rectifier element will be described later.

[0086] In one embodiment, the second DC signal can be pulsed. For example, a second waveform generation unit can be provided on the transmission line L1 on the output side (upper electrode side) of the second DC generation unit 32b. The second waveform generation unit generates a second voltage pulse sequence based on the second DC signal. Thus, a second DC signal having the second voltage pulse sequence can be applied to the upper electrode. The second voltage pulse can have a rectangular, trapezoidal, triangular, or a combination thereof pulse waveform. Alternatively, the second waveform generation unit can be integrally provided within the second DC generation unit 32b.

[0087] In one implementation, the second DC signal may not be pulsed. For example, the second DC signal may have a certain voltage level, and the second DC signal with a certain voltage level is applied to the upper electrode.

[0088] <An example of the first DC signal and the second DC signal>

[0089] Figures 4A to 4DThis is a timing diagram illustrating an example of the voltage waveforms of a first DC signal and a second DC signal. In one embodiment, the voltage waveforms of the first DC signal and the second DC signal can be repeated multiple times within a repetition period T (see [link to relevant documentation]). Figures 4A to 4D In one example, the first DC signal can have a repetition frequency (1 / T) ranging from 0.1 kHz to 50 kHz. In another example, the second DC signal can have a repetition frequency (1 / T) ranging from 0.1 kHz to 50 kHz. The repetition frequencies of the first and second DC signals can be the same or different. The first and second DC signals can be synchronized (see reference). Figures 4A to 4C They can also be asynchronous. For example, the first DC signal and the second DC signal can be out of phase by a specified value (180 degrees in one example).

[0090] Figure 4A This is an example where both the first DC signal (DC1) and the second DC signal (DC2) are pulsed. The first DC signal and the second DC signal can be generated by a first waveform generation unit and a second waveform generation unit, respectively. In one embodiment, the first DC signal has a first voltage pulse sequence during a first period T1 within a repetition period T, and this first voltage pulse sequence has a first voltage level V11. In one example, the first voltage pulse sequence can have a pulse frequency of 0.1 MHz to 2 MHz (hereinafter, a voltage pulse with this pulse frequency will be referred to as a "high-speed pulse"). The first DC signal has a reference voltage level V10 during a second period T2 within the repetition period T. The absolute value of the reference voltage level V10 is less than the absolute value of the first voltage level V11. In one embodiment, the first voltage level V11 has a negative polarity. In one embodiment, the reference voltage level V10 has a zero voltage level.

[0091] During the first period T1, the second DC signal (DC2) has a second voltage pulse sequence with a second voltage level V21. In one example, the second voltage pulse sequence may have a pulse frequency of 0.1 MHz to 2 MHz. The pulse frequency of the second voltage pulse sequence may be the same as or different from the pulse frequency of the first voltage pulse sequence. Additionally, the second DC signal has a reference voltage level V20 during the second period T2. The reference voltage level V20 is less than the absolute value of the second voltage level V21. In one embodiment, the second voltage level V21 has a negative polarity. In one embodiment, the reference voltage level V20 has a zero voltage level.

[0092] Figure 4B yes Figure 4AThe voltage waveform shown is a variation. A first DC signal (DC1) and a second DC signal (DC2) can be generated by a first waveform generation unit and a second waveform generation unit, respectively. Both the first and second DC signals are pulsed. In this example, the first DC signal has a third voltage pulse sequence during the second period T2 within the repetition period T, and this third voltage pulse sequence has a third voltage level V12. The absolute value of the third voltage level V12 is greater than the absolute value of the reference voltage level V10 and less than the absolute value of the first voltage level V11. The third voltage pulse sequence can have a pulse frequency of 0.1MHz to 2MHz. Furthermore, the second DC signal has a fourth voltage pulse sequence during the second period T2 within the repetition period T, and this fourth voltage pulse sequence has a fourth voltage level V22. The absolute value of the fourth voltage level V22 is greater than the absolute value of the reference voltage level V20 and less than the absolute value of the second voltage level V21. The fourth voltage pulse sequence can have a pulse frequency of 0.1MHz to 2MHz. The remaining points are similar to... Figure 4A The examples shown are the same. Additionally, in Figure 4B In the example shown, the repetition period T can also have a third period T3. Furthermore, the first DC signal can have a reference voltage level V10 during the third period T3 within the repetition period T. Additionally, the second DC signal can have a reference voltage level V20 during the third period T3 within the repetition period T.

[0093] Figure 4C yes Figure 4A The voltage waveform shown is a variation. Both the first DC signal (DC1) and the second DC signal (DC2) are pulsed. The first DC signal can be generated by the first waveform generation unit. The second DC signal can be generated by the second waveform generation unit (including the case where it is integrally formed with the second DC generation unit 32b), or it can be generated by the second DC generation unit 32b itself. In this example, the second DC signal has a second voltage pulse sequence during the repetition period T. That is, the second voltage pulse sequence in this example has a second voltage level V21 during the first period T1 and a reference voltage level V20 during the second period T2. The pulse frequency of the second voltage pulse sequence can be the same as the repetition frequency (1 / T) of the first DC signal, for example, it can be from 0.1kHz to 50kHz (hereinafter, voltage pulses at this pulse frequency are also referred to as "low-speed pulses"). The remaining points can be... Figure 4A The example shown is the same.

[0094] Figure 4D yes Figure 4AThe voltage waveform shown is a variation. In this example, only the first DC signal (DC1) is pulsed, and the second DC signal has a certain voltage level (second voltage level V21) during the first period T1 and the second period T2 within the repetition period T. The second DC signal can be generated by the second DC generation unit 32b. The remaining points can be related to... Figure 4A The example shown is the same.

[0095] <First Implementation Method>

[0096] Immediately after the first DC signal is supplied to the lower electrode (e.g., approximately 1 to 3 cycles of a high-speed pulse), a sudden surge of current (hereinafter referred to as "transition current") sometimes flows instantaneously through the upper electrode. The magnitude of the transition current tends to increase as the voltage level of the first DC signal (bias signal) increases. The transition current is considered to be the current required for plasma stabilization within the chamber; limiting the transition current through the circuit structure of the power supply 30, etc., may lead to plasma instability. When the plasma is unstable, abnormal discharges may occur, for example, in the upper electrode (e.g., the gas inlet 13c of the nozzle 13). In the first embodiment, by providing the plasma stabilization circuit described below, such plasma instability can be suppressed.

[0097] Figure 5 This diagram illustrates a configuration example of the plasma stabilization circuit according to the first embodiment. The first embodiment is a configuration example where a first DC signal of negative polarity is supplied to the lower electrode. Figure 5 As shown, a node N1 is provided on the transmission line L1 between chamber 10 (upper electrode) and the second DC generation unit 32b. A first rectifier element D1 and a plasma stabilization circuit 70 are provided on the transmission line L12 between node N1 and ground potential. Furthermore, a first filter F1 and a second filter F2 are provided on the transmission line L1 from chamber 10 (upper electrode) to the second DC generation unit 32b. Figure 5 In the example shown, node N1 is located on transmission line L1 between the first filter F1 and the second filter F2. Additionally, in Figure 5 In the example shown, the first rectifier element D1 is disposed on the transmission line L12 between node N1 and plasma stabilization circuit 70. In one embodiment, the first rectifier element D1 may be disposed on the transmission line L12 between plasma stabilization circuit 70 and ground potential.

[0098] In one embodiment, the second DC generation unit 32b generates a second DC signal with negative polarity. The second DC signal generated by the second DC generation unit 32b may have the following characteristics: Figure 4C The low-speed pulse shown. Furthermore, the second DC signal generated by the second DC generation unit 32b can have, for example, the low-speed pulse. Figure 4DThe voltage level shown is constant. Alternatively, a second waveform generation unit may not be provided. In one embodiment, the second DC generator 32b can generate a positive DC signal.

[0099] The plasma stabilization circuit 70 includes a capacitor C1. The capacitance of capacitor C1 is sufficient to instantaneously provide enough charge to the upper electrode. In one example, the capacitance of capacitor C1 is between 10 nF and 100 nF. Capacitor C1 can be composed of one or more capacitors.

[0100] In one embodiment, the plasma stabilization circuit 70 may include a resistor R as a charge removal circuit. The resistor R is connected in parallel with the capacitor C1. The resistor R may be configured to remove the charge from the capacitor C1 in approximately 1 to 10 seconds. Alternatively, an inductor may be used instead of the resistor R, or in addition to the resistor R, as the charge removal circuit. Furthermore, when the first rectifier element D1 is provided on the transmission line L12 between the plasma stabilization circuit 70 and the ground potential, the resistor R may be connected to a node on the transmission line L12 between the capacitor C1 and the first rectifier element D1.

[0101] Immediately after the plasma stabilization circuit 70 supplies the first DC signal (bias signal) to the lower electrode, it supplies the necessary amount of charge to the upper electrode. That is, the plasma stabilization circuit 70 can suppress plasma instability and allow sufficient transition current to flow through the upper electrode.

[0102] From the perspective of the plasma stabilization circuit 70, the first rectifier element D1 is configured such that the current is in the positive direction on the side of the chamber 10 (upper electrode).

[0103] In one embodiment, the first rectifier element D1 can be composed of a diode. In this case, the cathode electrode of the first rectifier element D1 (diode) can be electrically connected to node N1. Furthermore, the anode electrode of the first rectifier element D1 (diode) can be electrically connected to the plasma stabilization circuit 70. That is, the anode electrode of the first rectifier element D1 can be electrically connected to ground potential via capacitor C1 of the plasma stabilization circuit 70. In one example, the diode can be a mesa-type or planar-type PN junction diode. The first rectifier element D1 can be composed of multiple diodes, in which case the diodes can be connected in series or in parallel.

[0104] The rectification effect of the first rectifier element D1 suppresses the flow of the second DC signal from the second DC generation unit 32b to the plasma stabilization circuit 70. Therefore, the large-capacity capacitor C1 of the plasma stabilization circuit 70 can suppress voltage waveform distortion of the second DC signal.

[0105] The first filter F1 is configured to filter the bandband signal (hereinafter referred to as the "high-frequency signal") of the source radio frequency signal generated by the first radio frequency generation unit 31a. That is, the first filter F1 blocks or attenuates the high-frequency signal flowing from the cavity 10 (upper electrode) to the first rectifier element D1. This can suppress the heating of the first rectifier element D1 by all or part of the high-frequency signal passing through it, and thereby suppress the reduction of the rectification effect of the first rectifier element D1. Furthermore, it can suppress the high-frequency signal from entering the second DC generation unit 32b. However, when the first rectifier element D1 is disposed on the input side (cavity 10 side) of the first filter F1, the attenuation performance of the first filter F1 may be affected by changes in the impedance of the first rectifier element D1. Regarding this, in Figure 5 In the example shown, the first rectifier element D1 is disposed on the output side of the first filter F1 (on the side of the second DC generation section 32b). Therefore, the attenuation performance of the first filter F1 can be suppressed due to the impedance change of the first rectifier element D1.

[0106] Figure 6A This is a diagram illustrating an example of the first filter F1. (As shown...) Figure 6A As shown in (a) to (d), the first filter F1 may be constructed by including one or more inductors (ID) or capacitors (C). The capacitance of the capacitor of the first filter F1 is sufficiently small compared to the capacitor C1 of the plasma stabilization circuit 70, in one example being 0.01 nF to 1 nF.

[0107] The second filter F2 is configured to filter the pulse band signal (hereinafter referred to as the "bias pulse signal") of the first DC signal (bias signal) generated by the first DC generation unit 32a. That is, the second filter F2 blocks or attenuates the bias pulse signal flowing from the first rectifier element D1 to the second DC generation unit 32b. This suppresses the bias pulse signal from entering the second DC generation unit 32b. Alternatively, the second filter F2 may not be required if it interferes with the second DC signal. For example, if the second DC signal has a frequency close to the pulse frequency of the first DC signal (e.g., within ±10%), the second filter F2 may not be required.

[0108] Figure 6B This is a diagram illustrating an example of the second filter, F2. (As shown...) Figure 6BAs shown in (a) to (e), the second filter F2 may be configured as one or more inductors (ID) or capacitors (C). In one embodiment, the capacitance of the capacitor in the second filter F2 is sufficiently small compared to the capacitor C1 of the plasma stabilization circuit 70, and in one example is 0.01 nF to 1 nF. Alternatively, in one embodiment, the capacitance of the capacitor in the second filter F2 may be approximately the same as that of the capacitor C1 of the plasma stabilization circuit 70 (in one example, 10 nF to 100 nF). In this case, a rectifier element may be provided on the second filter F2. This rectifier element is capable of suppressing the second DC signal from the second DC generation unit 32b from flowing to the capacitor of the second filter F2, thereby preventing waveform distortion of the second DC signal.

[0109] Figure 7A and 7B This is a diagram showing other configuration examples for node N1. For example... Figure 7A As shown, node N1 can be located between the second filter F2 and the second DC generator 32b on transmission line L1. Figure 7B As shown, node N1 can be located between chamber 10 (upper electrode) and the first filter F1 on transmission line L1. Additionally, in Figure 7A and Figure 7B In the example shown, the first filter F1 and the second filter F2 can also be constructed as a single filter circuit.

[0110] In one embodiment, the position of node N1 on transmission line L1 can be suitably configured such that the current flowing from plasma stabilization circuit 70 to the upper electrode is unimpeded. For example, when the first filter F1 has a relatively high inductance (e.g., around 100 μH to 10000 μH), node N1 can be located between chamber 10 (upper electrode) and the first filter F1 (see reference). Figure 7B Therefore, the current flowing from the plasma stabilization circuit 70 to the upper electrode can be prevented from being blocked by the first filter F1. For example, when the first filter F1 has a relatively low inductance (e.g., around 0.1 μH to 10 μH), node N1 can be located between the first filter F1 and the second filter F2 (see reference). Figure 5 In this case, node N1 can be located between the second filter F2 and the second DC generation unit 32b (see...). Figure 7A This is because even with the presence of the first filter F1 or the second filter F2, the current flowing from the plasma stabilization circuit 70 to the upper electrode is difficult to obstruct.

[0111] Figure 8A and Figure 8B This diagram illustrates the function of the plasma stabilization circuit 70. Figure 8AThis is an example of a case where the plasma stabilization circuit 70 is not provided on the upper electrode. Figure 8B This is an example of a case where a plasma stabilization circuit 70 is installed on the upper electrode. Figure 8A and Figure 8B In the text, "DC1" represents an example of the voltage waveform of the first DC signal supplied to the lower electrode, and "I" represents an example of the current waveform of the transition current flowing through the upper electrode at this time.

[0112] like Figure 8A As shown, without the plasma stabilization circuit 70, the peak value (Ia) of the current waveform of the transition current in the upper electrode is suppressed. That is, there is not enough transition current flowing through the upper electrode. This is because not enough charge is supplied to the upper electrode. In this case, the plasma in chamber 10 becomes unstable, which may lead to abnormal discharges, etc. In contrast, as... Figure 8B As shown, with the plasma stabilization circuit in place, the transition current in the upper electrode does not suppress the peak value (Ib>Ia). That is, sufficient transition current flows through the upper electrode. This is because immediately after the first DC signal (bias signal) is supplied to the lower electrode, charge is instantaneously supplied from capacitor C1 of the plasma stabilization circuit 70 to the upper electrode. Thus, plasma instability in the chamber 10 can be suppressed.

[0113] Figure 9A and 9B This diagram illustrates the rectification function of the first rectifier element D1. Figure 9A This is an example of a case where the first rectifier element D1 is not installed on the transmission line L12. Figure 9B This is an example where the first rectifier element D1 is installed on transmission line L12. Figure 9A and Figure 9B The upper section shows an example of the voltage waveform of the second DC signal output from the second DC generation unit 32b. Figure 9A and Figure 9B The lower section shows an example of the voltage waveform of the second DC signal input to the upper electrode.

[0114] like Figure 9A As shown, without the first rectifier element D1, the voltage waveform of the second DC signal input to the upper electrode will be significantly distorted due to the influence of the large-capacity capacitor C1. In contrast, as... Figure 9B As shown, with the first rectifier element D1 provided, the effect of the large-capacity capacitor C1 is limited, and it can suppress the voltage waveform distortion of the second DC signal input to the upper electrode.

[0115] <Second Implementation Method>

[0116] Figure 10This diagram illustrates a configuration example of the plasma stabilization circuit according to the second embodiment. The second embodiment is a configuration example where a first DC signal with negative polarity is supplied to the lower electrode. Hereinafter, the description will focus on the structure that differs from the first embodiment.

[0117] exist Figure 10 In the example shown, the second waveform generation unit 50 is disposed on the transmission line L1 between node N1 and the second DC generation unit 32b. In one embodiment, the second DC signal generated by the second DC generation unit 32b has a negative polarity. The second waveform generation unit 50 is configured to pulse the second DC signal generated by the second DC generation unit 32b. The second DC signal output from the second waveform generation unit 50 may have... Figure 4A or Figure 4B The high-speed pulse shown. Additionally, the second DC signal output from the second waveform generation unit 50 may also have... Figure 4C The low-speed pulse shown. In one embodiment, the second DC generator 32b can generate a second DC signal with positive polarity.

[0118] exist Figure 10 In the example shown, no settings are provided. Figure 5 The second filter F2 is shown. The second filter F2 can be set when it does not interfere with the second DC signal. For example, when the first DC signal has a high-speed pulse and the second DC signal has a low-speed pulse, the second filter F2 can be set. In this case, the second filter F2 can be set on the transmission line L1 between the first filter F1 and the second waveform generation unit 50.

[0119] In the second embodiment, the plasma stabilization circuit 70 instantaneously supplies the necessary amount of charge to the upper electrode immediately after supplying the first DC signal (bias signal) to the lower electrode. Therefore, because a sufficient transition current flows through the upper electrode, plasma instability can be suppressed. Furthermore, due to the rectification effect of the first rectifier element D1, the second DC signal output from the second waveform generation unit 50 does not flow to the plasma stabilization circuit 70. Therefore, distortion of the voltage waveform of the second DC signal due to the large-capacity capacitor C1 of the plasma stabilization circuit 70 can be suppressed.

[0120] <Second rectifier element>

[0121] Because of the voltage (hereinafter also referred to as "VDC voltage") generated at the upper electrode by supplying a first DC signal (bias signal) to the lower electrode, the plasma controlled by the second DC signal sometimes becomes unstable. For example, if the voltage level of the VDC voltage at the upper electrode is greater than the voltage level of the second DC signal, a current with the opposite polarity to the second DC signal (i.e., current reverse flow) may occur at the upper electrode. During current reverse flow, the plasma cannot be controlled by the second DC signal, and the plasma in chamber 10 becomes unstable. To suppress this phenomenon, in one embodiment, a second rectifier element may be provided on the transmission line L1.

[0122] Figure 11 and Figure 12 This is a diagram showing an example of the second rectifier element D2. Figure 11 Is Figure 5 An example of a first embodiment showing a structure in which a second rectifier element D2 is provided. Figure 12 Is Figure 10 The example shown in the second embodiment includes a second rectifier element D2. The second rectifier element D2 can be disposed between node N1 and the second filter F2 in the transmission line L1 (see reference). Figure 11 Alternatively, it can be set between node N1 and the second waveform generation unit 50 (see reference). Figure 12 ).

[0123] The second rectifier element is configured to block or suppress current with a polarity opposite to the second DC signal generated by the second DC generation unit 32b. For example, in Figure 11 and Figure 12 In the example shown, when the second DC signal has a negative polarity, the second rectifier element D2 can be configured to block or suppress the current flowing from the second DC generation unit 32b or the second waveform generation unit 50 to the node N1 side through the transmission line L1.

[0124] In one embodiment, the second rectifier element D2 can be composed of a diode. In this case, the anode electrode of the second rectifier element D2 (diode) can be electrically connected to the chamber 10 (upper electrode). Alternatively, the cathode electrode of the second rectifier element D2 (diode) can also be electrically connected to the second DC generation section 32b or the second waveform generation section 50. In one example, the diode can be a mesa-type or planar-type PN junction diode. The second rectifier element D2 can be composed of multiple diodes, in which case the diodes can be connected in series or in parallel.

[0125] The second rectifier element D2 can block or suppress the reverse current flowing from the second DC generation unit 32b to the node N1 side on the transmission line L1. Therefore, it is possible to suppress the instability of the plasma controlled by the second DC signal. As a result, it is possible to suppress abnormal discharges and the like caused by plasma instability in the chamber 10.

[0126] <Third Implementation Method>

[0127] Figure 13 This is a diagram illustrating other examples of coupling between the power supply 30 of the plasma processing apparatus 1 and the chamber 10. Figure 13 In the example shown, instead of the second DC generation unit 32b, the impedance fixing circuit 60 is connected to the upper electrode via the transmission line L4.

[0128] Impedance fixing circuit 60 is a circuit used to define the impedance of the upper electrode. The impedance fixing circuit can be constructed by connecting inductors and / or capacitors in series or parallel, so that it has any impedance for any frequency. In one embodiment, impedance fixing circuit 60 may be similar to... Figure 6A or Figure 6B The first filter or the second filter shown.

[0129] Figure 14 This diagram illustrates a configuration example of the plasma stabilization circuit according to the third embodiment. The third embodiment is a configuration example where a first DC signal of negative polarity is supplied to the lower electrode. Figure 14 As shown, a node N2 is provided between the chamber 10 (upper electrode) and the impedance fixing circuit 60. The transmission line L42 between node N2 and the ground potential is provided with a first rectifier element D1 and a plasma stabilizing circuit 70, as described in the first and second embodiments.

[0130] In the third embodiment, after supplying a first DC signal (bias signal) to the lower electrode, the plasma stabilization circuit 70 instantaneously supplies the necessary amount of charge to the upper electrode. That is, the plasma stabilization circuit 70 can suppress plasma instability, allowing sufficient transition current to flow through the upper electrode.

[0131] The capacitor C1 in the plasma stabilization circuit 70 has a low impedance. Therefore, without the first rectifier element D1, the capacitor C1 could strongly influence the impedance of the impedance-fixing circuit 60 as observed from the chamber 10 (upper electrode) side. In the third embodiment, the first rectifier element D1 is provided on the transmission line L42 between node N2 and the plasma stabilization circuit 70. The first rectifier element D1 functions as a high-impedance element. Therefore, the influence of the capacitor C1 on the impedance of the impedance-fixing circuit 60 as observed from the chamber 10 (upper electrode) side can be suppressed.

[0132] <Variation Example>

[0133] Figure 15A This illustrates the first embodiment ( Figure 5 A diagram showing a variation of ). Figure 15B This illustrates the second embodiment ( Figure 10 The figures show variations of the DC signal generated by the first DC generation unit 32a. These examples are configuration examples where the first DC signal generated by the first DC generation unit 32a is positive. Furthermore, the second DC signal generated by the second DC generation unit 32b can be either positive or negative.

[0134] like Figure 15A and 15B As shown, a third rectifier element D3 is provided on the transmission line L12. The third rectifier element D3 is configured such that the rectification direction is opposite to that of the first rectifier element D1, that is, when viewed from the plasma stabilization circuit 70, the current is reversed on the side of the chamber 10 (upper electrode). Except for the fact that the rectification direction is reversed, the third rectifier element D3 can also be configured in the same way as the first rectifier element D1.

[0135] Figure 16 This is a diagram illustrating an example of a polarity switching circuit. (As shown...) Figure 16 As shown, the polarity switching circuit 80 can be provided on the transmission line L12. The polarity switching circuit 80 is configured to switch the first rectifier element D1 and the third rectifier element D3 at a given timing. For example, if the polarity of the first DC signal is reversed during processing, the polarity switching circuit 80 can switch the first rectifier element D1 and the third rectifier element D3. Specifically, when the first DC signal generated by the first DC generation unit 32a is negative, the polarity switching circuit 80 can turn on the switching element S-1 and turn off the switching element S-2, making the first rectifier element D1 active. In one example, when the first DC signal generated by the first DC generation unit 32a is positive, the polarity switching circuit 80 can turn off the switching element S-1 and turn on the switching element S-2, making the third rectifier element D3 active.

[0136] Figure 17 This is a diagram illustrating other coupling examples between the power supply 30 and the chamber 10. Figure 17 In the example shown, the second RF generation unit 31b is electrically connected to the lower electrode via transmission line L5. That is, the bias RF signal can also be provided to the lower electrode as a bias signal. The remaining points can be connected to... Figure 3 The example shown is the same. Similar to the first and second embodiments, the plasma stabilization circuit 70, etc., can be electrically connected to the upper electrode via node N1 of the transmission line L1.

[0137] Figure 18 This is a diagram showing other coupling examples between the power supply 30 and the chamber 10. Figure 18The example shown is one where the second DC generator 32b is electrically connected to the ring assembly 112 via transmission line L6. That is, a second DC signal can be supplied to the ring assembly 112. The remaining points can be connected to... Figure 3 The example shown is the same. Similar to the first and second embodiments, the plasma stabilization circuit 70, etc., can be electrically connected to the ring assembly 112 via the nodes of the transmission line L6.

[0138] like Figure 18 As shown, in one embodiment, the second DC generating unit 32b can be electrically connected to a conductive component other than the upper electrode. The conductive component can be disposed within the chamber 10, or it can form part of the chamber 10, as long as it is not a ground electrode (including the conductive path to the ground electrode). For example, the conductive component can be a ring electrode, separately disposed radially inside or outside the ring assembly 112, in addition to the aforementioned ring assembly 112. For example, the conductive component can be the inner wall of the chamber 10, a bushing disposed along the inner wall, or a baffle disposed around the substrate support 11. Similar to the first and second embodiments, a plasma stabilization circuit 70, etc., can be electrically connected at the node between the second DC generating unit 32b and the conductive component.

[0139] Figure 19 This is a diagram showing other coupling examples between the power supply 30 and the chamber 10. Figure 19 yes Figure 18 A variation of the structure shown. In this example, the impedance fixing circuit 60 is electrically connected to the ring assembly 112 instead of the second DC generation unit 32b. Similar to the third embodiment, the plasma stabilization circuit 70, etc., can be electrically connected to the ring assembly 112 via a node of the transmission line L7.

[0140] like Figure 19 As shown, in one embodiment, the impedance fixing circuit 60 can be electrically connected to a conductive component other than the upper electrode. The conductive component, as long as it is a non-grounded electrode, can be disposed within the chamber 10, or it can form part of the chamber 10. In addition to the aforementioned ring assembly 112, the conductive component can be a ring electrode, which is separated radially inside or outside the ring assembly 112. For example, the conductive component can be the inner wall of the chamber 10, a bushing disposed along the inner wall 10, or a baffle disposed around the substrate support portion 11. Similar to the third embodiment, a plasma stabilization circuit 70, etc., can be electrically connected at the node between the impedance fixing circuit 60 and the conductive component.

[0141] The embodiments of this disclosure also include the following aspects.

[0142] (Note 1)

[0143] A plasma processing device comprising:

[0144] Chamber;

[0145] A substrate support portion, disposed within the cavity, includes at least one lower electrode;

[0146] The upper electrode is disposed above the substrate support portion;

[0147] A radio frequency signal generator, electrically connected to any one of the at least one lower electrode or the upper electrode, is configured to generate a radio frequency signal to generate plasma in the cavity;

[0148] A first voltage signal generator, electrically connected to any one of the at least one lower electrode, is configured to generate a first voltage signal, wherein the first voltage signal has a first voltage pulse sequence:

[0149] The second voltage signal generator is electrically connected to the upper electrode and is configured to generate a second voltage signal.

[0150] Capacitors; and

[0151] The rectifier element includes a first electrode and a second electrode, wherein the first electrode is electrically connected to a node located between the upper electrode and the second voltage signal generator, and the second electrode is electrically connected to ground potential via the capacitor.

[0152] (Note 2)

[0153] According to the plasma processing apparatus described in Appendix 1, the second voltage signal has a second voltage pulse sequence.

[0154] (Note 3)

[0155] According to the plasma processing apparatus described in Appendix 1, the second voltage signal has a certain voltage level.

[0156] (Note 4)

[0157] According to the plasma processing apparatus described in Appendix 2, the second voltage signal has a negative polarity, the first electrode is a cathode electrode, and the second electrode is an anode electrode.

[0158] (Note 5)

[0159] According to the plasma processing apparatus described in Appendix 4, the first voltage pulse sequence has a first pulse frequency in the range of 0.1 MHz to 2 MHz.

[0160] (Note 6)

[0161] According to the plasma processing apparatus described in Appendix 4 or Appendix 5, the second voltage pulse sequence has a second pulse frequency in the range of 0.1 kHz to 50 kHz.

[0162] (Note 7)

[0163] The plasma processing apparatus according to any one of Annexes 1 to 6, wherein the plasma processing apparatus further comprises a filter circuit disposed on a transmission line between the upper electrode and the second voltage signal generator.

[0164] (Postscript 8)

[0165] The plasma processing apparatus according to any one of Annexes 1 to 7, wherein the plasma processing apparatus further comprises a filter circuit disposed on a transmission line between the upper electrode and the node.

[0166] (Note 9)

[0167] The plasma processing apparatus according to any one of Annexes 1 to 8, wherein the plasma processing apparatus further comprises a filter circuit disposed on the transmission line between the node and the second voltage signal generator.

[0168] (Postscript 10)

[0169] The plasma processing apparatus according to any one of Appendices 1 to 9, wherein the plasma processing apparatus further comprises: a first filter disposed on the transmission line between the upper electrode and the node, for filtering the radio frequency band signal of the radio frequency signal; and

[0170] A second filter is disposed on the transmission line between the node and the second voltage signal generator, configured to filter the pulse frequency band signal of the first voltage pulse sequence.

[0171] (Postscript 11)

[0172] A plasma processing device comprising:

[0173] Chamber;

[0174] A substrate support portion, disposed within the cavity, includes at least one lower electrode;

[0175] The upper electrode is disposed above the substrate support portion;

[0176] A radio frequency signal generator, electrically connected to any one of the at least one lower electrode or the upper electrode, is configured to generate a radio frequency signal to generate plasma in the cavity;

[0177] A voltage signal generator, electrically connected to any one of the at least one lower electrode, is configured to generate a voltage signal, wherein the voltage signal has a voltage pulse sequence:

[0178] An impedance-fixing circuit is electrically connected to the upper electrode.

[0179] Capacitors; and

[0180] The rectifier element includes a first electrode and a second electrode, wherein the first electrode is electrically connected to a node located between the upper electrode and the impedance fixing circuit, and the second electrode is electrically connected to ground potential via the capacitor.

[0181] (Postscript 12)

[0182] According to the plasma processing apparatus described in Appendix 11, the voltage pulse has a negative polarity, the first electrode is a cathode electrode, and the second electrode is an anode electrode.

[0183] (Postscript 13)

[0184] According to Appendix 11 or Appendix 12, the plasma processing apparatus wherein the voltage pulse sequence has a first pulse frequency in the range of 0.1 MHz to 2 MHz.

[0185] (Postscript 14)

[0186] The plasma processing apparatus according to any one of Annexes 11 to 13, wherein the impedance fixing circuit comprises at least one of a capacitor and an inductor.

[0187] (Postscript 15)

[0188] A plasma processing device comprising:

[0189] Chamber;

[0190] A substrate support portion, disposed within the cavity, includes electrodes;

[0191] A first voltage signal generator is electrically connected to the electrode and configured to generate a first voltage signal, wherein the first voltage signal has a first voltage pulse sequence;

[0192] Conductive components that form part of the chamber or are disposed within the chamber;

[0193] Capacitor;

[0194] The rectifier element includes a first electrode and a second electrode, wherein the first electrode is electrically connected to the conductive component, and the second electrode is electrically connected to ground potential via the capacitor.

[0195] (Postscript 16)

[0196] According to the plasma processing apparatus described in Appendix 15, the plasma processing apparatus further comprises a second voltage signal generator, which is electrically connected to a node located between the first electrode of the conductive component and the rectifier element, thereby generating a second voltage signal.

[0197] (Postscript 17)

[0198] According to Appendix 15, the plasma processing apparatus further includes an impedance fixing circuit electrically connected to a node located between the conductive component and the first electrode of the rectifier element.

[0199] (Postscript 18)

[0200] According to the plasma processing apparatus described in Appendix 17, the impedance fixing circuit includes at least one of a capacitor and an inductor.

[0201] (Postscript 19)

[0202] The plasma processing apparatus according to any one of Annexes 15 to 18, wherein,

[0203] The conductive component is any one of the following components:

[0204] (a) An upper electrode disposed above the substrate support portion;

[0205] (b) A ring assembly disposed on the substrate support in such a manner as to surround the substrate of the substrate support;

[0206] (c) A bushing disposed along the inner wall of the chamber; and

[0207] (d) A baffle configured to surround the substrate support portion.

[0208] The above embodiments are described for illustrative purposes only and are not intended to limit the scope of this disclosure. Various modifications can be made to the above embodiments without departing from the scope and spirit of this disclosure. For example, components from some embodiments can be added to other embodiments. Furthermore, some constituent elements of one embodiment can be replaced with corresponding constituent elements of another embodiment.

Claims

1. A plasma processing apparatus, comprising: Chamber; A substrate support portion, disposed within the cavity, includes at least one lower electrode; The upper electrode is disposed above the substrate support portion; A radio frequency signal generator, electrically connected to any one of the at least one lower electrode or the upper electrode, is configured to generate a radio frequency signal to generate plasma in the cavity; A first voltage signal generator, electrically connected to any one of the at least one lower electrode, is configured to generate a first voltage signal, wherein the first voltage signal has a first voltage pulse sequence: The second voltage signal generator is electrically connected to the upper electrode and is configured to generate a second voltage signal. Capacitors; and The rectifier element includes a first electrode and a second electrode, wherein the first electrode is electrically connected to a node located between the upper electrode and the second voltage signal generator, and the second electrode is electrically connected to ground potential via the capacitor.

2. The plasma processing apparatus according to claim 1, wherein, The second voltage signal has a second voltage pulse sequence.

3. The plasma processing apparatus according to claim 1, wherein, The second voltage signal has a certain voltage level.

4. The plasma processing apparatus according to claim 2, wherein, The second voltage signal has a negative polarity, the first electrode is the cathode electrode, and the second electrode is the anode electrode.

5. The plasma processing apparatus according to claim 4, wherein, The first voltage pulse sequence has a first pulse frequency in the range of 0.1 MHz to 2 MHz.

6. The plasma processing apparatus according to claim 5, wherein, The second voltage pulse sequence has a second pulse frequency in the range of 0.1 kHz to 50 kHz.

7. The plasma processing apparatus according to claim 1, wherein, The plasma processing apparatus also includes a filter circuit disposed on the transmission line between the upper electrode and the second voltage signal generator.

8. The plasma processing apparatus according to claim 1, wherein, The plasma processing apparatus also includes a filter circuit disposed on the transmission line between the upper electrode and the node.

9. The plasma processing apparatus according to claim 1, wherein, The plasma processing apparatus also includes a filter circuit disposed on the transmission line between the node and the second voltage signal generator.

10. The plasma processing apparatus according to claim 1, wherein, The plasma processing device also includes: A first filter is disposed on the transmission line between the upper electrode and the node to filter the radio frequency band signal of the radio frequency signal; and The second filter is disposed on the transmission line between the node and the second voltage signal generator, and is configured to filter the pulse frequency band signal of the first voltage pulse sequence.

11. A plasma processing apparatus, comprising: Chamber; A substrate support portion, disposed within the cavity, includes at least one lower electrode; The upper electrode is disposed above the substrate support portion; A radio frequency signal generator, electrically connected to any one of the at least one lower electrode or the upper electrode, is configured to generate a radio frequency signal to generate plasma in the cavity; A voltage signal generator, electrically connected to any one of the at least one lower electrode, is configured to generate a voltage signal, wherein... The voltage signal has a voltage pulse sequence: An impedance-fixing circuit is electrically connected to the upper electrode. Capacitor; and The rectifier element includes a first electrode and a second electrode, wherein the first electrode is electrically connected to a node located between the upper electrode and the impedance fixing circuit, and the second electrode is electrically connected to ground potential via the capacitor.

12. The plasma processing apparatus according to claim 11, wherein, The voltage pulse has a negative polarity, the first electrode is a cathode electrode, and the second electrode is an anode electrode.

13. The plasma processing apparatus according to claim 12, wherein, The voltage pulse sequence has a first pulse frequency in the range of 0.1 MHz to 2 MHz.

14. The plasma processing apparatus according to claim 13, wherein, The impedance-fixing circuit includes at least one of a capacitor and an inductor.

15. A plasma processing apparatus, comprising: Chamber; A substrate support portion, disposed within the cavity, includes electrodes; A first voltage signal generator, electrically connected to the electrodes, is configured to generate a first voltage signal, wherein... The first voltage signal has a first voltage pulse sequence; Conductive components that form part of the chamber or are disposed within the chamber; Capacitor; The rectifier element includes a first electrode and a second electrode, wherein the first electrode is electrically connected to the conductive component, and the second electrode is electrically connected to ground potential via the capacitor.

16. The plasma processing apparatus according to claim 15, wherein, The plasma processing apparatus further includes a second voltage signal generator, which is electrically connected to a node located between the conductive component and the first electrode of the rectifier element, thereby generating a second voltage signal.

17. The plasma processing apparatus according to claim 15, wherein, The plasma processing apparatus further includes an impedance fixing circuit, which is electrically connected to a node located between the conductive component and the first electrode of the rectifier element.

18. The plasma processing apparatus according to claim 17, wherein, The impedance-fixing circuit includes at least one of a capacitor and an inductor.

19. The plasma processing apparatus according to any one of claims 15 to 18, wherein, The conductive component is any one of the following components: (a) An upper electrode disposed above the substrate support portion; (b) A ring assembly disposed on the substrate support in such a manner as to surround the substrate on the substrate support; (c) A bushing disposed along the inner wall of the chamber; and (d) A baffle configured to surround the substrate support portion.

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