Integrated acquisition and control system of PLC analog and digital signals

Abstract

This invention discloses an integrated acquisition and control system for PLC analog and digital signals, specifically relating to the field of integrated acquisition and control technology. It includes a signal assembly module for acquiring analog input signals, digital input signals, and recent output action records collected by the edge PLC for the target controlled object within the current scan cycle, and performing association alignment according to the target controlled object to output the current signal group; a backtracking module for performing backtracking extraction on the historical cached data corresponding to the current signal group, solving for the analog state interval, digital state combination, and output action state of the target controlled object at the previous effective control moment, and combining them as the previous real state output; by associating and assembling the analog signals, digital signals, and output action records collected within the current scan cycle, and combining them with the previous real state to perform state evolution analysis and reachability determination, and then performing real state writing or conservative control based on the determination results.

Description

Technical Field

[0001] This invention relates to the field of integrated acquisition and control technology, and more specifically, to an integrated acquisition and control system for PLC analog and digital signals. Background Technology

[0002] In existing PLC control technology, the mainstream approach in the industry is to solve the problems of unified access, unified processing and linkage control of analog and digital signals. Typically, an edge PLC reads analog and digital inputs separately within a scanning cycle, and combines preset thresholds, interlocking conditions, debouncing rules or timing delay logic to directly generate control outputs to meet the real-time control needs of field equipment.

[0003] For example, in the edge control scenario of multi-pump valve linkage, the edge PLC needs to perform local integrated acquisition and control of heterogeneous signals such as operation feedback, valve position, pressure, flow, and current without relying on the continuous participation of the host computer, while simultaneously meeting the hard constraints of fixed scanning cycle, access of expansion modules, field response lag, and control output not being frequently switched erroneously.

[0004] However, under this constraint, the mainstream approach will consistently reveal an observable and verifiable defect: although the edge PLC can collect a set of valid analog and digital signals in the same cycle, this set of signals may not correspond to the physical state path that the equipment can actually evolve to from the previous real state. Typically, this manifests as the operation feedback being set but the pressure, current, and flow still maintaining shutdown characteristics, or the valve position signal being flipped but the upstream and downstream pressure difference and flow characteristics still corresponding to the off state. As a result, even if the input address is valid and the single-point condition is met, the control program may still mistakenly write the combination of heterogeneous signals that cannot be simultaneously established as the current real state and continue to output control commands. The reason for this is that the existing method focuses on static condition judgment of the current sampling results and lacks a reachability verification mechanism based on the previous real state, the most recent output action, and the timing relationship of the current heterogeneous signals.

[0005] The technical problem this application aims to solve is: how to determine whether the analog and digital signals currently acquired by the edge PLC meet the reachability conditions for evolution from the previous real state to the current state under edge computing conditions, so as to avoid writing physically unreachable signal combinations as the current real state and participating in subsequent control. Summary of the Invention

[0006] To overcome the above-mentioned defects of the prior art, embodiments of the present invention provide an integrated acquisition and control system for PLC analog and digital signals. The system associates and constructs analog signals, digital signals and output action records acquired in the current scanning cycle, and performs state evolution analysis and reachability determination in conjunction with the previous real state. Then, based on the determination result, it performs real state writing or conservative control.

[0007] To achieve the above objectives, the present invention provides the following technical solution: an integrated acquisition and control system for PLC analog and digital signals, comprising a signal composition module, a backtracking module, an evolution analysis module, a judgment module, and a control distribution module:

[0008] The signal assembly module is used to acquire the analog input signals, digital input signals and recent output action records collected by the edge PLC for the target controlled object in the current scan cycle, and perform association alignment according to the target controlled object to output the current signal group;

[0009] The backtracking module is used to perform backtracking extraction on the historical cache data corresponding to the current signal group, solve the analog quantity state range, digital quantity state combination and output action state of the target controlled object at the previous effective control time, and combine them as the previous real state output.

[0010] The evolution analysis module performs time-series correlation analysis on the analog input signals, digital input signals and most recent output action records in the current signal group based on edge computing, solves the direction of change, the order of change and the time interval of change, and outputs the state evolution characteristics.

[0011] The determination module is used to perform state reachability determination on the state evolution characteristics and the previous real state, to determine whether the current signal group meets the reachability conditions from the previous real state to the current state, and outputs the reachability determination result.

[0012] The control split module is used to perform control judgment on the reachability determination result. When the reachability determination result is reachable, the current signal group is written as the current real state and the control output signal is output. When the reachability determination result is unreachable, the previous real state is kept as the current control basis and the conservative control output signal and the verification result are output.

[0013] In a preferred embodiment, the signal assembly module includes:

[0014] The system acquires the analog input signals, digital input signals, and recent output action records within the current scanning cycle, and maps these signals to the corresponding target controlled objects based on the pre-established signal attribution relationship of the controlled objects, outputting the initial signal set of the objects.

[0015] Perform timing correction within the scan cycle on the initial signal set of the object, and solve the timing position of each signal relative to the most recent output action based on the acquisition time of each signal and the most recent output action time, and output the timing signal set of the object;

[0016] The timing signal set of the object is aligned according to the target controlled object. The analog input signals, digital input signals and the most recent output action records that belong to the same target controlled object and are within the same scan cycle association range are combined and the current signal group is output.

[0017] In a preferred embodiment, the backtracking module includes:

[0018] Based on the historical cached data corresponding to the current signal group, perform reverse time backtracking retrieval according to the target controlled object, solve for the most recent valid control time that meets the control output write condition, and output the valid control time mark;

[0019] Based on the effective control time marker, perform state inverse solution on the corresponding historical cache data, extract the analog quantity history value, digital quantity history value and output action history value corresponding to the effective control time, map the analog quantity history value to the analog quantity state interval, combine the digital quantity history value into the digital quantity state combination, determine the output action history value as the output action state, and output the state inverse solution result;

[0020] According to the effective control time, the state inverse solution result is combined at the same time, and the analog quantity state interval, digital quantity state combination and output action state combination are used as the previous real state output.

[0021] In a preferred embodiment, the evolutionary analysis module includes:

[0022] Based on the analog input signals, digital input signals and the most recent output action record in the current signal group, the execution time of each signal is adjusted according to a unified scanning time base, the relative timing position of each analog input signal and each digital input signal relative to the most recent output action record is solved, and the timing position set is output.

[0023] Based on the time-series position set, adjacent sample values ​​are compared for each analog input signal to determine the direction of increase, decrease, or maintenance of each analog input signal relative to the most recent output action record. State transition recognition is performed for each digital input signal to determine the flip direction of each digital input signal relative to the most recent output action record, and an output direction feature set is generated.

[0024] In a preferred embodiment, the evolutionary analysis module further includes:

[0025] Based on the directional feature set and the time sequence position set, sort the sequential relationship of each analog input signal, each digital input signal and the most recent output action record, solve the change order of each signal relative to the most recent output action record, calculate the time interval between adjacent change nodes, and output the sequence time interval set.

[0026] Based on the directional feature set and the sequence time interval set, the analog input signal, digital input signal and the most recent output action record corresponding to the same target controlled object are jointly arranged to output state evolution characteristics.

[0027] In a preferred embodiment, the process of outputting the temporal location set in the evolutionary analysis module further includes:

[0028] Based on the current signal group, the sampling time of each analog input signal, the transition time of each digital input signal, and the action time of the most recent output action record are extracted according to the unified scanning time base to construct a time sequence. The time base calibration is performed with the total time deviation and the total time jitter as constraints, and the calibration time base parameters and the initial time sequence position are output.

[0029] Based on the calibration time base parameters, segmented matching is performed on the time series. According to the conditions of consistency between the previous and next steps of each analog input signal, each digital input signal and the most recent output action record, the continuous scan period condition and the corresponding action response condition, time series segments that do not meet the conditions are filtered out, and a candidate time series position set is output.

[0030] Perform cycle-by-cycle verification based on the candidate timing position set, calculate the offset and conflict amount of each candidate timing position in adjacent scan cycles, and perform conflict resolution on each candidate timing position based on the offset and conflict amount to determine the final relative timing position of each analog input signal and each digital input signal relative to the most recent output action record, and output the timing position set.

[0031] In a preferred embodiment, the determination module includes:

[0032] Based on the previous real state, extract the previous analog state interval, the previous digital state combination, and the previous output action state, and generate a state evolution constraint set according to the previous output action state. The state evolution constraint set includes the allowed change direction of the analog quantity, the allowed crossing interval of the analog quantity, the allowed jump path of the digital quantity, the allowed holding path of the digital quantity, and the allowed change time interval, and output the state evolution constraint set.

[0033] Based on the state evolution constraint set, perform item-by-item consistency verification on the state evolution characteristics, calculate the analog quantity interval deviation, digital quantity combination conflict, and sequence time interval violation, and summarize the analog quantity interval deviation, digital quantity combination conflict, and sequence time interval violation to form the arrival violation set output.

[0034] The arrival determination is performed according to the arrival violation set. If there are no analog quantity interval deviation items, no digital quantity combination conflict items, and no order time distance violation items in the arrival violation set, the arrival determination result is "arrivable". Otherwise, the arrival determination result is "unarrivable".

[0035] In a preferred embodiment, the process of forming the reached violation set output in the determination module further includes:

[0036] Based on the allowed change direction, allowed cross-range, allowed jump path, allowed hold path and allowed change interval of analog quantity in the state evolution constraint set, constraint mapping is performed on the change direction, change order and change interval in the state evolution characteristics to construct analog quantity check pairs, digital quantity check pairs and time interval check pairs, and output a consistent check pair set.

[0037] Based on the consistent check pair set, perform interval projection comparison on each analog quantity check pair, calculate the out-of-bounds length and direction violation number between each analog quantity state interval and the corresponding allowed cross-interval, and generate analog quantity interval deviation based on the out-of-bounds length and direction violation number. Perform path matching comparison on each digital quantity check pair, calculate the number of missing nodes, reverse-order nodes and mutually exclusive nodes between each digital quantity state combination and the corresponding allowed jump path and allowed hold path, and generate digital quantity combination conflict based on the number of missing nodes, reverse-order nodes and mutually exclusive nodes. Output the analog quantity deviation set and the digital quantity conflict set.

[0038] Based on the time interval check pairs in the consistent check pair set, the sequential constraints of each change order and change time interval are solved. The time interval difference, the number of order inversions and the number of action mismatches between each adjacent change node are calculated. Based on the time interval difference, the number of order inversions and the number of action mismatches, the order time interval violation quantity is generated, and the time interval violation set is output.

[0039] Cross-checking is performed based on the analog quantity deviation set, digital quantity conflict set, and time interval violation set. The analog quantity interval deviation, digital quantity combination conflict, and order time interval violation that share the same change node are merged. The merged result is used to resolve conflicts and form a violation item set. The violation item set is then summarized into the arrival violation set output.

[0040] In a preferred embodiment, the control shunt module includes:

[0041] Based on the reachability determination result, the control branch is determined. When the reachability determination result is reachable, the analog input signal, digital input signal and the most recent output action record in the current signal group are extracted, and the current real state write set is generated. When the reachability determination result is unreachable, the analog state interval, digital state combination and output action state in the previous real state are extracted, and the conservative control basis set is generated.

[0042] In a preferred embodiment, the control shunt module further includes:

[0043] Based on the current real state write set, perform state overwrite write, replace the corresponding state record in the historical cache with the current real state write set, and call the preset control logic based on the current real state write set to solve the control output channel, control output value and control output time, and output the control output signal.

[0044] Perform conservative control calculations according to the conservative control basis set, maintain the control path and output boundary corresponding to the previous real state, perform verification acquisition on the current signal group and solve the verification signal group, perform consistency comparison between the verification signal group and the conservative control basis set, and output the conservative control output signal and verification result.

[0045] The technical effects and advantages of this invention are as follows:

[0046] 1. This scheme forms the previous real state by backtracking to the previous effective control moment, and performs reachability determination by combining the most recent output action and the current state evolution characteristics. This ensures that the currently acquired analog and digital signals are first verified by the physical evolution path before participating in the state writing, thereby relatively suppressing the problem of mistakenly writing the combination of physically unreachable heterogeneous signals as the current real state.

[0047] 2. The analog input signal, digital input signal and the most recent output action record are associated and aligned according to the target controlled object, and the relative timing position is solved under a unified scanning time base, so that the object boundary and timing boundary of the heterogeneous signal are consistent, thereby relatively improving the problem of misassociation in the same period caused by the dispersion of sampling time and the inconsistency of jump time;

[0048] 3. Perform reverse time backtracking retrieval on the historical cache data corresponding to the current signal group, and perform state inverse solution on the historical values ​​of analog quantity, digital quantity, and output action corresponding to the effective control time to form the previous real state, thereby providing a clear previous state benchmark for subsequent judgment and relatively reducing the risk of state chain breakage caused by static judgment based solely on the current sampling results;

[0049] 4. Perform item-by-item consistency verification on the direction of change, order of change, and time interval of change in the state evolution characteristics with the state evolution constraint set, and generate the deviation of analog quantity interval, the conflict of digital quantity combination, and the violation of order and time interval respectively, thereby transforming the originally scattered signal anomalies into a set of verifiable violations, and relatively improving the ability to identify the abnormal evolution process.

[0050] 5. In reachable branches, the current real state is overwritten and the control output signal is output. In unreachable branches, the previous real state is maintained, conservative control is performed, and verification data is collected. This makes the control output match the state reliability, which alleviates the problem of frequent erroneous switching of control output under abnormal sampling conditions. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of the system module structure of the present invention. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] Refer to the instruction manual appendix Figure 1 The integrated acquisition and control system for PLC analog and digital signals of the present invention includes a signal assembly module, a backtracking module, an evolution analysis module, a judgment module, and a control distribution module.

[0054] The signal assembly module is used to acquire the analog input signals, digital input signals and recent output action records collected by the edge PLC for the target controlled object in the current scan cycle, and perform association alignment according to the target controlled object to output the current signal group;

[0055] In this embodiment, the purpose of the signal assembly module is to: first, uniquely assign the analog input signals, digital input signals, and most recent output action records collected by the edge PLC within the current scan cycle to the target controlled object; then, perform time sequence alignment according to the time relationship within a unified scan cycle; and finally, combine them according to the same controlled object and the same scan cycle's associated range, thereby outputting the current signal group that can be directly read by the subsequent backtracking module. Its working mechanism is to first solve the problems of dispersed heterogeneous signal sources, independent channels, and different recording formats; then, to solve the problem of inconsistencies between sampling time, transition time, and action time; and finally, to organize the originally dispersed input quantities into a unified signal expression that can directly participate in subsequent state inversion and state reachability determination under the same controlled object. This implementation process includes the following steps:

[0056] By mapping the heterogeneous signals acquired in the current scan cycle to the corresponding target controlled object through the signal attribution relationship of the controlled object, an initial signal set for the object is formed. The input quantities include analog input signals, digital input signals, and the most recent output action record acquired by the edge PLC in the current scan cycle. Among them, the analog input signals include at least the channel number, sample value, and sampling time; the digital input signals include at least the channel number, status value, and transition time; and the most recent output action record includes at least the output channel number, action direction, action time, and action hold flag. The processing actions include: firstly, reading the pre-established controlled object signal attribution relationship table, which consists of I / O address, channel number, device identifier, control loop identifier, and output action identifier, and writing it into the edge PLC configuration area by the engineering configuration file.

[0057] Then, for each analog input signal, digital input signal, and most recent output action record, affiliation matching is performed. The matching order is: first, matching by output action identifier, then by control loop identifier, and then by device identifier. When all three match the same controlled object, the signal is mapped to that target controlled object. If a signal corresponds to multiple target controlled objects, the affiliation result with more matching fields is retained. If the number of matching fields is the same, one is selected according to the preset channel priority order. If a signal does not match any target controlled object, the signal is written to the unaffiliated signal buffer and an exception mark is attached. It is not included in the initial signal set of this object. The output is the initial signal set of the object. The initial signal set of the object is stored separately for each target controlled object. Each target controlled object includes at least the analog input signal, digital input signal, and most recent output action record that have been affixed in the current scan cycle, for the timing correction reading in the next step of the scan cycle.

[0058] The initial signal set of the target is subjected to time-series realignment under a unified scanning time base to determine the time-series position of each signal relative to the most recent output action time, forming the target time-series signal set. The input quantity is the initial signal set of the target, in which each target controlled object contains multiple analog input signal sampling times, multiple digital input signal transition times, and at least one most recent output action time. The processing actions include: firstly, reading the start time and end time of the current scanning cycle as a unified scanning time base, and extracting the sampling time of each analog input signal, the transition time of each digital input signal, and the action time of the most recent output action record in the initial signal set of the target to construct a time sequence under the same target controlled object; then, using the most recent output action time as the reference time, calculating the difference between the sampling time of each analog input signal and the reference time, and the difference between the transition time of each digital input signal and the reference time, to obtain the time-series position of each signal relative to the most recent output action record.

[0059] For the same controlled object with multiple recent output action records, the reference time is determined by the action record whose action time is closest to the end of the current scan cycle. For analog input signals with multiple sample values ​​within the current scan cycle, the sample time that falls within the current scan cycle and is closest to the reference time is taken as the timing adjustment time. For digital input signals without state transitions within the current scan cycle, the state holding time corresponding to the start of the current scan cycle is used as its transition time for calculation. If a signal is missing time information, the last valid time of the previous scan cycle is read and added. If the previous scan cycle is also missing, the signal is marked as a time missing signal and written into the abnormal area, and it is not included in the timing position solution of this round. The output is the object timing signal set, which includes the target controlled object identifier, signal type, signal value, reference time, and corresponding timing position for the next step of association alignment reading.

[0060] According to the target controlled object and the associated range of the same scan cycle, the object timing signal set is associated and aligned to form the current signal group that can be directly read by the traceback module. The input is the object timing signal set and the associated range parameter of the current scan cycle. The associated range parameter is jointly defined by the start point of the scan cycle, the end point of the scan cycle, and the action time corresponding to the most recent output action record. The start point and end point of the scan cycle are directly given by the edge PLC system clock, and the action time corresponding to the most recent output action record is determined by the previous step. The processing actions include: first, grouping the object timing signal set according to the target controlled object; then, within each target controlled object, filtering the analog input signals, digital input signals, and most recent output action records whose sampling time, transition time, or state holding time falls within the associated range of the current scan cycle.

[0061] Subsequently, analog input signals, digital input signals, and recent output action records belonging to the same controlled object and meeting the association range conditions are combined according to a unified field order to form the current signal group. The unified field order includes the controlled object identifier, the set of analog input signals, the set of digital input signals, the set of recent output action records, the reference action time, and the timing position of each signal. When a controlled object is missing an analog input signal in the current scan cycle, its digital input signal and recent output action record are retained to form an incomplete current signal group and an analog missing mark is added. The same processing is performed when a digital input signal is missing. When both analog and digital input signals are missing, only the recent output action record is retained and written to the pending review queue, and it is not output as the current signal group. The output is the current signal group, which is written to the current scan cycle buffer for the backtracking module to read and use to perform the reverse solution of the previous real state.

[0062] Through the above implementation process, the edge PLC can first complete the unique attribution of heterogeneous input signals and output action records within the current scan cycle, then complete the timing alignment under a unified scan time base, and finally form a current signal group for a single target controlled object. This eliminates subsequent state judgment errors caused by the dispersed sources, inconsistent times, and unclear object boundaries of analog input signals, digital input signals, and the most recent output action records. At the same time, this implementation process writes unassigned signals, signals with missing times, and incomplete signal groups into the corresponding abnormal areas or queues to be reviewed, so that the input objects read by the subsequent backtracking module and judgment module have clear sources, clear boundaries, and clear timing relationships.

[0063] In practical applications: Taking a pump-valve linkage control device as an example, after the analog input signal corresponding to the pump outlet pressure sensor, the digital input signal corresponding to the valve position switch, and the pump start-up output action record enter the edge PLC in the same scan cycle, they are first mapped to the same pump-valve controlled object based on the device identifier and control loop identifier. Then, the relative timing position of the pressure sampling time and the valve position jump time is calculated based on the pump start-up action time. Finally, the pressure signal, valve position signal, and start-up action record are combined into the current signal group of the pump-valve controlled object, which is used by subsequent steps to solve the previous real state and perform state evolution judgment. If the valve position switch does not upload the jump time in the scan cycle, the digital input signal is added according to the state holding time. If it is still missing after being added, the current signal group of the pump-valve controlled object is marked as a group to be reviewed and does not directly participate in the subsequent real state writing.

[0064] The backtracking module is used to perform backtracking extraction on the historical cache data corresponding to the current signal group, solve the analog quantity state range, digital quantity state combination and output action state of the target controlled object at the previous effective control time, and combine them as the previous real state output.

[0065] In this implementation, the purpose of the backtracking module is to: first locate the most recent valid control moment that meets the control output write conditions based on the historical cache data corresponding to the current signal group; then perform state inversion on the historical record corresponding to that moment; and finally form the previous real state that can be directly read by the evolution analysis module and the judgment module. Its working mechanism is that the current signal group formed within the current scanning cycle only reflects the current acquisition result. If subsequent state evolution analysis is performed directly based on this, a continuous relationship with the previous valid control result cannot be established. Therefore, it is necessary to backtrack from the historical cache data to the most recent control moment where the real state has been written and control output has been formed, and to uniformly restore the analog quantity, digital quantity, and output action at that moment to the previous real state as the starting point for subsequent state reachability determination. This implementation process includes the following steps:

[0066] The most recent valid control moment that meets the control output write condition is determined from the historical cache data corresponding to the current signal group, thus providing a unified time reference for subsequent state inversion. The input includes the target controlled object identifier in the current signal group, the current scan cycle identifier, and the historical cache data corresponding to the target controlled object. The historical cache data includes at least previous state write records, control output records, verification result records, and time markers. The processing actions include: first, extracting all historical records corresponding to the target controlled object from the historical cache based on the target controlled object identifier; then, performing a reverse time backtracking retrieval according to the time from the most recent to the oldest, and sequentially determining whether each historical record meets the control output write condition. The control output write condition includes three conditions: the current real state write is completed, the corresponding control output signal has been output, and the control has not entered the conservative control branch. When a historical record meets all three conditions, its time is determined as the most recent valid control moment.

[0067] If a historical record only completes state writing without generating control output, or generates control output but the corresponding verification result is inconsistent, then skip that historical record and continue backtracking. If no historical record that meets the conditions is found when backtracking to the initialization boundary, then the system initialization time is determined as the effective control time, and the initial state record of the target controlled object is used as the basis for subsequent reverse engineering. The output is a valid control time marker, which includes at least the target controlled object identifier, the valid control time value, and the corresponding historical record index, and is written to the backtracking result cache for the next step to read. If the historical cache data is missing, the record time is broken, or the target controlled object has no historical record, then the target controlled object is marked as a historical missing object, and the process switches to the initialization backtracking branch.

[0068] Based on the effective control time marker, the corresponding historical cache data is subjected to state inverse decomposition, restoring the discrete records under the effective control time into a state expression that can be directly used for subsequent judgment; the input includes the effective control time marker and the historical cache data corresponding to the effective control time. The historical cache data includes at least analog quantity historical value, digital quantity historical value, and output action historical value; the processing actions include: first, locating the analog quantity historical value record, digital quantity historical value record, and output action historical value record under the effective control time; then, performing interval mapping on the analog quantity historical value. The interval mapping is completed according to the preset segmented threshold table. The preset segmented threshold is derived from the equipment control rules or debugging calibration configuration. Each analog quantity input signal corresponds to at least two state interval boundaries. Whichever boundary segment the analog quantity historical value falls into is mapped to the corresponding analog quantity state interval;

[0069] Subsequently, a combination inverse solution is performed on the digital historical values. The bits are concatenated according to the channel order or function bit order of the digital input signals under the same controlled object to form a digital state combination. Then, the output action historical values ​​are used to determine the state, based on the output channel number, action direction, and action hold flag, to determine the output action state corresponding to the effective control moment. When analog historical values ​​are missing, the most recent valid analog historical value of the same controlled object before the effective control moment is read and added. If the missing value is still present after addition, the missing value is written according to the initialization interval corresponding to the analog input signal. The system replaces missing values ​​with alternative flags. When a digital historical value is missing, the channel's previous held value is read and added. If the value is still missing, the digital channel is marked as unacknowledged and written into the combined result. When an output action historical value is missing, the control output record corresponding to the effective control time is read to determine the output action status. If the control output record is also missing, it is treated as no action and an action missing flag is added. The output quantity is the state inverse solution result, which includes at least the set of analog state intervals, the combination of digital state, and the output action status. This result is written into the state inverse solution buffer for the next step to read.

[0070] The inverse state solution results are uniformly combined around the same effective control time, and the output is the previous true state with a unified time base and a unified object boundary. The input quantities include the inverse state solution results and the effective control time marker. The processing actions include: first, reading the analog state intervals, digital state combinations, and output action states from the inverse state solution results, and reading the time value from the effective control time marker; then, performing the same-time combination according to the same target controlled object and the same effective control time, merging the analog state intervals, digital state combinations, and output action states into a complete state entry. The complete state entry includes at least the target controlled object identifier, the effective control time, the set of analog state intervals, the digital state combinations, the output action state, and the state source marker.

[0071] The combined result is then subjected to an integrity check to determine whether the analog quantity state range, digital quantity state combination, and output action state have all formed valid fields. If all are valid, the combined result is determined as the previous real state. If there are missing fields, the formed fields are retained and a missing type mark is added. At the same time, the previous real state is written into the state area to be reviewed, so that the subsequent judgment module can read and process it according to the missing state branch. The output quantity is the previous real state, and the previous real state is written into the previous real state buffer area, so that the evolution analysis module and the judgment module can read it.

[0072] Through the above implementation process, the backtracking module can first stably locate the previous effective control moment from the historical cache data, and then reconstruct the analog quantity state range, digital quantity state combination, and output action state around that moment, forming the previous true state under a unified time reference. This provides a clear starting point for subsequent state evolution characteristic analysis and state reachability determination, avoiding the mistake of taking the instantaneous signal obtained solely from the current acquisition results as the true previous state in the continuous control chain. At the same time, this implementation process provides supplementation, replacement, or marking processing for historical missing, time break, analog quantity missing, digital quantity missing, and output action missing, respectively, so that the previous true state has a clear source, clear boundaries, and clear time attribution.

[0073] In practical applications: Taking a pump-valve linkage control device as an example, when the current signal group indicates that the pump outlet pressure, valve position feedback, and pump start-up action record have formed an input set under the same target controlled object, the backtracking module first searches in reverse chronological order in the historical cache data of the pump-valve object for the most recent historical record that has been written into the current real state, has output control commands, and has not entered the conservative control branch, and determines the time of this record as the effective control time; then it reads the historical value of the outlet pressure at this time and maps it to the corresponding pressure state interval according to the pressure interval threshold; it reads the historical value of the valve position and forms a digital state combination according to the channel position sequence; it reads the historical value of the pump start-up output action to determine the output action state; finally, it combines the above three results according to the same effective control time to form the previous real state, which is used by subsequent modules to determine whether the currently collected pressure change, valve position flip, and start-up action response can evolve from the previous real state; if there is no control record that meets the conditions in the historical cache of the pump-valve object, the initial pressure interval, initial valve position combination, and no action state corresponding to the system initialization time are directly taken as the previous real state.

[0074] The evolution analysis module performs time-series correlation analysis on the analog input signals, digital input signals and most recent output action records in the current signal group based on edge computing, solves the direction of change, the order of change and the time interval of change, and outputs the state evolution characteristics.

[0075] In this embodiment, the purpose of the evolution analysis module is to: based on the current signal group, integrate analog input signals, digital input signals, and the most recent output action record into a timing analysis framework under the same scan time base, first forming a verifiable timing position set, then solving the change direction, change sequence, and change interval based on this, and jointly arranging them into state evolution features, so that the judgment module can generate a state evolution constraint set and perform state reachability judgment; its working mechanism is that the input sampling and output action of the edge PLC are in different stages within the scan cycle, the analog input signal changes continuously, and the digital input signal flips discretely. If it is not first aligned to the most recent output action record and form a stable relative timing position, the subsequent calculation of the change direction, change sequence, and change interval will have same-cycle misalignment and cross-cycle drift, thus affecting the reachability judgment result; this implementation process includes the following steps:

[0076] The timing of each signal in the current signal group is aligned to a unified scanning time base, and the relative timing positions of each analog input signal and each digital input signal relative to the most recent output action record are determined, forming a timing position set. The input quantities include analog input signals, digital input signals, and the most recent output action record in the current signal group. The analog input signals include at least the channel number, sample value, and sampling time; the digital input signals include at least the channel number, status value, and transition time; and the most recent output action record includes at least the output channel number, action direction, and action time. The processing actions include: first, reading the start and end times of the current scan cycle given by the edge PLC system clock as a unified scanning time base; then, extracting the sampling time of each analog input signal, the transition time of each digital input signal, and the action time of the most recent output action record in the current signal group, calculating the difference between each sampling time and action time, and the difference between each transition time and action time, and using the time difference as the relative timing position of each signal.

[0077] When multiple recent output action records exist for the same controlled object, the action time closest to the end of the current scan cycle is selected as the current action time. When multiple sampled values ​​exist for an analog input signal in the current scan cycle, the sampled value closest to the action time and falling within the current scan cycle is selected as the sampled value for the current analog input signal. When no transition occurs for a digital input signal in the current scan cycle, the hold state corresponding to the start of the scan cycle is read, and the start time of the scan cycle is determined as the hold time of the digital input signal for use in timing position calculation. The output is a timing position set, which includes at least the target controlled object identifier, signal channel number, signal type, action time, sampling time or transition time, and relative timing position, and is written to the evolution analysis buffer for the next step. When a signal is missing a sampling time or transition time, the last valid time of the previous scan cycle is read and added. If the addition fails, the signal is written to the time missing list and removed from the timing position set.

[0078] Based on the timing position set, the direction of change of each analog input signal and each digital input signal relative to the most recent output action record is calculated to form a direction feature set. The input quantities include the timing position set and the sampled values ​​of each analog input signal and the state values ​​of each digital input signal in the current signal group. The processing actions include: first, reading the sampled value selected in the current scan cycle for each analog input signal, and reading the last valid sampled value of the analog input signal in the previous scan cycle as the adjacent sampled value; then, performing an adjacent sampled value comparison, calculating the difference between the current sampled value and the adjacent sampled value, and determining the direction of increase if the difference is greater than zero, the direction of decrease if the difference is less than zero, and the direction of hold if the difference is equal to zero.

[0079] Subsequently, for each digital input signal, the state value of the current scan cycle is read, and the last valid state value of the digital input signal in the previous scan cycle is read as the adjacent state value. Then, state transition recognition is performed. If the current state value is inconsistent with the adjacent state value, it is determined to be a flip direction. If the current state value is consistent with the adjacent state value, it is determined to be a hold direction. The output is a directional feature set. The directional feature set is collected according to the target controlled object and written into the evolution analysis buffer. Each directional feature includes at least the signal channel number, signal type, relative timing position, and change direction, which is used for the next step to calculate the change order and change interval. When an analog input signal is missing an adjacent sample value, the most recent valid sample value of the signal is read and added. If the addition fails, the signal is written into the sample missing list and removed from the directional feature set. When a digital input signal is missing an adjacent state value, it is added according to the hold state at the beginning of the scan cycle. If the addition fails, the signal is written into the state missing list and removed from the directional feature set.

[0080] The order of change of each signal relative to the most recent output action record is determined according to the directional feature set and the temporal position set, and the change time interval is calculated. At the same time, the direction and the order time interval are jointly arranged into a state evolution feature. The input includes the directional feature set, the temporal position set, and the action time of the most recent output action record. The processing actions include: first, taking the most recent output action record as the action node, and taking each feature in the directional feature set as the change node; then, sorting according to the relative order of the sampling time or jump time of each change node with the action time to obtain the change order of the action node and each change node; if multiple change nodes have the same sampling time or jump time, a fixed sorting is performed according to the node type order, with the node type order being output action nodes first, digital change nodes first, and digital change nodes first, analog change nodes.

[0081] Subsequently, the time interval between two adjacent nodes is calculated according to the sorting result. The time interval is obtained by subtracting the time of the previous node from the time of the next node, and the intervals are collected to form an order time interval set. Finally, joint arrangement is performed based on the direction feature set and the order time interval set. The change direction of each changed node under the same target controlled object, the node's position in the change order, and the time interval with adjacent nodes are written into the same evolution record to form a state evolution feature and written into the state evolution feature cache for the judgment module to read. Anomaly handling includes: when a changed node is missing time information, the node time is first deduced from the relative time position in the time position set. If the deduction result falls into the current scan cycle, the node is retained; otherwise, the node is written into the time inconsistency list and removed from the sorting. When the number of changed nodes is zero after removal, only the action node is retained to generate an empty evolution record and add a no-change mark.

[0082] Time base calibration is performed on the action and signal times under a unified scan time base to obtain calibration time base parameters that can be used to generate the initial timing position, thereby reducing the impact of cross-cycle time drift on the timing position set. The input quantities include the sampling times of each analog input signal in the current signal group, the transition times of each digital input signal, and the action times of the most recently output action records. The processing actions include: first, constructing the above times into a time sequence according to the unified scan time base; then, defining the legal interval of the time sequence with the start and end points of the scan cycle, and calculating the time deviation of each time relative to the start of the scan cycle, which is obtained by subtracting the start of the scan cycle from the time; then, calculating the difference in the time deviation of the corresponding signal channel within adjacent scan cycles, and using the difference as the jitter amount.

[0083] Then, the absolute values ​​of the time deviations of all signal channels within the current scan cycle are summed to obtain the total time deviation, and the absolute values ​​of all jitter are summed to obtain the total time jitter. The total time deviation and the total time jitter are used as constraints to perform time base calibration, and the calibration time base parameters and the initial timing position calculated based on the calibration time base parameters are output. The output is the calibration time base parameters and the initial timing position, which are written to the time base calibration buffer for the next step to read. When there are missing moments in the time sequence, they are first filled in according to the last valid moment of the previous scan cycle. If the filling fails, the channel is written to the missing moment list and removed from the time base calibration calculation.

[0084] Based on the calibration time base parameters, the time sequence is segmented and matched to filter out time segments that do not meet the conditions of consistent sequence, continuous scan cycle, and corresponding action response, forming a candidate time sequence location set. The input quantities include calibration time base parameters, time sequence, and action response correspondence rules. The action response correspondence rules are given by the equipment control rules or debugging and calibration configuration and written into the edge PLC configuration area. The processing actions include: first, performing time correction on the time sequence based on the calibration time base parameters to obtain the corrected time sequence; then, segmenting the corrected time sequence according to the start and end points of the scan cycle, and grouping the times falling into the same scan cycle into the same time sequence segment.

[0085] Subsequently, conditional filtering is performed on each time segment. The conditional filtering includes the following conditions: the action moment is unique within the segment; the digital quantity transition moment satisfies the condition of consistent sequence relative to the action moment; the analog quantity sampling moment satisfies the condition of continuous scan cycle relative to the action moment; and the analog quantity directional feature and the digital quantity directional feature satisfy the condition of corresponding action response. When a time segment satisfies all of the above conditions, the relative time position corresponding to the segment is used as a candidate time position and written into the candidate time position set. When a time segment has multiple action moments or no action moment, the segment is written into the action abnormal segment list and removed. The output is the candidate time position set, which is categorized by the target controlled object and written into the candidate set buffer for the next step to read.

[0086] The candidate temporal position set is checked cycle by cycle. The offset and conflict amount of the candidate temporal positions in adjacent scan cycles are calculated and the conflicts are resolved accordingly to obtain the final relative temporal positions, thereby outputting a stable temporal position set. The input includes the candidate temporal position set and the candidate temporal position set corresponding to adjacent scan cycles. The processing actions include: first, for the same signal channel in adjacent scan cycles under the same target controlled object, the difference of the candidate relative temporal positions is calculated, and the difference is used as the offset; then, overlap detection is performed on the candidate relative temporal positions of different signal channels in the same scan cycle. When two candidate relative temporal positions correspond to the same node time but different node types, they are recorded as conflict items and included in the conflict amount.

[0087] Subsequently, conflict resolution is performed based on the offset and conflict amount. The conflict resolution rules include prioritizing candidate relative timing positions with zero offset, prioritizing candidate relative timing positions with zero conflict amount, and determining the final relative timing position as the candidate relative timing position that simultaneously satisfies both zero offset and zero conflict amount. When no candidate relative timing position satisfies the above rules, the priority is determined by the number of segments that meet the screening conditions corresponding to the candidate relative timing position, and the final relative timing position is determined accordingly. The output is a timing position set, which includes the final relative timing position of each analog input signal and each digital input signal relative to the most recent output action record, and is written into the evolutionary analysis buffer for the aforementioned steps to read. When the candidate timing position set is empty, the output timing position set is empty and a candidate missing mark is added for the decision module to process according to the missing branch.

[0088] Through the above implementation process, the evolution analysis module can first form a verifiable set of time-series positions under a unified scanning time base, then calculate the direction, order, and time interval of change of analog and digital quantities relative to the most recent output action record, and jointly arrange them into state evolution features. This provides verifiable input basis for the judgment module to generate a set of state evolution constraints and perform reachability judgment. At the same time, time base calibration, segmented matching, and cycle-by-cycle verification enable the time-series position set to have verifiable sources and conflict resolution rules, avoiding distortion of evolution features caused by cross-cycle drift and same-cycle misalignment.

[0089] In practical applications: taking pump-valve linkage control equipment as an example, the pump start-up action record is used as the action node, the valve position switch transition time is used as the digital quantity change node, and the sampling time when the outlet pressure sample value crosses the pressure range boundary is used as the analog quantity change node. The evolution analysis module first calculates the relative timing position of the valve position transition and pressure sampling based on the start-up action time. Then, it determines the pressure change direction by comparing adjacent sample values ​​and determines the valve position flip direction by identifying the state transition. Subsequently, the action node, valve position node, and pressure node are sorted sequentially to obtain the change order and the time interval between nodes is calculated to form a sequence time interval set. Finally, the directional features and sequence time intervals are combined and arranged into a state evolution feature for the judgment module to read. When the valve position transition time is missing in a certain scan cycle, it first participates in the timing adjustment according to the holding time and enters the cycle-by-cycle review of the candidate timing position set. If the review of adjacent cycles produces a conflict, the candidate is eliminated according to the conflict resolution rule and a candidate missing mark is output, so that the subsequent judgment module enters the missing branch instead of directly writing the cycle signal as the real state.

[0090] The determination module is used to perform state reachability determination on the state evolution characteristics and the previous real state, to determine whether the current signal group meets the reachability conditions from the previous real state to the current state, and outputs the reachability determination result.

[0091] In this embodiment, the purpose of the determination module is to: use the state evolution features output by the evolution analysis module as the current state expression, and the previous true state output by the backtracking module as the previous state reference; firstly, generate a state evolution constraint set from the previous true state; then, perform item-by-item consistency verification on the state evolution features according to the state evolution constraint set to form an arrival violation set; finally, output the reachability determination result based on the arrival violation set. Its working mechanism is that although the current signal group has completed object attribution, timing adjustment, and evolution feature extraction, whether these evolution features can actually evolve from the previous true state under the constraints of the previous output action state still needs to be confirmed through a unified verification process oriented towards analog quantities, digital quantities, and time interval relationships. Therefore, it is necessary to first establish state evolution constraints consistent with the previous true state, then map the current state evolution features item by item to this constraint for comparison, and finally determine whether the current signal group meets the arrival conditions for evolution from the previous true state to the current state based on the existence of violation items. This implementation process includes the following steps:

[0092] A set of state evolution constraints is generated from the previous real state, which can be directly called by the subsequent verification step, thereby transforming the previous real state into a specific judgment boundary for the evolution characteristics of the current state. The input quantities include the previous analog quantity state interval, the previous digital quantity state combination, and the previous output action state in the previous real state. The processing actions include: first, reading the target controlled object identifier corresponding to the previous real state, and extracting the previous analog quantity state interval, the previous digital quantity state combination, and the previous output action state corresponding to each analog quantity input signal under the target controlled object; then, generating a set of state evolution constraints according to the previous output action state, specifically including: determining the allowed change direction of each analog quantity input signal based on the previous output action state and the previous analog quantity state interval. The allowed change direction of the analog quantity is given by the control rule table, which is derived from the preset configuration or debugging calibration configuration.

[0093] Based on the previous analog state interval and the target state interval boundary table, the allowed analog input signal intervals are determined. The target state interval boundary table is derived from the device control rules. Based on the previous digital state combination and the previous output action state, the allowed digital transition paths and allowed digital hold paths for each digital input signal are determined. The allowed transition paths and allowed hold paths are given by the action path rule table of the controlled object. Based on the previous output action state and the corresponding device response time rule, the allowed change interval between each change node is determined. The device response time rule is derived from rule constraints or debugging calibration configuration. The output is a state evolution constraint set, which includes at least the allowed analog change direction, the allowed analog span interval, the allowed digital transition path, the allowed digital hold path, and the allowed change interval. This set is written to the decision buffer for the next step to read. When there are missing fields in the previous real state, the missing analog state intervals are filled in according to the initialization interval, the missing digital state combinations are filled in according to the previous hold combination, and the missing output action states are filled in according to the no-action state. The missing source mark is added to the filled fields.

[0094] Based on the state evolution constraint set, constraint mapping and item-by-item consistency verification are performed on the state evolution features to form a consistency verification set. On this basis, the analog quantity interval deviation, digital quantity combination conflict, and sequence time interval violation are solved. The input quantities include the state evolution constraint set and the state evolution features, where the state evolution features include at least the direction of change, the order of change, and the time interval of change. The processing actions include: firstly, based on the allowed change direction of the analog quantity, the allowed cross-interval of the analog quantity, the allowed jump path of the digital quantity, the allowed hold path of the digital quantity, and the allowed change time interval in the state evolution constraint set, the state evolution is... The change direction, change order, and change interval in the features are constrained and mapped. Specifically, each analog quantity change direction is mapped one-to-one with the corresponding allowed change direction of the analog quantity, and the actual state interval of the analog quantity is mapped one-to-one with the corresponding allowed crossing interval to construct an analog quantity check pair; each digital quantity state combination change result is mapped one-to-one with the corresponding allowed jump path and allowed hold path to construct a digital quantity check pair; the actual time interval of each adjacent change node is mapped one-to-one with the corresponding allowed change interval to construct a time interval check pair; then the above three types of check pairs are summarized to form a consistent check pair set and written into the check buffer area.

[0095] Subsequently, a consistent check is performed item by item based on the consistent check pair set: For each analog quantity check pair, an interval projection comparison is performed, mapping the actual analog quantity state interval to the corresponding allowed cross-interval coordinate axis, calculating the length exceeding the allowed cross-interval as the out-of-bounds length, and calculating the number of times the change direction is inconsistent with the allowed change direction as the direction violation count, and then generating the analog quantity interval deviation based on the out-of-bounds length and the direction violation count; For each digital quantity check pair, a path matching comparison is performed, comparing the actual digital quantity state combination sequence with the corresponding allowed jump path and allowed hold path node by node, recording the number of missing nodes if the expected node is not found, the number of reversed nodes if the node order is inconsistent, and the number of mutually exclusive nodes if they are found. Then, based on the number of missing nodes, the number of reversed nodes, and the number of mutually exclusive nodes, a digital combination conflict quantity is generated. The output quantities are the analog quantity deviation set and the digital quantity conflict set. The analog quantity deviation set includes at least the out-of-bounds length, direction violation number, and analog quantity interval deviation for each analog quantity channel. The digital quantity conflict set includes at least the number of missing nodes, the number of reversed nodes, the number of mutually exclusive nodes, and the digital quantity combination conflict quantity for each digital quantity channel. Both are written to the judgment buffer for the next step to read. When a check pair is missing an actual state interval or actual state combination, the previous valid state evolution record in the same scan cycle is read first to fill it in. If the filling fails, the check pair is written to the missing check pair list and treated as a violation item in subsequent judgments.

[0096] Based on the time interval check pairs in the consistency check pair set, the sequence constraints of each change order and change time interval are solved, and the sequence time interval violation is output to supplement the time sequence check results other than analog and digital quantities. The input quantities include the time interval check pairs in the consistency check pair set, the change order and change time interval in the state evolution characteristics, and the allowable change time interval in the state evolution constraint set. The processing actions include: first, reading the actual node sequence and actual time interval of each change node according to the target controlled object; then comparing the actual node sequence with the allowable node sequence specified in the constraint set item by item. If a later node appears before the preceding node in the actual sequence, it is counted as one sequence reversal count; then, the difference between the actual time interval of each pair of adjacent change nodes and the corresponding allowable change time interval is calculated to obtain the time interval difference value, which is the actual time interval minus the allowable change time interval.

[0097] Then, the correspondence table between action nodes and response nodes is read to determine whether each response node is consistent with its corresponding action node. If they are inconsistent, an action mismatch is counted. Finally, the order-time violation is generated based on the time difference, the number of order reversals, and the number of action mismatches. The output is a time violation set, which includes at least the time difference, the number of order reversals, the number of action mismatches, and the order-time violation for each node pair. This set is written to the decision buffer for the next step. When a node pair is missing an actual time interval, the actual time interval is first deduced from the time position set. If the deduction fails, the node pair is written to the time missing list, and the order-time violation for that node pair is recorded as a violation.

[0098] Cross-checking and node merging are performed on the analog quantity deviation set, digital quantity conflict set, and time interval violation set to form an arrival violation set that can be directly used for arrival determination. The input quantities include the analog quantity deviation set, digital quantity conflict set, and time interval violation set. The processing actions include: firstly, cross-checking is performed on the three types of results according to the target controlled object and the change node identifier, and the analog quantity interval deviation, digital quantity combination conflict, and order time interval violation that share the same change node are merged into the same node record to form a node merging result; then, conflict resolution is performed on the node merging result. Conflict resolution includes: when the same node has analog quantity interval deviation, digital quantity combination conflict, and order time interval violation, the violation items directly related to the previous output action state are retained first, and then the duplicate violations caused by the repetition of the same missing field are removed.

[0099] When multiple violations of the same type exist at the same node, the node that appears earlier in the order of change is retained first. Then, the node merging results after conflict resolution are used to generate a violation item set one by one. The violation item set includes at least the node identifier, violation type, violation source, and violation value. Finally, all violation item sets are summarized to form the arrival violation set and written to the decision buffer. The output is the arrival violation set, which is read by subsequent steps for arrival decision. When all three types of input results are empty, an empty arrival violation set is output with a no-violation flag attached.

[0100] Based on the arrival violation set, the reachability determination result is directly output to determine whether the current signal group meets the arrival conditions for evolution from the previous real state to the current state; the input quantity includes the arrival violation set; the processing actions include: first, reading all violation items in the arrival violation set; then, sequentially determining whether there are analog quantity interval deviation items, whether there are digital quantity combination conflict items, and whether there are sequence time interval violations; if none of the three types of violations exist, the reachability determination result is determined to be reachable; if any type of violation exists, the reachability determination result is determined to be unreachable.

[0101] The reachability determination result, along with the target controlled object identifier and the current scan cycle identifier, is then written into the determination result cache for the control diversion module to read. The output is the reachability determination result. Anomaly handling includes: when the reach violation set is accompanied by a missing check pair marker, a time interval missing marker, or a field filling marker, if there are no analog quantity interval deviation items, digital quantity combination conflict items, or order time interval violation items at the same time, the determination result is still recorded as unreachable and a missing source marker is added to avoid directly writing the current real state when the information is incomplete.

[0102] The intermediate data after the reachability determination result is formed is written back and connected to ensure that the output of the determination module and the input of the control distribution module maintain a consistent standard. The input quantities include the state evolution constraint set, the consistency check set, the analog quantity deviation set, the digital quantity conflict set, the time distance violation set, the arrival violation set, and the reachability determination result. The processing actions include: first, writing the state evolution constraint set into the constraint buffer area for subsequent review process calls; then, writing the consistency check set, the analog quantity deviation set, the digital quantity conflict set, and the time distance violation set into the intermediate result buffer area for traceability and anomaly review reading; finally, writing the arrival violation set and the reachability determination result into the determination result buffer area and sending the determination result index to the control distribution module.

[0103] When the reachability determination result is unreachable, the arrival violation set index is sent to the control flow distribution module for conservative control calculation and verification collection. When the reachability determination result is reachable, only the determination result index is sent for the control flow distribution module to write the current real state. The output consists of the determination result index and the arrival violation set index for the control flow distribution module to read. Exception handling includes: when the cache write fails, the corresponding target controlled object is marked as a write-back failure object, and the reachability determination result of that object is forcibly set to unreachable.

[0104] Through the above implementation process, the judgment module can transform the previous real state into a set of state evolution constraints, and then map the state evolution features onto specific constraint boundaries to perform three types of consistency checks: analog quantity, digital quantity, and time interval. Finally, it forms a set of arrival violations and outputs the reachability judgment result, thereby transforming the original static judgment based solely on the current sample value into a dynamic arrival judgment based on the constraints of the previous real state, the previous output action state, and the current evolution features. At the same time, node merging, conflict resolution, and missing branch processing make the source of the violation item clear, the boundary clear, and the write-back link clear, which facilitates the subsequent control diversion module to perform real state writing or conservative control according to a unified standard.

[0105] In practical applications: Taking a pump-valve linkage control system as an example, when the previous real state indicates that the pump is in a stopped state, the valve is in a closed combination, and the previous output action state is a start action, the determination module first generates a state evolution constraint set for the pump-valve object. The allowed direction of change for the analog quantity corresponding to pressure is increasing, the allowed pressure range is from the stop pressure range to the operating pressure range, the allowed jump path for the digital quantity corresponding to the valve position is from closed to open, and the allowed change time interval is given by the equipment response rules for valve position feedback and pressure establishment after pump start-up. Then, the pressure change direction, valve position change sequence, and pressure establishment time in the current state evolution characteristics are mapped to the constraint set. If... If the actual pressure range exceeds the allowable range, an analog range deviation is generated. If the actual valve position combination does not change according to the closed to open path, a digital combination conflict is generated. If the valve position arrival time is later than the allowable change time interval specified by the rules, a sequence time interval violation is generated. Then, the three types of violations are merged according to the shared node to form an arrival violation set. If any violation exists, the reachability judgment result corresponding to the current signal group of the pump valve object is output as unreachable, and the control diversion module performs conservative control along the previous real state. If none of the three types of violations exist, the reachability judgment result is output as reachable, and the control diversion module writes the current signal group as the current real state.

[0106] The control split module is used to perform control judgment on the reachability determination result. When the reachability determination result is reachable, the current signal group is written as the current real state and the control output signal is output. When the reachability determination result is unreachable, the previous real state is kept as the current control basis and the conservative control output signal and the verification result are output.

[0107] In this embodiment, the purpose of the control branching module is to: use the reachability determination result output by the determination module as the branch trigger condition; in the reachable branch, complete the overwrite of the current real state and output the control output signal accordingly; in the unreachable branch, maintain the previous real state as the control basis and output a conservative control output signal; and simultaneously perform verification acquisition on the current signal group to form a verification result, thereby transforming the reachability determination result into an executable control output and a traceable verification conclusion. Its working mechanism is that the reachability determination result reflects whether the current signal group meets the reachability condition for evolution from the previous real state to the current state. Only when reachable is it allowed to update the real state and drive the control logic with the current signal group; otherwise, conservative control needs to be maintained along the control path and output boundary of the previous real state, and the reliability of the current signal group is verified through verification acquisition to avoid erroneous writing of the real state under unreachable input, which could lead to subsequent control link drift. This implementation process includes the following steps:

[0108] Based on the reachability determination result, the control branch is determined and a current real state write set or a conservative control basis set is generated respectively, thus providing a unified input object for subsequent writing or conservative calculation. The input includes the reachability determination result, the current signal group and the previous real state, wherein the current signal group includes at least analog input signals, digital input signals and the most recent output action record, and the previous real state includes at least analog state intervals, digital state combinations and output action states. The processing actions include: first, reading the reachability determination result output by the determination module, and locating the current signal group and the previous real state by the target controlled object identifier; when the reachability determination result is reachable, extracting the analog input signals, digital input signals and the most recent output action record corresponding to the target controlled object from the current signal group, and constructing the current real state write entries according to a unified field order, which includes the target controlled object identifier, scan cycle identifier, write time, analog input signal set, digital input signal set and most recent output action record set, and then aggregating the write entries to form the current real state write set;

[0109] When the reachability determination result is unreachable, the analog quantity state interval, digital quantity state combination, and output action state corresponding to the target controlled object are extracted from the previous real state. Conservative control entries are constructed according to a unified field order, which includes the target controlled object identifier, effective control time, set of analog quantity state intervals, digital quantity state combination, and output action state. The conservative control entries are then aggregated to form a conservative control basis set. The output quantity is either the current real state write set or the conservative control basis set, and both are written to the control split buffer for the next step to read. When the current signal group is missing an analog quantity input signal or a digital quantity input signal, a missing mark is added when constructing the current real state write entry, and the entry is written to the pending review queue and does not enter the current real state write set.

[0110] The system performs a state overwrite write based on the current real state write set and deciphers the control output signal accordingly, thereby converting the determination result of the reachable branch into an executable control output. The input quantities include the current real state write set, historical cache data, and preset control logic, wherein the preset control logic is given by the control program or configuration rules and written into the edge PLC program area. The processing actions include: first, locating the corresponding state record in the historical cache data according to the target controlled object identifier, and reading the record index and record time of the state record; then, performing a state overwrite write based on the current real state write set, replacing the corresponding state record in the historical cache data with the write entry in the current real state write set that matches the target controlled object identifier, updating the write time to the write time in the current write entry, and writing the replaced old state record to the historical retention area for traceability.

[0111] Subsequently, based on the current real state, the preset control logic is invoked. Specifically, the set of analog input signals, the set of digital input signals, and the set of most recent output action records in the write entry are used as inputs to the control logic. The control output channel, control output value, and control output time are solved according to the output mapping relationship of the control logic. The control output time is taken as the end time of the current scan cycle or the time when the control logic is completed. The control output value is written to the output mapping area to drive the output channel to execute. Finally, the control output signal is generated and written to the control output record area. The output quantity is the control output signal, which includes at least the target controlled object identifier, the control output channel, the control output value, and the control output time, for the generation and reading of the most recent output action record in the next scan cycle. When the state overwrite fails or the control logic execution fails, the target controlled object is marked as a write failure object, and its branch is forcibly switched to an unreachable branch to enter conservative control calculation.

[0112] Conservative control calculations are performed based on the conservative control reference set, and a verification result is generated to maintain the control output boundary under unreachable branches and verify the reliability of the current signal group. Inputs include the conservative control reference set, the current signal group, and the verification acquisition configuration. The verification acquisition configuration is provided by a preset configuration and written into the edge PLC configuration area, and includes at least the verification acquisition trigger time and the verification acquisition cycle. Processing actions include: firstly, performing conservative control calculations according to the conservative control reference set; specifically, reading the output action state from the conservative control reference set and determining the control path and output boundary corresponding to the previous real state. The control path is determined by the control logic corresponding to the previous output action state. The logical branch is determined, and the output boundary is determined by the control output channel and the allowable range of the control output value corresponding to the previous real state. Then, within the current scan cycle, the control output channel is processed to maintain output or block output, and a conservative control output signal is generated and written to the control output record area. Then, the current signal group is subjected to verification acquisition. The verification acquisition trigger time is taken as the start time of the next scan cycle or the verification acquisition configuration specified time, and the verification acquisition period is taken as the verification acquisition configuration specified period. During the verification acquisition process, the analog input signal and digital input signal corresponding to the target controlled object are reacquired, and the corresponding most recent output action record is read to form a verification signal group.

[0113] Subsequently, a consistency comparison is performed between the verification signal group and the conservative control basis set. The consistency comparison includes mapping the analog input signals in the verification signal group to verification analog state intervals, combining the digital input signals in the verification signal group into verification digital state combinations, and comparing the verification analog state intervals and verification digital state combinations with the analog state intervals and digital state combinations in the conservative control basis set item by item. If all are consistent, the verification result is output as consistent; if there are inconsistencies, the verification result is output as inconsistent, and the inconsistencies are written to the verification difference record area. The output quantities are the conservative control output signal and the verification result. The conservative control output signal includes at least the target controlled object identifier, control output channel, control output value, and control output time. The verification result includes at least the target controlled object identifier, verification mark, verification time, and verification difference record index. Both are written to the control split result buffer area for subsequent backtracking modules to read as valid control time filtering criteria. When a signal is missing during the verification acquisition process, it is filled in according to the hold value of the channel corresponding to the previous real state and a missing mark is added. If the missing mark exists, the verification result is directly recorded as inconsistent.

[0114] Through the above implementation process, the control splitting module can realize the reachability determination result into two mutually exclusive branches. In the reachable branch, the current real state is written as the basis for control logic input and the control output signal is output. In the unreachable branch, the control path and output boundary are constrained by the conservative control basis set and the conservative control output signal is output. At the same time, the verification result is formed by verification collection and consistency comparison, thereby avoiding the control link drift caused by directly writing the real state under the unreachable input condition, and providing the subsequent backtracking module with the verification basis that can be used to screen the effective control time.

[0115] In practical applications: Taking pump-valve linkage control equipment as an example, when the judgment module outputs the reachability judgment result of the pump-valve object as reachable, the control diversion module extracts the pressure analog quantity, valve position digital quantity, and start action record from the current signal group to generate the current real state write set, and replaces the corresponding state record of the pump-valve object in the historical cache. Then, it calls the pump-valve control logic to solve the output values ​​of the pump start output channel and the valve opening output channel, and writes them into the output mapping area at the end of the current scan cycle to form a control output signal. When the reachability judgment result is unreachable, the control diversion module extracts the shutdown pressure range, valve position closing combination, and the previous output action state from the previous real state to generate a conservative control basis set. It uses the shutdown control path to block the pump start output channel and maintains the previous output value for the valve output channel to form a conservative control output signal. At the same time, in the next scan cycle, it re-acquires the valve position and pressure to form a verification signal group and compares it with the conservative control basis set to output the verification result. If the verification result is inconsistent, the difference is written into the verification difference record area for the subsequent backtracking module to avoid using this cycle as a valid control moment.

[0116] The working principle of this scheme is as follows: First, the edge PLC collects analog input signals, digital input signals, and the most recent output action record within the current scan cycle, and groups them into the current signal group according to the same target controlled object; then, it backtracks from the historical buffer to obtain the previous effective control moment to obtain the previous real state; subsequently, it analyzes the change direction, change order, and change time interval of the current signal group relative to the most recent output action, and compares it with the evolution constraints corresponding to the previous real state to determine whether the current signal group can actually evolve from the previous real state; if it can, the current signal group is written as the current real state and a control signal is output; if it cannot, the previous real state is maintained, conservative control is performed, and verification data is collected; its core is not to directly control according to the current sampled value, but to first determine whether the current sampled result is real and reliable, and then decide whether to participate in the control;

[0117] For example, in a pump-valve linkage scenario, after the system collects pressure values, valve position feedback, and start-up action records within a scan cycle, it does not immediately assume that the equipment has entered the operating state. Instead, it first reviews the actual state of the pump and valve at the previous moment and then judges whether the current valve position change, pressure change, and start-up action sequence is reasonable. If the valve acts first and the pressure is established subsequently, and the time sequence conforms to the equipment response pattern, then control is executed according to the current signal. If the valve position signal and pressure change do not match, or the action sequence is abnormal, the current sampling result is not directly written into the actual state. Instead, control is maintained according to the previous actual state and re-verified. This can avoid misjudgment and miscontrol.

[0118] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An integrated acquisition and control system for PLC analog and digital signals, comprising a signal assembly module, a backtracking module, an evolution analysis module, a judgment module, and a control distribution module, characterized in that: The signal assembly module is used to acquire the analog input signals, digital input signals and recent output action records collected by the edge PLC for the target controlled object in the current scan cycle, and perform association alignment according to the target controlled object to output the current signal group; The backtracking module is used to perform backtracking extraction on the historical cache data corresponding to the current signal group, solve the analog quantity state range, digital quantity state combination and output action state of the target controlled object at the previous effective control time, and combine them as the previous real state output. The evolution analysis module performs time-series correlation analysis on the analog input signals, digital input signals and most recent output action records in the current signal group based on edge computing, solves the direction of change, the order of change and the time interval of change, and outputs the state evolution characteristics. The determination module is used to perform state reachability determination on the state evolution characteristics and the previous real state, to determine whether the current signal group meets the reachability conditions from the previous real state to the current state, and outputs the reachability determination result. The control splitting module is used to perform control judgment on the reachability determination result. When the reachability determination result is reachable, the current signal group is written as the current real state and the control output signal is output. When the reachability determination result is unreachable, the previous true state is maintained as the current control basis, and a conservative control output signal and verification result are output. The backtracking module includes: Based on the historical cached data corresponding to the current signal group, perform reverse time backtracking retrieval according to the target controlled object, solve for the most recent valid control time that meets the control output write condition, and output the valid control time mark; Based on the effective control time marker, perform state inverse solution on the corresponding historical cache data, extract the analog quantity history value, digital quantity history value and output action history value corresponding to the effective control time, map the analog quantity history value to the analog quantity state interval, combine the digital quantity history value into the digital quantity state combination, determine the output action history value as the output action state, and output the state inverse solution result; According to the effective control time, the state inverse solution result is combined at the same time, and the analog state interval, digital state combination and output action state combination are used as the previous real state output. The determination module includes: Based on the previous real state, extract the previous analog state interval, the previous digital state combination, and the previous output action state, and generate a state evolution constraint set according to the previous output action state. The state evolution constraint set includes the allowed change direction of the analog quantity, the allowed crossing interval of the analog quantity, the allowed jump path of the digital quantity, the allowed holding path of the digital quantity, and the allowed change time interval, and output the state evolution constraint set. Based on the state evolution constraint set, perform item-by-item consistency verification on the state evolution characteristics, calculate the analog quantity interval deviation, digital quantity combination conflict, and sequence time interval violation, and summarize the analog quantity interval deviation, digital quantity combination conflict, and sequence time interval violation to form the arrival violation set output. The arrival determination is performed according to the arrival violation set. If there are no analog quantity interval deviation items, no digital quantity combination conflict items, and no order time distance violation items in the arrival violation set, the arrival determination result is "arrivable"; otherwise, the arrival determination result is "unarrivable". The control splitting module includes: Based on the reachability determination result, the control branch is determined. When the reachability determination result is reachable, the analog input signal, digital input signal and the most recent output action record in the current signal group are extracted, and the current real state write set is generated. When the reachability determination result is unreachable, the analog state interval, digital state combination and output action state in the previous real state are extracted, and the conservative control basis set is generated. The control and diversion module also includes: Based on the current real state write set, perform state overwrite write, replace the corresponding state record in the historical cache with the current real state write set, and call the preset control logic based on the current real state write set to solve the control output channel, control output value and control output time, and output the control output signal. Perform conservative control calculations according to the conservative control basis set, maintain the control path and output boundary corresponding to the previous real state, perform verification acquisition on the current signal group and solve the verification signal group, perform consistency comparison between the verification signal group and the conservative control basis set, and output the conservative control output signal and verification result.

2. The integrated acquisition and control system for PLC analog and digital signals according to claim 1, characterized in that: The signal assembly module includes: The system acquires the analog input signals, digital input signals, and recent output action records within the current scanning cycle, and maps these signals to the corresponding target controlled objects based on the pre-established signal attribution relationship of the controlled objects, outputting the initial signal set of the objects. Perform timing correction within the scan cycle on the initial signal set of the object, and solve the timing position of each signal relative to the most recent output action based on the acquisition time of each signal and the most recent output action time, and output the timing signal set of the object; The timing signal set of the object is aligned according to the target controlled object. The analog input signals, digital input signals and the most recent output action records that belong to the same target controlled object and are within the same scan cycle association range are combined and the current signal group is output.

3. The integrated acquisition and control system for PLC analog and digital signals according to claim 2, characterized in that: The evolutionary analysis module includes: Based on the analog input signals, digital input signals and the most recent output action record in the current signal group, the execution time of each signal is adjusted according to a unified scanning time base, the relative timing position of each analog input signal and each digital input signal relative to the most recent output action record is solved, and the timing position set is output. Based on the time-series position set, adjacent sample values ​​are compared for each analog input signal to determine the direction of increase, decrease, or maintenance of each analog input signal relative to the most recent output action record. State transition recognition is performed for each digital input signal to determine the flip direction of each digital input signal relative to the most recent output action record, and an output direction feature set is generated.

4. The integrated acquisition and control system for PLC analog and digital signals according to claim 3, characterized in that: The evolution analysis module also includes: Based on the directional feature set and the time sequence position set, sort the sequential relationship of each analog input signal, each digital input signal and the most recent output action record, solve the change order of each signal relative to the most recent output action record, calculate the time interval between adjacent change nodes, and output the sequence time interval set. Based on the directional feature set and the sequence time interval set, the analog input signal, digital input signal and the most recent output action record corresponding to the same target controlled object are jointly arranged to output state evolution characteristics.

5. The integrated acquisition and control system for PLC analog and digital signals according to claim 4, characterized in that: The process of outputting the temporal location set in the evolutionary analysis module also includes: Based on the current signal group, the sampling time of each analog input signal, the transition time of each digital input signal, and the action time of the most recent output action record are extracted according to the unified scanning time base to construct a time sequence. The time base calibration is performed with the total time deviation and the total time jitter as constraints, and the calibration time base parameters and the initial time sequence position are output. Based on the calibration time base parameters, segmented matching is performed on the time series. According to the conditions of consistency between the previous and next steps of each analog input signal, each digital input signal and the most recent output action record, the continuous scan period condition and the corresponding action response condition, time series segments that do not meet the conditions are filtered out, and a candidate time series position set is output. Perform cycle-by-cycle verification based on the candidate timing position set, calculate the offset and conflict amount of each candidate timing position in adjacent scan cycles, and perform conflict resolution on each candidate timing position based on the offset and conflict amount to determine the final relative timing position of each analog input signal and each digital input signal relative to the most recent output action record, and output the timing position set.

6. The integrated acquisition and control system for PLC analog and digital signals according to claim 5, characterized in that: The process of generating the arrival violation set output in the determination module also includes: Based on the allowed change direction, allowed cross-range, allowed jump path, allowed hold path and allowed change interval of analog quantity in the state evolution constraint set, constraint mapping is performed on the change direction, change order and change interval in the state evolution characteristics to construct analog quantity check pairs, digital quantity check pairs and time interval check pairs, and output a consistent check pair set. Based on the consistent check pair set, perform interval projection comparison on each analog quantity check pair, calculate the out-of-bounds length and direction violation number between each analog quantity state interval and the corresponding allowed cross-interval, and generate analog quantity interval deviation based on the out-of-bounds length and direction violation number. Perform path matching comparison on each digital quantity check pair, calculate the number of missing nodes, reverse-order nodes and mutually exclusive nodes between each digital quantity state combination and the corresponding allowed jump path and allowed hold path, and generate digital quantity combination conflict based on the number of missing nodes, reverse-order nodes and mutually exclusive nodes. Output the analog quantity deviation set and the digital quantity conflict set. Based on the time interval check pairs in the consistent check pair set, the sequential constraints of each change order and change time interval are solved. The time interval difference, the number of order inversions and the number of action mismatches between each adjacent change node are calculated. Based on the time interval difference, the number of order inversions and the number of action mismatches, the order time interval violation quantity is generated, and the time interval violation set is output. Cross-checking is performed based on the analog quantity deviation set, digital quantity conflict set, and time interval violation set. The analog quantity interval deviation, digital quantity combination conflict, and order time interval violation that share the same change node are merged. The merged result is used to resolve conflicts and form a violation item set. The violation item set is then summarized into the arrival violation set output.

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